DRAFT - NOT FOR PUBLICATION 16 July 2003 – ITRS Public Conference

Lithography Update

ITRS Meeting

San Francisco, CA

July 14 - 16

DRAFT - NOT FOR PUBLICATION 16 July 2003 – ITRS Public Conference

Potential Solutions200390nm

200480nm

200570nm

200665nm

200757nm

200850nm

200945nm

2010 2011 201232nm

2013 2014 201522nm

2016 2017 201816nm

2019

90 193 nm + RET

193 nm + RET + litho-friendly designs

65 157 nm + RET + litho-friendly designs

EPL

PEL

Im m ersion 193 nm lithography + RET + litho-friendly designs

45 157 nm + RET + litho-friendly designs

EUV, EPL, ML2

PEL

EUV

157 nm im m ersion + RET + litho-friendly designs Narrow32 EPL, Im print lithography options

ML2

EUV, EPL Narrow22 ML2, Im print lithography options

Innovative Technology

16 Innovative Technology NarrowML2, EUV + RET options

Narrow Options

First Year of IC Production

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ML2 = Maskless Lithography EUV = Extreme Ultra Violet PEL = Proximity Electron LithographyEPL = Electron Projection Lithography RET = Resolution Enhancement Technology

DRAFT - NOT FOR PUBLICATION 16 July 2003 – ITRS Public Conference

• Key changes.• X-ray and ion projection lithography removed. • Immersion lithography added.• Imprint lithography has been added.

Potential Solutions

DRAFT - NOT FOR PUBLICATION 16 July 2003 – ITRS Public Conference

Major Changes to ITRS Lithography Tables

• Lithography requirements.• New roadmap node definitions incorporated.• MPU CD control studied through simulations.

• ± 10% control retained.• Enabled by larger CDs in resist and more trim etch.

• Optical masks.• Changes for living in an optical-proximity corrected

world.• CD control capability re-colored.• 5X reduction eliminated.

• NGL masks.• Items for further study have been identified.

DRAFT - NOT FOR PUBLICATION 16 July 2003 – ITRS Public Conference

Major Changes to ITRS Lithography Tables

• Need lithography-friendly designs.• Near-term for optical lithography.• EPL.• Any solution for 22 nm and 16 nm nodes.

• Red items in 2004.• MPU CD control• Mask CD control for contacts

• Large MEF with binary masks.• Defects in resist

• Primarily a measurement issue.

DRAFT - NOT FOR PUBLICATION 16 July 2003 – ITRS Public Conference

Year of Production  2003 2004 2005 2006 2007 2008 2009

DRAM ½ Pitch (nm) 90 80 70 65 57 50 45

Contact in resist (nm) 110 100 90 80 70 60 55

Contact after etch (nm) 100 90 80 70 65 55 50

Overlay 32 28 25 23 21 19 18

CD control (3 sigma) (nm) 12.1 10.7 9.4 8.7 7.6 6.7 6.0

MPU ½ Pitch (nm) 107 90 80 70 65 57 50

MPU gate in resist (nm) 70 60 50 45 40 35 30

MPU gate length after etch (nm) 45 37 32 28 25 22 19

Contact in resist (nm) 122 100 90 80 75 65 60

Contact after etch (nm) 107 90 80 70 65 55 50

Gate CD control (3 sigma) (nm) 4.0 3.3 2.9 2.5 2.2 2.0 1.7

Minimum field area 704 704 704 704 704 704 704

Chip size (mm 2 )

DRAM

MPU

Lithography Requirements

DRAFT - NOT FOR PUBLICATION 16 July 2003 – ITRS Public Conference

Difficult Challenges - Short TermFive difficult challenges 50

nm before 2009. Summary of issues

Optical and EPL mask fabrication with resolution enhancement techniques and post-optical mask fabrication

Registration, CD control, defectivity, and 157 nm pellicles; defect free EPL membrane masks.

Equipment infrastructure (writers, inspection, repair).

Cost control and return-on-investment (ROI)

Achieving constant/improved ratio of tool cost to throughput over time.

Cost-effective resolution enhanced optical masks and post-optical masks.

Sufficient lifetimes for the technologies, Resources for developing multiple technologies at the

same time. Process control Processes to control gate CDs to less than 1.6 nm (3)

New and improved alignment and overlay control methods independent of technology option to 21 nm overlay.

Accuracy of OPC. Resists for ArF, F2, and

immersion lithography Outgassing, LER, SEM induced CD changes, defects

31 nm. CaF2 Yield, cost, quality.

DRAFT - NOT FOR PUBLICATION 16 July 2003 – ITRS Public Conference

Difficult Challenges - Long Term

Five difficult challenges 45 nm

beyond 2009.

Summary of issues

Mask fabrication and process control

Defect-free NGL masks. Equipment infrastructure (writers, inspection, repair). Mask process control methods.

Metrology and defect inspection

Capability for critical dimensions down to 9 nm and metrology for overlay down to 9 nm, and patterned wafer defect inspection for defects < 32 nm.

Cost control and return on investment (ROI)

Achieving constant/improved ratio of tool cost to throughput. Development of cost-effective post-optical masks. Achieving ROI for industry with sufficient lifetimes for the

technologies. Gate CD control

improvements; process control; resist materials

Development of processes to control gate CDs < 1 nm (3 sigma) with appropriate line-edge roughness.

Development of new and improved alignment and overlay control methods independent of technology option to < 9 nm overlay.

Tools for mass production

Post optical exposure tools capable of meeting requirements of the Roadmap.