Ec 452 Dc & Vhdl Lab Manual Final

EC 452: DIGITAL COMMUNICATIONS AND VHDL LAB MANUAL

Prepared byT. RAJASEKHAR

Assistant Professor

DEPARTMENT OF ECECHALAPATHI INSTITUTE OF ENGINEERING AND TECHNOLOGY

LAM, GUNTUR - 522034(AFFILIATED TO ACHARYA NAGARJUNA UNIVERSITY)

LIST OF EXPERIMENTS

Experiments Based on Hardware

1. Generation and Detection of ASK.

2. Generation and Detection of FSK.

3. Generation and Detection of PSK.

4. Generation and Detection of TDM.

5. Generation and Detection of PCM

VHDL Modeling and Synthesis of the Following Experiments

6. Logic Gates.

7. 4 bit Magnitude Comparator.

8. Multiplexers/Decoders.

9. JK, D & T Flip-Flops.

10. Synchronous Counters

1. GENERATION AND DETECTION OF AMPLITUDE SHIFT KEYING

AIM:

To generate and detect modulation and demodulation techniques by using ASK method.

EQUIPMENTS:

Kits for ASK modulation and demodulation.

Patch Chords.

Power supply.

20MHz Dual Trace Oscilloscope.

PROCEDURE:

1. Refer to the block diagram and carry out the following connections and switch settings.

2. Connect power supply in proper polarity to the kits DCL-05 and DCL- 06 and switch it on.

3. Connect CLOCK and DATA generated on DCL-05 to CODING CLOCK IN and DATA INPUT respectively by means of the patch-chords provided.

4. Connect the NRZ-L data input to the CONTROL INPUT of the CarrierModulator logic.

5. Connect carrier component SIN2 to INPUT1 and GROUND to INPUT2 of the Carrier Modulator Logic.

6. Connect ASK modulated signal MODULATOR OUTPUT on DCL-05 to the ASK IN of the ASK DEMODULATOR on DCL-06.

7. Observe various waveforms as mentioned below.

PRECAUTIONS:

1. Keep the switch faults in off position.

2. Avoid loose connections

BLOCKDIAGRAM OF ASK:

WAVE FORMS:

RESULT:

2. GENERATION AND DETECTION OF FREQUENCY SHIFT KEYING

AIM:

To generate and detect modulation and demodulation techniques by using FSK method.

EQUIPMENTS:

Kits for FSK modulation and demodulation.Patch Chords.Power supply.20MHz Dual Trace Oscilloscope.

PROCEDURE:


2. Connect power supply in proper polarity to the kits DCL-05 and DCL-06 and switch it on.



5. Connect carrier component SIN 1 to INPUT2 and SIN 2 to INPUT1 of the Carrier Modulator Logic.

6. Connect FSK modulated signal MODULATOR OUTPUT on DCL-05 to the FSK IN of the FSK DEMODULATOR on DCL-06.


PRECAUTIONS:



BLOCKDIAGRAM OF FSK:

WAVE FORMS:

RESULT:

3. GENERATION AND DETECTION OF PHASE SHIFT KEYING

AIM: To generate and detect modulation and demodulation techniques by using PSK method.

EQUIPMENTS:

Kits for PSK modulation and demodulation.Patch Chords.Power supply.20MHz Dual Trace Oscilloscope.

PROCEDURE:


2. Connect power supply in proper polarity to the kits DCL-05 and DCL-06 and switch it on.



5. Connect carrier component SIN 2 to INPUT1 and SIN 3 to INPUT2 of the Carrier Modulator Logic.

6. Connect PSK modulated signal MODULATOR OUTPUT on DCL-05 to the PSK IN of the PSK DEMODULATOR on DCL-06.


PRECAUTIONS:



BLOCK DIAGRAM OF PSK:

WAVE FORMS:

RESULT:

4. GENERATION AND DETECTION OF TIME DIVISION MULTIPLEXING

AIM:

To generate and detect time division multiplexing modulation and demodulation..

EQUIPMENTS:

Kits for TDM modulation and demodulation.

Patch Chords.

Power supply.


PROCEDURE:

1. Refer to the Block Diagram and Carry out the following connections

and switch settings.

2. Connect power supply in proper polarity to the kit DCL-02 & switch

it.

3. Connect 250Hz, 500Hz, 1KHz, and 2KHz sine wave signals from

the Function Generator to the multiplexer inputs channel CH0, CH1,

CH2, CH3 by means of the connecting chords provided.

4. Connect the multiplexer output TXD of the transmitter section to

the

demultiplexer input RXD of the receiver section.

5. Connect the output of the receiver section CH0, CH1, CH2, CH3 to

the IN0, IN1, IN2, IN3 of the filter section.

6. Connect the sampling clock TX CLK and Channel Identification Clock

TXSYNC of the transmitter section to the corresponding RX CLK and

RX

SYNC of the receiver section respectively.

7. Set the amplitude of the input sine wave as desired.

8. Take observations as mentioned below.

PRECAUTIONS:

7. Keep the switch faults in off position.8. Avoid loose connections.

BLOCK DIAGRAM OF TDM:

:WAVE FORMS:

RESULT:

5. GENERATION AND DETECTION OF PULSE CODE MODULATION (PCM)

AIM:

To generate and detect modulation and demodulation techniques by using PCM.

EQUIPMENTS:

Kits for PCM modulation and demodulation.

Patch Chords.

Power supply.


PROCEDURE:

1. Refer to the Block Diagram & Carry out the following connections.

2. Connect power supply in proper polarity to the kits and switch it on.

3. Connect sine wave of frequency 500Hz and 1KHz to the input CH0

and CH1 of the sample and hold logic.

4. Connect OUT 0 to CH0 IN & OUT 1 to CH1 IN.

5. Set the speed selection switch SW1 to FAST mode.

6. Select parity selection switch to NONE mode on both the Modulation

and demodulation kits.

7. Connect TXDATA, TXCLK and TXSYNC of the transmitter section to

the corresponding RXDATA, RXCLK, and RXSYNC of the receiver

section

8. Connect posts DAC OUT to IN post of demultiplexer section in

demodulator kit.

9. Ensure that FAULT SWITCH SF1 as shown in switch setting

diagram

introduces no fault.

10. Take the observations as mentioned below.

11. Repeat the above experiment with DC Signal at the inputs of the

Channel CH 0 and CH 1.

12. Connect ground points of both the kits with the help of connecting

chord provided during all the experiments.

BLOCK DIAGRAM:

WAVE FORMS :

RESULT:

6. DESIGN OF LOGIC GATES

Aim:

To design and simulate all basic logic gates.

Software required:

Active HDL 7.2 SE

Logic diagram:

GATE: TRUTH TABLE:

A B

NOT GATE

A B 0 11 0

EX-NOR GATE

A B C0 0 10 1 01 0 01 1 1

PROGRAM:

(i) AND GATE:

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity andd is port(

a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC

);end andd;

architecture andd of andd isbegin

c<= a and b;

end andd;

(ii) OR GATE:


entity orr is port(


);end orr;

architecture orr of orr isbegin

c<= a or b;

end orr;

(iii) EX - OR GATE:


entity exorr is port(


);end exorr;

architecture exorr of exorr isbegin

c<= a xor b;

end exorr;

(iv) NAND GATE:


entity nandd is port(


);end nandd;

architecture nandd of nandd isbegin

c<= a nand b;

end nandd;

(v) NOR GATE:


entity norr is port(


);end norr;

architecture norr of norr isbegin

c<= a nor b;

end norr;

(vi) EX - NOR GATE:


entity exnorr is port(


);end exnorr;

architecture exnorr of exnorr isbegin

c<= a xnor b;

end exnorr;

(vii) NOT GATE:


entity nott is port(

a: in STD_LOGIC; b :out STD_LOGIC );

end nott;

architecture nott of nott isbegin

b<= not a;

end nott;

Waveforms:

AND GATE WAVE FORM

OR GATE WAVE FORM

EXOR GATE WAVE FORM

NAND GATE WAVE FORM

NOR GATE WAVE FORM

EXNOR GATE WAVE FORM

NOT GATE WAVE FORM

Result:

7. 4 - BIT MAGNITUDE COMPARATOR

Aim:

To Design and Simulate 4 - Bit Magnitude Comparator.

Software required:

Active HDL 7.2 SE

Block diagram:

A [0:3] → → EQ B [0:3] → → GT

→ LT

4-BITCOMPARATOR

Program:


entity COMPARATOR is port(

A : in STD_LOGIC_VECTOR(0 to 3); B : in STD_LOGIC_VECTOR(0 to 3); EQ : out STD_LOGIC; GT : out STD_LOGIC; LT : out STD_LOGIC

);end COMPARATOR;

--}} End of automatically maintained section

architecture COMPARATOR of COMPARATOR isbegin

-- enter your statements here --PROCESS (A,B) BEGINIF A=B THEN EQ<= '1';GT<='0';LT<='0';ELSIF A<B THEN EQ<= '0';GT<='0';LT<='1';ELSIF A>B THEN EQ<= '0';GT<='1';LT<='0';

END IF;END PROCESS;

end COMPARATOR;

Waveforms:

Result:8. 8x1 MULTIPLEXER & 2 to 4 DECODER

Aim:

To design and simulate 8x1 MUX and 2 to 4 DECODER

Software required:

Active HDL 7.2 SE

Logic diagram: 8x1 MUX

Truth table:

Program:

library IEEE;use IEEE.std_logic_1164.all;

entity mux151 isport(D:in STD_LOGIC_VECTOR (7 downto 0); --8 i/p linesS :in STD_LOGIC_VECTOR (2 downto 0); --3 data select linesen_l:in STD_LOGIC;--active low enable i/py :out STD_LOGIC--output line);end mux151;

architecture mux151 of mux151 isbeginprocess(D,S ,en_l)beginif en_l='0' thencase s iswhen"000" => y <= D(0);when"001" => y <= D(1);when"010" => y <= D(2);when"011" => y <= D(3);when"100" => y <= D(4);when"101" => y <= D(5);when"110" => y <= D(6);

when"111" => y <= D(7);when others=>null;end case; end if;end process;end mux151;

2 to 4 DECODER:

Logic diagram:

Truth table:

Program:


entity decoder is port(

EN : in STD_LOGIC; I : in STD_LOGIC_VECTOR(1 downto 0); Y : out STD_LOGIC_VECTOR(3 downto 0)

);end decoder;

--}} End of automatically maintained section

architecture decoder of decoder isbegin

-- enter your statements here --process(EN,I)

beginif(EN='1') thenif(I = "00") theny <= "0001" ;elsif(I = "01") theny <= "0010" ;elsif(I = "10") theny <= "0100" ;elsey <= "1000" ;end if;elsey <= "1111";end if;end process;

end decoder;

Waveforms:

8x1 MULTIPLEXER WAVE FORM

DECODER WAVE FORM

Result:

9. D ,JK AND T- FLIPFLOPS

Aim:

To Design and Simulate D ,Jk And T- Flipflops..Software required:

Active HDL 7.2 SE

Block diagram: D FLIP-FLOP

Truth Table:

Program:


entity dff is port(

d : in STD_LOGIC; clk : in STD_LOGIC; Q : out STD_LOGIC

);end dff;

architecture dff of dff isbegin

-- enter your statements here --process(d, clk)

begin

-- clock rising edge

if (clk='1' and clk'event) then Q <= d;end if;

end process;

end dff;

JK FLIP-FLOP

Truth table:

Program:

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity JKFF is

port(

clk : in STD_LOGIC;

j : in STD_LOGIC;

k : in STD_LOGIC;

q : inout STD_LOGIC;

qn : inout STD_LOGIC

);

end JKFF;

architecture JKFF of JKFF is

begin

-- enter your statements here -- process(clk,j,k)

begin

if (clk='1' and clk'event) then

if(j='0' and k='0') then q<=q;qn<=qn ;

elsif(j='0' and k='1') then q<='0';qn<='1' ;

elsif(j='1' and k='0') then q<='1';qn<='0' ;

elsif(j='1' and k='1') then q<=not q;qn<=q ;

end if;

end if;

end process;

end JKFF;

T FLIP-FLOP:

Truth table:

Characteristic table Excitation table

T Q Qnext Comment Q Qnext T Comment

0 0 0 hold state (no clk) 0 0 0 No change

0 1 1 hold state (no clk) 1 1 0 No change

1 0 1 toggle 0 1 1 Complement

1 1 0 toggle 1 0 1 Complement

Program:

library IEEE;

http://en.wikipedia.org/wiki/Excitation_table

http://en.wikipedia.org/wiki/State_transition_table


entity tff is

port(

clk : in STD_LOGIC;

t : in STD_LOGIC;

q : inout STD_LOGIC

);

end tff;

architecture tff of tff is

begin

-- enter your statements here --

process(clk,t)

begin

q<='0';

if (clk='1' and clk'event) then

if(t='0') then q<=q ;

elsif(t='1') then q<=not q;

end if;

end if;

end process;

end tff;

Waveforms:

D FLIP-FLOP WAVE FORM

JK FLIP-FLOP WAVE FORM

T FLIP-FLOP WAVE FORM

Result:

10. 3-BIT SYNCHRONOUS UP/DOWN COUNTERAim:

To Design and Simulate Synchronous Up/Down Counter.

Software required:

Active HDL 7.2 SE

Logic diagram:

EXCITATION TABLE:

PRESENT STATE MODE NEXT STATE

QC QB QA UP/DOWN QC QB QA

0 0 0 0 1 1 1

0 0 0 1 0 0 1

0 0 1 0 0 0 0

0 0 1 1 0 1 0

0 1 0 0 0 0 1

0 1 0 1 0 1 1

0 1 1 0 0 1 0

0 1 1 1 1 0 0

1 0 0 0 0 1 1

1 0 0 1 1 0 1

1 0 1 0 1 0 0

1 0 1 1 1 1 0

1 1 0 0 1 0 1

1 1 0 1 1 1 1

1 1 1 0 1 1 0

1 1 0 1 0 0 0

PROGRAM:

library IEEE;


use ieee.std_logic_unsigned.all;

entity counter is

port(

clk : in STD_LOGIC;

reset : in STD_LOGIC;

up_down : in STD_LOGIC;

Q : out STD_LOGIC_VECTOR(0 to 2)

);

end counter;

architecture counter of counter is

--begin

-- enter your statements here --

signal count :std_logic_vector (0 to 2);

begin

process (clk, reset) begin

if (reset = '1') then

count <= (others=>'0');

elsif (clk='1' and clk'event) then

if (up_down = '1') then

count <= count + 1;

else

count <= count - 1;

end if;

end if;

end process;

Q <= count;

end counter;

Waveforms:

Result:

Documents

Ec 452 Dc & Vhdl Lab Manual Final