Ece471 Win11 Mar3 Memories

7/28/2019 Ece471 Win11 Mar3 Memories

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Digital Integrated Circuits2nd Memories

Digital Integrated

CircuitsA Design Perspective

Semiconductor

Memories

Jan M. Rabaey

Anantha ChandrakasanBorivoje Nikolic

December 20, 2002


2/85


Chapter Overview

Memory Classification

Memory Architectures

The Memory Core Periphery

Reliability

Case Studies


3/85


Semiconductor Memory Classification

Read-Write MemoryNon-Volatile

Read-Write

Memory

Read-Only Memory

EPROM

E2PROM

FLASH

Random

Access

Non-Random

Access

SRAM

DRAM

Mask-Programmed

Programmable (PROM)

FIFO

Shift Register

CAM

LIFO


4/85


Memory Architecture: Decoders

Word 0

Word 1

Word 2

WordN2 2

WordN2 1

Storagecell

Mbits Mbits

Nwords

S0

S1

S2

SN2 2

A0

A1

AK2 1

K5 log2N

SN2 1

Word 0

Word 1

Word 2

WordN2 2

WordN2 1

Storagecell

S0

Input-Output(Mbits)

Intuitive architecture for N x M memory

Too many select signals:

N words == N select signalsK = log

2N

Decoder reduces the number of select signals

Input-Output(Mbits)

Decoder


5/85


Block Diagram of 4 Mbit SRAM

Subglobal row decoderGlobal row decoderSubglobal row decoder

Block 30Block 31

128 K Array Bloc

Block 1

Clockgenerator

CS, WEbuffer

I/Obuffer

Y-addressbuffer

X-addressbuffer

x1/x4controller

Z-addressbuffer X-addressbuffer

Predecoder and block selector

Bit line load

Transfer gate

Column decoder

Sense amplifier and write driver Local row dec

[Hirose90]


6/85


Read-Only Memory Cells

WL

BL

WL

BL

1WL

BL

WL

BL

WL

BL

0

VDD

WL

BL

GND

Diode ROM MOS ROM 1 MOS ROM 2


7/85 Digital Integrated Circuits2nd Memories

MOS OR ROM

WL [0]

VDD

BL [0]

WL [1]

WL [2]

WL [3]

Vbias

BL [1]

Pull-down loads

BL [2] BL [3]

VDD



MOS NOR ROM

WL [0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

VDD

BL [1]

Pull-up devices

BL [2] BL [3]

GND



MOS NOR ROM Layout

Programmming using the

Active Layer Only

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

Cell (9.5l x 7l)



MOS NOR ROM Layout

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

Cell (11l x 7l)

Programmming using

the Contact Layer Only


11/85


MOS NAND ROM

All word lines high by default with exception of selected row

WL [0]

WL [1]

WL [2]

WL [3]

VDD

Pull-up devices

BL [3]BL [2]BL [1]BL [0]


12/85


MOS NAND ROM Layout

No contact to VDD or GND necessary;

Loss in performance compared to NOR ROM

drastically reduced cell size

Polysilicon

Diffusion

Metal1 on Diffusion

Cell (8l x 7l)

Programmming using

the Metal-1 Layer Only


13/85


NAND ROM Layout

Cell (5l x 6l)

Polysilicon

Threshold-altering

implant

Metal1 on Diffusion

Programmming using

Implants Only


14/85


Equivalent Transient Model for MOS NOR ROM

Word line parasitics Wire capacitance and gate capacitance

Wire resistance (polysilicon)

Bit line parasitics Resistance not dominant (metal)

Drain and Gate-Drain capacitance

Model for NORROMV

DD

Cbit

rword

cword

WL

BL


15/85


Equivalent Transient Model for MOS NAND ROM

Word line parasitics Similar to NOR ROM

Bit line parasitics Resistance of cascaded transistors dominates

Drain/Source and complete gate capacitance

Model for NAND ROMVDD

CL

rword

cword

cbit

rbit

WL

BL


16/85


Decreasing Word Line Delay

Metal bypass

Polysilicon word lineKcells

Polysilicon word lineWL

Driver

(b) Using a metal bypass

(a) Driving the word line from both sides

Metal word line

WL

(c) Use silicides


17/85


Precharged MOS NOR ROM

PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.

WL [0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

VDD

BL [1]

Precharge devices

BL [2] BL [3]

GND

pref


18/85


Non-Volatile Memories

The Floating-gate transistor (FAMOS)

Floating gate

Source

Substrate

Gate

Drain

n+ n+_p

tox

tox

Device cross-section Schematic symbol

G

S

D


19/85


Floating-Gate Transistor Programming

0 V

25 V 0 V

DS

Removing programming

voltage leaves charge trapped

5 V

22.5 V 5 V

DS

Programming results inhigher VT.

20 V

10 V 5 V 20 V

DS

Avalanche injection


20/85


FLOTOX EEPROM

Floating gate

Source

Substratep

Gate

Drain

n1 n1

FLOTOX transistor Fowler-NordheimI-Vcharacteristic

2030 nm

10 nm

-10 V

10 V

I

VGD


21/85


EEPROM Cell

WL

BL

VDD

Absolute threshold controlis hard

Unprogrammed transistor

might be depletion

2 transistor cell


22/85


Flash EEPROM

Control gate

erasure

p-substrate

Floating gate

Thin tunneling oxide

n1 source n1 drainprogramming

Many other options


23/85


Cross-sections of NVM cells

EPROMFlash

Courtesy Intel


24/85


NAND Flash Memory

Word linesSelect transistor

Bit line contact Source line contact

Active area

STI

Courtesy Toshiba


25/85


Characteristics of State-of-the-art NVM


26/85


Read-Write Memories (RAM)

STATIC (SRAM)

DYNAMIC (DRAM)

Data stored as long as supply is applied

Large (6 transistors/cell)

Fast

Differential

Periodic refresh required

Small (1-3 transistors/cell)

Slower

Single Ended


27/85


6-transistor CMOS SRAM Cell

WL

BL

VDD

M5M6

M4

M1

M2

M3

BL

QQ


28/85


CMOS SRAM Analysis (Read)WL

BL

VDD

M5

M6

M4

M1V

DDVDD VDD

BL

Q=1Q=0

Cbit Cbit


29/85


CMOS SRAM Analysis (Read)

00

0.2

0.4

0.6

0.8

1

1.2

0.5

Voltage rise [V]

11.21.5 2

Cell Ratio (CR)

2.5 3

Vo

ltage

Ris

e(V)


30/85


CMOS SRAM Analysis (Write)

BL=1 BL=0

Q=0

Q=1

M1

M4

M5

M6

VDD

VDD

WL


31/85


CMOS SRAM Analysis (Write)


32/85


6T-SRAM Layout

VDD

GND

QQ

WL

BLBL

M1 M3

M4M2

M5 M6


33/85


Resistance-load SRAM Cell

Static power dissipation -- Want RLlargeBit lines precharged to VDDto address tpproblem

M3

RL RL

VDD

WL

Q Q

M1 M2

M4

BL BL


34/85


SRAM Characteristics


35/85


3-Transistor DRAM Cell

No constraints on device ratios

Reads are non-destructive

Value stored at node X when writing a 1 = VWWL-VTn

WWL

BL 1

M1 X

M3

M2

CS

BL 2

RWL

VDD

VDD2VT

DVVDD2VTBL2

BL1

X

RWL

WWL


36/85


3T-DRAM Layout

BL2 BL1 GND

RWL

WWL

M3

M2

M1


37/85


Sense Amp Operation

DV(1)

V(1)

V(0)

t

VPRE

VBL

Sense amp activatedWord line activated


38/85


1-T DRAM Cell

Uses Polysilicon-Diffusion Capacitance

Expensive in Area

M1wordline

Diffusedbit line

Polysilicongate

Polysiliconplate

Capacitor

Cross-section Layout

Metal word line

Poly

SiO2

Field Oxiden+ n+

Inversion layerinduced byplate bias

Poly


39/85


SEM of poly-diffusion capacitor 1T-DRAM


40/85


Advanced 1T DRAM Cells

Cell Plate Si

Capacitor Insulator

Storage Node Poly

2nd Field Oxide

Refilling Poly

Si Substrate

Trench Cell Stacked-capacitor Cell

Capacitor dielectric layerCell plate

Word line

Insulating Layer

IsolationTransfer gateStorage electrode


41/85


Static CAM Memory Cell

CAM

Bit

Word

Bit

CAM

Bit Bit

CAM

Word

Wired-NOR Match Line

MatchM1

M2

M7M6

M4 M5M8 M9

M3

intSWord

CAM

Bit Bit

S


42/85


CAM in Cache Memory

Address Decoder

Hit Logic

CAM

ARRAY

Input Drivers

Tag HitAddress

SRAM

ARRAY

Sense Amps / Input Drivers

DataR/W


43/85


Periphery

Decoders Sense Amplifiers

Input/Output Buffers Control / Timing Circuitry


44/85


Row Decoders

Collection of 2M

complex logic gatesOrganized in regular and dense fashion

(N)AND Decoder

NOR Decoder

Hi hi l D d


45/85


Hierarchical Decoders

A2A2

A2A3

WL0

A2A3A2A3A2A3

A3 A3A0A0

A0A1A0A1A0A1A0A1

A1 A1

WL1

Mult i-stage implementat ion improves performance

NAND decoder using

2-input pre-decoders


46/85


Dynamic Decoders

Precharge devices

VDDf

GND

WL 3

WL 2

WL 1

WL 0

A 0A 0

GND

A 1A 1 f

WL 3

A 0A 0 A1A 1

WL 2

WL 1

WL 0

VDD

VDD

VDD

VDD

2-input NOR decoder 2-input NAND decoder

4 i t t i t b d l


47/85


4-input pass-transistor based column

decoder

Advantages: speed (tpddoes not add to overall memory access time)

Only one extra transistor in signal path

Disadvantage: Large transistor count

2-input NOR decoder

A 0S0

BL 0 BL 1 BL 2 BL 3

A 1

S1

S2

S3

D


48/85


4-to-1 tree based column decoder

Number of devices drastically reducedDelay increases quadratically with # of sections; prohibitive for large decoders

buffersprogressive sizingcombination of tree and pass transistor approaches

Solutions:

BL0 BL1 BL2 BL3

D

A0

A0

A1

A1


49/85


Decoder for circular shift-register

VDD

VDD

R

WL0

VDD

f

ff

f

VDD

R

WL1

VDD

f

ff

f

VDD

R

WL2

VDD

f

ff

f


50/85


Sense Amplifiers

tp

C DV

Iav

----------------=make

DV as small

as possible

smalllarge

Idea: Use Sense Amplifer

outputinput

s.a.smalltransition


51/85


Differential Sense Amplifier

Directly applicable to

SRAMs

M4

M1

M5

M3

M2

VDD

bitbit

SE

Outy

Latch Based Sense Amplifier (DRAM)


52/85


Latch-Based Sense Amplifier (DRAM)

Initialized in its meta-stable point with EQ

Once adequate voltage gap created, sense amp enabled with SEPositive feedback quickly forces output to a stable operating point.

EQ

VDD

BL BL

SE

SE

Charge Redistribution Amplifier


53/85


Charge-Redistribution Amplifier

EPROM

SE

VDD

WLC

Load

Cascodedevice

Columndecoder

EPROMarray

BL

WL

Vcasc

Out

Cout

Ccol

CBLM1

M2

M3

M4

Open bitline architecture with


54/85


Open bitline architecture with

dummy cells

CS CS CS CS

BLL

L L1 L0 R0

CS

R1

CS

L

BLR

VDD

SE

SE

EQ

Dummy cell Dummy cell

DRAM Read Process with Dummy Cell


55/85


DRAM Read Process with Dummy Cell3

2

1

00 1 2 3

VBL

BL

t (ns)

reading 0

3

2

1

00 1 2 3

VSE

EQ WL

t (ns)

control signals

3

2

1

00 1 2 3

VBL

BL

t (ns)

reading 1


56/85


Voltage Regulator

-

+

VDD

VREF

Vbias

Mdrive

Mdrive

VDL

VDL

VREF

Equivalent Model


57/85


DRAM Timing


58/85


RDRAM Architecture

memory

array

mux/demuxnetwork

Data

bus

Clocks

Column

Rowdemux packet dec.

packet dec.

Bus

kk3l

demux


59/85


Address Transition DetectionDELAY

tdA0

DELAYtdA1

DELAYtdAN21

VDD

ATD ATD


60/85


Reliability and Yield

S i P i DRAM


61/85


Sensing Parameters in DRAM

From [Itoh01]

4K

10

100

1000

64K 1M 16M256M 4G 64G

Memory Capacity (bits /chip)

C

D,QS,CS,VDD,Vsmax

CD(1F)

CS(1F)

QS(1C)

Vsmax(mv)

VDD(V)

QS5 CSVDD/2

Vsmax5 QS/(CS1 CD)

N i S i 1T DR


62/85


Noise Sources in 1T DRam

Ccross

electrode

a-particles

leakageCS

WL

BL substrateAdjacent BL

CWBL


63/85


Open Bit-line Architecture Cross Coupling

SenseAmplifierC

WL1

BL

CBL

CWBL

CWBL

CC

WL0

C

CBLC C

WLD WLD WL0 WL1

BL

EQ


64/85


Alpha-particles (or Neutrons)

1 Part ic le ~ 1 Mil l ion Carriers

WL

BL

VDD

n1

a-particle

SiO21

1

11

11 2

2

22

2

2

Yi ld


65/85


Yield

Yield curves at different stages of process maturity

(from [Veendrick92])

R d d


66/85


Redundancy

MemoryArray

Column Decoder

Row Decoder

Redundantrows

Redundantcolumns

RowAddress

ColumnAddress

FuseBank

:

E C ti C d


67/85


Error-Correcting Codes

Example: Hamming Codes

with

e.g. B3 Wrong

1

1

0

= 3

R d d d E C ti


68/85


Redundancy and Error Correction

Sources of Power Dissipation in


69/85


Sources of Power Dissipation in

Memories

PERIPHERY

ROW

DEC

selected

non-selected

CHIP

COLUMN DEC

nCDEVINTf

mCDEVINTf

CPTVINTf

IDCP

ARRAY

m

n

m(n21)ihld

miact

VDD

VSS

IDD5 SCiDVif1S IDCP

From [Itoh00]

Data Retention in SRAM


70/85


Data Retention in SRAM

(A)

1.30u

1.10u

900n

700n

500n

300n

100n

0.00 .600 1.20 1.80

Factor 7

0.13 m CMOSm

0.18 m CMOSm

VDD

Ileakage

SRAM leakage inc reases w ith techno logy scaling

S i L k i SRAM


71/85


Suppressing Leakage in SRAM

SRAMcell

SRAMcell

SRAMcell

VDD,int

VDD

VDD VDDL

VSS,int

sleep

sleep

SRAMcell

SRAMcell

SRAMcell

VDD,int

sleep

low-threshold transistor

Reducing the supply vo l tageInsert ing Extra Resis tance


72/85


Case Studies

Programmable Logic Array

SRAM

Flash Memory

PLA ers s ROM


73/85


PLA versus ROM Programmable Logic Array

structured approach to random logictwo level logic implementation

NOR-NOR (product of sums)NAND-NAND (sum of products)

IDENTICAL TO ROM!

Main differenceROM: fully populatedPLA: one element per minterm

Note: Importance of PLAs has drastically reduced1.slow2.better software techniques (mutli-level logic

synthesis)But

Programmable Logic Array


74/85


Programmable Logic ArrayGND GND GND GND

GND

GND

GND

VDD

VDD

X0X0 X1 f0 f1X1 X2X2

AND-plane OR-plane

Pseudo-NMOS PLA

Dynamic PLA


75/85


Dynamic PLAGND

GNDVDD

VDD

X0X0 X1 f0 f1X1 X2X2

ANDf

ANDf

ORf

ORf

AND-plane OR-plane

Clock Signal Generation


76/85


Clock Signal Generation

for self-timed dynamic PLAf

tpre teval

fAND

f

fAND

fAND

fOR

fOR

(a) Clock signals (b) Timing generation circuitry

Dummy AND row

Dummy AND row

PLA Layout


77/85


PLA LayoutVDD

GNDfAnd-Plane Or-Plane

f0

f1

x0x0x1x1x2x2

Pull-up devices Pull-up devices

Bit line Circuitry


78/85


Bit-line Circuitry

Bit-lineload

Blockselect ATD

BEQ

LocalWL

Memory cell

I/O lineI/O

B/T

CD

Sense amplifier

CD CD

I/O

B/T

Sense Amplifier (and Waveforms)


79/85


Sense Amplifier (and Waveforms)

BS

I/O I/O

DATA

Blockselect ATD

BSSA SA

BS

SEQ

SEQ

SEQ

SEQSEQ

Dei

I/O Lines

Address

Data-cut

ATD

BEQ

SEQ

DATA

Vdd

GND

SA, SA

Vdd

GND

125mm21Gbit NAND Flash Memory


80/85


125mm 1Gbit NAND Flash Memory

10

.7m

m

11.7mm

2kBPage

buf

fer

&cac

he

Charge

pump

16896 bit lines

32 word lines

x 1024 blocks

From [Nakamura02]


81/85


125mm21Gbit NAND Flash Memory

Technology 0.13m p-sub CMOS triple-well1poly, 1polycide, 1W, 2Al

Cell size 0.077m2 Chip size 125.2mm2

Organization 2112 x 8b x 64 page x 1k block Power supply 2.7V-3.6V

Cycle time 50ns

Read time 25s

Program time 200s / page Erase time 2ms / block

From [Nakamura02]

Semiconductor Memory Trends


82/85


(up to the 90s)

Memory Size as a function of time: x 4 every three years



83/85


(updated)

From [Itoh01]

Trends in Memory Cell Area


84/85


Trends in Memory Cell Area

From [Itoh01]



85/85


Technology feature size for different SRAM generations

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Ece471 Win11 Mar3 Memories