Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-Based wafer bonding process

0885–3010/$25.00 © 2009 IEEE

1074 IEEE TransacTIons on UlTrasonIcs, FErroElEcTrIcs, and FrEqUEncy conTrol, vol. 56, no. 5, May 2009

Abstract—We report the fabrication and experimental test-ing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It al-lows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 µm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of ~9 MHz in immersion with a −6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characteriza-tion results.

I. Introduction

In the medical field, ultrasound imaging is a mature tech-nology and is a commonly used diagnostic tool due to

its relative low cost [when compared with other imaging technologies such as magnetic resonance imaging (MrI)], lack of ionizing radiation (X-rays) and potential portabil-ity [1]. The dominant transducer technology for the gen-eration of diagnostic ultrasound is piezoelectric crystals.

Piezoelectric crystals experience a strain when an elec-tric potential is applied across them. applying a voltage pulse to a crystal will cause it to expand and contract yielding a pressure wave into the surrounding medium. conversely, an incoming pressure wave will cause strains in the crystal that are converted back into a voltage across the crystal, which can in turn be amplified and measured [2]. Using these properties, piezoelectric crystals form the basis of diagnostic ultrasound transducers.

There are, however, some drawbacks associated with piezoelectric transducers. Piezoelectric materials only

generate sufficient ultrasound power when operating at or near the resonant frequency. The resonant frequency is governed principally by the thickness of the piezo layer, thereby limiting a given element to operation around a single frequency [3]. Given the nature of piezoelectric fab-rication, there can be difficulty in obtaining a reasonably even response across array elements because a relatively small variation in the layer thickness or kerf width can af-fect the performance noticeably [3]. arrays are necessary to generate a multidimensional image without the need for mechanical scanning.

The bandwidth of the piezoelectric transducers tends to be fairly narrow at 70 to 80% [4], reducing depth reso-lution and limiting their suitability for advanced imaging techniques, such as harmonic imaging [5].

The acoustic impedance of the piezoelectric crystals tends to be much higher than that of the fluids it may be used in. The acoustic mismatch in air is quite large. a typical piezoelectric transducer may have an acoustic impedance of ~30 Mrayl while that of air is ~400 rayl [6], [7]. This implies that the sound will be coupled very inefficiently into the air. The situation with water is not quite as bad; the impedance of water is 1.5 Mrayl [7]. In this case, coupling layers are still required, and finding appropriate matching layer materials can still be trouble-some [8].

Ultrasonic transducers based on electrostatic forces have been subject to increasing interest since the mid 1990s as microfabrication technology has matured [9]–[12]. Termed capacitive micromachined ultrasonic transducers or cMUTs, the basic unit (or cell) consists of a membrane suspended over a shallow cavity with a fixed electrode at the bottom and a patterned electrode on top of the mem-brane. In transmit mode, one of the electrodes is electri-cally grounded and the other is biased with a deflecting dc voltage and subjected to a short voltage pulse causing a further deflection of the membrane toward the other electrode. The membrane vibrates with the release of the electrostatic force and some of the energy is coupled into the surrounding media as pressure waves. In receive mode, the membrane is dc biased and the incoming pressure waves cause the membrane to vibrate and change the ca-pacitance of the cell, which in turn induces a measurable current. a typical transducer element is made of many individual cells that are activated in parallel. The general design of a cMUT cell is shown in Fig. 1.

cMUTs have several advantages when compared with piezoelectric transducers; one of the biggest advantages

Fabricating Capacitive Micromachined Ultrasonic Transducers with a Novel Silicon-

Nitride-Based Wafer Bonding Processandrew logan, Student Member, IEEE and John T. W. yeow, Senior Member, IEEE

Manuscript received september 5, 2008; accepted January 18, 2009. This work is supported by the natural sciences and Engineering re-search council of canada, the canadian Institutes of Health research, and the University of Waterloo.

The authors are with the advanced Micro- /nano-devices laboratory at the University of Waterloo, Waterloo, on, canada (email: [email protected], [email protected]).

digital object Identifier 10.1109/TUFFc.2009.1141

is how they are manufactured, specifically with respect to the fabrication of high-frequency arrays. To make an array using piezoelectric crystals, each individual element is diced either mechanically or by using a focused laser to isolate it electrically from its neighbor, and the cut is filled with an insulating material [13]–[15]. To do a fully elec-tronic sector scan (as opposed to mechanically moving the transducer) with no grating lobes, the element pitch of the array needs to be less than or equal to half the wavelength of sound [16]. When using a transducer at 40 MHz, the element pitch needs to be less than 19 μm when one as-sumes a speed of sound of 1500 m/s. Making cuts narrow enough for a not-significant reduction in the active area of the element is quite challenging [3]. cMUTs, being fabri-cated using standard semiconductor techniques and tools, are not limited by the dimensions of the elements in the same way as the piezoelectric devices. defining array ele-ments photolithographically permits high-quality uniform arrays with minimal area lost to spacing.

cMUT arrays also typically have large bandwidths in immersion, commonly greater than 100%. This occurs be-cause the membrane is strongly damped due to the fluid loading on the surface. This leads to shorter acoustic puls-es and hence improves depth resolution. Their acoustic impedance is also lower and hence can be used in air more efficiently.

over the past 10 years, much work has been done with cMUTs in terms of fabrication methods, element design, and device implementation. The fabrication process has moved from a purely surface micromachining process that involves sacrificial release [8], [17]–[20] to include a fusion-bonding method that reduces design restrictions, simplifies fabrication, and permits easy vacuum sealing of the cells while also increasing the active area of the device [21], [22]. In a fabrication process somewhat similar to the one presented here, Midtbø et al. demonstrated a fusion-bonding process where a thin silicon nitride layer (100 nm) is bonded to silicon to create a cMUT cell [23]. In that case, the membrane appears to be thin enough to not require a polishing step, and no insulation layer is used above the bottom electrode.

II. Motivation

Wafer-bonded cMUT fabrication using a user-grown insulating membrane has several advantages over the pre-viously reported method using silicon-on-insulator (soI) wafers to supply the membrane.

A. Avoiding SOI Wafers

soI wafers in general are relatively easy to acquire from silicon wafer suppliers, although their cost is typi-cally more than 10 times that of standard wafers and can be difficult to acquire in a timely manner with the desired device layer thickness and conductivity. This is especial-ly true in research where relatively infrequent and small

quantities form the basis of typical orders. Employing a user-deposited membrane largely eliminates this problem with only a marginal increase in fabrication time and cost and a minor penalty in thickness uniformity.

B. Insulating Membrane

It has been shown that an ideal layout of the top elec-trode minimizes the parasitic capacitance and maximizes the transduction efficiency [24]. Transduction efficiency improves when the dc displacement of the membrane is maximized. Increasing the electrode coverage of the mem-brane increases the capacitance of the cell and thus re-sults in a greater displacement for the same bias voltage. However, increasing the electrode coverage beyond 50% yields diminishing returns as the increase in transduction efficiency becomes minimal. This is primarily because the edges of the membrane are fixed and the outer edge of the membrane cannot deflect to as great an extent as the center of the membrane. The extra capacitance however does reduce the bandwidth of the transducer due to an increase in the time constant of the electrical component of the circuit.

a semiconducting membrane behaves somewhere be-tween a conducting and insulating membrane. one can imagine a simple model of this situation with a resistor in parallel with a capacitor. at low frequencies, the reac-tance of the silicon is larger than the resistance, and the membrane behaves as a conductor. at a high frequency, the opposite occurs: the reactance diminishes and the membrane behaves as an insulator [25]. What is consid-ered a high and low frequency depends on the dimensions of the membrane as well as its conductivity. This in and of itself can cause some design problems because the opera-tion of the cell will be quite sensitive to the conductivity of the membrane. When the membrane behaves as a con-ductor, one can no longer optimize the electrode coverage to achieve good efficiency and low parasitic capacitance. If the entire membrane behaves as a conductor, then the whole device would be a capacitor, and patterning the top electrode will have little effect.

an insulating membrane does not suffer these issues, and its electrical behavior is well understood and is con-sistent with frequency. The dielectric constant of silicon nitride ensures that the capacitance of the gap will still be the dominant capacitance of the cell.

1075logan and yeow: fabricating cMUTs with a novel silicon-nitride-based wafer bonding process

Fig. 1. Basic schematic of a cMUT cell.

C. Reduction of Charge Buildup in the Insulating Layer

Trapping of electric charges in the dielectric insulating layer can lead to a degradation of performance in cMUT type devices over time [26], [27]. It has been shown in the soI wafer-bonding technique that these charging ef-fects can lead to a dramatic change in the dc operating point of the device [28]. In more extreme cases, the mem-branes do not return from their collapsed position after the bias voltage has returned to zero [28] (collapse occurs when the electrostatic force from the dc bias exceeds the mechanical restoring force of the membrane, causing the membrane to snap-down to the bottom of the cell cavity). little has been published on the effects of charging in surface-micromachined cMUTs, whereas in many articles on soI wafer-bonded devices, the effects of charging are mentioned as a problem in need of a solution [21], [25], [28], [29]. It therefore seems reasonable to assume that dielectric charging occurs more readily in silicon dioxide than in silicon nitride. This assumption is validated in ex-periments presented in section IV where charging effects in silicon nitride over extended periods of time are shown to be minimal.

Using silicon nitride as the material for both the mem-brane and the insulation layer reduces the problems as-sociated with charging. This eliminates the need for an extra few steps that have been shown to mitigate this problem, i.e., fabricating posts into the cavity to prevent short-circuiting of the 2 electrodes instead of a uniform dielectric layer [28], [29]. another potential benefit is a reduction in the required operating voltage. Because the insulating material (sio2 or sixny) has a higher dielectric constant than the vacuum, the effective distance between the electrodes is increased when posts are used instead of a uniformly thick layer. This in turn requires a higher dc bias voltage to achieve the same displacement.

III. Fabrication Process

The fabrication process of these wafer-bonded devices is similar to that used in the soI wafer-bonding process reported by Huang et al. [21]. only 3 masks are needed to achieve the final device. Fabrication was done at the cor-nell nanofabrication Facility (cnF) at cornell University in Ithaca, new york. a ⟨100⟩ 100-mm silicon wafer is used for both the membrane and the bottom electrode/cavity. The bottom wafer is lightly p-doped with boron and has a resistivity of 1 to 5 Ω-cm. The electrical properties of the membrane wafer are not important because it serves only as a mechanical platform for the membrane.

Because the bottom wafer has only moderate conduc-tivity, a layer of lPcVd p+ polysilicon 750 nm thick is deposited at 600°c (the dopant is boron) to reduce the series resistance of the bottom electrode, Fig. 2(a). The bulk of the wafer and the polysilicon layer will be used as the bottom electrode in the transducer. In future work, a highly conductive silicon wafer will be used that will obvi-

ate the need for the polysilicon layer. The bottom wafer is then annealed at 1000°c for 1 h, which increases the polysilicon grain sizes and increases the conductivity. The resistivity of the annealed polysilicon is measured to be ~9 mΩ-cm using a 4-point resistance mapper. The sheet resistance of the annealed polysilicon on top of the silicon wafer is measured to be ~30 Ω/sq.

The resulting increase in grain size that comes from the annealing process makes the polysilicon very rough with peaks of 50 to 100 nm being common. For that rea-son, a short chemical mechanical polishing (cMP) step is used to smooth the surface again, Fig. 2(b). The wafer is polished for about 30 s using a slurry of silicon dioxide particles suspended in a very dilute KoH solution. about 50 nm of material is removed in the polishing step. The rMs roughness before polishing is ~18 nm, and after it is ~2 nm. atomic force microscopy (aFM) scans of pre- and postpolished polysilicon are given in Fig. 3.

next, low-stress lPcVd silicon nitride is deposited on top of the polysilicon as a spacer and insulation. at the same time, nitride is deposited on the top wafer for what will be the membrane, Fig. 2(c). The low-stress nitride is deposited at 800°c. The residual tensile stress of the low-stress nitride deposited from the lPcVd system has previously been characterized by cnF technicians as ap-proximately 200 MPa.

although lPcVd nitride is not nearly as rough as the annealed polysilicon, it must still be polished because fu-sion bonding is very sensitive to roughness and, to achieve a good quality bond, as smooth a surface as possible is necessary [30], [31]. Both the top and bottom wafers are polished for about 50 s using the same silicon dioxide particle slurry, Fig. 2(d). about 30 nm of material is re-moved, and the rMs roughness of the membrane wafer is improved from 14 Å to 4 Å. The surface of the bottom wafer is slightly worse at ~8 Å after polishing. a surface plot of an aFM scan of the pre- and post-polished mem-brane wafer is given in Fig. 4.

care must be taken immediately after the polishing step. The postpolished wafers must be rigorously washed and scrubbed to remove the silicon dioxide particles re-maining on the surface from the cMP slurry. These par-ticles can prevent bonding in their local area. If too many remain on the surface before bonding, the yield will suf-fer.

The maximum rMs roughness typically cited as being required for decent quality spontaneous fusion bonding is 5 Å [31]–[33]. The surface roughness of the nitride on poly-silicon is somewhat greater than this apparent maximum value. a discussion of the bonding yield and potential ex-planations of the results are given in section V.

Following the polishing step, the cell cavities are etched into the bottom wafer nitride layer using a cF4 reactive ion etch (rIE) process after a photolithography step us-ing Mask I. The etch depth is about 160 nm. The step is illustrated in the left-hand diagram of Fig. 2(e).

after the rIE etch, both the top and bottom wafers are cleaned in both an rca 1 and rca 2 bath, a low-


power oxygen plasma descum followed by another rca 1 clean. The 2 wafers are then fusion-bonded at 300°c in a chamber at a pressure of 0.7 μbar. a compressive force of 3500 n is applied for 10 min, Fig. 2(f). The low pressure is required so that each of the cells is effectively a vacuum. This reduces the squeeze film dampening from within the cell. Following the bonding step, the wafers are annealed at 900°c for 4 h.

The silicon nitride on the back side of the bonded mem-brane wafer is removed via a cF4 rIE process. With the nitride layer removed, the silicon of the handle wafer is exposed and is removed by a 25% KoH etch at 95°c. The etch takes about 5 h to remove the 500 μm wafer com-pletely. The bonded wafer with the handle wafer removed is shown in Fig. 2(g).

next, a photolithography step is done using Mask II to pattern the ground electrodes. a cF4 rIE etch is per-formed to etch through the nitride membrane and spacer layers to expose the ground electrode for metallization, shown in Fig. 2(h). Finally, the top electrodes and contact pads are patterned using Mask III and a lift-off process. Titanium and aluminum are evaporated using an e-beam. about 30 nm of titanium are used as an adhesion layer and about 100 nm of aluminum are deposited on top. an illustration of the completed 1-d array is given in Fig. 2(i).

The device design was chosen to be relatively conserva-tive (in terms of membrane thickness, cell diameter, and fill factor) to ensure successful fabrication while obtaining operating parameters that would prove insightful to fu-ture generations of devices that will eventually be used for endoscope- or catheter-based in vivo imaging. Based on simulations done in coventorWare (coventor, Inc., cary, nc) as well as work previously reported in the literature, dimensions were chosen to yield a resonant frequency at ~17 MHz in air and ~5 to 10 MHz in immersion. a table of the device properties is given in Table I. scanning elec-tron microscopy (sEM) images of a completed device are given in Fig. 5.

IV. characterization

A. Electrical Characterization

The resonant frequency of the device in air is deter-mined by measuring the impedance of an element as a function of frequency. at resonance there is a sharp peak in the real component of the impedance as energy is ef-ficiently dissipated. The measurements are made using a probe station and an agilent 8714Es Vector network analyzer (Vna) (agilent Technologies, Inc., santa clara, ca). To measure the resonant frequency at different dc biases, an Inmet 8800sMF1–06 bias-T (aeroflex/Inmet, ann arbor, MI) is used to add the dc component to the rF supplied by the Vna. a schematic of the electrical layout is given in Fig. 6. The resonant frequency with no bias voltage is 17.5 MHz. The collapse voltage can be


Fig. 2. summary of the fabrication process of a 1-d cMUT array. (a) deposit p+ lPcVd polysilicon and anneal at 1000°c. (b) smooth the surface with a short cMP step. (c) deposit low-stress lPcVd silicon ni-tride on both wafers. (d) Perform a short polish of the sin layer on both wafers. (e) define cell cavities with an rIE step. (f) Fusion-bond the top and bottom wafers. (g) release the membrane in a KoH etch. (h) Expose the ground electrode with an rIE. (i) Pattern the top electrodes and contact pads using lift-off of evaporated metals.

determined by an abrupt change in the impedance charac-teristics as the bias voltage is swept. For the devices tested here, the collapse voltage is approximately 55 V. at a bias voltage of 50 V, the resonant frequency is 15.8 MHz. a plot of the real part of the impedance at several differ-ent bias voltages is shown in Fig. 7. The effect of spring softening can be observed as the bias voltage increases, i.e., the resonant peak shifts to lower frequencies. The nonflat baseline impedance is due to rF noise pollution of the baseline signal (because the system setup is not fully shielded) and not related to cMUT membrane motion. a plot of the imaginary impedance at a 50 V bias is shown in Fig. 8.

B. Acoustic Characterization

In immersion, the peak center frequency and band-width of a single element is determined by measuring the acoustic signal using a commercial hydrophone (onda

HGl-0200 and onda aH-2010 20 dB preamplifier, onda corporation, sunnyvale, ca) at a given distance from the cMUT element. The signal is recorded with a high-speed oscilloscope. The fluid used is vegetable oil because an insulating fluid is needed to prevent electrical shorting of the exposed leads. The acoustic impedance and absorp-


Fig. 3. aFM scans of the polysilicon layer pre- (left) and post- (right) chemical mechanical polishing. The rMs roughness before polishing is 18 nm and after is 2 nm.

Fig. 4. aFM scan of the pre- (left) and post- (right) polished silicon nitride layer. The rMs roughness before polishing is 1.4 nm and afterwards it is 0.4 nm.

TaBlE I. Physical Properties of the First-Generation devices.

Property

Membrane diameter 22 μmMembrane thickness 400 nmElectrode diameter 11 μmcavity depth 140 nmInsulation thickness 260 nmElement length 8000 μmElement width 330 μm# of elements 23# of cells per element 4140

tion of oil are also reasonably similar to that of tissue [17]. In the future, an insulating coating will be applied to the array. an applied −40 V dc bias is added to a short negative voltage pulse from a commercial pulser/receiver (Panametrics 5073, Panametrics, Inc., Waltham, Ma). The distance between cMUT and hydrophone is estimated by measuring the time between the voltage pulse and the measuring of the acoustic signal with the hydrophone. a speed of sound of 1430 m/s is assumed [7]. correcting for oil absorption, diffraction, and the hydro-phone frequency response gives a better indication of the transducer characteristics. The vegetable oil used in these experiments is an unknown mixture of canola and soybean oils. chanamai and Mcclements have characterized the absorption coefficients of many edible oils including canola and soybean [34]. The coefficients of these oils are similar enough that it is not necessary to know the proportion of canola and soybean in the vegetable oil to correct for the absorption. compensating for diffraction losses is done using the equations developed by Kino for a rectangular transducer [6]. The hydrophone and preamplifier frequen-cy response are taken into account using characterization data provided by the manufacturer.

The pitch-catch experiment is performed with the hy-drophone at a distance of 8 mm. The uncompensated cen-ter frequency is 9.3 MHz and the −3 dB bandwidth is 8.6 MHz, which translates to a relative bandwidth of 92%. after compensating for the absorption of the oil, diffrac-tion, and the response of the hydrophone, the center fre-quency is 9.2 MHz and the −3 dB bandwidth is 10.5 MHz

for a relative bandwidth of 114%. The center frequency is defined as midway between the two −3 dB points. Plots of the time and frequency domain signal from a single-array element are shown in Fig. 9 and Fig. 10.

The devices are also tested in a pulse-echo configura-tion. In this experiment, one element of the array is used to generate the ultrasound pulse while another is used to receive the signal reflected from a steel block placed at a given distance. The transmit-and-receive elements are separated by about 1 mm on the surface of the transducer array. Using different elements to transmit and receive is done to simplify the electronics required for this experi-ment. In future work, a more sophisticated circuit will be employed to permit transmission and reception from the same element. a Texas Instruments operational amplifier (oPa 657, Texas Instruments, dallas, TX) is wired in a transimpedance configuration with a gain of 4 kΩ to amplify and convert the small current generated by the receiving element to a voltage. The signal is recorded with an oscilloscope. a schematic of the transmission/receiving circuit is illustrated in Fig. 11. The inductor and resis-tor protect the amplifier from the voltage spike from the


Fig. 5. sEM images of the 23 × 1 cMUT array.

Fig. 6. Electrical schematic of circuit used to characterize the cMUT array.

Fig. 7. real component of the impedance of a single element of the 23 × 1 array at different bias voltages.

pulser. The capacitors block the dc signal from the pulser and the amplifier.

as with the transmission measurements, the frequency response of the transducer is corrected for oil absorption and diffraction. Time and frequency domain plots of the signal reflected from a steel block ~12 mm away are given in Fig. 12 and Fig. 13. Before compensating for diffraction and oil absorption losses, the −6 dB center frequency is 8 MHz with a bandwidth of 9.6 MHz for a relative band-width of 120%. after compensation, the center frequency is 9 MHz with a bandwidth of 11.1 MHz for a relative bandwidth of 123%. The center frequency is defined as the midpoint between the two −6 dB points.

notches in the frequency spectrums at approximately 7.5 MHz are clearly visible in Fig. 10 and Fig. 13. These

correspond to the substrate ringing modes of the bulk silicon as has been described previously by ladabaum et al. [35].

C. Charging Characterization

Measurements studying the effects of dielectric charg-ing are made by monitoring the capacitance of a cMUT element over a period of more than 5 d. If charging occurs, one would expect a shift in the pull-in and snap-back volt-ages over time.

In the experiment, a previously unused element is bi-ased at −80 V (past the collapse voltage of ~50 V), and negative voltage spikes from a Panametrics 5073 pulser at 1 kHz are applied for approximately 30 min. Experience indicates that this step stabilizes the performance of a new device. although the reason for this is not entirely clear, it is hypothesized that this is due to charges trapped during the fabrication process rearranging themselves [28]. after this initialization step, the element is biased at −40 V (in the noncollapsed regime), and the same negative volt-


Fig. 8. Imaginary component of the impedance of a single element of the 23 × 1 array at a bias of 50 V.

Fig. 9. Time domain plot of transmission pulse of a single-element 8 mm away from the hydrophone, biased at −40 V.

Fig. 10. compensated and uncompensated frequency domain plot of the transmission pulse from a single-element 8 mm away from the hydro-phone. The element is biased at −40 V. The compensated response is corrected for both the oil absorption and the hydrophone response. The uncompensated and compensated −3 dB center frequencies are 9.3 MHz and 9.2 MHz, respectively. The relative bandwidths are 92% and 114% for the uncompensated and compensated responses, respectively.

Fig. 11. schematic of the circuit used for pulse-echo measurements.

age spikes are applied at a 1-kHz repetition rate. The capacitance of the element is determined by setting up a voltage divider circuit consisting of a 100-kΩ resistor in series with a cMUT element and measuring the potential drop across the cMUT. The same bias-T configuration illustrated in Fig. 6 was used to add the dc bias to a 20-kHz 1-V p-p sine wave from a function generator. The bias voltage is monotonically swept from 0 to −80 V, then from −80 V to +80 V, and finally from +80 V to 0 V. symmetric capacitive behavior from the device when it is biased both positively and negatively indicates that there has been neither significant charging nor an accumula-tion of trapped charges. Measurements were taken after the initialization step, after 1 h of charging, after 25 h of charging, and after 140 h of charging. The measurements were done by disconnecting the pulser and connecting a function generator to apply the small ac signal. The mea-surements took about 45 min, after which the pulser was reconnected and the charging continued.

a plot of the capacitance as a function of (positive) bias voltage after different charging times is shown in Fig. 14. as can be seen, the collapse voltage is initially between 45 and 50 V, and the snapback voltage is between 10 and 20 V. In theory, the transition to and from the collapse re-gime should be a very sharp. This is not observed because the individual membranes that make up the element can have slightly different collapse voltages, and this tends to smear out the transition to and from the collapse regime. over time, it can be seen that there is little change in either the shape of the graph or the values of the collapse and snapback voltages. after 140 h of charging, there is a small increase (<5%) in the absolute capacitance mea-sured but otherwise little else of note.

as stated above, the symmetry of the capacitance about the 0 V bias point is also indicative of the dielectric charging. shown in Fig. 15 are plots of the capacitance

as a function of both positive and negative bias voltage. notwithstanding the postcollapse capacitance values in Fig. 15(a) plot and a deviation of less than 5 pF in the Fig. 15(d) data set near the collapse and snap-back volt-ages, the data are essentially symmetrical. It is, there-fore, reasonable to conclude that wafer-bonded cMUTs with a low-stress silicon nitride membrane and insulation layer suffer from minimal charging effects and can be op-erated for long periods of time with little change in per-formance.


Fig. 12. Time domain plot of a pulse-echo signal. The signal is reflected off a steel block ~12 mm away. The elements are biased at −40 V.

Fig. 13. Fourier transform of a transmit-receive signal from one element to another. The signal is reflected off a steel block ~12 mm away. Both elements are biased at −40 V. The uncompensated and compensated −6 dB center frequencies are 8 MHz and 9 MHz, respectively. The rela-tive bandwidths are 120% and 123% for the uncompensated and com-pensated responses, respectively.

Fig. 14. demonstration of the lack of charging effects with sixny wafer-bonded devices.

V. discussion

The primary goal of this work is to demonstrate the viability of fusion bonding of chemically mechanically pol-ished silicon nitride to silicon nitride for the purpose of fabricating ultrasound transducers. results indicate that the devices produced operate as expected, with a band-width greater than 120% and frequency of operation with-in the desired range. They have also proven to be robust enough to operate for extended periods of time with little to no change in operating performance. Extended experi-ence with the devices has shown that those that are suc-cessfully fabricated are extremely durable and are unlikely to fail while handling or in operation.

The fabrication process described is relatively straight-forward and takes many of the best attributes of the typical surface fabrication and wafer-bonding processes described in the literature. The process requires only 3 masks and can be completed by an individual in less than a week. The bonding process allows for the design and fab-rication of the membrane and cavity wafers independently of one another, which adds flexibility to the design. It also permits tighter packing of the individual cells because sacrificial release channels are not required. Elimination of the etch channels is important because future work in high-frequency 2-d arrays will put strict limitations on element size and as large an active area as possible will be needed to obtain a sufficiently high signal-to-noise ratio.

The process also allows one to avoid the use of expen-sive soI wafers, which can be difficult to obtain in the smaller numbers required in research. Using an insulating membrane permits one to optimize the top electrode cov-erage to permit good bandwidth and efficient operation simultaneously. The electrical performance can more eas-ily be modeled because an insulator is being used instead

of a semiconductor. Finally, using a silicon nitride as the insulation layer reduces the effect of charge buildup, which has been reported as being an issue when silicon dioxide is used.

The fabrication yield is strongly dependent on the cMP step and the cleanliness of the wafers. although cMP is an established microfabrication process, experi-ence has shown that it is not quite as predictable as other tools. The polishing rate is not uniform across the surface of the wafer. The removal rate tends to be higher away from the center of the wafer. Wafer bonding is not overly sensitive to wafer flatness (when compared with smooth-ness), however, the difference in polishing rate can result in variations in thickness of the membrane layer across the wafer. These differences are less than the variations observed from the deposition of low-stress lPcVd silicon nitride. Variations in thickness will reduce the uniformity of the frequency of operation across devices.

despite some of the challenges associated with cMP, the membrane yield achieved with the fusion-bonding process was reasonably good. defining success as having at least 99.5% of the membranes bonded to the bottom wafer after release, slightly more than 80% (20 of 24) of the transducers released would be considered successful. Bonding at a local level is quite good; when failure to bond occurs, it tends to be clusters of 5 adjacent mem-branes or more. Therefore, failure to bond appears to be more likely a result of contamination of one of the wafer surfaces as opposed to a surface too rough to bond. Given the roughness of the bottom wafer (measured rMs rough-ness of ~8 Å) it is somewhat surprising that the yield is as high as it is. a maximum rMs roughness of 5 Å is usually cited when bonding is done at room temperature with little additional pressure. It is possible that by operating in a vacuum at an elevated temperature with a relatively large compressive force being applied to the wafer pair (3600 n), the tolerance for roughness is eased somewhat. More work will need to be done to investigate where the discrepancy occurs. as has been stated previously, future generations of devices will eliminate the polysilicon layer and hence the roughness penalty associated with that layer.

For various reasons (mainly hedging against unexpect-ed processing mishaps), only 8 transducers were taken from the released stage to completion. of the 8 that were completed, 7 have no nonfunctioning elements or only one nonfunctioning element. The remaining device has 2 non-functioning elements. The failure mechanism of the ele-ments is related to the nonbonded membranes that have peeled off. The insulating layer alone is unable to prevent dielectric breakdown when the bias voltage exceeds 40 to 50 V. Further electrical testing of the low-stress nitride indicates its relatively weak dielectric strength.

Future work will incorporate stoichiometric nitride into the insulation layer. The stoichiometric nitride has been tested to have a dielectric strength close to that of thermally grown oxide (~900 V/μm). Work will also be done to improve the fabrication process by eliminating


Fig. 15. Plots of the capacitance of a cMUT element as a function of bias voltage after charging for (a) 0 h, (b) 1 h, (c) 25 h, and (d) 140 h.

the unnecessary polysilicon deposition step and improving the cMP processing step to improve the yield. The next generation of devices will consist of elements with a pitch sufficient to satisfy the nyquist sampling theorem and al-low for testing of devices from this fabrication process as imaging transducers.

VI. conclusion

In this paper, we present a new wafer-bonding fabri-cation process for cMUTs that combines many of the benefits of traditional surface fabrication and the soI-based wafer-bonding process. The fabrication process is relatively short and can improve the active area of the devices, which will be important for 2-d array applica-tions. avoiding soI wafers reduces costs and makes it possible to optimize both the bandwidth and efficiency of the transducer by having a patterned top electrode on an insulating membrane. Tests done on devices indicate they perform as expected both electrically and mechani-cally. The devices resulting from this fabrication process are promising and should provide an excellent platform for future work in 1- and 2-d cMUT arrays for endoscopic- and catheter-based ultrasound imaging.

acknowledgment

Fabrication of the devices was performed at the cor-nell nanoscale Facility, in Ithaca, ny, a member of the national nanotechnology Infrastructure network, which is supported by the national science Foundation (Grant Ecs-0335765).

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Andrew S. Logan (s’08) received the B.Eng. and M.a.sc. degrees in engineering physics at Mc-Master University in Hamilton, on, canada, in 2003 and 2006, respectively. He is currently pursu-ing a Ph.d. degree in systems design engineering at the University of Waterloo, Waterloo, on, canada.

His current research interests include the de-sign, fabrication, and testing of novel capacitive micromachined ultrasonic transducer arrays for medical imaging purposes.

John T. W. Yeow (s’99–M’04–sM’08) received the B.a.sc. degree in electrical and computer en-gineering and the M.a.sc. and Ph.d. degrees in mechanical and industrial engineering from the University of Toronto, Toronto, on, canada, in 1997, 1999, and 2003, respectively.

He is currently a faculty member in the de-partment of systems design Engineering, Uni-versity of Waterloo, Waterloo, on. His current research interests are in the field of developing miniaturized biomedical instruments.

dr. yeow is a recipient of the PEo Engineering Medal, nsErc In-novation challenge award, douglas r. colton’s Medal of research Ex-cellence, Micralyne Microsystems design award, ontario Ministry of research and Innovation’s Early researcher award, and 7T6 Early ca-reer award.


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Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-Based wafer bonding process