Hardware Implementation of Communication Systems

7/28/2019 Hardware Implementation of Communication Systems

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Hardware Implementation of

Communication Systems

Introduction to

FPGA & Microcontroller

Dr Mohamed Zorkany


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Introduction to FPGATechnology and Devices


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FPGA

FieldProgrammable GateArray

FPGA is an integrated circuit designed to be

configured by a customer or a designer after

manufacturinghence "field-programmable

The FPGA configuration is generally specified using

a hardware description language (HDL).

Small development overheadQuick time to market

No minimum quantity order

Reprogrammable
http://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Field-programmablehttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Field-programmablehttp://en.wikipedia.org/wiki/Field-programmablehttp://en.wikipedia.org/wiki/Field-programmablehttp://en.wikipedia.org/wiki/Integrated_circuit


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How can we make a

programmable logic?

One time programmable

Fuses (destroy internal links with current)

Anti-fuses (grow internal links) PROM

Reprogrammable

EPROM (erasable programmable ROM) EEPROM(Electrically Erasable PROM)

Flash

SRAM (Static RAM)


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FPGA types

SRAM-based One Time programmableOTP

uses anti-fusesneeds a serial PROM


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BlockRAMs

BlockRAMs

Configurable

Logic

Blocks

I/OBlocks

What is an FPGA?

Block

RAMs

Post layout timingFast register pipeliningexceeding the 10 million gateWafer 90 nm technology,

eight- layer metal process technology


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Module 1: FPGA structure

PSM:ProgrammableSwitchMatrices

CLB:ConfigurableLogicBlock


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FPGA Architecture


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Major FPGA Vendors

SRAM-based FPGAs

Xilinx, Inc.

Altera Corp.

Atmel

Lattice Semiconductor

Flash & antifuse FPGAs

Actel Corp.

Quick Logic Corp.

Share over 60% of the market


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Field Programmability

Field programmability is achieved through switches

(Transistors controlled by memory elements or

fuses)

Switches control the following aspects Interconnection among wire segments

Configuration of logic blocks

Distributed memory elements controlling the

switches and configuration of logic blocks aretogether called Configuration Memory


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Technology of Programmable

Elements

Vary from vendor to vendor. All share thecommon property: Configurable in one of the twopositionsON or OFF

Can be classified into three categories: SRAM based

Fuse based

EPROM/EEPROM/Flash based

Desired properties: Minimum area consumption

Low on resistance; High off resistance

Low parasitic capacitance to the attached wire (unwantedcapacitance that exists between the parts of an electronic component)

Reliability in volume production
http://en.wikipedia.org/wiki/Capacitancehttp://en.wikipedia.org/wiki/Electronic_componenthttp://en.wikipedia.org/wiki/Electronic_componenthttp://en.wikipedia.org/wiki/Capacitance


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SRAM Programming

Technology Employs SRAM (Static RAM) cells to

control pass transistors and/or

transmission gates

SRAM cells control the configuration of

logic block as well Volatile

Needs an external storage

Needs a power-on configuration

mechanism

In-circuit re-programmable

Occupies relatively larger area

Pass Transistors


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Anti-fuse Programming

Technology (1)

1. An antifuse is the opposite of a regular fuse


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Anti-fuse Programming

Technology

Very low ON Resistance

Limited size of anti-fuse elements; Interconnects occupy

relatively lesser area

Offset : Larger transistors needed for programming One Time Programmable

Cannot be re-programmed

(Design changes are not possible)

Retain configuration after power off


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EPROM Programming

Technology

No external storage mechanism

Re-programmable (Not all!) Not in-system re-programmable

Re-programming is a time consuming task


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Basic Spartan-II FPGA Block

Diagram


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FPGA Architecture Layout


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Configurable Logic Block

A

B

S

Y

AND

0

B

S

Y

Not

1

0

S

Y

OR

A

1

S

Y

B S Y

0 0 0

0 1 B1 0 0

1 1 B

S Y

0 1

1 0

A S Y

0 0 A

0 1 11 0 A

1 1 1


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F5IN

CINCLKCE

COUT

D Q

CK

S

REC

D Q

CK

REC

O

G4G3G2G1

Look-Up

Table

Carry

&

Control

Logic

O

YB

Y

F4F3F2F1

XB

X

Look-Up

Table

BY

SR

S

Carry

&

Control

Logic

SLICE

COUT

D Q

CK

S

REC

D Q

CK

REC

O

G4G3G2G1

Look-Up

Table

Carry

&

Control

Logic

O

YB

Y

F4F3F2F1

XB

X

Look-Up

Table

F5IN

BY

SR

S

Carry

&

Control

Logic

CINCLKCE SLICE

CLB Structure

Each slice has 2 LUT-FF pairs with associated carry logic

Two 3-state buffers (BUFT) associated with each CLB,

accessible by all CLB outputs


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LUT Function

4 inputs logic function

5 inputs logic function

4x1 multiplexer

16x1 RAM / Single and Dual-Ports

Serial in, serial out shift register

CLB Sli S


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CLB Slice Structure

Each slice contains two sets of the

following: Four-input LUT

Any 4-input logic function,

or 16-bit x 1 sync RAM

or 16-bit shift register Carry & Control

Fast arithmetic logic

Multiplier logic

Multiplexer logic

Storage element

Latch or flip-flop

Set and reset

True or inverted inputs

Sync. or async. control


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LUT (Look-Up Table)

Functionality

Look-Up tablesare primary

elements for

logic

implementation Each LUT can

implement any

function of 4

inputs

x1 x2 x3 x4

y

x1 x2

y

LUT

x1x2x3x4

y

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

0100010

101001100

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

1111111

111110000

x1 x2 x3 x4

y

x1 x2 x3 x4

y

x1 x2

y

x1 x2

y

LUT

x1x2x3x4

y

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

0100010

101001100

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

0100010

101001100

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

1111111

111110000

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

1111111

111110000


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5-Input Functions

implemented using two LUTs

One CLB Slice can implement any function of 5 inputs

Logic function is partitioned between two LUTs

F5 multiplexer selects LUT

A4

A3

A2

A1WS DI

D

LUT

ROMRAM

1

0

F4

F3F2

F1

A4

A3A2

A1

WS DI

D

LUT

ROM

RAM

F5

GXOR

G

nBX

BX

1

0

BX

X

F5

A4

A3

A2

A1WS DI

D

LUT

ROMRAM

A4

A3

A2

A1WS DI

D

LUT

ROMRAM

1

0

1

0

F4

F3F2

F1

A4

A3A2

A1

WS DI

D

LUT

ROM

RAM

A4

A3A2

A1

WS DI

D

LUT

ROM

RAM

F5

GXOR

G

F5

GXOR

G

nBX

BX

1

0

nBX

BX

1

0

BX

X

F5


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5-Input Functions implemented

using two LUTs

LUTLUT

X5 X4 X3 X2 X1 Y

0 0 0 0 0 0

0 0 0 0 1 1

0 0 0 1 0 0

0 0 0 1 1 0

0 0 1 0 0 1

0 0 1 0 1 1

0 0 1 1 0 0

0 0 1 1 1 0

0 1 0 0 0 1

0 1 0 0 1 0

0 1 0 1 0 0

0 1 0 1 1 1

0 1 1 0 0 1

0 1 1 0 1 1

0 1 1 1 0 1

0 1 1 1 1 1

1 0 0 0 0 0

1 0 0 0 1 0

1 0 0 1 0 0

1 0 0 1 1 0

1 0 1 0 0 0

1 0 1 0 1 0

1 0 1 1 0 01 0 1 1 1 1

1 1 0 0 0 0

1 1 0 0 1 1

1 1 0 1 0 0

1 1 0 1 1 1

1 1 1 0 0 0

1 1 1 0 1 1

1 1 1 1 0 0

1 1 1 1 1 0

LUTLUT

OUT


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CLB

MUXF6

Slice

LUT

LUT

MUXF5

Slice

LUT

LUT

MUXF5

Dedicated Expansion

Multiplexers

MUXF5 combines 2 LUTs to create

Any 5-input function (LUT5)

Or selected functions up to 9 inputs

Or 4x1 multiplexer

MUXF6 combines 2 slices to form Any 6-input function (LUT6)

Or selected functions up to 19 inputs

8x1 multiplexer

Dedicated muxes are faster and more

space efficient


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RAM16X1S

O

DWE

WCLK

A0

A1

A2

A3

RAM32X1S

O

DWE

WCLK

A0A1A2A3A4

RAM16X2S

O1

D0

WE

WCLKA0

A1

A2A3

D1

O0

=

=

LUT

LUT or

LUT

RAM16X1D

SPO

D

WEWCLK

A0

A1

A2

A3

DPRA0 DPO

DPRA1

DPRA2

DPRA3

or

Distributed RAM

CLB LUT configurable as

Distributed RAM

A LUT equals 16x1 RAM

Implements Single and

Dual-Ports

Cascade LUTs to increase

RAM size

Synchronous write

Synchronous/Asynchronousread

Accompanying flip-flops used

for synchronous read


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D Q

CE

D Q

CE

D Q

CE

D Q

CE

LUT

INCE

CLK

DEPTH[3:0]

OUTLUT =

Shift Register

Each LUT can be

configured as shift register

Serial in, serial out

Dynamically addressable

delay up to 16 cycles

For programmable pipeline

Cascade for greater cycle

delays

Use CLB flip-flops to adddepth


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Shift Register

Register-rich FPGA Allows for addition of pipeline stages to increase

throughput

Data paths must be balanced to keep desiredfunctionality

64

Operation A

4 Cycles 8 Cycles

Operation B

3 Cycles

Operation C

64

12 Cycles

3 Cycles

9-Cycle imbalance


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COUT

D Q

CK

S

REC

D Q

CK

REC

O

G4G3G2G1

Look-Up

TableCarry

&

Control

Logic

O

YB

Y

F4F3F2F1

XB

X

Look-Up

Table

F5IN

BY

SR

S

Carry

&

Control

Logic

CINCLKCE

SLICE

Carry & Control Logic


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Each CLB contains separatelogic and routing for the fastgeneration of sum & carrysignals Increases efficiency and

performance of adders,subtractors, accumulators,comparators, and counters

Carry logic is independent ofnormal logic and routingresources

Fast Carry Logic

LSB

MSB

CarryLog

ic

Routing


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Accessing Carry Logic

All major synthesis tools can infer carry

logic for arithmetic functions Addition (SUM


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Block RAM

Spartan-IITrue Dual-Port

Block RAM

PortA

P

ortB

Block RAM

Most efficient memory implementation

Dedicated blocks of memory

Ideal for most memory requirements

4 to 14 memory blocks

Use multiple blocks for larger memories 4096 bits per blocks

Builds both single and true dual-port RAMs


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Dual Port Block RAM


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RAMB4_S4_S16

Port A Out

4-Bit Width

Port B In

256-Bit Depth

Port A In

1K-Bit Depth

Port B Out

16-Bit Width

DOA[3:0]

DOB[15:0]

WEA

ENA

RSTA

ADDRA[9:0]

CLKA

DIA[3:0]

WEB

ENB

RSTB

ADDRB[7:0]

CLKB

DIB[15:0]

Dual-Port Bus Flexibility

Each port can be configured with a different data buswidth

Provides easy data width conversion without any

additional logic


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I/O Banking

O


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IOB Functionality

IOB provides interface between the package

pins and CLBs

Each IOB can work as uni- or bi-directional

I/O

Outputs can be forced into High Impedance

Inputs and outputs can be registered

advised for high-performance I/O

Inputs can be delayed

R i R


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Routing Resources

PSM PSM

CLB

PSM PSM

CLB CLB

CLBCLB CLB

CLBCLB CLB

ProgrammableSwitch

Matrix


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Advance architecture on

modern FPGAs


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Additional components

RAM blocks

Dedicated multipliers

Tri-state buffers

Transceivers

Processor cores

DSP blocks


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FPGA Tools


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Design process (1)Design and implement a simple unit permitting to

speed up encryption with RC5-similar cipher with

fixed key set on 8031 microcontroller. Unlike in

the experiment 5, this time your unit has to be able

to perform an encryption algorithm by itself,

executing 32 rounds..

Library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity RC5_core is

port(clock, reset, encr_decr: in std_logic;

data_input: in std_logic_vector(31downto0);

data_output: out std_logic_vector(31downto0);

out_full: in std_logic;

key_input: in std_logic_vector(31downto0);

key_read: out std_logic;

);

end AES_core;

Specification (Lab Experiments)

VHDL description (Your Source Files)

Functional simulation

Post-synthesis simulationSynthesis


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Design process (2)

Implementation

Configuration

Timing simulation

On chip testing

A ti HDL


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Active-HDL


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Simulation Tools

Synthesis Tools

L i S th i


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architecture MLU_DATAFLOW of MLU is

signal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;

begin

A1


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Features of synthesis tools

Interpret RTL code

Produce synthesized circuit netlist in a

standard EDIF format

Give preliminary performance estimates

Some can display circuit schematics

corresponding to EDIF netlist

I l t ti


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Implementation

After synthesis the entire implementation

process is performed by FPGA vendor tools

Xilinx ISE foundation

Altera Quartus

3rd party tools for alliance version

Circuit Compilation


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Circuit Compilation

LUT

LUT

?

Assign a logical

LUT to a physical

location.

Select wire segments

And switches for

Interconnection.

1. Technology Mapping

2. Placement

3. Routing

Routing Example


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Routing Example

Programmable Connections

FPGA

Configuration


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Configuration

Once a design is implemented, you must

create a file that the FPGA can understand This file is called a bit stream: a BIT file (.bit

extension)

The BIT file can be downloaded directly tothe FPGA, or can be converted into a PROM

file which stores the programming information


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INTRODUCTION TO

MICROCONTROLLERS


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What is a Microcontroller?

A microcontroller is a kind of miniature computerthat found in all kinds of gizmos

Generally speaking, if a device has buttons and

a digital display, chances are it also has a

programmable microcontroller brain.

Microcontrollers cont


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Microcontrollers cont.

Microcontrollers are 'single chip'

computers specifically designed to: Read input devices, such as buttons and sensors

Process data or information

Control output devices, such as lights, displays,

motors and speakers


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Embedded Control

Microcontrollers are placed in devices, orembedded, for operation and control.

Can you name other devices in your life thathave embedded control?


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Microprocessor vs. Microcontroller

A microprocessoris the brain of a computersystem

Generally referred to as the central processingunit (CPU), the microprocessor by itself is

practically useless To be useful, one must have means of

communicating with it using input and outputdevices

One must also add memory (ROM and RAM)so that the system can be programmed.


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Microprocessor vs. Microcontroller Cont.

A microcontrolleris a computer chip designed for

control-oriented applications Unlike ordinary microprocessors, microcontrollers

have built-in features that make them operate

almost independent of additional circuitry This is possible because microcontrollers contain

things like memory (ROM, EPROM, RAM, etc)

input and output ports timers

serial and parallel communication capability

analog-to-digital converters

Diff B t FPGA d


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Difference Between FPGA and

Microcontroller

1. Microcontrollers are custom built mini computers in an IC

while FPGAs are only composed of logic blocks that can be

rewired electrically

2. Microcontrollers consume less power than FPGAs

3. FPGAs take a considerably longer time to set-up while

there are ready built microcontrollers being sold for specific

uses

4. Building devices with FPGAs are more costly than

microcontrollers

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Hardware Implementation of Communication Systems