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FP7 projectFabrice Lemonnier, Hipeac 2012
2 /2 /
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Industrial issues
Reduction of Time To Market
Rapid adaptation for a product line
Products are more and more adaptive, dynamic and interactive to their environment
Reduction of power consumption
Increase of resilience to faults
Smart cameraCognitive radio Drone
3 /3 /
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Challenges
Challenge 1: To address the steadily increasing application dynamicity using self-adaptive capabilities.
Challenge 2: To increase the software development productivity of manycore for Time to Market and cost reasons and to enable the reuse of legacy software and hardware codes.
Challenge 3: To increase accessibility to manycore technologies and propose a European alternative on the worldwide market of this technology.
Challenge 4: To increase energy efficiency for embedded systems and High-Performance Computing (HPC) systems.
4 /4 /
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Objectives of the project
Objective 1: To raise the programming efficiency of heterogeneous manycores.
Objective 2: To develop a dynamic reconfigurable technology with pre-emption and relocation capabilities.
Objective 3: To enable self-adaptation with a virtualisation layer.
Objective 4: To develop a heterogeneous manycore based on available IPs: definition of generic interfaces.
5 /5 /
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State of art
Existing manycores provide static allocation and sheduling
• TILE-Gx™ 8000 from Tilera (16 to 100 cores)
• MPPA® from Kalray (256 to 1024 cores)
• PicoArray from Picochip (248 cores)
Projects:
Morpheus
Hardware Flexibility / dynamicity
Prog
ram
mab
ility
FlexTiles
FOSFOR (ANR)
ReconOS
AetherApple-Core
Tsar Mosart
with reconfigurable technologywithout reconfigurable technology
ADAM
6 /6 /
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Objective 1: To develop a heterogeneous manycore based on available IPs: definition of generic
interfaces
7 /7 /
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Objective 1: To develop a heterogeneous manycore based on available IPs: definition of generic
interfaces
Virtu
alisation
Layer
Kern
el
Reso
urce M
on
itorin
g
& A
llocatio
n
Tile
Tile
Tile
Tile
Tile
Tile
Virtu
al C
od
e g
eneratio
n
Virtu
al B
itstream
gen
eration
Reco
nfig
urab
le area
reconfigurable
area
GPP
DMU
controldata
NI
GAI
Tile core : generic part
dedicated
function
GAI
LMEM
Internal communication resource
Tile accelerators : specific part
Tile
NoC
8 /8 /
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Objective 2: To raise the programming efficiency of heterogeneous manycores
Virtualisation layer
reloadable binary code
Parallelisation, partioning
Application
Hardware Tile
Compilation Synthesis, P&R
reloadable bitstream
Hardware Abstraction Layer
Hardware Abstraction Layer API
Operating Library API
Kernel
Resource Monitorin & Allocation
DIAGNOSISO = F(L)
ACTION
SYSTEM
The toolchain
The operating library
The heterogenousmulticore
MONITORING
9 /9 /
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Objective 3: To enable self-adaptation with a virtualisation layer
DDR
Noc
GPP DMA
LMEM
INOC DSP
GPP DMA
LMEM
INOC DDR
GPP DMA
LMEM
INOC REC
GPP DMA
LMEM
INOC REC
GPP DMA
LMEM
INOC DSP
GPP DMA
LMEM
INOC I/O
GPP DMA
LMEM
INOC REC
GPP DMA
LMEM
INOC REC
GPP DMA
LMEM
INOC DSP
Heterogeneous Hardware
Controlled byKernel and
Virtualization layerEthernet
IMDCT MatrixMult
Accelerator/Virtual Code
Run-timeallocation / binding
I/O
DIAGNOSISO = F(L)
ACTION
SYSTEM
MONITORING
10 /10 /
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Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
Objective 4: To develop a new dynamic reconfigurable technology with pre-emption and
relocation capabilities
3D stacked reconfigurable layer
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
11 /11 /
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Tool flow
Application (C code)
C to SpearDE representation
Conversion (Cosy)
Data parallelisation Mapping (SpearDE)
Graphic input
(manual)
Streaming optimisation (Cosy)
Compilation (Cosy)
Virtual executable code running on manycore
layer
architecture representation
Catapult
P&R
Virtual bitstream generator
Virtual bitstream running on eFPGA layer
12 /12 /
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Parallelisation and mapping of an application
I/O
NoC
Tile
Acc1
Tile
Acc1
Tile
Acc3
Tile
Acc4I/O
Tile
DDR ctrl
Tile
thread1 thread2 thread3 thread4
API
thread1 thread2
thread1 thread2thread3 thread4
API
thread1
thread2
Application
Tools for parallelisation and mapping
Acc1
Acc1
Acc3
Acc4
Dynamic allocation
Dynamic allocation
Tools for parallelisation and mapping
13 /13 /
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Results
Heterogeneous manycore with self adaptive capabilities• Heterogeneous manycore
• Reconfigurable technology with relocation and migration capabilities; virtual bitstream
• Virtualisation layer to provide an abstraction of the heterogeneous manycore and self adaptive services
• Feasability study of 3D stacking with a dedicated layer to reconfigurable technology above the manycore layer
• Tools chain for parallelisation and compilation
Deliverables :
• SystemC simulator and FPGA demonstrators for the heterogeneous manycore architecture
• Physical design results for embedded reconfigurable technology on a layer of 3D stacking
• Virtualisation layer code, kernel• Tool chain code
14 /14 /
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FlexTiles in few words
Project coordinator: THALES
Funding budget: 3,670,000€
Starting date: 15/10/2011
Duration: 36 months
8 partners in 5 countries
Website: www.flextiles.eu
15 /15 /
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Consortium
Partners & Third Party
Country Main scientific and technical contributions
THALES France Infrastructure and applications
KIT Germany Virtualisation layer
TUE Netherlands Kernel ; NoC
CSEM Switzerland DSP
CEA France NoC ; 3D stacking
UR1 France Reconfigurable technology
SUNDANCE United Kingdom
FPGA Demonstrator
ACE Netherlands Parallelisation and compilation Tools
16 /16 /
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Conclusion and perspectives
• The main objective of the FlexTiles project is to define a new type of manycore providing a breakthrough in terms of self adaptivity.
• This high flexibility will be based on a new eFPGA technology providing seamless relocation and migration
• Re-location will be done at runtime to obtain the best trade off between performance and power consumption
• We will propose a solution for the programming issue of the manycores chip.
Perpectives: definition of the platform specifications with keeping homogeneous approach from the programming model to the architecture definition.
17 /17 /
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Questions ??
