IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS …jchae2/Research_files/HearingAid...IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 5, NO. 3, JUNE 2011 201 A MEMS-Based Power-Scalable

IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 5, NO. 3, JUNE 2011 201

A MEMS-Based Power-ScalableHearing Aid Analog Front End

Ilker Deligoz, Syed R. Naqvi, Tino Copani, Associate Member, IEEE, Sayfe Kiaei, Fellow, IEEE,Bertan Bakkaloglu, Senior Member, IEEE, Sang-Soo Je, and Junseok Chae

Abstract—A dual-channel directional digital hearing aid frontend using microelectromechanical-systems microphones, and anadaptive-power analog processing signal chain are presented. Theanalog front end consists of a double differential amplifier-basedcapacitance-to-voltage conversion circuit, 40-dB variable gain am-plifier (VGA) and a power-scalable continuous time sigma deltaanalog-to-digital converter (ADC), with 68-dB signal-to-noiseratio dissipating 67 W from a 1.2-V supply. The MEMS micro-phones are fabricated using a standard surface micromachiningtechnology. The VGA and power-scalable ADC are fabricated ona 0.25- m complementary metal–oxide semciconductor TSMCprocess.

Index Terms—Continuous time sigma-delta modulation, digitalhearing aids, directional microphone array, microelectromechan-ical-systems (MEMS) microphone.

I. INTRODUCTION

H EARING loss is one of the most common human impair-ments. It is estimated that by year 2015 more than 700

million people will suffer mild deafness [1]. Most can be helpedby hearing aid devices depending on the severity of their hearingloss.

This paper describes the implementation and characterizationdetails of a dual channel transmitter front end (TFE) for digitalhearing aid (DHA) applications that use novel microelectrome-chanical-systems (MEMS) audio transducers and ultra-lowpower-scalable analog-to-digital converters (ADCs), whichenable a very-low form factor, energy-efficient implementationfor next-generation DHA. The contribution of the design is theimplementation of the dual channel MEMS microphones andpower-scalable ADC system.

The first generation of hearing aids usually consisted of analogvariable gain amplifiers, electret microphones and speakers thatcompensated for hearing loss. They dissipated a considerableamount of power and had flat frequency characteristics that madethese devices uncomfortable for most patients since hearing lossusually varies across different frequencies [1]. The next gener-ation of devices adopted analog filter banks in which band-passfilters were used in parallel to amplify the acoustic signal toa specific level in each different frequency band. This design,however, resulted in bulky devices that still required high power

Manuscript received March 24, 2010; revised June 24, 2010; accepted August27, 2010. Date of publication October 28, 2010; date of current version May 25,2011. This work was supported by the National Science Foundationm Researchto Aid Persons with Disabilities Program under Grants 062777 and 0652136.This paper was recommended by Associate Editor D. Cumming.

The authors are with the Electrical, Computer and Energy Engineering De-partment, Arizona State University, Tempe, AZ 85287 USA..

Digital Object Identifier 10.1109/TBCAS.2010.2079329

Fig. 1. DHA system block diagram.

consumption [2]. A major breakthrough was achieved throughthe development of DHAs that exploited the power of digitalsignal processors (DSPs) that allowed full programmability andcustomization to a patient’s hearing characteristic [3]–[7].

A typical DHA system, shown in Fig. 1, consists of a Trans-mitter Front-End (TFE), DSP, and a Receiver Front-End (RFE).The TFE consists of the microphone, a variable gain amplifier(VGA) and an ADC. The RFE receives the processed digitalsignal from the DSP and converts it to the analog domain. Atthe backend, a speaker delivers the acoustic sound to excite thepatient’s eardrums.

One of the major issues with existing DHAs is the rapiddegradation of performance in noisy environments in whichthe TFE becomes saturated due to the ambient acoustic contentand background noise. Background noise interferes with thedesired conversation thereby impairing intelligibility. While theuse of a very high dynamic range TFE can help relieving thisproblem, it comes at the expense of high power consumptionand complexity.

Recently developed DHAs also employ microphone arrayscombined with adaptive array processing that improve audioquality and perception in real-life environments through noisecancellation mechanisms. Directional DHAs exploit the useof multiple microphone arrays (MMAs) to provide the patientwith information on the spatial position of the desired acousticsource, while attenuating the ambient noise at the same time[8]. MMAs apply adaptive beam forming techniques to estimatethe signal direction and cancel ambient noise [9], [10].

MMAs’ microphone characteristics and performance are im-portant features of modern DHA devices. The most widely usedmicrophones in hearing aids are electret microphones; howevertheir large size prohibits the application of MMA techniques incompletely in-the-ear-canal systems.

MMA hearing systems require precise adaptive matching ofthe gain and phase responses of both of the audio transducersand the analog front ends of each channel. For example, toachieve 10 dB of background noise cancellation, the gain ofthe two transmitter front ends should match within or less than0.5 dB [8]. This implementation enables a MMA hearing system

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202 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 5, NO. 3, JUNE 2011

Fig. 2. Power spectral density of the noise floor in (a) a quiet environment and(b) noisy environment.

with small size due to high level of integration and low mis-match in the amplification gains of the two channels. A smallsize dual-channel approach allows using two microphones perear, giving directionality information to the patient.

The paper is organized as follows: Section II describes themotivations behind the choice of an adaptive signal-to-noiseratio (SNR) hearing aid architecture and then provides systemspecifications. Section III provides details of the implementedMEMS microphone and electrical interface. Section IV presentsthe front-end adaptive modulator design and implementa-tion. Section V describes the physical IC design and measure-ment data. Finally, Section VI provides a conclusion along witha summary of the research.

II. ADAPTIVE HEARING AID

In general, the dynamic range and power level of an audiosignal have different characteristics in different environments.As illustrated in Fig. 2(a), the audio spectrum of a conversationin quiet environments shows that the noise floor is at about

TABLE IDESIGN OBJECTIVES FOR HEARING AIDS

Fig. 3. Implemented DHA architecture.

0 dB-SPL (dB Sound Pressure Level), and the acoustic signal hasa 65-dB dynamic range. Fig. 2(b) shows the spectrum of the sameconversation in a noisy environment (i.e., street) where the noisefloor has increased to 25 dB-SPL and the dynamic range is nowonly 55 dB. Clearly, to cope with the ambient noise, the personwho is speaking raises his voice level, but only up to a certainlevel. Consequently, it is clear that changes in signal power,dynamic range and noise floor can all be exploited to optimizethe TFE circuit power consumption. In fact, in high backgroundnoise environments, the DHA system can decide to relax thefront-end noise performance and optimize its parameters to avoiddegradation (i.e., clipping) of the high sound-level desired signal.

Conventional hearing aid architectures have a fixed front-enddynamic range (e.g., as high as 120 dB) to cope with differentambient noise conditions but require high power consumption.In contrast, the proposed architecture adapts to noise floor con-ditions by adjusting system linearity and SNR of the analogfront end (AFE) to maintain optimal performance. This architec-ture can optimize power consumption depending on the ambientconditions, thereby maximizing battery life. However, changingthe system architecture to scale SNR can lead to transient ar-tifacts, such as clicks or pops, or potential system instability.These issues have been also addressed in this work.

The target requirements of a hearing aid are summarized inTable I, and the implemented DHA architecture is shown inFig. 3. In Fig. 3, incident acoustic waves on the dual MEMS mi-crophones are converted into capacitive modulations. A micro-phone interface circuit (i.e., C2V in Fig. 3) translates the capac-itive modulation into an electrical signal. A VGA is employed

DELIGOZ et al.: A MEMS-BASED POWER-SCALABLE HEARING AID ANALOG FRONT END 203

Fig. 4. A 3-D view of the MEMS capacitive microphone.

to set the optimal voltage level for the following ADC stage.An adaptive dynamic range fourth-order continuous timemodulator is employed as the ADC. Ambient noise reductionand directivity are achieved through manipulation of the phaseinformation of the two incoming channels in the back-end DSPand are adjusted to each individual patient’s hearing needs.

This system implements power/SNR scalability at the TFE tomaximize battery life and optimize noise performance. Further-more, in the following sections it will be shown how the adoptedscaling technique avoids transient noise glitches in the RFE,which can lead to user’s ear fatigue and hearing discomfort.

III. MEMS MICROPHONE AND INTERFACE

A. Capacitive MEMS Microphone System

Fig. 4 depicts the construction of the capacitive MEMS mi-crophone. The device size is 2.5 2.5 0.5 mm and it consistsof a multi layered parylene diaphragm suspended over a siliconsubstrate [11]–[13]. The 1 m gap between the diaphragm andsubstrate forms a parallel plate capacitor. The substrate acts asthe capacitor backplate and acoustic holes are etched from thebackside of the substrate to let the air in the gap move freely.

Minute capacitance variations of tens of femto farads, gener-ated by the MEMS microphone is then converted into an elec-trical signal by a capacitive interface circuit. The design of theinterface presents unique challenges due to the small sensingcapacitance, the high output impedance, robust dc bias require-ments, and circuit noise (mechanical and electrical).

A typical MEMS condenser microphone needs to be con-nected to a bias voltage source through a high impedance path[14]. To first order, the MEMS microphone can be modeled asa variable capacitor. Sound pressure moves one side of the par-allel plate capacitor, creating a capacitance change. The charge

vs. voltage relationship of a capacitor isexpressed by

(1)

The sensed voltage of a MEMS microphone can be derived from(1), by applying the charge conservation law

(2)

Fig. 5. Microphone capacitance change with respect to dc bias.

Fig. 6. Acoustic characterization curve of the MEMS microphone.

where C is the capacitance variation, is the dc ca-pacitance value and is the dc bias voltage of the micro-phone.

Fig. 5 shows the measured capacitance change as the dcvoltage bias is swept from 100 mV to 900 mV. When thedc bias voltage is in the 700–900 mV range, the capacitancechange of the microphone peaks and saturates around 100 fF.The 200 fF data point is an outlier in Fig. 5.

The capacitance change is converted to voltage signal by acapacitance-voltage interface, which will be discussed in sec-tion C. Fig. 6 shows the acoustic response of the MEMS micro-phone. A 1 kHz acoustic signal with 20 to 80 dB SPL was ap-plied to the MEMS microphone. The microphone’s capacitancevariation was measured by a LCR meter (Agilent 4263B). Themeasured MEMS microphone’s capacitance modulation showsa linear characteristic.

B. MEMS Microphone Interface

Capacitive sensing circuit architectures can be roughlydivided into three broad categories: 1) the switched capacitorcharge integration (SCI) usually implemented in CMOS, with


Fig. 7. FDDA-based MEMS interface circuit interfaced to the TFE system.

Fig. 8. FDDA amplifier transistor-level schematic.

its main disadvantage being the high noise floor due to noisefolding and high kT/C noise; 2) the continuous-time current(CTC) sensing based on charge amplifiers, which are limitedby input parasitic capacitance and noise; and 3) the continuoustime voltage sensing (CTV), which can achieve superior noiseperformance over the other two approaches [15]–[19].

A CTV approach based on a fully differential differenceamplifier (FDDA) [20]–[22] is presented in this paper as areference design, which can be implemented in the sameprocess as the rest of the analog front end (Fig. 7, 8). TheFDDA achieves single ended to differential conversion and 6dB gain. The FDDA consists of dual differential input pairs,namely, a primary and auxiliary pair. The primary pair isconnected to the MEMS microphone, while the auxiliary pairforms a feedback loop. The primary pair and the auxiliarypair implement a virtual short circuit, which provides the highinput impedance required for the MEMS microphone and a lowoutput impedance to drive the next stage.

The back-to-back diodes turn on as the voltage of the highimpedance sense node drifts from the bias point thereby essen-tially clamping the voltage of the sense node to the bias point.

A block diagram of an ideal FDDA is shown in Fig. 9 wheretwo differential input voltages primary and auxiliary

are converted into currents through the transconduc-tance stages, and then amplified by an output stage [22].In this way, the ideal FDDA amplifies the differential voltageswhile suppressing the common mode voltage. With respect toFig. 9, the FDDA behavior is ideally defined by

(2)

Fig. 9. Block diagram of a fully differential difference amplifier.

An ideal FDDA with infinite forward gain in negative feed-back configuration forces the following relationship between thetwo differential inputs

(3)

Since there are two differential pairs, the gain matching of thetwo parallel transconductance stages (i.e., and ) is animportant issue and sufficient matching to guarantee correct cir-cuit operation is required. The signal transfer function of theFDDA can be written as

(4)

where and are the differential gain and input-referredoffset, defined similar to the case of conventional opamps. How-ever, the parameters are unique to the FDDA dueto the dual input pairs. The and are thecommon mode rejection ratios of the primary and the auxiliaryinput pairs, whereas the is a measure of the differenceof the differential inputs, which also becomes a common modesignal, defined as

(6)

Fig. 8 shows the device level schematic of the FDDA. Theinput pairs of the FDDA are implemented using PMOS deviceswith large gate areas in order to reduce the flicker noise contri-bution. The output consists of a class AB stage to drive the rel-atively low input impedance of the next stage. The FDDA has adc gain of 75 dB, and GBW of 9 MHz.

C. MEMS Capacitive Readout Linearity

The interface circuit is expected to achieve more than 90 dBdynamic range as shown in Fig. 10. A plot of the simulated THDas a function of the input sound pressure in dBSPL at1.05 kHzis shown in Fig. 11. No significant distortion is manifested inthe front and the THD is less than 1%( dB) for a SPL lessthan 100 dB.


Fig. 10. Dynamic range simulation results.

Fig. 11. THD of the differential output voltage Vs SPL at 1.05 kHz.

D. VGA Design

A VGA is used to amplify the signal in order to maximizethe resolution of the following ADC at various input signallevels. The VGA, shown in Fig. 7, includes a linearized MOS re-sistor at the input and an OTA with resistive feedback [23], [24].The input resistor is a cross-coupled depletion-mode NMOStransistor pair, whereas the feedback resistor is a high-resistiveprogrammable poly resistor with four settings of 100, 200, 400,and 800 k . The gate voltage of the cross-coupled transistorssets the gain of the VGA together with the switchable feedbackresistor banks. The simulation results of the VGA programmablegain are reported in Fig. 12. The schematic of the OTA used in theVGA is shown in Fig. 13. A cross-coupled NMOS load is used toincrease the gain with positive feedback, which is then followedby a class-B output stage. The class-B stage increases the outputcurrent drive capability while keeping the quiescent current atan optimum value to reduce power consumption.

IV. FRONT-END ARCHITECTURE AND CIRCUIT

Fig. 14 shows the block diagram of the implemented ar-chitecture, which is a fourth-order continuous time mod-

Fig. 12. Small-signal gain of the VGA, with respect to vct of four feedbackresistor setting.

Fig. 13. Class B OTA schematic.

Fig. 14. Implemented continuous time modulator.

ulator with a 1.5-b quantizer [25]. The input stage isan active-RC integrator whereas the subsequent stages are gm-Cintegrators. Furthermore, the topology uses return-to-zero cur-rent-steering DACs in the feedback while two comparators im-plement the 1.5-b flash quantizer.

The design of ADCs for the DHA architectures isvery challenging because of the requirements for extremelylow power consumption and high SNR at the same time. Indiscrete-time modulators, integrators are usually imple-mented using switched capacitor circuit techniques. However,


Fig. 15. NTF and STF of the discrete time prototype.

Fig. 16. Continuous time -ADC block diagram.

in order to satisfy the SNR requirement, the switched-capacitorintegrators are required to settle to their final value in halfthe clock period which, in turn, requires a very high gainbandwidth product (GBW) for the OTAs and, thus, high-powerconsumption. In contrast, the loop filter frequency response ofcontinuous time modulators is required to cover only thesignal bandwidth, which usually results in a much lower GBWproduct requirement and then power consumption [26].

A. Design of the Loop

To simplify the ADC system design, a discrete-time proto-type for the loop was used as a starting point and thenconverted to a continuous time equivalent system by using im-pulse invariant transform [25], [28]. The resulting loop isa fourth-order modulator with an in-band optimized zero in thenoise transfer function (NTF). The simulated NTF and signaltransfer functions (STF) of the designed discrete time prototypeare shown in Fig. 15.

The block diagram shown in Fig. 16 was used to validatethe discrete-to-continuous time transformation. Lossy integratormodels were used to derive each integrator’s dc gain specifi-cation to achieve the required SQNR (signal- to–quantization-noise ratio). A minimum dc gain of 60 dB in the first integratorOTA is needed to achieve the desired SQNR level.

B. First-Stage Adaptive Active RCI Integrator

Power scaling of the system is implemented at the firstintegrator stage of the modulator wherein the highestpower consumption is budgeted to the first stage in order toguarantee high SNR and linearity. Three parallel binary-scaled

Fig. 17. Schematic of the unit OTA used at the adaptive active RC design.

OTAs implement the power/SNR scaling, which consists of 4power consumption steps (i.e., 8.4, 16.8, 33.6, and 67.2 W,respectively, from a 1.2-V supply). Fig. 17 shows the schematicof the unit OTA used to build the adaptive active RC integrator.Depending on which OTAs are enabled, the input integrationresistors are scaled accordingly to increase the linearity per-formance (Fig. 19) At low power levels and high input soundlevels, higher input resistance is used to decrease the integrationcurrent thereby optimizing the linearity and dynamic range ofthe first stage at the expense of higher input-referred noise.However, as discussed in Section II, in this situation, ambientnoise dominates the system noise budget and, therefore, thenoise performance of the ADC can be relaxed.

In order to maintain a constant loop filter response, integra-tion capacitors are scaled as well when the input resistor isvaried. The input resistor is scaled to 100, 200, 400, and 800 kwhen lowering the power consumption while the integration ca-pacitor can assume the values of 100, 50, 25, and 12.5 pF, re-spectively. Furthermore, additional fine-tuning of resistors andcapacitors is employed to guarantee loop frequency response ac-curacy against process variations and mismatches.

Fig. 18 shows the simulated input-referred noise spectrum ofthe active-RC integrator when different parallel OTAs are en-abled (i.e., at different levels of power/SNR scaling of the inte-grator performance).

The calculated integrated input-referred noise in a 10-KHzbandwidth and corresponding SNR value are shown in Table I.Effective SNR of the system can be varied from 81 to 90 dBwith the appropriate power setting.

C. Switching Transients

Discrete SD modulators usually exploit idle clock phasesto perform architecture reconfigurations without affecting thesignal integrity (i.e., glitches, bursts). However, there is noavailable clock phase to change the power/SNR configurationof the first integrator in the adopted continuous time modulator.Thus, in order to avoid hearable signal artifacts (e.g., poppingsounds) and also modulator instability, the transient response


Fig. 18. Noise performance of an adaptive active RC implementation.

of the system must be carefully analyzed when parallel OTAsare engaged and/or disengaged.

Ideally, when the auxiliary OTAs are connected, instabilityand glitches will be avoided as long as the input and outputvoltages of the auxiliary OTA settle to the same values of theOTA already active in the loop. Unfortunately, this is not fea-sible because the input signal and the feedback DAC (DAC 1)continuously change the input and output node voltages of thefirst integrator so that a very fast tracking of the input and theoutput of the integrator would be required, which would lead tohigh power and die area costs.

However, a system analysis shows that if the input and theoutput of the auxiliary integrator are kept at the common modevoltage before insertion, the effects of the transient are reducedand the impact to the output of the modulator is negligible. Thesimplified schematic of the active-RC integrator with two par-allel OTAs is shown in Fig. 19. Before connecting the additionalOTA into the loop, its input nodes are connected to the commonmode voltage , while the feedback capacitor is shorted bytransmission-gate (TG) switches, so that the OTA is placed intoa unity gain configuration with zero differential input. After theadditional OTA is powered up and its output nodes are settledto the common mode voltage, the input nodes are disconnectedfrom the common mode supply, and the TG switches that areshorting the feedback capacitors are opened. The input resistorsare then scaled to the required value only after the input andoutput nodes of the additional OTA are connected to the wholeintegrator. This power up procedure ensures that the transienteffect to the loop is negligible.

When the auxiliary OTAs disengage, the effect on the loopstability is inherently very small. Indeed, the extra integrationcapacitance is disconnected from the loop and the integrationresistor size is increased accordingly. Since the capacitors arealready precharged from the previous operation, the only distur-bance is due to charge injection from the CMOS switches, whichhas been minimized by adopting well known techniques [29].

Adaptive power scaling of the fourth-order CT achieves68-dB SNR at 120 W, which can be scaled down to 61-dBSNR with 67 W power consumption. Fig. 20 shows measured

Fig. 19. Adaptive power scaling of the active RC integrator.

TABLE IIPOWER/SNR SCALING FOR THE ACTIVE RC INTEGRATOR

Fig. 20. Zero input noise floor for power programming.

noise level with zero input for the four power settings. The noisefloor decreases about 2–3 dB with each doubling of the first inte-grator power. Fig. 21 shows the transient response of the powerswitching. In this test the power of the modulator is changedfrom minimum to maximum and vice-versa every 1 ms. Thedigital bit stream is decimated and filtered with a seventh-orderdigital Butterworth filter. The output does not show dramaticartifacts (popping or clicking). This measurement shows that


Fig. 21. Transient effects of dynamic power scaling.

Fig. 22. circuit schematic.

when the environment conditions change and the DSP com-mands a different power level setting, the modulator adapts tothe change quickly, with only very little effect on the signal am-plitude. However, environment changes happen at a low repeti-tion rate in real life (e.g., once every few seconds or minutes).Therefore the amplitude changes in the output will not be rec-ognized by the user.

D. -C Integrators

The stage circuit topology that has been used as thevoltage to current converter is shown in Fig. 22. A folded-cas-code structure is used to maximize the integrator dc gain.Resistive source degeneration is used to set the transconduc-tance value and improve linearity. Two helper amplifiers (Av)increase the precision of the input source followers, allowingvoltages and to accurately appear at the degenerationresistor nodes [27]. The input differential voltage is thus con-verted into a small-signal current through , which flows atthe drains of the input PMOS devices. The differential currentis then applied to the folded output stage to increase outputimpedance and dc gain.

The -C integrators have a 69-dB dc gain, a power dissipa-tion of 9.6 W from a 1.2-V supply, and the integration con-stants are 65.9, 103.9, and 596.8 kRad/s.

Fig. 23. -Z transconductance stage.

Fig. 24. Schematic of the quantizer.

E. Noise Transfer Function (NTF) Zero

In the modulator block diagram of Fig. 14, the local feed-back block implements a zero in the NTF just at the edgeof the modulator passband, which helps to increase the SQNRby dB [28]. Note that his NTF zero is required in order tomeet the system specifications. Because of the low frequency ofthe NTF zero, the required value to implement the zero is atleast two orders of magnitude lower than the other stages.

The implemented transconductance stage is shown inFig. 23. The circuit consists of a modified version of the foldedcascode transconductance stage. To achieve a low transcon-ductance value without increasing the size of the degenerationresistor, the signal current of the input stage is scaled downto the desired value in three current mirroring stages (i.e.,200:40:4:1). The -C integrator has a 42 dB dc gain, withan integration constant of 500 rad/s. The power dissipation is5.7 W from a 1.2-V supply.

F. Comparator

The schematic of the adopted three-level (1.5 b) quantizer isshown in Fig. 24. Return-to-Zero phase consists of a third levelin the DAC. By using a three-level quantizer, the zero state isgenerated as a digital code, which helps the loop stability andincreases the SQNR. The adopted comparator architecture con-sists of a preamplifier and a regenerative latch [30]. The pream-plifier compares the input differential signal with the differentialreference voltage. When the digital clock signal is low, the re-generative latch is equalized, and the input signal is compared;when the clock is high, the current differential at the output ofthe preamplifier stage triggers the regenerative latch to its finalvalue.

As shown in Fig. 25, the quantizer uses a two-phase clock.When is low, the quantizer is equalized; when is high,


Fig. 25. Clock timing diagram.

the output of the quantizer is latched. Furthermore, whenis high, a logic AND between the output of the quantizer andthe clock is performed, which gives the Return-to-Zero state.A non-overlapping clock generation circuit is used to producethe clock signals. The input to this circuit is a 50% duty-cycleclock, and the output is a clock with a larger duty cycle, whichis determined by the delay of the feedback signals at NANDgates’ inputs. The current-starved delay architecture is used toguarantee that the rising edge of the clock comes later thanthe rising edge of the comparator enable signal [31].

G. Digital-to-Analog Converter (DAC)

Current steering non-return-to-zero (NRZ) or return-to-zero(RZ) DACs are typically used in modulators because theyenable simple feedback architecture. A complementary currentsource and sink architecture is used in this design to ease re-quirements on the common mode feedback circuit of the OTAs[32]. When a positive pulse comes from the comparator, DACs’PMOS current sources supply a positive current to the positiveintegration node and NMOS current sources sink a negative cur-rent from negative integration node. With a negative pulse, di-rection of the current sources is inverted with PMOS currentsources supplying to the negative integration node, and NMOSsources sinking current from positive integration node. For theRZ phase, the PMOS current sources are directly connected tothe NMOS current sources.

The DAC1 block, shown in Fig. 26, has the most stringent re-quirements because it is directly applied to the modulator inputnodes. In particular, DAC1 should be as linear as the wholesystem. Dynamic current calibration and glitch optimization isused to overcome DAC1’s non-idealities [33]. Moreover, cur-rent scaling is implemented for power/SNR optimization. A biascircuit generates gate voltages for the NMOS and PMOS cur-rent sources in the circuit. However, when the current sources

Fig. 26. DAC1 schematic implementation.

are scaled up to generate the required DAC output, the NMOSand PMOS transistors are scaled differently, leading to a currentmismatch. To equate the source and sink currents dynamic cal-ibration is therefore required. During the calibration phase, theswitches controlled by are closed. The up current andthe down current are equalized while all the switchesclosed. The equalization is implemented by forcing a voltage

on the hold capacitor to compensate for the mismatch inthe up PMOS and down NMOS devices. During normal DACoperation, switch is open and the capacitor holds the cal-ibrated gate voltage. Usually, in a conventional dynamic cali-bration DAC, two identical DACs are designed [33] During oneclock phase, one of the DACs is calibrated and then during thenext phase, the calibrated DAC is used in the feedback. Mean-while, the other DAC is calibrated. The major difference be-tween this implementation and previous DACs is that the cal-ibration is done during the return-to-zero phase. By using thisscheme, an extra DAC is not needed, which saves power and diearea.

DAC2, DAC3, and DAC4 requirements are more relaxedthan DAC1 because the gain of each preceding integrator stagereduces the impact of the corresponding DAC’s limitations[26]. Fig. 27 shows the implemented unity current cell of theseDACs. Dynamic current calibration is not used in this case;however; a diode-based common-mode hold circuit is used toavoid the DAC common-mode drift. During the zero phase,the PMOS current source and the NMOS current source areconnected to each other and because of the mismatches betweenthe current sources with their inherent high output impedance;the output can drift either to or . The diode divider setsthis common mode to a known voltage in less than half of aclock period so that neither of the current sources is pushed outof saturation. This scheme reduces transient glitches, therebyimproving modulator stability and the overall SQNR of themodulator.

H. Excess Loop Delay and Jitter

Fig. 28 shows a general discrete time modulator and itscontinuous time counterpart [34]. The discrete time modulatorand continuous time modulator are assumed equivalent if theerror signal e[n] in both modulators is equivalent. In the signal


Fig. 27. Implemented DAC2, DAC3, DCA4.

Fig. 28. Excess loop delay.

path, this equivalency is satisfied when an impulse-invarianttransformation is used to derive the continuous time transferfunction H(s).

The continuous time sigma delta loop, with emphasis on thefeedback DAC, and the clock signals used in the sigma deltamodulator are shown in Figs. 28 and 29, respectively. C1(t) isthe clock for the comparator, and C2(t) is the clock for the RZDAC used, C3(t) is the NRZ DAC pulse. These signals are gen-erated from a single clock, with a non-overlapping clock gener-ator. When C1(t) is zero, the comparator is kept at the auto-zerophase, where the regenerative latch is kept at center point. Attime T1, comparator is released; the design makes sure the com-parator latches before T2. From time T2 to T3 a quantized sam-pled signal is fed back with the current steering DACs, whereand are the turn on and turn off time of the DAC, respectively.The DAC architecture used is a RZ architecture, where the DACcurrent is turned on after the quantizer stabilizes, and is kept onfor half a clock cycle. The DAC pulse returns back to zero be-fore the next sampling cycle. As a result of this clocking, thisDAC architecture does not show any excess loop delay. Sincethe loop is closed before the next cycle, the sigma delta modu-lator is a cycle-to-cycle equivalent to the discrete counterpart.

Fig. 29. Jitter timing.

In the NRZ case, the feedback signal is turned on and off withthe comparator output. Because of the finite turn on time, ,and the finite turn off time, , actual current pulses are delayedfrom the comparator output. As a result of this delay, the nextsampling occurs before the full charge transfer, resulting in ex-cess loop delay. This characteristic leads to SNR degradationand higher signal distortion.

The effect of jitter in continuous-time SD modulators hasbeen previously studied [35]. The effect of a clock jitter is anincrease in the noise floor and then a reduction of the dynamicrange of the modulator. In a higher order modulator, com-parator input is de-correlated from signal amplitude. As a resultof this, the jitter effect of the quantizer is negligible. On the otherhand, jitter in the feedback DAC has major effects on modulatorperformance [35]. Because the DAC current is fed back to theintegrators during a clock phase, uncertainty of the turn on andturn off time of the current sources has a major effect on systemperformance. Fig. 30 shows the simulated SNR degradation dueto jitter on the designed fourth-order modulator. Effect onthe system performance is negligible if the clock jitter is lowerthan 10 pS.

V. IC DESIGN AND MEASUREMENTS

Fig. 31 shows the implemented DHA system. The analogfrontend is fabricated on a 0.25- m CMOS process whereasthe MEMS microphones are fabricated at the Arizona StateUniversity’s cleanroom facility with a custom MEMS process.The CT- modulator has a sampling frequency of 1 MHz;with an input signal bandwidth of 10 KHz. Fig. 32 shows themeasured modulator SNR against input amplitude. At


Fig. 30. Jitter model FFT.

Fig. 31. Micrograph of the dual-channel ADC and application board.

Fig. 32. Measured SNR versus input signal amplitude.

the highest quiescent power setting, the CT modulatorachieves 68-dB SNR, 65-dB SNDR, and 60-dB THD, respec-tively. Fig. 33 shows the measured signal transfer function of

Fig. 33. Measured transfer curve of the Sigma Delta ADC showing no peakingand channel gain flatness.

Fig. 34. Directivity index characterization of the dual microphone system.

the modulator. The measured frequency response is flatover the 10-kHz bandwidth, and does not show any frequencypeaking. The directivity index (DI) is defined by the ratio ofradiated sound intensity at a remote point on the principal axisof a loudspeaker or other transducer, to the average intensityof the sound transmitted through a sphere passing throughthe remote point and concentric with the transducer. A higherdirectivity index proves better phase and amplitude matchingbetween the audio signal chains. As shown in the Fig. 34after the gain calibration is performed, overall system achievesa directivity index of 5 at 1 kHz, which provides excellentrejection of sideband audio components.


VI. CONCLUSION

In this paper, a dual-channel, power-scalable transmitter front-end digital hearing aid is presented. The system can be integratedin a multichip module, which will reduce the costs of hearingaids while offering superior battery life and background noisesuppression. The MEMS microphone achieves a sensitivity of5.2 mV/Pa with 600-mV bias. Finally, the power scalablemodulator shows a 68-dB SNR over a 10-kHz bandwidth.

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Ilker Deligoz was born in Amasya, Turkey, in1979. He received the B.S. degree in electrical andeletronics engineering from Bilkent University,Turkey, in 2002, the M.S. degree in electrical en-gineering from Arizona State University, Tempe,in 2005, where he is currently pursuing the Ph.D.degree in electrical engineering.

He has completed several internships, one withIntel Corporation at the GSM RFIC DevelopmentGroup and one with Freescale Semiconductor Inc.at next-generation Cellular Power Amplifiers Re-

search and Development Group. He joined Qualcomm Corp., Chandler, AZ,as a Senior Electrical Engineer in 2008. His research interest is analog andmixed-signal solutions for power-management integrated circuits.

Syed R. Naqvi received the B.S. degree in electricalengineering from NED University of Engineeringand Technology, Karachi, Pakistan, in 1989, andthe M.S. degree in electrical engineering fromArizona State University, Tempe, in 1993, where heis currently pursuing the Ph.D. degree in microelec-tromechanical-systems interface circuit design fordigital hearing aids.

Currently, he is a Senior Staff Analog Engineerfor the Embedded Computing Group (ECG) at IntelCorp., Chandler, AZ. Previously, he worked on

digital module design, clocking, DLL, phase-locked loop, frequency dividers,bandgaps, digital-to-analog conversion, modulator design, and radio-frequencyreceivers.


Tino Copani (A’08) was born in Catania, Italy, in1972. He received the Laurea degree in electronicsengineering and the Ph.D. degree in electronicsand automation engineering from the Universityof Catania, Catania, Italy, in 1998 and 2004,respectively.

From 2000 to 2004, he was with the RadioFrequency Advanced Design Group, a joint researchgroup between the University of Catania and STMi-croelectronics, where he was involved in the designand development of radio-frequency integrated

circuits (RFICs) for satellite communications. In 2005, as a PostdoctoralResearch Associate, he joined Connection One Center, Arizona State Univer-sity, Tempe. His current research interest is the design of voltage-controlledoscillators, frequency synthesizers, and building blocks for low-power RFICsand monollithic microwave integrated circuits.

Sayfe Kiaei (S’86–M’87–SM’93–F’02) was aSenior Member of the Technical Staff with theWireless Technology Center and Broadband Op-erations at Motorola from 1993 to 2001, where hewas responsible for the development of wirelesstransceiver integrated circuits (ICs) and digitalsubscriber line (DSL) transceivers. Before joiningMotorola, he was an Associate Professor at OregonState University, Corvallis, from 1987 to 1993,where he taught courses and performed research indigital communications, very-large scale integration

system design, advanced complementary metal–oxide semiconductor inte-grated-circuit design, and wireless systems. Currently, he is a Professor and theDirector of the Connection One Center (NSF I/UCRC Center) at Arizona StateUniversity. His research interests are in wireless transceiver design as wellas RF and mixed-signal ICs in complementary metal–oxide semiconductorsand SiGe. He is currently the Associate Dean of Research at Arizona StateUniversity. He has published more than 100 journal and conference papers andholds several patents.

Prof. Kiaei is the recipient of the Carter Best Teacher Award, Oregon StateCollege of Engineering; IEEE Darlington Award; IEEE Fellow, and Motorola10X Design award. He is a member of the IEEE Circuits and Systems Society,IEEE Solid State Circuits Society, and IEEE Communication Society. He hasbeen on the technical program committee and/or chair of many conferences,including RFIC, MTT, ISCAS, and other international conferences.

Bertan Bakkaloglu (M’94–SM’08) received thePh.D. degree from Oregon State University, Cor-vallis, in 1995.

He joined Texas Instruments Incorporated’sMixed Signal Wireless Design Group, Dallas, TX,working on analog, RF, and mixed-signal front endsfor wireless and wireline communication integratedcircuits (ICs). As a Design Leader, he worked onsystem-on-chip designs with integrated batterymanagement and analog baseband functionality. In2004, he joined the Electrical Engineering Depart-

ment, Arizona State University, Tempe, AZ as an Associate Professor. Hisresearch interests include radio-frequency (RF) and power-amplifier supplyregulators, RF synthesizers, biomedical and instrumentation circuits andsystems, high-speed RF data converters, and RF built-in-self-test circuits forcommunication ICs.

Dr. Bakkaloglu has been a Technical Program Chair and Steering CommitteeMember for the IEEE RFIC conference and an Associate Editor of the IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS.

Sang-Soo Je received the M.S. degree in electricalengineering from the Georgia Institute of Tech-nology, Atlanta, in 2000 and the Ph.D. degree inelectrical engineering from Arizona State University,Tempe, in 2009.

From 2009 to 2010, he was a Research Engineerwith Silicon Audio, LLC, Austin, TX, developingoptical microphones and seismometers. Currently,he is a Postdoctoral Researcher in biomedicalengineering with the University of Texas at Austin,developing blood pressure/flow sensors. His research

interests are microelectromechanical-systems (MEMS) sensors/actuators, nan-otechnology, Bio MEMS, and radio-frequency MEMS.

Junseok Chae received the B.S. degree in metal-lurgical engineering from Korea University, Seoul,Korea, in 1998, and the M.S. and Ph.D. degrees inelectrical engineering and computer science fromthe University of Michigan, Ann Arbor, in 2000 and2003, respectively.

He joined Arizona State University in 2005 asan Assistant Professor and now he is an AssociateProfessor of electrical engineering. He has publishedmore than 75 journal and conference articles, twobook chapters, one book, and holds two U.S. patents.

His areas of interests are microelectromechanical (MEMS) sensors/actu-ators, MEMS-based biosensors, MEMS integration with electronics, andmicropackaging.

Dr. Chae received the first place prize and the best paper award in the De-sign Automation Conference student design contest in 2001. He received theNational Science Foundation Career award on MEMS protein sensor array.

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS …jchae2/Research_files/HearingAid...IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 5, NO. 3, JUNE 2011 201 A MEMS-Based Power-Scalable