www.ceibo.com

MCS-86

8086 – 8088 – 80C86 – 80C88

Ceibo In-Circuit

Emulator

Supporting

MCS-86:

DS-186

http://ceibo.com/eng/products/ds186.shtml

Chapter 1

Introduction

Manual Organization

8086 Family Architecture

Functional Distribution

- Microprocessors

- Interrupt Controller

- Bus Interface Components

Multiprocessing

Bus Organization

- Local Bus

- System Bus

- Processing Modules

- Bus Implementation Examples

Development Aids

Chapter 2

The 8086 and 8088 Central Processing Units

Processor Overview

Processor Architecture - Execution Unit

- Bus Interface Unit

- General Registers

- Segment Register

- Instruction Pointer

- Flags

- 8080 /8085 Register and Flag Correspondance

- Mode Selection

Memory -Storage Organization

- Segmentation

- Physical address Generation

- Dynamically Relocatable Code

- Stack Implementation

- Dedicated and Reserved Memory Locations

-8086/8088 Memory Access Differences

Input/Output - Input/Output Space

- Restricted I/O Locations

- 8086/8088 Memory Access Differences

- Memory-Mapped I/O

- Direct Memory Access

- 8089 Input/Output Processor (IOP)

Multiprocessing Features - Bus Lock

- WAIT and !TEST

- Escape

- Request / Grant Lines

- Multibus Architecture

-8289 Bus Arbiter

Processor Control and Monitoring - Interrupts

* External interrupts

* Internal Interrupts

* Interrupt Pointer Table

* Interrupt Procedures

* Single-step (Trap) Interrupt

* Breakpoint Interrupt

- System Reset

-Instruction Queue Status

- Processor halt

-Status Lines

Instruction Set - Data Transfer Instructions

* General Purpose Data Transfers

* Address Object Transfers

* Flag Transfers

- Arithmetic Instructions

* Arithmetic Data Formats

* Arithmetic Instructions and Flags

* Addition

* Substraction

* Multiplication

* Division

-Bit Manipulation Instructions

* Logical

* Shifts

* Rotates

-String instructions

- Program Transfer Instructions

* Unconditional Transfers

* Iteration Control

* Interrupts Instructions

- Processor Control Instructions

* Flag Operations

* External Synchronization

* No Operation

- Instruction Set Reference Information

Addressing Modes - Register and Immediates Operands

- Memory Addressing Modes

* The Effective Address

* Direct Addressing

* Register Indirect Addressing

* Based Addressing

* Indexed Addressing

* Based Indexed Addressing

* String Addressing

- I/O Addressing

Programming Facilities -Software Development Overview

-PL/M-86

* Statements and Comments

* Data Definition

* Assignment Statement

* Program Flow Statements

* Procedures

-ASM-86

* Statements

* Constants

* Defining Data

* Records

* Structures

* Addressing Modes

* Segment Controls

* Procedures

LINK-86

LOC-86

LIB-86

OH-86

CONV-86

Sample Programs

Programming Guidelines and Examples

- Programming Guidelines

* Segments and Segment Registers

* Self Modifying Code

* Input/output

* Operating Systems

* Interrupt Service Procedures

* Stack-Based Parameters

* Flag Images

- Programming Examples

* Procedures

* Jump and Calls

* Records

* Dynamic Code Relocation

* Memory-Mapped I/O

* Breakpoints

* Interrupt Procedures

* String Operations

Chapter 3

The 8089 INPUT / OUTPUT PROCESSOR

Processor Overview - Evolution

- Principles of Operation

* CPU/IOP Communications

* Channels

* Channel Programs (Task Blocks)

* DMA Transfers

* Bus Configurations

* A Sample Transaction

- Applications

Processor Architecture - Common Contro Unit (CCU)

- Arithmetic / Logic Unit (ALU)

- Assembly / Disassembly Registers

- Instruction Fetch Unit

- Bus Interface Unit (BIU)

Channels

* I/O Control

* Registers

* Program Status Word

* Tag Bits

* Concurrent Channel Operation

Memory - Storage Organization

- Dedicated and Reserved Memory Locations

- Dynamic Relacation

- Memory Access

Input /Output

- Programmed I/O

* I/O Instructions

* Device Addressing

* I/O Bus Transfers

- DMA Transfers

* Preparing the Device Controller

* Preparing the channel

* Beginning the Transfer

* DMA Transfer Cycle

* Following the Transfer

Multiprocessing Features - Bus Arbitration

* Request / Grant Line

* 8289 BusArbiter

* Bus Arbitration for IOP Configurations

- Bus Load Limit

- Bus Lock

Processor Control and Monitoring - Initialization

-Channel Commands

-DRQ (DMA Request)

-EXT (External Terminate)

-Interrupt

- Status Lines

Instruction Set - Data transfer Instructions

- Arithmetic Instructions

- Logical and Bit Manipulation Instructions

- Program Transfer Instructions

- Processor Control Instructions

- Instruction Set Reference Information

Addressing Modes - Register and Immediate Operands

-Memory addressing Modes

* The Effective Address

* Based Addressing

* Offset Addressing

* Indexed Addressing

* Index Auto-Increment Addressing

Programming Facilities ASM-89

- Statements

- Constants

- Defining Data

- Structures

- Addressing Modes

- Program Transfer Targets

- Procedures

- Segment Control

- Intermodule Communication

- Sample Program

- Linking and locating ASM-89 Modules

Programming Guidelines and Examples - Programming Guidelines

- Segments

-Self-Modifying Code

- I/O System Design

-Programming Examples

Initialization and Dispatch

Memory-to-Memory Transfer

Saving and Restoring Registers

Chapter 4

Hardware Reference Information

Introduction

8086 and 8088 CPUs - CPU Architecture

- Bus Operation

- Clock Circuit

- Minimum / Maximum Mode

* Minimum Mode

* Maximum Mode

- External Memory Addressing

- I/O Interfacing

- Interrupts

- Machine Instruction Encoding and Decoding

8086 Instruction Sequence

8089 I/O Processor -System Configuration

* Local Mode

* Remote Mode

- Bus Operation

- Initialization

- I/O Dispatching

- DMA Transfers

- DMA Termination

-Peripheral Interfacing

- Instruction Encoding