Lecture 2 Introduction to Computer Architecture Topics Representations of Data Computer Architecture C Programming Unsigned Integers Signed magnitude Two’s

Lecture 2Introduction to Computer

Architecture

Lecture 2Introduction to Computer

Architecture TopicsTopics

Representations of Data Computer Architecture C Programming Unsigned Integers Signed magnitude Two’s complement

January 12, 2011

CSCE 212 Computer Architecture

– 2 – CSCE 212H Spring 2011

Course PragmaticsCourse PragmaticsSyllabusSyllabus

Instructor: Amber Mckenzie Slides from Publisher


What is Computer Architecture?What is Computer Architecture?Computer Architecture is the attributes of a the attributes of a

[computing] system as seen by the programmer…, [computing] system as seen by the programmer…, as distinct from …the physical implementation. as distinct from …the physical implementation.

– Amdahl, Blaaw, and Brooks, 1964– Amdahl, Blaaw, and Brooks, 1964

The term computer architecture was first used in 1964 the designers of the IBM System/360.

The IBM/360 was a family of computers all with the same architecture, but with a variety of organizations(implementations).


Instruction Set ArchitectureInstruction Set Architecture


Register- Type (R-type) MIPS InstructionsRegister- Type (R-type) MIPS Instructions

R-type Instruction formatR-type Instruction format

Encoding Add r2, r4, r3 // R2 Encoding Add r2, r4, r3 // R2 R4 + R3 R4 + R3

Opcode for Add ? Opcode for Add ?

rsrs

rtrt

rdrd


MIPS MicroarchitectureMIPS Microarchitecture


Instruction Set ArchitectureInstruction Set ArchitectureInstruction Set Architecture:Instruction Set Architecture:1. abtraction that hides the low-level details of a processor from the user2. the interface between the hardware and software3. everything you need to know to “use” the processor:

instruction set instruction representations addressing modes etc…

““Families” of processors are defined by their ISA:Families” of processors are defined by their ISA: Sun Sparc Intel IA-32 MIPS IBM 360 Motorola/IBM PowerPC


ISAs TodayISAs Today


Processor ClassesProcessor Classes

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MIPS ISAMIPS ISA100 million MIPS processors manufactured in 2002100 million MIPS processors manufactured in 2002

MIPS processors used in:MIPS processors used in: Products from ATI, Broadcom, NEC, Texas Instruments, Toshiba SGI workstations Series2 TiVo Windows CE devices Cisco/Linksys routers Nintendo 64 Sony Playstation 1, PS2 (Emotion), PSP Cable boxes

Competes against XScale/ARM for cell phones

John L. Hennessy (Stanford, 1981)John L. Hennessy (Stanford, 1981) 1984: MIPS Computer Systems R2000 (1985), R3000 (1988), R4000 (64-bit, 1991) SGI acquisition (1992) => MIPS Technologies Transition to licensed IP: MIPS32 and MIPS64 (1999) “Heavyweight” embedded processor

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Lecture OutlineLecture OutlineInstruction Set ArchitecturesInstruction Set Architectures

MIPS ISAMIPS ISA

MIPS Instructions, Encoding, Addressing ModesMIPS Instructions, Encoding, Addressing Modes

MIPS Assembly ExamplesMIPS Assembly Examples

SPIMSPIM

Procedure Calling ConventionsProcedure Calling Conventions

I/OI/O

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MIPS MicroarchitectureMIPS Microarchitecture

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RISC vs. CISCRISC vs. CISCDesign “philosophies” for ISAs: RISC vs. CISCDesign “philosophies” for ISAs: RISC vs. CISC CISC = Complex Instruction Set Computer RISC = Reduced Instruction Set Computer

Tradeoff:Tradeoff: Execution time =

instructions per program * cycles per instruction * seconds per cycle

Problems with CISC:Problems with CISC: Compilers Off-chip memory references Complex control, unbalanced instruction set made parallelizing difficult

MIPS is the first implementation of a RISC architectureMIPS is the first implementation of a RISC architecture

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RISC vs. CISCRISC vs. CISCMIPS R2000 ISAMIPS R2000 ISA

Designed for use with high-level programming languagesEasy for compilersExample: mapping IA32 instruction CRC32 (accumulate CRC32

value)

Balance amount of work per instruction (pipelining)

Load-store machineForce user to minimize off-chip accesses

Fixed instruction width (32-bits), small set of uniform instruction encodings

Reduce implementation complexity

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MIPS ISAMIPS ISA



SPIMSPIM


I/OI/O

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MIPS Instruction TypesMIPS Instruction TypesMIPS instructions fall into 5 classes:MIPS instructions fall into 5 classes: Arithmetic/logical/shift/comparison Control instructions (branch and jump) Load/store Other (exception, register movement to/from GP registers, etc.)

Three instruction encoding formats:Three instruction encoding formats: R-type (6-bit opcode, 5-bit rs, 5-bit rt, 5-bit rd, 5-bit shamt, 6-bit function

code)

I-type (6-bit opcode, 5-bit rs, 5-bit rt, 16-bit immediate)

J-type (6-bit opcode, 26-bit pseudo-direct address)

– 17 – CSCE 212H Spring 2011

Partial MIPS Instruction Set (see Appendix. A)Partial MIPS Instruction Set (see Appendix. A)

Arithmetic R-type:Arithmetic R-type: addadd, addu, , addu, subsub, subu, subu

Arithmetic I-type:Arithmetic I-type: addi, addiuaddi, addiu

Logical R-type:Logical R-type: andand, , oror, , nornor, xor, xor

Logical I-type:Logical I-type: andiandi, , oriori, xori, xori

Compare R-type:Compare R-type: sltslt, sltu, sltu

Compare I-type:Compare I-type: sltislti, sltiu, sltiu

Shift R-type:Shift R-type: sllsll, sllv, , sllv, srlsrl, srlv, sra, srav, srlv, sra, srav

Load/Store I-type:Load/Store I-type: lui, lui, lwlw, lh, lhu, lb, lbu, , lh, lhu, lb, lbu, swsw, sh, sb, sh, sb

Branch I-type:Branch I-type: beq, bne, bgez, bgezal, bgtz, blez, blezal, bltz

Jump J-type:Jump J-type: jj, , jaljal

Jump R-type:Jump R-type: jrjr, jalr, jalr

OS support:OS support: syscallsyscall

Multiply/divide:Multiply/divide: mult, multu, div, divumult, multu, div, divu result held in 2 special registers (hi,lo)

Floating-point instructionsFloating-point instructions

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MIPS RegistersMIPS Registers

32 x 32-bit general purpose 32 x 32-bit general purpose integerinteger registers registers Some have special purposes These are the only registers the programmer can directly

use $0 => constant 0 $1 => $at (reserved for assembler) $2,$3 => $v0,$v1 (expression evaluation and results of a function) $4-$7 => $a0-$a3 (arguments 1-4) $8-$15 => $t0-$t7 (temporary values)

» Used when evaluating expressions that contain more than two operands (partial solutions)

» Not preserved across function calls $16-$23 => $s0->$s7 (for local variables, preserved across function calls) $24, $25 => $t8, $t9 (more temps) $26,$27 => $k0, $k1 (reserved for OS kernel) $28 => $gp (pointer to global area) $29 => $sp (stack pointer) $30 => $fp (frame pointer) $31 => $ra (return address, for branch-and-links)

Program counter (PC) contains address of next instruction to be Program counter (PC) contains address of next instruction to be executedexecuted

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Design ConsiderationsDesign ConsiderationsMost arithmetic instructions have 3 operands Most arithmetic instructions have 3 operands simplifies the hardwaresimplifies the hardware Limits the number of datapaths on the processor

Limiting to 32 registers speeds up register access Limiting to 32 registers speeds up register access timetime For memories, smaller is faster Influences clock cycle time

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ArithmeticArithmeticArithmetic (R-type) instructionsArithmetic (R-type) instructionsadd a,b,c a = b + c

sub a,b,c a = b - c

C code:C code: f = (g + h) – (i + j)

to…to…add t0,g,h

add t1,i,j

sub f,t0,t1

t0, t1, f, g, h, i, j must be registerst0, t1, f, g, h, i, j must be registers

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RegistersRegistersff, , gg, , hh, , ii, , jj in in $s0$s0, , $s1$s1, , $s2$s2, , $s3$s3, , $s4$s4

To…To…add $t0,$s1,$s2

add $t1,$s3,$s4

sub $s0,$t0,$t1

Similar instructions:Similar instructions: addu, subu and, or, nor, xor slt, sltu

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Encoding R-type InstructionsEncoding R-type Instructions

ADD $2, $3, $4ADD $2, $3, $4 R-type A/L/S/C instruction Opcode is 0’s, rd=2, rs=3, rt=4, func=100000 000000 00011 00100 00010 00000 100000

0000 0000 0110 0100 0001 0000 0010 0000 0000 0000 0110 0100 0001 0000 0010 0000 00641020

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Immediate InstructionsImmediate InstructionsSecond operand is a 16-bit Second operand is a 16-bit immediateimmediate

Signed (-32,768 to 32,767) or unsigned (0 to 65,535)Signed (-32,768 to 32,767) or unsigned (0 to 65,535)

Encoded with I-typeEncoded with I-type

addi $s0, $t0, -4addi $s0, $t0, -4

Similar I-type instructions:Similar I-type instructions: addiu andi, ori, xori lui

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Encoding I-Type Arithmetic/Logical/CompareEncoding I-Type Arithmetic/Logical/Compare

ADDI $2, $3, 12ADDI $2, $3, 12 I-type A/L/S/C instruction Opcode is 001000, rs=3, rt=2, imm=12 001000 00011 00010 0000000000001100

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Load Upper ImmediateLoad Upper ImmediateNeed more than 16 bits?Need more than 16 bits?

Example:Example: Initialize register $t0 with 1234567816

lui $t0, 1234 addi $t1, $0, 5678 or $t0, $t0, $t1

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Shift InstructionsShift InstructionsShift left-logical:Shift left-logical: 001010012 by 210 => 101001002

Multiply 4110 by 2210 = 16410

Shift right-logical:Shift right-logical: 001010012 by 210 => 000010102

Divide 4110 by 2210 (round down) = 1010

Shift right-arithmeticShift right-arithmetic 111101012 by 210 => 111111012

Divide -1110 by 2210 (round down) = -310

Amount (0-31) is encoded in SHAMT field for SLL, SRL, SRAAmount (0-31) is encoded in SHAMT field for SLL, SRL, SRA

Held in a register (rs field) for SLLV, SRLV, SRAVHeld in a register (rs field) for SLLV, SRLV, SRAV

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Load and StoreLoad and Store

Memory units:Memory units: word (32 bits, 4 bytes) halfword (16 bits, 2 bytes) byte (8 bits)

Assume Assume ff, , gg, , hh, , ii, , jj are stored are stored as words and contiguouslyas words and contiguously la $t2, f lw $s1,4($t2) lw $s2,8($t2) lw $s3,12($t2) lw $s4,16($t2) … sw $s0,0($t2)

• Similar instructions:

– lh, lhu, lb, lbu– sh, sb

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Encoding I-Type Load/StoreEncoding I-Type Load/Store

SW $2, 128($3)SW $2, 128($3) I-type memory address instruction Opcode is 101011, rs=00011, rt=00010, imm=0000000010000000 101011 00011 00010 0000000010000000

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Branch InstructionsBranch InstructionsBranch and jump instructions are required for program controlBranch and jump instructions are required for program control if-statements loops procedure calls

Unconditional branchUnconditional branch b <label>

Conditional branchConditional branch beq, bgez, bgezal, bgtz, blez

“and-link” variants write address of next instruction into $31 (only if branch is taken)

Branch targets are 16-bit immediate offset (offset in words)

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Encoding I-Type BranchEncoding I-Type Branch

BEQ $3, $4, 4BEQ $3, $4, 4 I-type conditional branch instruction Opcode is 000100, rs=00011, rt=00100, imm=4 (skips next 4 instructions) 000100 00011 00100 0000000000000100

Note:Note: bltz, bltzal, bgez, bgezal all have opcode 1, func in rt field

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Jump InstructionsJump InstructionsUnconditional branchUnconditional branch

Two types: R-type and J-typeTwo types: R-type and J-type

JR $31JR $31

JALR $3JALR $3 R-type jump instruction Opcode is 0’s, rs=3, rt=0, rd=31 (by default), func=001001 000000 00011 00000 11111 00000 001001

J 128J 128 J-type pseudodirect jump instruction Opcode is 000010, 26-bit pseudodirect address is 128/4 = 32 000010 00000000000000000000100000

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MIPS Addressing ModesMIPS Addressing ModesMIPS addresses register operands using 5-bit fieldMIPS addresses register operands using 5-bit field Example: ADD $2, $3, $4

MIPS addresses branch targets as signed instruction MIPS addresses branch targets as signed instruction offsetoffset relative to next instruction (“PC relative”) in units of instructions (words) held in 16-bit offset in I-type Example: BEQ $2, $3, 12

Immediate addressingImmediate addressing Operand is help as constant (literal) in instruction word Example: ADDI $2, $3, 64

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MIPS Addressing Modes (con’t)MIPS Addressing Modes (con’t)MIPS addresses jump targets as register content or MIPS addresses jump targets as register content or 26-bit “pseudo-direct” address26-bit “pseudo-direct” address Example: JR $31, J 128

MIPS addresses load/store locationsMIPS addresses load/store locations base register + 16-bit signed offset (byte addressed)

Example: LW $2, 128($3)

16-bit direct address (base register is 0)Example: LW $2, 4092($0)

indirect (offset is 0)Example: LW $2, 0($4)

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Integer Multiply and DivideInteger Multiply and Dividemult $2, $3mult $2, $3 result in hi (32 bits) and lo (32 bits) mul $2, $3, $4 is psuedo (low 32 bits) madd $2, $3 – multiply and accumulate in hi and lo

div $2, $3div $2, $3 quotient in lo and reminder in hi div $2, $3, $4 is psuedo (quotient)

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PseudoinstructionsPseudoinstructionsSome MIPS instructions don’t have direct hardware Some MIPS instructions don’t have direct hardware implementationsimplementations Ex: abs $2, $3

Resolved to:» bgez $3, pos» sub $2, $0, $3» j out» pos: add $2, $0, $3» out: …

Ex: rol $2, $3, $4 Resolved to:

» addi $1, $0, 32» sub $1, $1, $4» srlv $1, $3, $1» sllv $2, $3, $4» or $2, $2, $1

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MIPS ISAMIPS ISA



SPIMSPIM


I/OI/O

– 37 – CSCE 212H Spring 2011

Complex Arithmetic ExampleComplex Arithmetic Examplez=(a*b)+(c/d)-(e+f*g);z=(a*b)+(c/d)-(e+f*g);

lw $s0,alw $s0,a

lw $s1,blw $s1,b

mult $s0,$s1mult $s0,$s1

mflo $t0mflo $t0

lw $s0,clw $s0,c

lw $s1,dlw $s1,d

div $s0,$s1div $s0,$s1

mflo $t1mflo $t1

add $t0,$t0,$t1add $t0,$t0,$t1

lw $s0,elw $s0,e

lw $s1,flw $s1,f

lw $s2,glw $s2,g

mult $s1,$s2mult $s1,$s2

mflo $t1mflo $t1

add $t1,$s0,$t1add $t1,$s0,$t1

sub $t0,$t0,$t1sub $t0,$t0,$t1

sw $t0,zsw $t0,z

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If-StatementIf-Statementif ((a>b)&&(c==d)) e=0; else e=f;if ((a>b)&&(c==d)) e=0; else e=f;

lw $s0,alw $s0,a

lw $s1,blw $s1,b

bgt $s0,$s1,next0bgt $s0,$s1,next0

b nopeb nope

next0:next0: lw $s0,clw $s0,c

lw $s1,dlw $s1,d

beq $s0,$s1,yupbeq $s0,$s1,yup

nope:nope: lw $s0,flw $s0,f

sw $s0,esw $s0,e

b outb out

yup:yup: xor $s0,$s0,$s0xor $s0,$s0,$s0

sw $s0,esw $s0,e

out:out: ……

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For LoopFor Loopfor (i=0;i<a;i++) b[i]=i;for (i=0;i<a;i++) b[i]=i;

lw $s0,alw $s0,a

li $s1,0li $s1,0

loop0:loop0: blt $s1,$s0,loop1blt $s1,$s0,loop1

b outb out

loop1:loop1: sll $s2,S1,2sll $s2,S1,2

sw $s1,b($s2)sw $s1,b($s2)

addi $s1,$s1,1addi $s1,$s1,1

b loop0b loop0

out:out: ……

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Pre-Test While LoopPre-Test While Loopwhile (a<b) {while (a<b) {

a++;

}}

lw $s0,a

lw $s1,b

loop0: blt $s0,$s1,loop1

b out

loop1: addi $s0,Ss0,1

sw $s0,a

b loop0

out: …

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Post-Test While LoopPost-Test While Loopdo {do {

a++;

} while (a<b);} while (a<b);

lw $s0,a

lw $s1,b

loop0: addi $s0,$s0,1

sw $s0,a

blt $s0,$s1,loop0

…

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Complex LoopComplex Loopfor (i=0;i<n;i++) a[i]=b[i]+10;for (i=0;i<n;i++) a[i]=b[i]+10;

li $2,$0li $2,$0 # zero out index register (i)# zero out index register (i)

lw $3,nlw $3,n # load iteration limit# load iteration limit

sll $3,$3,2sll $3,$3,2 # multiply by 4 (words)# multiply by 4 (words)

la $4,ala $4,a # get address of a (assume < 2# get address of a (assume < 21616))

la $5,bla $5,b # get address of b (assume < 2# get address of b (assume < 21616))

j testj test

loop:loop: add $6,$5,$2add $6,$5,$2 # compute address of b[i]# compute address of b[i]

lw $7,0($6)lw $7,0($6) # load b[i]# load b[i]

addi $7,$7,10addi $7,$7,10 # compute b[i]=b[i]+10# compute b[i]=b[i]+10

add $6,$4,$2add $6,$4,$2 # compute address of a[i]# compute address of a[i]

sw $7,0($6)sw $7,0($6) # store into a[i]# store into a[i]

addi $2,$2,4addi $2,$2,4 # increment i# increment i

test:test: blt $2,$3,loopblt $2,$3,loop # loop if test succeeds# loop if test succeeds

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MIPS ISAMIPS ISA



SPIMSPIM


I/OI/O

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SPIMSPIM

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SPIMSPIMASM file must be edited with text editorASM file must be edited with text editor

Must have Must have mainmain label label

Must Must jr $31jr $31 at end at end

Use .data and .text to specify sectionsUse .data and .text to specify sections

Load source file into SPIMLoad source file into SPIM

Run, step, or use breakpointsRun, step, or use breakpoints

Appendix A is good referenceAppendix A is good reference

In-class example: ASCII to binary conversionIn-class example: ASCII to binary conversion

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Example CodeExample Code

.datamystr: .asciiz "2887"

.textmain: addi $s0,$0,0 # initialize $s0 (current value)

addi $s1,$0,0 # initialize $s1 (string index)addi $s3,$0,10 # initialize $s3 (value 10)

loop: lb $s2,mystr($s1)# load a character from stringbeqz $s2,done # exit if it's the NULL charactermul $s0,$s0,$s3 # multiply current value by 10

addi $s2,$s2,-48 # subtract 48 from character (convert to binary)add $s0,$s0,$s2 # add converted value to current value

addi $s1,$s1,1 # add one to indexb loop # loop

done: jr $31 # return to OS

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MIPS ISAMIPS ISA



SPIMSPIM


I/OI/O

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ProceduresProceduresJAL, JALR, and BGEZAL are designed to call JAL, JALR, and BGEZAL are designed to call subroutinessubroutines

Return address is linked into $31 ($ra)Return address is linked into $31 ($ra)

Need to:Need to: save the return address on a stack to save the return

address save the state of the callee’s registers on a stack have a place for arguments have a place for return value(s)

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Memory AllocationMemory Allocation

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The StackThe StackStack is designed to hold variable-sized recordsStack is designed to hold variable-sized records

Stack grows downStack grows down

Normally the old $fp must be stored in the AR to popNormally the old $fp must be stored in the AR to pop

Don’t need $fp for fixed-sized AR’sDon’t need $fp for fixed-sized AR’s

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A Simple Procedure Calling ConventionA Simple Procedure Calling Convention

Caller:Caller: Place arguments in $a0 - $a3 (limit to 4) Jump-and-link or branch-and-link to subroutine

Callee:Callee: Pushes an activation record onto the stack (decrement $sp) Save the return address ($ra) on the AR Save registers $s0 - $s7 on the AR Perform computation Save return values to $v0 and $v1 Restore $s0 - $s7 Restore $ra JR $ra

Caller:Caller: Reads $v0 and $v1 and continues

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NotesNotesThis convention:This convention: Limited to 4 arguments and 2 return values (bad!) Doesn’t save $t0 - $t9, $v0 - $v1, and $a0 - $a3 (bad!) Doesn’t allow (variable-size) space on the AR for argument list (saves regs) Doesn’t allow (variable-size) space on the AR for callee’s local variables

(bad!) Doesn’t allow space on the AR for return value (saves regs) Fixed AR size (good!) Doesn’t require the caller to prepare and/or teardown the AR (good!)

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Stack ExampleStack Example

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A Simple Procedure Calling ConventionA Simple Procedure Calling Convention

comp: …

add $s0,$s1,$s2

jal fact

fact: add $sp,$sp,-36

sw $s0,0($sp)

sw $s1,4($sp)

…

sw $ra,32($sp)

…

lw $s0,0($sp)

lw $s1,4($sp)

…

lw $ra,32($sp)

add $sp,$sp,36

jr $ra

(instruction after jal fact)

$ra for comp

$sn for comp’s caller

$sp

$sp+36

$ra for comp

$sn for comp’s caller

$sp+36

$sp+72

$ra for fact

$sn for comp caller

$sp

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ExampleExamplefact:fact:

sltislti $t0,$a0,3$t0,$a0,3 # test for n < 3# test for n < 3

beqbeq $t0,$zero,L1$t0,$zero,L1 # if n >= 1, go to L1# if n >= 1, go to L1

addiaddi $v0,$zero,2$v0,$zero,2 # return 2# return 2

jrjr $ra$ra # return# return

L1:L1:

addiaddi $sp,$sp,-8$sp,$sp,-8 # allocate space for 2 items# allocate space for 2 items

swsw $ra,4($sp)$ra,4($sp) # save return address# save return address

swsw $a0,0($sp)$a0,0($sp) # save argument# save argument

addiaddi $a0,$a0,-1$a0,$a0,-1 # set argument to n-1# set argument to n-1

jaljal factfact # recurse# recurse

lwlw $a0,0($sp)$a0,0($sp) # restore original argument# restore original argument

lwlw $ra,4($sp)$ra,4($sp) # restore the return address# restore the return address

addiaddi $sp,$sp,8$sp,$sp,8 # pop 2 items# pop 2 items

mulmul $v0,$a0,$v0$v0,$a0,$v0 # return value = n * fact(n-1) -glad we saved # return value = n * fact(n-1) -glad we saved $a0$a0

jrjr $ra$ra # go back to caller# go back to caller

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MIPS ISAMIPS ISA



SPIMSPIM


I/OI/O

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I/OI/OI/O is performed with reserved instructions / memory I/O is performed with reserved instructions / memory spacespace

Performed by the operating system on behalf of user Performed by the operating system on behalf of user codecode

Use syscall instructionUse syscall instruction

Call code in $v0 and argument in $a0Call code in $v0 and argument in $a0

Return value in $v0 (or $f0)Return value in $v0 (or $f0)

SPIM services:SPIM services:

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ExampleExample.data.data

str:str: .asciiz.asciiz “the answer = ““the answer = “

.text.text

lili $v0,4$v0,4

lala $a0, str$a0, str

syscallsyscall

lili $v0,1$v0,1

lala $a0,5$a0,5

syscallsyscall

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Example ExerciseExample ExerciseCopy words from the address in register $a0 to the address in register $a1, Copy words from the address in register $a0 to the address in register $a1, counting the number of words in $v0counting the number of words in $v0

Stops when 0 is readStops when 0 is read

Do not preserve $a0, $a1, $v0Do not preserve $a0, $a1, $v0

Terminating word should be copied but not countedTerminating word should be copied but not counted

addi $v0, $zero, 0addi $v0, $zero, 0

loop:loop: lw $v1, 0($a0)lw $v1, 0($a0)

sw $v1, 0($a1)sw $v1, 0($a1)

addi $a0, $a0, 4addi $a0, $a0, 4

addi $a1, $a1, 4addi $a1, $a1, 4

beq $v1, $zero, loopbeq $v1, $zero, loop

– 60 – CSCE 212H Spring 2011

Example ExerciseExample ExerciseTranslate from binary to assembly:Translate from binary to assembly:

AE0B0004AE0B0004

8D0800408D080040

Change MIPS:Change MIPS:8 registers

10 bit immediate constants

What is the new size of R and I type instructions?

– 61 – CSCE 212H Spring 2011

Example ExerciseExample Exercise

Extract the bits from field in register $t0 and place Extract the bits from field in register $t0 and place them into the least significant bits of $t1them into the least significant bits of $t1

i = 22, j = 5i = 22, j = 5

31-i bits i-j bits j bits

field

Documents

Lecture 2 Introduction to Computer Architecture Topics Representations of Data Computer Architecture C Programming Unsigned Integers Signed magnitude Two’s