Designed and Presented by

Dr. Ayman Elshenawy Elsefy

Dept. of Systems & Computer Eng..

Al-Azhar University

Email : eaymanelshenawy@yahoo.com

eaymanelshenawy.wordpress.com

Lectures on Memory Interface

Chapter 11: Basic I/O Interface

Lecture 5: Interrupts

Chapter Objectives

• Explain the interrupt structure of the Intel family of MP.

• Explain the operation of software interrupt instructions INT,INTO, INT 3, and BOUND.

• Explain how the interrupt enable flag bit (IF) modifies theinterrupt structure.

• Describe the function of the trap interrupt flag bit (TF) andthe operation of trap-generated tracing.

• Develop interrupt-service procedures that control lower-speed, external peripheral devices.

• Expand the interrupt structure of the microprocessor byusing the 82S9A programmable interrupt controller andother techniques.

• Explain the purpose and operation of a real-time clock.

Purpose of interrupt

• Interrupts are useful when interfacing I/O devices thatprovide or require data at relatively low data transfer rates.

• A keyboard example, Unlike the polling technique, interruptprocessing allows the MP to execute other software whilethe keyboard operator is thinking about what key to typenext. As soon as a key is pressed, the keyboard encoderdebounces the switch and puts out one pulse thatinterrupts the MP.

• The MP executes other software until the key is actuallypressed, when it reads a key and returns to the programthat was interrupted. As a result, the MP can print reportsor complete any other task while the operator is typing adocument and thinking about what to type next.

Purpose of interrupt• Figure 12-1 shows a time line that indicates a typist typing data

on a keyboard, a printer removing data from the memory, and aprogram executing. The program is the main program that isinterrupted for each keystroke and each character that is toprint on the printer. Note that the keyboard interrupt serviceprocedure, called by the keyboard interrupt, and the printerinterrupt service procedure each take little time to execute.

Interrupt

• The interrupts of the entire Intel family of microprocessorsinclude two hardware pins that request interrupts (INTRand NMI), and one hardware pin ( 𝐼𝑁𝑇𝐴 ) thatacknowledges the interrupt requested through INTR.

• In addition to the pins, the microprocessor also hassoftware interrupts INT, INTO, INT 3, and BOUND.

• Two flag bits, IF (interrupt flag) and TF (trap flag), are alsoused with the Interrupt structure and a special returninstruction, IRET (or IRETD in the 80386, 80486, orPentium–Pentium 4).

Interrupt Vector Table

• The interrupt vector table is located in the first 1024 bytesof memory at addresses 000000H–0003FFH. It contains 256different four-byte interrupt vectors.

• An interrupt vector contains the address of the interruptservice procedure (ISP).

• Figure 12–2 illustrates the interrupt vector table for themicroprocessor.

• Intel reserves the first 32 interrupt vectors for their use invarious microprocessor family members. The last 224vectors are available as user interrupt vectors. Each vectoris four bytes long in the real mode and contains the startingaddress of the ISP.

Interrupt Vector Table

• The interrupt vector table for the microprocessor and the contents of an interrupt vector.

Dedicated Interrupts in MP

• TYPE 0 The divide error whenever the result from a divisionoverflows or an attempt is made to divide by zero.

• TYPE 1 Single-step or trap occurs after the execution ofeach instruction if the trap (TF) flag bit is set. Uponaccepting this interrupt, the TF bit is cleared so that the ISPexecutes at full speed.

• TYPE 2 The non-maskable interrupt occurs when a logic 1is placed on the NMI input pin to the MP. This input is non-maskable, which means that it cannot be disabled.

• TYPE 3 A special one-byte instruction (INT 3) that uses this vector to access its ISP. The INT 3 instruction is often used to store a breakpoint in a program for debugging.

Dedicated Interrupts in MP• TYPE 4 Overflow is used with the INTO instruction. The INTO

instruction interrupts the program if an overflow conditionexists, as reflected by the overflow flag (OF).

• TYPE 5 The BOUND instruction compares a register withboundaries stored in the memory. If the contents of theregister are greater than or equal to the first word inmemory and less than or equal to the second word, nointerrupt occurs (the register contents are within bounds).If the register contents are out of bounds, type 5 interruptensues.

• TYPE 6 An invalid opcode interrupt occurs whenever anundefined opcode is encountered in a program.

• TYPE 7 The coprocessor not available interrupt occurs whena coprocessor is not found in the system.

Dedicated Interrupts in MP• TYPE 8 A double fault interrupt is activated whenever two

separate interrupts occur during the same instruction.

• TYPE 13 The general protection fault occurs for mostprotection violations in the 80286–Core2 protected modesystem. (These errors occur in Windows as generalprotection faults.) such as

– Privilege rules violated

– Write to code segment that is protected

• Type: 14: Page fault interrupts occur for any page faultmemory or code access in the MP.

Interrupt Instruction1. BOUND instruction, which has two operands, compares a

register with two words of memory data. For example, ifthe instruction BOUND AX,DATA is executed, AX iscompared with the contents of DATA and DATA+1 and alsowith DATA+2 and DATA+3. If AX is less than or greater thanthe contents of DATA and DATA+1, a type 5 interruptoccurs. If AX is within the bounds of these two memorywords, no interrupt occurs.

2. INTO instruction checks or tests the overflow flag (O). If O= 1, the INTO instruction calls the procedure whoseaddress is stored in interrupt vector type number 4. If O =0, then the INTO instruction performs no operation andthe next sequential instruction in the program executes.

Interrupt Instruction3. INT n instruction calls the ISP that begins at the address

represented in vector number n. For example, an INT 80Hor INT 128 calls the ISP whose address is stored in vectortype number 80H (000200H–00203H), multiply the vectortype number (n) by 4, which gives the beginning addressof the four-byte long interrupt vector. For example, INT 5 =4 × 5 or 20 (0014H-0017H. Each INT instruction is stored intwo bytes of memory: opcode, the interrupt type number.

• The only exception to this is the INT 3 instruction, a one-byte instruction. The INT 3 instruction is often used as abreakpoint-interrupt because it is easy to insert a one-byteinstruction into a program. Breakpoints are often used todebug faulty software.

Interrupt Instruction4. The IRET instruction is a special return instruction used to

return for both software and hardware interrupts. The IRET instruction is much like a far RET, because it retrieves the return address from the stack.

The Operation of a Real Mode Interrupt• When the MP completes executing the current instruction,

it determines whether an interrupt is active by checkinginterrupt conditions such as instruction executions, NMI,INTR, and INT instructions. If one or more of interruptconditions are present, the following sequence of eventsoccurs:

– The contents of the flag register are pushed onto the stack.

– Both the interrupt (IF) and trap (TF) flags are cleared. Thisdisables the INTR pin and the trap feature.

– The contents of the code segment register (CS) and instructionpointer (IP) are pushed onto the stack.

– The interrupt vector contents are fetched, and then placed intoboth IP and CS so that the next instruction executes at theinterrupt service procedure addressed by the vector.

Interrupt Flag bits• The interrupt flag (IF) and the trap flag (TF) are both

cleared after the contents of the flag register are stackedduring an interrupt.

• When the IF bit is set, it allows the INTR pin to cause aninterrupt; when the IF bit is cleared, it prevents the INTRpin from causing an interrupt.

• When TF = 1, it causes a trap interrupt (type number 1) tooccur after each instruction executes. This is why we oftencall trap a single-step. When TF = 0, normal programexecution occurs. This flag bit allows debugging.

• The interrupt flag is set and cleared by the STI and CLIinstructions, respectively. There are no special instructionsthat set or clear the trap flag.

Interrupt Flag bits

Interrupt Flag bits

Hardware InterruptThe microprocessor has two hardware interrupt inputs:

• non-maskable interrupt (NMI) and Whenever the NMIinput is activated, a type 2 interrupt occurs because NMI isinternally decoded.

• Interrupt request (INTR). The INTR input must be externallydecoded to select a vector. Any interrupt vector can bechosen for the INTR pin, but we usually use an interrupttype number between 20H and FFH.

Non-Maskable Interrupt (NMI)• Is an edge-triggered input that requests an interrupt on the

positive edge (0-to-1 transition). After a positive edge, theNMI pin must remain a logic 1 until it is recognized by themicroprocessor. Note that before the positive edge isrecognized, the NMI pin must be a logic 0 for at least twoclocking periods.

• The NMI input is often used for parity errors and other major system faults, such as power failures. Power failures are easily detected by monitoring the AC power line and causing an NMI interrupt whenever AC power drops out. In response to this type of interrupt, the microprocessor stores all of the internal register in a battery-backed-up memory or an EEPROM.

Non-Maskable Interrupt (NMI)• Figure 12–6 shows a power failure detection circuit that

provides a logic 1 to the NMI input whenever AC power is interrupted.

Non-Maskable Interrupt (NMI)• In this circuit, an optical isolator provides isolation from the

AC power line. The output of the isolator is shaped by a Schmitt-trigger inverter that provides a 60 Hz pulse to the trigger input of the.

• If the AC power fails, the 74LS122 no longer receives trigger pulses from the 74ALS14, which means that Q becomes a logic 0 and becomes a logic 1, interrupting the MP through the NMI pin. The ISP, not shown here, stores the contents of all internal registers and other data into a battery-backed-up memory.

Non-Maskable Interrupt (NMI)

Figure 12–7 shows a circuit that supplies power to a memory after the DC power fails.Here, diodes are used to switch supply voltages from the DC power supply to the battery. Thediodes used are standard silicon diodes because the power supply to this memory circuit is elevated above +5.0 V to +5.7 V. The resistor is used to trickle-charge the battery, which is eitherNiCAD, lithium, or a gel cell.When DC power fails, the battery provides a reduced voltage to the VCC connection on thememory device. Most memory devices will retain data with VCC voltages as low as 1.5 V, so thebattery voltage does not need to be +5.0 V. The pin is pulled to VCC during a power outage,so no data will be written to the memory.

INT and INTA• The interrupt request input (INTR) is level-sensitive, which

means that it must be held at a logic 1 level until it isrecognized.

• The INTR pin is set by an external event and cleared insidethe ISP.

• This input is automatically disabled once it is accepted bythe microprocessor and re-enabled by the IRET instructionat the end of the ISP.

• The microprocessor responds to the INTR input by pulsingthe output in anticipation of receiving an interrupt vectortype number on data bus connections D7–D0.

• Figure 12–8 shows the timing diagram for the INTR andpins of the microprocessor. There are two pulsesgenerated by the system that are used to insert the vectortype number on the data bus.

INT and INTA• Figure 12–8 shows the timing diagram for the INTR and

pins of the microprocessor. There are two pulsesgenerated by the system that are used to insert the vectortype number on the data bus.

INT and INTA• Figure 12–9 illustrates a simple circuit that applies

interrupt vector type number FFH to the data bus inresponse to an INTR. Notice that the INTA pin is notconnected in this circuit.