Multilevel Buck/Boost-Type DC–DC Converter for High-Power ... em periódicos/64... · boost-type multilevel dc–dc converter suitable for high-power and medium/high-voltage application

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 6, NOVEMBER/DECEMBER 2014 3931

Multilevel Buck/Boost-Type DC–DC Converter forHigh-Power and High-Voltage Application

Levy Ferreira Costa, Samir Ahmad Mussa, Member, IEEE, and Ivo Barbi, Fellow, IEEE

Abstract—This paper presents a new nonisolated buck/boost-type multilevel dc–dc converter suitable for high-power andmedium/high-voltage application. The main features of the pro-posed topology are as follows: low voltage across the semiconduc-tors, low switching losses, and reduced volume of the output filter.The theoretical analysis is carried out for a five-level bidirectionalstructure of the proposed converter, operating in Buck mode. Theproposed topology presents some capacitors, and their voltagemust be balanced for proper operation of the converter. Thus,a capacitor voltage balancing active control using a feedforwardtechnique is proposed and analyzed in detail. In order to validatethe theoretical analysis, a prototype with 10 kW output powercapability, 1.3 kV to 800 V input-to-output voltage, and 20 kHzof switching frequency was built and experimented. The resultsattest the advantages of the new dc–dc topology, as well as the newcapacitor voltage control technique.

Index Terms—Bidirectional power flow, dc–dc power convert-ers, linear feedback control systems.

I. INTRODUCTION

M EDIUM-VOLTAGE (MV) and high-voltage (HV) high-power dc–dc converters have been intensively inves-

tigated to be used in several applications such as largeoffshore wind farms (3–6 MW) [1]–[7], subsea compressorsin offshore oil and gas applications (6–80 MW) [8], [9], andHV dc (HVDC) transmission system applications (>100 MW)[10], [11]. As a particular example, Fig. 1 shows a simplifiedblock diagram of a future dc subsea electric transmission anddistribution system for oil and gas production, as reported in[9]. In this application, an HV dc–dc converter is required, ashighlighted in Fig. 1, to step down the HV to MV, in orderto feed the distribution system composed by variable-speeddrivers. Nevertheless, this kind of converter is still a challengeto power electronics due to the technological limitation of semi-

Manuscript received August 9, 2013; revised January 14, 2014; acceptedFebruary 25, 2014. Date of publication March 25, 2014; date of currentversion November 18, 2014. Paper 2013-IPCC-620.R1, presented at the 2012IEEE/IAS International Conference on Industry Applications, Fortaleza, Brazil,November 5–7, and approved for publication in the IEEE TRANSACTIONS ON

INDUSTRY APPLICATIONS by the Industrial Power Converter Committee ofthe IEEE Industry Applications Society.

L. F. Costa was with the Power Electronics Institute (INEP), Federal Univer-sity of Santa Catarina (UFSC), 88040-470 Florianopolis, Brazil. He is now withSchneider Electric, 61760-000 Fortaleza, Brazil (e-mail: [email protected]).

S. A. Mussa and I. Barbi are with the Power Electronics Institute (INEP),Federal University of Santa Catarina (UFSC), 88040-470 Florianopolis, Brazil(e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIA.2014.2313715

Fig. 1. Simplified block diagram of the future dc subsea electric transmissionand distribution system, employing an HV dc–dc converter.

conductors available in the market, mainly about its blockingvoltage.

Currently, the most used semiconductors for HV applicationare the integrated gate-commutated thyristor (IGCT; with thebreakdown voltage rated up to 6.9 kV) [12] and the HV insu-lated gate bipolar transistor (IGBT; with the maximum blockingvoltage rated up to 6.5 kV) [13]. However, those devices stillhave very high switching losses; thus, in practice, the switchingfrequency is limited to about 1 kHz [13]. For high-switching-frequency operation (>10 kHz), the most attractive switchesare the MOSFET and IGBT (up to the 1200-V blocking voltageclass). On the other hand, these switches are unattractive forHV and high-power application.

Therefore, for HV and high-frequency operation, conven-tional dc–dc converters are not the best choice. Some commonsolutions of dc–dc converters with high-frequency operationapplied to high voltage have been described in the literature,and they will be discussed here.

The first solution is based on an isolated converter, with twolegs of a full-bridge converter connected in series in the primaryside, as proposed in [14]. The voltage across the switches is halfof the input voltage. An extension of this topology is presentedin [15] and [16], in which the authors have used three legsof a full-bridge converter connected in series in the primaryside, associated with a three-phase high-frequency transformer.Although these converters present reduced voltage stress onthe switches, their application is limited to 10 kV of the inputvoltage since the voltage across the switches is always one third(or one half) of the input voltage. In order to reduce the voltageacross the switches even more, it is necessary to increase thenumber of full-bridge legs connected in series in the primaryside, as well as the quantity of phase in the transformer. Thus,the extension of this topology becomes very complex.

Another common solution is to employ low-voltage con-verters with series-input and parallel-output connections, as

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3932 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 6, NOVEMBER/DECEMBER 2014

Fig. 2. Proposed multilevel dc–dc converter. (a) Buck-type topology. (b) Boost-type topology. (c) Bidirectional topology.

described in [17]. This converter has the features of low voltageacross switches and modularity, and it can be extended regard-less of the input voltage. On the other hand, the output voltageis always very low; thus, it is limited to application that requireshigh input and low output voltage.

A series connection of semiconductors, as presented in [18]and [19], is also commonly found in the literature. The mainadvantage of this technique is modularity. The drawback isthe necessity of a complex balancing circuit, which takes intoconsideration the static and dynamic characteristics of semicon-ductors, as presented in [18] and [19].

Within this context, this paper presents a novel nonisolatedmultilevel dc–dc converter suitable for HV and high-powerapplication, such as presented in Fig. 1. The proposal includesthe buck-type, boost-type, and bidirectional topologies, and allgeneralized topologies are shown in Fig. 2. The buck- andboost-type converters were previously introduced in [20] and[21], respectively. The application described in Fig. 1 does notrequire isolation of the HV dc–dc converter; thus, the proposedbuck-type multilevel converter [see Fig. 2(a)] is appropriate forthis application. The main features of the proposed convertersare as follows: reduced voltage across the semiconductors, lowswitching losses, reduced output filter volume, and low voltageacross the inner capacitors. The most critical component of themultilevel dc–dc converter is the capacitors C1 and C2 becausethey are submitted to high voltage (half of the input voltage).On the other hand, most of HV converters also present thesefeature [14]–[16], [18]. According to the input voltage value, aseries connection of capacitors may be necessary.

For proper operation of the proposed multilevel converter, thecapacitors must have their voltage balanced all the time. Somevoltage balancing techniques were proposed in the literature, asshown in [22]–[24]. In an effective passive technique proposedby Salta [22], the authors added RLC circuits to performthe balancing voltage, increasing the losses of the converter.For medium- and high-power application, the increased lossescaused by the balancing circuit might be significant, invalidat-ing this technique for the proposed application. In [22] and [24],a capacitor voltage balancing strategy based on active controlwas employed to regulate the capacitor voltages of a three-level converter. The technique consists in a voltage balancing

Fig. 3. Proposed and studied five-level dc–dc converter.

TABLE IOPERATION REGION OF THE FIVE-LEVEL CONVERTER

control loop incorporated to the main control system. It doesnot require additional components, but only measurement ofvoltage capacitors. Since the voltage sense is simple to beimplemented, the present technique becomes very attractive.Thus, this technique is employed in this paper, and it is analyzedin detail.

In addition to the proposal of the dc–dc multilevel converter,this paper presents as additional contribution the completeinvestigation of the capacitor voltage balancing active controland the proposal of a feedback control, which improves thedynamic response of the capacitor voltage in light loads. Thistopic is addressed in Section IV of this paper.

The complete converter analysis, including the capacitorvoltage balancing control, is carried out for a five-level bidi-rectional proposed converter, as shown in Fig. 3, operating in

COSTA et al.: MULTILEVEL BUCK/BOOST-TYPE DC–DC CONVERTER FOR HIGH-POWER AND HV APPLICATION 3933

TABLE IIDESCRIPTION OF CAPACITOR CURRENTS IN EACH TOPOLOGICAL STATE OF THE PROPOSED FIVE-LEVEL CONVERTER

buck mode, i.e., the power flows from Vi to Vo. The theoreticalanalysis, capacitor voltage balancing active control, as well asexperimental results are shown in this paper. The primary goalof the prototype is to confirm the analytically studied convertercapabilities by experimental results. Hence, a 10-kW, 1.3-kV to800-V input-to-output voltage prototype was built, tested, andevaluated to confirm the theoretical analysis.

II. THEORETICAL ANALYSIS

The theoretical analysis is performed for the topology shownin Fig. 3, operating in buck, steady-state, and continuous-conduction modes. Therefore, the voltage over the semicon-ductors and the capacitors C3 and C4 is Vi/4, whereas thevoltage across the capacitors C1 and C2 is Vi/2, where Vi isthe input voltage. As cited above, the capacitor voltages mustbe balanced for the correct operation of the proposed converter.Therefore, the modulation strategy should enable the chargeand discharge of these capacitors, so that balancing voltage con-trol may be performed. Here, the modulation strategy and thefour operation regions of the five-level converter are described.The switching states and main waveforms for each operationregion are shown and explained. The mathematical expressionof the output–input voltage relationship (static gain) is derived,such as the inductor current ripple and the capacitor voltageripple. The current and voltage effort in the components of theproposed converter is also presented.

A. Modulation Strategy, Switching States,and Main Waveforms

The adopted modulation strategy is based on phase-shiftpulsewidth modulation (PWM), with four triangular carriersshifted off 90◦. Each carrier is used to generate the gatingsignal of the switches S1, S2, S7, and S8. The gating signalsof the switches S3, S4, S5, and S6 are generated from thegating signal of the switches S1, S2, S7, and S8, respectively,using complementary logic. This modulation technique allows

the charge and discharge of the capacitors individually, makingpossible the implementation of the capacitor voltage balancingstrategy based on active control. This control is discussedin Section III. Using this modulation strategy, the five-levelconverter presents four operation regions, according to the duty-cycle value D, as described in Table I. The region of operationdefines the output voltage limits, as shown in Table I.

As the five-level converter has four independent switches(S1, S2, S7, and S8), it implies 16 combinations and 16switching states consequently. Table II shows the states of theswitches, the loading current of the capacitors, the voltage vaas a combination of the capacitor voltage, and the instanta-neous value of the unfiltered output voltage va, for all switch-ing states. As can be observed, the converter has redundantswitching states that give the same output voltage but differ-ent capacitor loadings. Thus, the proposed converter presentsenough switching states to ensure the voltage balancing of thecapacitors.

Fig. 4 shows the main waveforms for one switching periodTs of the five-level proposed converter, considering the fouroperations regions described earlier. The switching states ofthe five-level converter are also indicated in this figure. Ascan be seen, some switching states are not available in thismodulation strategy. Moreover, for one operation region, onlyfew switching states are used.

The operation frequency of voltage va and, consequently,inductor current iL is four times the switching frequency. Inaddition to that, the volt-second across the inductor is mini-mized due to the reduced voltage across the inductor. Therefore,a reduced inductor volume is expected for this topology.

Table III shows the time interval during the storage energystage t1 and the transfer energy stage t2, as illustrated in Fig. 4,for the four operation regions.

B. Static Gain

In order to obtain the output–input voltage relationship of thefive-level converter, operating in buck mode, the volt-second


Fig. 4. Main waveforms of the proposed five-level converter, including thegating signals of the switches, unfiltered output voltage va, inductor current,current through the capacitors, and, finally, the switching states, for all opera-tion regions. (a) Region R1. (b) Region R2. (c) Region R3. (d) Region R4.

TABLE IIITIME INTERVAL FOR CHARGE AND DISCHARGE OF

THE INDUCTOR FOR ALL OPERATION REGIONS

balance of the inductor L for one fourth of the switching periodis analyzed, i.e.,

4

TS

to+TS4∫

to

vL(t)dt = 0. (1)

Considering that the converter is operating in region R1(see Fig. 4) and using (1), the following expression is obtained:(

Vi

4− Vo

)DTs = Vo

(1

4−D

)Ts. (2)

Rearranging (2), the mathematical expression of the staticgain as a function of duty cycle D is obtained, as shown in the

Fig. 5. Normalized inductor current ripple of the five-level converter and theconventional two-level converter.

following equation:

Vo

Vi= D. (3)

This equation shows that the static gain of the five-level con-verter operating in buck mode is the same as that of the conven-tional two-level buck converter. This analysis was carried outconsidering the converter operating in region R1. On the otherhand, expression (3) is valid regardless of the operation region.

C. Inductor Current Ripple

The current ripple in the inductor can be calculated duringthe storage energy stage or the transfer energy stage and usingthe following expression:

ΔiL =1

L

t1∫0

vL(t)dt. (4)

The time interval t1 has different values, depending on theoperation region, and it is obtained from Table III.

The inductor current ripple has different behaviors, accordingto the operation region. Thus, (4) must be used for all operationregions of the five-level converter. By doing this, the currentripple equation for each operation region is obtained, as shownin the following equation:

ΔiL =

⎧⎪⎪⎪⎪⎨⎪⎪⎪⎪⎩

Vi

4fSL (1− 4D)D, D < 14

Vi

4fSL(1−2D)(4D−1)

2 , 14 ≤ D < 1

2Vi

4fSL(3−4D)(2D−1)

2 , 12 ≤ D < 3

4Vi

4fSL (1−D)(4D − 3), 34 ≤ D < 1

(5)

where fS is the switching frequency.Fig. 5 shows the normalized current ripple of the inductor

for the five-level converter and the conventional two-level con-verter. The normalization is given by ΔiL = ΔiL4fSL/Vi. Asexpected, the inductor current presents reduced ripple. Compar-ing with the conventional two-level converter, the current rippleis reduced in 16 times for the five-level converter. Furthermore,the inductor current has no ripple in some specific pointsof the duty cycle. These points are exactly the transitionsbetween the operation regions. For each operation region, there


is a duty cycle that implies the maximum current ripple of theinductor. Thus, the inductance expression is derived consider-ing the maximum current ripple, i.e.,

L =Vi

64 · fs ·ΔiL. (6)

D. Capacitor Voltage Ripple

Here, the voltage ripple on the capacitors C1, C2, C3, andC4 is analyzed. The voltage ripple on the capacitor Co isnot calculated since it may be made using the low-pass filterequations.

The voltage ripple on the capacitor can be calculated duringthe storage energy stage or the transfer energy stage and usingthe following equation:

ΔvC =1

C

Δtc∫0

iC(t)dt. (7)

Some parameters are required in (7), as the charge or dischargetime interval Δtc and the instantaneous capacitor current ic(t).These parameters will be discussed in the text.

For the capacitors C1 and C2, the charge time intervalis given by Δtc = DTs for D < 1/2 and by Δtc = (1−D)Ts for D > 1/2. The charge current of these capacitors areiC(t) = IL/2, regardless of the duty cycle. Replacing thesevalues in (7), the voltage ripple of the capacitors C1 and C2

is obtained, as shown in the following equation:

ΔvC1,2 =

{IL

2fSC1,2D, D < 1

2IL

2fSC1,2(1−D), D > 1

2 .(8)

Likewise, for the capacitors C3 and C4, the charge timeinterval is given by Δtc = DTs for D < 1/4; Δtc = Ts/4 for1/4 < D < 3/4 and by Δtc = (1−D)Ts for D > 3/4. Thecharge current of these capacitors is iC(t) = IL, irrespectiveof the duty cycle. Replacing these values in (7), the voltageripple of the capacitors C1 and C2 is obtained, as shown in thefollowing equation:

ΔvC3,4 =

⎧⎪⎨⎪⎩

ILfSC3,4

D, D < 12

IL4fSC3,4

, 14 < D < 3

4IL

fSC3,4(1−D), 3

4 < D < 1.

(9)

Fig. 6 shows the normalized voltage ripple of the capacitorsas a function of duty cycle. It is observed that the maximumvoltage ripple occurs for D = 0.5 for all capacitors. Thus, thecapacitance expression is derived considering the maximumvoltage ripple, as presented in the following equation:

C =IL

4 · fS ·ΔC. (10)

E. Current and Voltage Component Effort

All semiconductors of the five-level proposed converter aresubmitted to the same blocking voltage stress; however, the

Fig. 6. Normalized voltage ripple of the capacitors.

current stress is not the same for all switches. The switchesS1, S2, S7, and S8 are submitted to the same current stress,whereas the switches S3, S4, S5, and S6 are submitted to thesame current stress. The equations to determine the averageand RMS current stresses and blocking voltage stresses on thepower semiconductor are specified in the following:

VS1−8,max =Vi

4(11)

IS1,2,7,8,avg = IL ·D (12)

IS1,2,7,8,RMS = IL ·√D (13)

IS3−6,avg = IL · (1−D) (14)

IS3−6,RMS = IL ·√(1−D). (15)

III. CAPACITOR VOLTAGE BALANCING CONTROL

As cited above, the capacitor voltage must be balanced forproper operation of the proposed converter. For some reasons,the capacitor voltage can change (e.g., during the start ofthe converter, input-voltage variations, or a slight differencebetween the drive signals of the switches). As a result, thevoltage on switches can increase to an unsafe value, and then, abalancing strategy is required. Thus, a capacitor voltage balanc-ing strategy based on active control, as previously introduced in[23] and [24], is employed in this paper.

Here, the complete analysis of the capacitor voltage balanc-ing strategy based on active control applied to the proposed five-level converter is carried out, including the capacitor voltagebalancing mechanism, the strategy to balance the capacitor volt-age, and the small-signal modeling, in which the mathematicalmodel of the capacitor voltages is found, such as the transferfunctions required in the control design. Moreover, the proposaland description of a control structure that improves the dynamicresponse of the capacitor voltages, even in light load, are alsoaddressed here.

A. Capacitor Voltage Balancing Mechanism

The analysis of the capacitor voltage balancing mechanismis performed considering a constant current source in the con-verter output, as shown in Fig. 7. To understand the capacitorvoltage behavior, it is necessary to study the capacitor currentsince the capacitor voltage and current are directly related.


Fig. 7. Simplified circuit of the proposed converter used in the theoreticalanalysis of the capacitor voltage balancing strategy.

Thus, analyzing the current through the capacitors of the circuitshown in Fig. 7, the following equations are obtained:

iC1(t) = i1(t)− iS1(t) (16)iC2(t) = i1(t)− iS8(t) (17)iC3(t) = iS1(t)− iS2(t) (18)iC4(t) = iS8(t)− iS7(t). (19)

The input voltage is considered constant and free of oscilla-tion, and it is defined as Vi = vC1(t) + vC2(t). Hence, the volt-ages vC1(t) and vC2(t) cannot be simultaneously controlled,but only one of them must be controlled. To ensure balanceof the voltages vC1(t) and vC2(t), the average current of thecentral branch in must be zero. The instantaneous current ofthe central branch is given by

in(t) = iC1(t)− iC2(t). (20)

Replacing (16) and (17) in (20), the following equation isobtained:

in(t) = −iS1(t) + iS8(t). (21)

It is observed that the currents iC3, iC4, and in are functionsonly of the switch current, i.e., iS1, iS2, iS7, and iS8.

When the switch is turned on, the output current IL flowsthrough it. When the switch is turned off, its current is zero. Then,the generic switch instantaneous current can be described as

iSx(t) = dSx(t) · IL (22)

where x = {1, 2, 7, 8} represents the generic switch.Replacing (22) in (18), (19), and (21), the capacitor current

and central branch current expressions are obtained as a func-tion of instantaneous duty cycle and output current, as shown inthe following:

iC3(t) = [dS1(t)− dS2(t)] · IL (23)iC4(t) = [dS8(t)− dS7(t)] · IL (24)in(t) = [dS8(t)− dS1(t)] · IL. (25)

From these equations, it can be seen that the capacitorcurrents and the central branch current depend not only onthe instantaneous duty cycle but also on the instantaneous

Fig. 8. PWM circuit of the multilevel converter, including the perturbationsignals (ΔdS1, ΔdS2, and ΔdS7).

difference of duty cycles. If the average values of all duty cyclesare the same, then the capacitor current average values arezero, and consequently, there is no voltage variation over thecapacitors. Moreover, these equations show that it is possibleto change the current and, consequently, the voltage of thecapacitors through variation in IL or through an introductionof a slight difference between the duty cycle of two selectedswitches. As a result, the capacitor voltages can be controlledthrough differences among duty cycles.

B. Voltage Balancing Strategy

As aforementioned, the capacitor voltage balancing is per-formed through differences among duty cycles. In order to doso, it is proposed to apply perturbation in duty cycles for thefive-level converter, according to the following equation.

dS1(t) =D +ΔdS1(t)

dS2(t) =D +ΔdS2(t)

dS8(t) =D −ΔdS1(t)

dS7(t) =D +ΔdS7(t). (26)

That is, the duty cycle of the switch S1, given by dS1, iscomposed of the effective duty cycle D, responsible for control-ling the output current or voltage, and the perturbation ΔdS1,responsible for controlling the voltage across the capacitor C1.It is extended to other switches, in which the perturbationsΔdS2 and ΔdS7, applied to dS2 and dS7, respectively, areresponsible for controlling the voltages across the capacitors C3

and C4, respectively. The perturbations ΔdS1, ΔdS2, and ΔdS7

are the control variables, whereas the capacitor voltages are thecontrolled variables of the capacitor voltage control system.Then, the perturbations are generated by a capacitor voltagecompensator, and it is added to duty cycle D, in the PWMcircuit. Fig. 8 shows the circuit of the PWM of the multilevelconverter.

Replacing (26) in (23)–(25), the capacitor current and centralbranch current equations as a function of the duty-cycle pertur-bations are obtained, as shown in the following equations:

iC3(t) = [ΔdS1(t)−ΔdS2(t)] · IL (27)

iC4(t) = [−ΔdS1(t)−ΔdS7(t)] · IL (28)

in(t) = − 2 ·ΔdS1(t) · IL. (29)


Fig. 9. Switch gate signals and capacitor currents illustrating the effect of aduty-cycle perturbation on the capacitor currents.

As can be observed in (29), the current in is a function onlyof the perturbation ΔdS1 and load current. For this reason,ΔdS1 is chosen to control the current in and, consequently,the voltages over capacitors C1 and C2. As can be seen in(27), the current iC3 depends on the perturbations ΔdS1 andΔdS2. Therefore, ΔdS2 is chosen to control the current iC3

and, consequently, the voltage across the capacitor C3 sinceΔdS1 is already responsible for controlling the current in.Likewise, it is observed in (28) that the current iC4 depends onthe perturbations ΔdS1 and ΔdS7. Therefore, ΔdS7 is chosento control the current iC4 and, consequently, the voltage acrossthe capacitor C4. The influence of ΔdS1 on currents iC3 andiC4 will be taken into consideration during the modeling andcontrol design.

The influence of duty-cycle perturbation on the capacitor cur-rent can be also observed by the analysis of the gating signal andcapacitor current waveforms. Therefore, Fig. 9 shows the car-rier signals, modulator signal, all gating signals, and capacitorcurrent. From this figure, it is observed that perturbing the dutycycle of the switch S1 (ΔdS1), the currents of the capacitorsC1, C2, and C3 are affected. Consequently, the voltages of thesecapacitors are also affected. Likewise, perturbing the duty cycleof the switch S2 (ΔdS2), only the current of the capacitor C3

is affected. Perturbing the duty cycle of the switch S3 (with avalue of ΔdS3), the currents of the capacitors C1, C2, and C4

are affected. Finally, perturbing on the duty cycle of the switchS4 (with a value of ΔdS4), only the current of the capacitorC4 is affected. This result is in agreement with that obtainedin (27)–(29). This brief analysis based on Fig. 9 is performedconsidering the operation region R2. Nevertheless, it is validfor all operation regions.

C. Small-Signal Modeling

To design the control system, it is necessary to discoverthe transfer functions and small-signal model of the converter.The modeling is based on (27)–(29). Equations (27) and (28)describe the behavior of iC3 and iC4, respectively, and they canbe related to vC3 and vC4. However, (29) describes the behaviorof in; thus, it is necessary to find the relationship betweenin and vC1. From (20), the central branch current can bedescribed as

in(t) = C1 ·dvC1(t)

dt− C2 ·

dvC2(t)

dt. (30)

As the input voltage is given by Vi = vC1(t) + vC2(t), thenthe derivatives of voltages vC1 and vC2 are related by

dV1

dt=

dvC1(t)

dt+

dvC2(t)

dt= 0

dvC2(t)

dt= − dvC1(t)

dt. (31)

Considering C1 = C2, and replacing (31) in (30), the re-lationship between in and vC1 is obtained, as shown in thefollowing:

in(t) = 2 · C1 ·dvC1(t)

dt. (32)

Rewriting (27) and (28) as a function of the derivative ofcapacitor voltage and replacing (32) in (27), the followingequations are found:

C3 ·dvC3(t)

dt= [ΔdS1(t)−ΔdS2(t)] · IL (33)

C4 ·dvC4(t)

dt= [−ΔdS7(t)−ΔdS1(t)] · IL (34)

2 · C1 ·dvC1(t)

dt= − 2 ·ΔdS1(t) · IL. (35)

Perturbing, linearizing, and applying the Laplace transfor-mation in (33)–(35), the following dynamic equations areobtained:

vC3(s) =IL

s · C3·ΔdS1(s)−

ILs · C3

·ΔdS2(s) (36)

vC4(s) = − ILs · C4

·ΔdS1(s)−IL

s · C4·ΔdS7(s) (37)

vC1(s) = − ILs · C1

·ΔdS1(s). (38)

From previous equations, a cross coupling among the vari-ables can be observed, quantified by (36) and (37), i.e., theindependent control variable ΔdS1 has an undesirable influenceon the controlled variables vC3 and vC4. The cross couplingamong the variables is clearly observed in the block diagramof the converter model, as shown in Fig. 10(a). Furthermore, itcan be also observed that the converter model is a function ofoutput current IL. Thus, the transfer function changes its gainaccording to the load, and consequently, the system crossoverfrequency also changes according to the load current. It is


Fig. 10. Block diagram of main systems. (a) Converter model. (b) Standard control system without the decoupling action. (c) Proposed control system with thedecoupling action. (d) Capacitor C1 feedback control without the feedforward action. (e) Capacitor C1 feedback control with the feedforward action.

another undesirable characteristic of the system. Therefore, thecross coupling and the load dependence on the converter modelmust be taken into consideration in control design.

D. Proposed Control Structure

As described earlier, the perturbations that are responsible forcontrolling the capacitor voltages are generated by a capacitorvoltage controller. The basic control structure of the capacitorvoltage is shown in Fig. 10(b). As can be seen in this figure,the capacitor voltages are measured and compared with areference value, resulting in the error signal. The error signalis processed by a controller (CVC1

, CVC3, and CVC4

), and then,the perturbations are generated. However, in this configuration,the voltages vC3 and vC4 suffer an undesirable influence ofperturbation ΔdS1.

As can be observed in the model block diagram [seeFig. 10(a)], the influence of ΔdS1 on vC3 and vC4 is known,i.e., the response of vC3 and vC4 to a ΔdS1 variation canbe predicted. Hence, a decoupling action can be included tothe control structure, in order to cancel the effect of ΔdS1

on vC3 and vC4. The capacitor voltage control strategy with adecoupling action is shown in Fig. 10(c). From the model blockdiagram, it is observed that the perturbation ΔdS1 is subtractedfrom ΔdS2, and the result passes through the transfer functionGVC3

, generating vC3 Thus, to cancel the effect of ΔdS1 onvC3, it is necessary just to add ΔdS1, generated by the capacitorcontroller, to ΔdS2, such as shown in Fig. 10(c).

The system transfer function has an integrator characteristic;thus, a proportional controller (P-type) can meet the dynamicperformance requirement of a closed-loop system. These re-quirements are as follows: high gain in low frequency, provid-ing a low error in steady state and an open-loop unity gain witha −20 dB/dec slope. Then, the capacitor controllers will be asimple P-type.

Fig. 10(d) shows the voltage vC1 feedback control, in whichHVC1

is the transfer function of the measurement circuit andKVC1

is the capacitor voltage proportional controller. The

feedback control of voltages vC3 and vC4 is similar to thatshown in Fig. 10(d), and then, they will be omitted in thispaper. Considering the system shown in Fig. 10(d), the open-loop transfer function is given by (39), whereas the open-loopsystem crossover frequency is given by (40), i.e.,

L(s) =KVC1·HVC1

· ILs · C1

(39)

ω0 =KVC1

·HVC1· IL

C1. (40)

As can be observed, the crossover frequency is a functionof load current. However, arg(|L(jω)|) is constant and equalto −π/2, regardless of the load current or system crossoverfrequency. Although the open-loop system is stable for a widerange of load, the dynamic response depends on the load. Forlight load, the crossover frequency is very low, and conse-quently, the capacitor voltage dynamic response is slow andoscillatory.

In order to avoid the load influence on the converter modeland, consequently, to improve the capacitor voltage dynamicresponse, it is proposed to use a load current feedforwardtechnique, in which the inverse of load current is multiplied bythe output controller, as shown in Fig. 10(e). By doing this, theopen-loop transfer function becomes

L(s) =KVC1

·HVC1

s · C1. (41)

The open-loop system crossover frequency is given by

ω0 =KVC1

·HVC1

C1. (42)

As can be observed, the system crossover frequency and theargument do not depend on the load current. arg(|L(jω)|) isstill constant and equal to −π/2, resulting in a phase marginof 90◦, regardless of the load current. Likewise, the systemcrossover frequency is constant and does not depend on the loadcurrent. Finally, Fig. 11 shows the complete block diagram of


Fig. 11. Complete block diagram of the proposed feedback control system.

TABLE IVFIVE-LEVEL BUCK CONVERTER SPECIFICATION

TABLE VPROTOTYPE COMPONENTS

the proposed feedback control system employed to balance thecapacitor voltage, with the decoupling action and load currentfeedforward action.

IV. EXPERIMENTAL RESULTS

In order to verify the operation and evaluate the performanceof the proposed five-level converter, a 10-kW prototype wasdesigned, and the proposed topology was verified experimen-tally. The converter specifications are shown in Table IV. Dueto the relation of the input–output voltage, the converter oper-ates in region R3. The prototype design was performed usingthe equations previously presented in this paper. The selectedcomponents are shown in Table V. A 600-V IGBT was used asthe main switch.

The capacitor voltage balancing control and the convertercontrol were digitally implemented through a Texas Instru-ments TMS320F28335 floating-point digital signal processor(32-bit CPU, 150 MHz), with a sampling period of Ta = 5 ·10−5 s.

The measurement circuit transfer function of the capacitorvoltages is defined as HVC1

= 7.59 · 10−4. With this parame-ter, the crossover frequency of the open-loop system withoutconsidering the controller is 3 Hz. A crossover frequency of theopen-loop system equal to 50 Hz is desired; then, the requiredgain of the capacitor voltage controller to meet this requirementis KVC1

= KVC3= KVC4

= 16.57.

Fig. 12. Power topology of proposed five-level converter and the blockdiagram of the control system, including the capacitor voltage feedback loop,output voltage loop, and inductor current loop.

Fig. 13. Implemented 10-kW five-level dc–dc converter hardware prototype(mechanical dimensions: 320 mm × 245 mm × 135 mm; power density:1 kW/dm3 = 16.38 W/in3; switching frequency: fS = 20 kHz).

In addition to the capacitor voltage control, an output voltagecontrol loop and an output current control loop were alsoimplemented. The analysis and design of these loops were notaddressed in detail in this paper because it is very similar to theconventional two-level converter. The transfer functions used todesign the control system are the same as the conventional two-level converter. The output current loop presents a crossoverfrequency equal to 2.5 kHz and a margin phase equal to 45◦.The output voltage loop presents a crossover frequency equalto 200 Hz and a margin phase equal to 65◦.

Fig. 12 shows the topology of the proposed converter withthe block diagram of the complete control system and the PWMcircuit.

Fig. 13 presents a 10-kW hardware implementation of theproposed five-level converter depicted in Fig. 3. The overalldimensions of the system are 320 mm × 245 mm × 135 mm,resulting in a power density of 1 kW/dm3.


Fig. 14. Experimental results of the converter operating in nominal condi-tions, i.e., 10 kW output power, 1.3 kV to 800 V (D = 0.615, operationregion R3). (a) Filtered output voltage Vo, unfiltered output voltage va, inductorcurrent iL, and drain-to-source voltage of the switch S1. (b) Voltage and currentof the switch S1. (c) Voltage and current of the switch S4.

The experimental results consist of relevant voltage and cur-rent waveforms for steady-state and dynamic operation of theconverter. The main waveforms obtained from the implemented

Fig. 15. Experimental results of the capacitor voltages of the converteroperating at nominal conditions (10 kW output power, 1.3 kV input voltage,and 800 V output voltage).

prototype operating at nominal load are shown in Figs. 14 and15, and they will be discussed in the following.

A. Steady-State Operation Waveforms

The steady-state waveforms are shown in Figs. 14 and 15,and they were obtained by the converter operating at nominalconditions, i.e., 10 kW output power and 1.3 kV to 800 V input-to-output voltage, resulting a duty cycle of D = 0.615 and theoperation region R3.

Fig. 14(a) shows the filtered output voltage, the output volt-age before the filter, the inductor current, and the voltage acrossthe switch S1. It is observed that the low-pass output filteroperates at a frequency four times higher than the switchingfrequency. Moreover, a low current ripple is observed.

Fig. 14(b) shows the capacitor C1 voltage (i.e., Vi/2) and thevoltage and current of the switch S1. Likewise, Fig. 14(c) showsthe voltage and current of the switch S4. The voltage across thesemiconductors is clamped with a maximum value of 325 V(Vi/4). The current waveform is according to the theoreticalwaveform, as shown in Fig. 4.

Fig. 15 shows the voltage over the capacitors. These voltagesare balanced in their correct values.

B. Transient Operation Waveforms

The experimental results consists of the capacitor voltagewaveforms, taking into consideration some unbalancing con-ditions, and its main purpose is to evaluate the proposed controlof capacitor voltages. These results are shown in Fig. 16.

The dynamic tests were performed with the converter op-erating at hard load (IL = 10 A) and at light load (IL =3 A), with input voltage equal to 400 V, since the con-verter was forced to work under an unbalancing condition.Thereby, the voltage across some semiconductors was higherthan the designed value. Furthermore, the capacitor voltagecontrol system without the feedforward action and the capacitor


Fig. 16. Experimental results of the capacitor voltage regulation, for hard load(IL = 10 A) and light load (IL = 3 A), considering the control structure withthe feedforward technique and without the feedforward technique. (a) Capacitorvoltage regulation for the hard load (IL = 10 A) condition and control systemwithout the feedforward technique. (b) Capacitor voltage regulation for thelight load (IL = 3 A) condition and control system without the feedforwardtechnique. (c) Capacitor voltage regulation for the hard load (IL = 10 A)condition and control system with the feedforward technique. (d) Capacitorvoltage regulation for the light load (IL = 3 A) condition and control systemwith the feedforward technique.

voltage control system with the feedforward action are evalu-ated experimentally.

Fig. 16(a) and (b) shows the experimental results consideringthe capacitor voltage control system without the feedforwardaction. Fig. 16(a) shows the capacitor voltage waveforms for aconverter operating at hard load (IL = 10 A). In this figure, thecapacitor voltages are previously in an unbalanced condition,and then, the capacitor voltage control acts to balance thevoltages. As can be seen in this figure, the steady-state error iszero, and the dynamic response is fast and damped. Likewise,Fig. 16(b) shows a result similar to the previous one, but for aconverter operating at light load (IL = 3 A). From this figure,it is observed that the steady-state error is zero. On the otherhand, the dynamic response is very oscillatory and slowly.

Likewise, Fig. 16(c) and (d) shows the experimental resultsconsidering now the capacitor voltage control system with thefeedforward action. Fig. 16(c) shows the action of the capacitorvoltage control for a converter operating at hard load (IL =10 A). As can be observed in this figure, the steady-state error iszero, and the dynamic response is fast and damped, as expected.Finally, Fig. 16(d) shows a result similar to the previous one,but for a converter operating at light load (IL = 3 A). Inthis condition, the steady-state error is zero, and the dynamicresponse is also fast and damped due to the load current feedfor-ward technique. Thus, using the proposed control system, thedynamic response of capacitor voltages is damped, regardlessof the load. Nevertheless, for extremely light load (IL ≈ 0),the proposed control and the classic control are not so efficientbecause the current through the capacitors is zero.

Fig. 17. Efficiency curve of the converter as a function of the output powerobtained experimentally.

C. Efficiency

Finally, Fig. 17 shows the efficiency curve of the proposedfive-level converter as a function of the output power ex-perimentally obtained using the digital wattmeter YokowagaWT500. The test was performed with input equal to 1 kV dueto the limitation of the measurement device. Because of this,the maximum obtained output power was 7.6 kW. It is observedthat the converter reaches the maximum efficiency of 96.85% at3 kW output power. In addition to that, in the maximummeasured output power (7.6 kW), the converter reaches an effi-ciency of 96.7%. The calculated theoretical efficiency at nomi-nal power (10 kW) is 97.6%. Thus, the calculated efficiency andmeasured efficiency experimentally presented similar results.

V. CONCLUSION

Nonisolated buck-type, boost-type, and bidirectional mul-tilevel converters were proposed, and a five-level structureoperating in buck mode was analyzed in detail in this paper.The theoretical analysis has shown that the static gain of theproposed five-level converter is the same as the standard two-level converter. The voltage stresses in semiconductors arereduced to one fourth of input (for the five-level structure), forbuck mode, making it suitable for high applications.

As an additional contribution of this paper, a capacitorvoltage balancing active control was presented and analyzedin detail. The small-signal modeling was performed, and theobtained mathematical model has presented an undesirablecoupling among the variables, as well as undesirable depen-dence on the load current. To overcome these problems, avoltage control system with a decoupling action and a loadcurrent feedforward technique was proposed and discussed.Moreover, it was demonstrated that it is possible to use a simpleproportional compensator to control the capacitor voltage, dueto the integrator characteristic of the system transfer functions.

A 10-kW prototype was designed and built, and experi-mental results were obtained. The results have demonstratedthe performance and feasibility of the proposed converter. Inaddition to that, experimental results have demonstrated thatthe proposed capacitor voltage balancing control improves thedynamic response of the capacitor voltage, even in light load.

The main advantages of the proposed multilevel con-verter predicted in theoretical analysis and attested through


experimental results are as follows: reduced blocking voltageof semiconductors, reduced inductance, and low voltage overthe capacitors.

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Levy Ferreira Costa received the B.S. degree inelectrical engineering from the Federal Universityof Ceará, Fortaleza, Brazil, in 2010 and the M.S.degree from the Federal University of Santa Catarina(UFSC), Florianopolis, Brazil, in 2013.

He is currently with Schneider Electric, Fortaleza,Brazil, where he is involved in research and develop-ment of uninterruptible power systems.

Samir Ahmad Mussa (M’06) was born in Jaguari,Brazil, in 1964. He received the B.S. degree inelectrical engineering and the second degree inmathematics/physic from the Federal University ofSanta Maria, Santa Maria, Brazil, in 1988 and theM.Eng. and Ph.D. degrees in electrical engineer-ing from the Federal University of Santa Catarina(UFSC), Florianopolis, Brazil, in 1994 and 2003,respectively.

He is currently an Adjunct Professor withthe Power Electronics Institute (INEP), Fed-

eral University of Santa Catarina (UFSC), Florianopolis, Brazil. Hisresearch interests include digital control applied to power electron-ics, power factor correction techniques, and digital signal processor/field-programmable gate array applications.

Dr. Mussa is a member of the Brazilian Power Electronics Society.

Ivo Barbi (M’78–SM’90–F’11) was born inGaspar, Brazil, in 1949. He received the B.S. andM.S. degrees in electrical engineering from theFederal University of Santa Catarina, Florianopolis,Brazil, in 1973 and 1976, respectively, and the Dr.Ing. degree from the Institut National Polytechniquede Toulouse, Toulouse, France, in 1979.

He is currently a Professor with the Power Elec-tronics Institute (INEP), Federal University of SantaCatarina (UFSC), Florianopolis, Brazil.

Prof. Barbi is the Founder of the Brazilian PowerElectronics Society and of INEP, UFSC.

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Multilevel Buck/Boost-Type DC–DC Converter for High-Power ... em periódicos/64... · boost-type multilevel dc–dc converter suitable for high-power and medium/high-voltage application