IAEA-TECDOC-309

NUCLEAR ELECTRONICSLABORATORY MANUAL

A TECHNICAL DOCUMENT ISSUED BY THEINTERNATIONAL ATOMIC ENERGY AGENCY, VIENNA, 1984

NUCLEAR ELECTRONICS LABORATORY MANUALIAEA, VIENNA, 1984IAEA-TECDOC-309

Printed by the IAEA in AustriaMay 1984

PLEASE BE AWARE THATALL OF THE MISSING PAGES IN THIS DOCUMENT

WERE ORIGINALLY BLANK

The IAEA does not normally maintain stocks of reports in this series.However, microfiche copies of these reports can be obtained from

IN IS ClearinghouseInternational Atomic Energy AgencyWagramerstrasse 5P.O. Box 100A-1400 Vienna, Austria

Orders should be accompanied by prepayment of Austrian Schillings 100,-in the form of a cheque or in the form of IAEA microfiche service couponswhich may be ordered separately from the INIS Clearinghouse.

FOREWORD

The Nuclear Electronics Laboratory Manual is a joint product of severalelectronics experts who have been associated with IAEA activity in thisfield for many years. It is based on the experience of conducting eighteentraining courses on nuclear electronics, and in this respect, the contri-bution of many other scientists are hidden in the final manuscript.

The manual does not include experiments of a basic nature, such ascharacteristics of different active electronics components. It starts byintroducing small electronics blocks, employing one or more activecomponents. The most demanding exercises instruct a student in the designand construction of complete circuits, as used in commercial nuclear instru-ments. It is expected that a student who completes all the experiments inthe manual should be in a position to design nuclear electronics units andalso to understand the functions of advanced commercial instruments whichneed to be repaired or maintained.

The future tasks of nuclear electronics engineers will be increasinglyoriented towards designing and building the interfaces between a,nuclearexperiment and a computer. The manual pays tribute to this development byintroducing a number of experiments which illustrate the principles and thetechnology of interfacing.

Part of the manual, i.e. Special Projects IV, V and VI were prepared bythe Central Unit for Electronics, Kernforschungsanlage Jülich; this work wassponsored by the Government of the Federal Republic of Germany.

The following experts contributed to the manual: D. Camin (Argentina),J. Lopes (Portugal), F. Manfred! (Italy), J. Pahor (Yugoslavia), Z. Zamori(Hungary), and J. Dolnicar, H. Kaufmann and R. Lelliott (all IAEA).

CONTENTS

Introduction ........................................................... 7

Part 1. Basic circuitsExperiment I: Discriminator ............................. 11Hints for laboratory work: How to make printed boards ................ ISHints for laboratory work: Resistors and capacitors color code ....... 23Experiment 2 : Integrator with reset ..................... 31Experiment 3: Univibrator ............................... 33Experiment 4: Inverting amplifier ....................... 35Experiment A: Signal and pulse generator ................ 37

Part 2. Power suppliesExperiment 5: Rectifier board with filter capacitors .... 43Experiment 6: Auxiliary power supply ±15 V/100 mA ....... 45Experiment B: Regulated power supply using an operational

amplifier ................................ 47Experiment C: Regulated power supply using a monoline

voltage regulator ........................ 51Experiment 7: High voltage power supply ................. 55

Part 3: Analog circuitsExperiment 8: Coaxial cables and delay lines ............ 59Experiment 9: Filtering and decoupling in nuclear

electronics .............................. 63Experiment 10: Pole zero cancellation .................... 65Hints for Laboratory Work: How to make reliable analog circuits ...... 69Experiment 11: Baseline restoration ...................... 73Experiment D: Complete linear system for detector

signal processing ........................ 77Experiment E: Time interval-to-amplitude conversion ..... 93

Part 4: Digital circuitsExperiment 12: Correct use of logic gates ................ 105Experiment 13: Digital setting of amplifier gain ......... 109Experiment F: Flip flop, counters and displays .......... IllExperiment 14: Voltage to frequency converter ............ 117Experiment 15 : Sample and hold ........................... 119Experiment G: ADC (Wilkinson) ........................... 121

Part 5. Basic interfacing circuitsExperiment 16: Digital switches .......................... 127Experiment 17 : Power drivers ............................. 131Experiment 18: Driving of stepping motors ................ 135Experiment 19 Tristate buffers and buses ................ 139Experiment 20: Shaft encoder ............................. 143

Part 6 InterfacingExperiment 21: Output ports .............................. 149Experiment 22 : Input ports ............................... 155Experiment H: Measurement of physical properties by

computer ................................. 157Experiment K: Computer control of nuclear measurement ... 159

Part 7: Special projectsSpecial project I: Geiger-Mueller ratemeter .................. 163Special project II: Single channel analyzer ................... 167Special project III: Sealer-timer .............................. 173Special project IV: HP-SHP bus converter ...................... 183Special project V: Serial I/O board .......................... 195Special project VI: Memory .................................... 215

Part 8: Data sheets

INTRODUCTION

The Laboratory Manual is an effort to provide orientation in trainingin the field of nuclear electronics. It gives information about theprinciples of nuclear electronics circuits while simultaneously introducingcontemporary electronics technology. It is intended for students who have abackground in basic electronics.

The exercises in this Laboratory Manual are sorted into threecategories:

I. Experiments 1 to 22 are intended to demonstrate the basic buildingblocks as used in nuclear electronics. The completion of anexperiment should require at the most three hours in thelaboratory.

II. Experiments A to I are extensive, full scale exercises that mightrequire several days of laboratory work.

III. Special Exercise I to VI are designed to show a student how tomake a useful electronics device or computer interface. In fact,these exercises reach beyond the normal course in electronics, andproduce a real instrument applicable to a nuclear experiment.

The exercises have been designed for the IAEA interregional nuclearelectronics course which is conducted on a rather advanced level, and runsfor 13 weeks. In this course, about 60% of the time is devoted to practicallaboratory work. It is obvious that for a shorter course on a lowertechnical level, appropriate exercises have to be selected, and the moresophisticated experiments will have to be deleted.

Each experiment is introduced by an explanation of the circuitoperation on the physics principles. In this way, the Laboratory Manual canserve at the same time as an introductory textbook for nuclear electronics.

The final part of the Manual is reserved for literature on the activeelectronic components used in the experiments. Short tips on production ofprinted boards and on design of circuits are also included in Parts 1 and 3.

To avoid the inconvenient letters for resistivity and. capacitance, asimplified notation has been selected. Resistors are described inR (ohms), K (kiloohms) and M (megaohras); 10 R means 10 ohms, 2K7 stands for2.7 kiloohm, 1M5 is 1.5 megaohm. The values of capacitors are given in pF,nF, or uF, in the drawings also p (for picofarad) and n (for nanofarad) areused.

Most of the wiring diagrams include the values of all the active andpassive components used in the design. For some experiments, only thesuggested values are given, challenging the student to determine and selectthe most suitable components himself.

It is expected that the students in nuclear electronics will learn howto design a printed board, and how to produce it. However, it would be tootime consuming if every student would prepare every printed board describedin this Manual. Therefore, a set of masks for the boards was prepared, asis availble on request.

PARTI

BASIC CIRCUITS

EXPERIMENT 1

DISCRIMINATOR

Objectives; Studies of the input-output relation for an open loopoperational amplifier application are performed to obtain a practicalvoltage discriminator. The influence of the positive feedback isdemonstrated.

Fig(A

IntroductionThe output voltage VQ of an operational amplifier represented in

, 1.1 is VQ = A (v+ - v~), where A is a very large number105). With v~ = 0 the relation between input V+ and output VQ

is plotted in Fig. 1.2.

VV

Fig. 1.1 Operational Amplifier

"o +E =HIGH

-E+= LOW

Fig. 1.2 Input-output relation forthe operational amplifierwith Vref = 0 V

Fig. 1.3 Input-output relationfor the operationalamplifier with Vref = 3 V

The output voltage VQ exhibits a sharp jump in the vicinity of thezero input voltage, and the amplifier output voltage swing is limited by theamplifier operating voltages E+ and -E~.

Accepting the -E+ voltage as the logical low state and the E+voltage as the logical high state, the circuit can tell the polarity of theinput voltage applied to the input.

If the voltage Vref instead of the zero voltage is connected to thenoninverting input the input-output relation becomes, for Vref = 3V, vo= A(v+-3>, as represented in Fig. 1.3.

The circuit can discriminate between input voltages smaller than Vrefand greater than Vref. However, with v~ = Vref the output VQ mightbe zero.

11

1OOKczR2

Fig. 1.4 Discriminator with possible feedback

In order to improve the sensitivity of the system, positive feedback isintroduced (Fig. 1.4). Previously stable circuit becomes unstable, i.e.only E+ or -E~ output states are possible. This can be proved asfollows. Assume that both input signals v~ and vj are zero; VQ isalso expected to be zero. But if the output voltage even slightly deviatesfrom zero, as is practically the case, one percent of this deviation istransferred to the non-inverting input, causing faster and faster growing ofthe output voltage. The final state (either E+ or -E~) depends on theinitial polarity of VQ.

Fig. 1.5: Input-output rotation forcircuit of Fig. 4 with

Fig. 1.6: Input-output rotationfor circuit of Fig. 4 withvref = 3 V

The introduction of the positive feedback thus results in the sharptransition between high and low output state represented in Fig. 1.5. Forthe circuit in Fig. 4 the gap width is 0.02V. When the output is in thehigh state, 10V for example, the input voltage sufficient to cause high tolow output transition must be larger than -0.01V to pull the voltage at thenoninverting input below zero. The similar consideration shows that theinput voltage greater than 0.01V is required for the low to high transition.

With increasing value of the input resistor R^ and the decreasing ofthe feedback resistor R2, the influence of the output voltage VQ becomesstronger, and the gap in hysteresis is wider.

Finally, the transition points can be shifted left and right by theproper choice of the Vref voltage (Fig. 1.6).

Consider the modified discriminator pulse response. The discriminatorlevel Vref should be equal to the amplitude of the incoming pulse. Theoutput pulse in the modified version is still of the finite length(Fig. 1.7a) while in the original version the output pulse length goescontinuously to zero (Fig. 1.7b).

12

Vref

Fig. 1.7: Effect of hysteresis on output pulse width

The additional advantage of the hysteresis is the clear recognition ofthe zero crossing for slow varying signals in the presence of noise or hum(Fig. 1.8).

Fig. 1.8: Using hysteresis to avoid multiple triggering

In nuclear electronics, specially designed circuits for the pulsediscriminator are used. They are faster than operational amplifiers due tothe faster recovery from saturation. Output voltage swings between 3,5 Vand -0,5 V. Some typical representatives are 710 with a response time of 10ns, LM 360 (14 ns), LM 311 (200 ns>, TL 510 (30 ns) and Am 685 (6 ns,fastest but expensive).

When assembling the printed circuit board according to Fig. 9 leave the100 k resistor out. Provide the PCB with OIL sockets, to have thepossibility to interchange different types of operational amplifiers: 741,LF 356, LF 357 and CA 3130 (for the last one the operating voltage shouldnot exceed 12 V). Use the triangular input voltage and displaysimultaneously the input and output signals. Prove that slowly varyingsignals give unclear output response when passing the Vref.

13

ore

lOOK

Fig. 1.9: Circuit diagram of discriminator

Display the output voltage versus the input voltage in the X-Yoscilloscope mode. Verify curves shown in Fig. 1.2 and Fig. 1.3. Theninsert feedback resistor and verify curves shown in Fig. 5 and Fig. 6. Findthe proper resistor and Vref for hysteresis giving the up transition at 10V, and down transition at 0 V.

The transition times are not identical for all different amplifiers.The fastest output rise time expressed in V/^us is called slew rate.Estimate slew rates for different amplifiers having the same pindistribution.

Remember the range between 0.5 V//us for 741 (very slow) with about 10V//US for LF 356 (typical contemporary) and with 1500 V/us for NE 531 (veryfast).

14

HINTS FOR LABORATORY WORK

HOW TO MAKE PRINTED BOARDS

IntroductionAll contemporary circuits are assembled on printed circuit boards

(PCB). The basic material for PCB is vetronite (epoxy resin strengthenedwith glass fibers), single or double sided coated with copper of 35 or70 pan thickness. For normal use, 35 un is preferable. The standardthickness of the copperised plate is 1,6 mm. The fabricated boards of thisthickness can be shaped to enter directly in female flat connectors, likeAMP Latch (2,54 mm contact separation); in this case the hard gold platedcontacts are required to assure the reliable electric contacts (Fig. 1.).The contact density of 40 per 100 mm of the Eurocard side length can beachieved but even this high density does not meet the contemporaryrequirements of digital electronics. Therefore Siemens C42334-A (DIN 41612)connector providing 96 contacts in three rows on the same length ispreferable (Fig. 2).

For the simple digital as well as for the analog circuits, single sidePCB can be used. The analog circuits contain many resistors and capacitorswhich can be used as bridges across the PCB conducting lines (Fig. 2).

Fig. 1 Plugging a PCB directly to a connector

For the digital circuits with few resistors, double sided PCB arenormally employed to avoid large numbers of jumpers, a jumper is a wirecrossing the PCB conducting lines (Fig. 3).

Interconnecting conducting lines on different sides of the PCB is madeby inserting short wires through holes and soldering.

More advanced technology is to make the plated-through connections, i.e.to join electrically both sides of PCB through holes by a galvanic process.The area of plated-through connections is smaller than the area required forthe classical wired connections. Therefore, more dense PCB can be manu-factured by using the plated through technology. For the most densearrangements even this technology is insufficient and is extended to multi-layer (or laminated) PCB. For such circuits, thinner separate PCBs areprepared, joined in a thicker one and equipped with the conductive holeswhere necessary. For a PCB made of 5 separate sheets the crossing of

15

conductors at 6 different levels is possible. PCBs with as many as 20separate layers have been produced. However, such technology is impossiblewithout special machines. Therefore, only production of single or doublesided PCBs is described below.

oAen

IOOB

Uro

_<x_earth4-5V

+24V return+24V

L-i.':IJ

Fig. 3 Resistor bridge

+ I5Vanalog GNO-ICVdigital GNDearth Fig. 4 Jumper

Fig. 2 DIN 41612 64-pin allignments correspond to the instrument'sconnector. The indicated pins IAEA series of plug-in.

For the production of PCS, the copper plated board is coated with anetch resistive material following the conducting lines joining the circuitcomponents. By etching, all uncoated copper is removed from the board.Then holes for the component mounting are drilled. To avoid the oxidation,the copper protecting material is removed from the plate shortly before thecomponents are soldered in.

The protection of the copper plate by the etch resist pattern is usuallyachieved by coating the board with a photosensitive laquer from the"POSITIVE 20" spray then exposing the board to the light through thefull-size negative. The exposed board is immersed in an aqueous solution ofNaOH washing off the exposed parts of the laquer.

PhotomaskBefore starting with the design, all circuit components should be

collected.

16

The design starts from the front plate,be fixed directly on the front plate; in thiselements in the front plate and the PCB mustwrong connection. A preferable method is todirectly on the PCB, in such a way that theyWith the well-defined positions of the input,points, the design can start (Fig. 5). Notecircuit sides to allow room for cardlifters.

The electronics components cancase, the wiring between the

be carefully done, to avoid asolder the control elementsreach through the front plate.output, control and supplythe 5 to 10 mm margin along all

Simple circuits can be designed in one step, starting from the hand-madesketch drawn by black pencil to allow erasing. For jumpers, the colourpencil is recommended. The enlarged scale is useful to save your eyes.

1 CIRCUIT

AREA

+12

JL+5-12

Fig. 5 Defining essential points on a PCB

As a design example Fig. 6 shows a small circuit for which a PCB has tobe produced. The part of the sketch is shown in Fig. 7.

Very often the circuit is complex. Watch carefully the circuit diagramand try to recognise smaller blocks connected with other blocks by theminimal number of interconnecting wires. Then try to draw the separateblocks which will be put together later. Try to have all ICs oriented inthe same direction.

Taking a piece of the precision inch grid (Fig. 8), overlay it with thetracing paper and transfer the sketch on the paper taking care about theactual size Fig. 7. Normally 2:1 scale is preferable to produce the printedcircuit artwork, however, for the production of the final photomask thephotographic procedure is required in this case. Therefore we will limitourselves to 1:1 scale mask design.

High precision drawing is still not required at this phase, with theexception of all the future soldering points that should strictly coincidewith the crossing points of the grid lines. It is recommended keeping thesame distance (0,4 inch for instance) for all 1/4W and 1/8W resistors. Forcapacitors which greatly vary in dimension, two or three different holespacing are foreseen. Do not forget one 100 nF bypass capacitor for any 2to 4 digital ICs.

rO OUT

Fig. 6. Wiring diagram of a 45 ns pulse generator to be designed

17

ACTUALSIZE

10X10 Fig. 7 Sample of an inch grid

\ « tsrjHnü_JFig. 8 Initial sketch Fig. 9 Final drawing Fig. 10 Part of

produced photomask.Note the inverselettering

Fix your final drawing (Fig. 9) on the table, overlay it with theprecision transparent inch grid and with a transparent polyester foil ofapproximately 0,1 to 0,2 mm thick. Foils used for overhead projectors aresuitable.

Photomask is produced by using self-adhesive tapes, precut forms andstickons. There is a large choice of these articles and they areexpensive. The most useful forms are shown in Fig. 10. In the first step,the socket configurations and transistor configurations printed ontransparent stickons are removed from their supporter by sharp nose tweezersand transferred to the transparent foil, then the donut pads (round terminalareas) are pressed on.

For conductors, opaque tapes produced in the variety of sizes are used.One mm width is popular,- and 0.4 m is the thinest that should be used. Takewider lines for the power lines (at the rate of 2 mm width for 1 A) andground lines.

9I9I6I9I9I9I69101910191619o eo oo o

0 0 0 0 0 0 0

0 0 0 0 0 0 0

0*0

10

«Î* Fig. 11 Some precut formsand stick-ons

18

Leave all centre circles of the donut pads open. These pinholes willhelp to centre the drills.

The minimal conductor spacing 0,40 mm is sufficient for voltages up to50 V. Increase this spacing according to Table 1 if higher voltages areapplied.

TABLE 1

voltage (V)0 - 5 050 - 150150 - 300300 - 500

separation (mm)0,400,651,302,50

the add 0,50 mm for each new 100 V

Fig. 12 Examples of PCB network

As shown in Fig. 12 several conducting lines can be inserted betweenboth lines of terminals of DIL socket. One line can be inserted between twoneightbour pins of 1C if some paints are carefully scratched off. Use asharp knife with an exchangeable blade to cut off the excess tape. Withpractice, the proper pressure will be applied, to cut only the tape whilethe paint on stickons will remain unsplit.

After being produced, the photomask should be carefully inspected.Remove all small pieces of the tape which have remained attached to thephotomask. Observing the mask against the light might reveal some pointswhere the conductor lines are discontinued.

For the proper circuit orientation as well as for easier assembling andcontrol of the PCB, significant points (pin 1 of ICs, polarity of theelectrolytic capacitors and dides diodes) are marked. Note that letteringmust be made from the opposite side of the photomask (not the taped one).

For the final photomask check, overlay it with tracing paper, andcompare all lines with the circuit scheme. Draw all components (resistor,capacitors and ICs) on the tracing paper and follow interconnections byusing the circuit scheme.

19

Plate sensitivationCut the board out from the basic material.

It should be 15 mm wider and longer than the photomask dimensions.Clean the surface by a hard eraser (used with typewriters), and do not touchthe already cleaned surface to avoid greasy fingerprints. The dry and cleansurface (but not hot if heat was used during drying) is sprayed over theboard in the horizontal position with POSITIVE 20, from a distance of 20 to30 cm. Spray until the separate droplets are joined. Move spray in bothdirections to get the uniformly painted surface. You do not need a darkroombut avoid direct sunlight. Store the coated plate in a completely darkplace. The drying time at normal room temperature is from 12 to 24 hours.When heating facilities are available, the drying time of 20 minutes issufficient but the temperature should not exceed 60°C.

Note the thicker photosensitive layer along the edges,reason for making the PCB lareger than the photomask.

This is the

The above procedure can be shortened by using fabrically precoatedboards according to the Eurocard . If necessary plates are cut into smallerpieces of the exact size. The black self-adhesive plastic foil protectingthe photosensitive surface against the light should not be removed.

The photosensitive board to be exposed is overlayed with the photomaskwhich is pressed down by a piece of perspex or glass.

Fig. 13 Exposure of PCB

There are two types of illuminating devices using either diffused orpoint light sources. With the later (Fig. 14), more sharp patterns can bereproduced from hand-made photomasks where the overlapping tapes can not bepressed closely enough to the photosensitive surface.

Exposure and processingWith a 500 W incandescent lamp the exposing times between 2 and 6

minutes can be expected if the distance between the lamp and the board isapproximately 40 cm.

For the best results make a probe on a strip with the step increase ofexposure time (Fig. 15). Avoid overlapping two or more stickons, even

20

transparent when producing the photomask. Due to the reduced transparencythe surface below will be underexposed.

After exposure the already visible pattern has to be processed in 7 gper liter aqueous solution of NaOH. Use the prepacked bags for 1 liter ofsolution if you want to avoid weighting. When preparing solution from yourown NaOH supply, keep in niind that NaOH is strongly hygroscopic. Ifweighted wet, more diluted and less active solutions will be prepared. Thesolution attacks and etches the skin also. If by accident, it reached aneye, wash it with water and vinegar for neutralisation.

For processing, the photographic trays are acceptable. The normalprocessing time is up to 2 minutes at temperatures from 20 to 25°C. Usingcolder solutions, this time will be longer (10 minutes or more), and is notrecommended. Using a hotter solution, (about 35°C) even the unexposedparts will be washed off. The same effect will be caused by a moreconcentrated solution. Note that the solution left in an open vessel andexposed to the atmosphere with large surface will be ineffective in a coupleof hours. This is due to the neutralisation of NaOH through the absorptionof C02 from the air.

LIGHT

MOVE 3 cm AFTER EACH MIN.STARTING WITH 3 MIN. \\

'////////////////////////////ASHIELD

$£______________________________f;T"^ r~l-PERSPEX PLATE

Fig. 14 Checking the optimal exposure time

Etching

Before etching check the protective pattern over the copper again. Therevealed discontinuities (scratches, and similar) would result in breaks oflines. Therefore it should be repaired by using either the etch resisttapes, pressure-sensitive tapes (LETRASET) or etch resist flomaster.

Put the PCB into a low and flat tray with an etching solution (aqueousFe Clß solution close to saturation). Do not etch several PCBssimultaneously; they will scratch each other. Assure the flow of thesolution across the PCB by moving up and down one side of the tray.However, the best etching results are obtained with PCBs oriented verticallyin the etching vessel. The etching solution should be warm; the recommendedtemperature is around 40°C. Normal etching times are between 15 and 30minutes. In a colder solution, the etching times are longer.

DrillingFor drilling, the high speed (5000 to 10000 rpm) drilling machines are

preferable. Use of the hard metal drills, resistant to glass content in thePCB material, is recommended. A normal drill it will be ruined afterdrilling two or three PCBs. The hole diameter 0,8 or 0,9 is good for themajority of the elements. For bigger capacitors a 1,2 mm diameter isrequired.

21

The above described method of PCB manufacturing deals with the simplescase only of a single-sided PCB, as used in the nuclear electronics trainingcourse. For more advanced methods of producing a more sophisticated PCB,consult the literature.

As before, the black connecting lines are followed when the lower sidephotomask is produced. The upper side photomask which contains connectionson the component-side could be produced by overlaying the first photomask bythe new transparent sheet and following the colour lines. Actually this isthe normal way for producing photomasks for double-sided PCBs.

In the most advanced technology, instead of making two separate maskseach with a black pattern, one double coloured mask is made. Red and bluetransparent elements are used for the upper and the lower side elements.Only elements which have to be reproduced on both sides are put in black.At the photographic reduction, the blue pattern alone can be reproduced byusing the photographic material insensitive to the red colour .

The similar method is employed for the reproduction of the red patternalone.

After making the first photomask it must be removed and fixed to thetable with tapes face downwards, together with the inverted final drawing.All three sheets (grid, final drawings and the upper side photomask) areoverlayed with the new fresh transparent foil. The colour lines arefollowed to produce the lower side photomask.

22

HINTS FOR LABORATORY WORK

RESISTORS AND CAPACITORS COLOR CODE

In the following pages, the most important information on thespecification, standard value and color codes of resistors and capacitorsis presented.

— IllFirst Tsignificant— 1figure

Second

figure

^ : *t=,

^ l

Failure -rate' — level (established

reliability typesonly)

Multiplier

(atApprox 15 times

Equal width width of remainingI bands/"

' A B C

="=iPl

First |significant-JdigitSecond

D1 E-^

ilii =»*=

—— Terminal

.

d'9'f Multiplier

/'A;

"oleronce

Visibly wider spacing

0020*Typical ref —— » « ——

0031* —— J • —Typical ref

•=»= i

¥ 1First f 'significant —— 1digitSecond

digit

between bands toidentify direction ofreading (from leftto_ ^

i'

L __ ( rlgM)

\ ="=

•— Tolerance

— Decimalmultiplier

Third significant digit

(c)

Fig. 1 Color coding of resistors, (a)MIL-R-39008 composition and certainwirewound types. MIL-STD-1285 speci-fics two significant figures for 5, 10, and20 percent purchase tolerances. EIARS-172 composition and RS-344 wire-wound-type markings are identical to thisexcept that the failure-rate band isomitted, the first band is wide for wire-wound types, and the tolerance band isomitted for 20 percent tolerance, (b)Film type per MIL-R-22684. Gold Dband is ±5 percent tolerance and red is±2 percent. White E band denotessolderable leads. Although now super-seded by non-color-coded MIL-R-39017types, these parts may still be encoun-tered, (c) Film type per EIA RS-196with three significant digits. "NOTE: Allband widths and spacing are for refer-ence only and may be scaled up or down.

Yellow

Red

1-o Green

• Clockwise

fa}

to)

Fig. 2 Circuit diagram and terminalidentification for variable resistors (rota-tion is operating shaft, viewed from op-erated end), (a) Required by MIL-STD-1285 and EIA RS-360. (b) Alter-nate allowed by MIL-STD-1285.

TABLE 1 General Color-Number Significance for Resistors and Capacitors and Approved Standard Abbreviations for Color Names

Color

BlackBrownRedOrangeYellowGreenBlueVioletGrayWhiteGold"Silverb

Number

0123456789

Multiplier, EIA-MIL

Resistor

11010'103

10'10'10'10'

10-'10-'

Capacitor

110102

10 =10-c

lo-vKT'firr1*10'J*

Resistor value** tolerances

MILresistor,

(*)%

2012

510

EIAresistor,

(±)%

12

0.50.250.100.05

510

Abbreviations

MIL-STD-12

BLKBRNREDORNYELCRNBLUVIOGYWHT(a)SI L

EIA3-lctter

BlkBrnRedOrnYclGrnBluVioGraWhtGldSil

EIAalternate

BKBRR,RDO,ORYGN,GBLVGYWH,W

MIL-STD-128Spart- typeidentifier

Capacitor

Inductor

MIL-STD-1285failurerate?

M )M (10")P (10J)R ( l O ' jS (10)

23

Bevel edge is positiveterminal

Can

Molded chip

Positive lead Positive may havered dot or plus sign

Unencapsulated chip

Jl

Dipped

Long leadis positive

Molded(a)

Glass header

(b)

Can is negative

2 \ Term #1 always .l°1

430

cathode ( 01 20 |Term #2alwaysanode of outersection

Blank ear

Multisection concase negative

(d)

Con is negative

Weld

(e)

(f)

Fig. 3 Capacitor polarity conventions, (a) Tantalum, solid electrolyte (polarized).(b) Military tantalum (polarized). Hermetic (wet or solid) metal casing, (c)Tantalum, wet electrolyte (polarized). Red bands or dots are also sometimes usedon electrolytic capacitors to denote anode, (d) Aluminum foil, electrolytic (polar-ized), (e) Paper, plastic film (nonpolarized). Band denotes connection for out-side foil, (f) Ceramic (nonpolarized). Wide band and colored ends denote innerelectrodes.

TABLE 2 Color Coding of EIA Standard RS-228 Tanta-lum Capacitors

Color

BlackBrownRed*OrangeYellowGreenBlueVioletGrayWhiteNo colorSilverGold

Significantfigures

0123456789

Multiplier

1001,000

10,000100,000

1,000,000

Capacitancetolerance, %

±20±10t 5

* Red may also be used to identify the positive lead.

24

Innerelectrode-termination —l

Temp range forcharacteristic

determination ,°C

-55 to +85-30 to +85

+ 10 to +85-55 to +125+ 10 to +65

m^r i

Max.capac.changeover

temp, ronge.%

11

Ï1.5i2.213.3J4.7î7.5

±10.0±15.0J22.0

+ 22,- 3 3+ 22,- 56+ 22 — 82

3r

1st and 2dsigificantfigure of

capacitance——0123456789

rr\ • i

Multiplier

——11O1001000

10.000———

O.010.1

>

Toleranceon

capacitance, %

——

120———

+ 10O.-0±5——

+ 80, -20; 10

Color

GoldSilverBlackBrownRedOrangeYellowGreenBlueVioletGrayWhite

Fig. 4 Color-code marking of EIA standard RS198 general-purpose ceramic capac-itors. (Electronic Industries Association.) 1. Use lowest decimal multiplier toavoid alternate coding; for example, 2.0 pF should be red, black, white, not black,red, black. 2. Listing of complete range of characteristics does not necessarily implycommercial availability of all values but is for the purpose of providing a standardidentification code for future development.

Fig. 5 Color-code marking of EIA standard RS335 composition capacitors withratings as follows: Working potential, 500 V; Operating temperature, 85°C.( Electronic Industries Assticiation. )

Color

BlackBrownRedOrangeYellowGreenBlueVioletGrayWhiteGoldSilverNo color band

First and secondbands: first and

second significantfigure of capacitance

01234567B9

Third banddecimal multiplier

110

0.010.10

Use lowest possiblenumerical multi-plier

Fourth band:capacitancetolerance, %

±5±10±20

Capacitance-tolerance deoignation

JK

M

25

EIA Identifier(white)\ 1st Significant

digit 2nd Significantdigit

Characteristic

O O Q """Indicator styleS2——> \^ optional

\Multiplier

Capacitance tolerance

Fig. 6 Color-code marking of EIA standard RS153 mica capacitors. The multiplieris the factor by which the two significant figures are multiplied to yield the nominalcapacitance.

Color

BlackBrownRedOrangeYellowGreenBluePurpleGrayWhiteGoldSilver

Characteristic

Letterdesignator

BCDEF

Temperaturecoefficient

of capacitance,ppm/°C

Not specified±200±100

-20 to +1000 to +70

Maximumcapacitance

drift

Not specified± ( 0 . 5 % + 0.1 pF)±(0 .3% + 0.1 pF)± ( 0 . 1 % + 0 1 pF)±(0 .05% + 0.1 pF)

Capacitance

Firstand secondsignificant

figures

0123456789

Multiplier

110

1001,000

10,000

0.10.01

Capacitancetolerance,

%

±20 (M)±1 (F)±2 (G)

±5 (J)

± M (E)±10 (K)

Inner electrodetermination

5-Dot system

1

Do not use for T C values l\„„„~„ 6

Temperoturecoeff cient

of copoc i t ance(5-dot system)

ppm/°C

0-33-75

- 150-220-330-470-750

General purpose(Note A )

General purpose(Note B )

| shown in 5-dot system J I ^-Dot system

v J 4 1S ignif icont figureof temperaturecoeff icientof

capacitance(6-dot system)

0 0

1.01 5

2 23 34 77 5

General purpose( Note C)

Multiplier to opplyto significant figure

of temperaturecoefficient

(6-dotsystem)

- 1-10-100-1000- 10000+ 1+ 10+ 100+ 1000

+ 10000

Color

BlockBrown

RedOrangeYellowGreenBlueVioletGray

White

1stand2dsignificantfigure of

capacitance

01234

5678

9

Decimal multiplierof capacitance

(use lowest possiblenumericalmultiplier )

t

10100100010000

0 01

0 1

1Tolerance ofcapacitance

Nominal10 pF

or less.pF

Î2 0*0 1

»05

*025Î1 0

Nominalover

10pF,%

!20± 1"-ZÎ 3

±5

Î10

Fig 7 Color-code marking of EIA standard RS198 temperature-compensating capacitors. (Electronic Industries Association.) Notes:(A) This is a general-purpose capacitor having any nominal temperature coefficient between +150 and —1500 ppm/°C; coefficient to beused at option of capacitor manufacturer. (B) This is a general-purpose capacitor having any nominal temperature coefficient between+ 100 and —750 ppm/°C, coefficient to be used at option of capacitor manufacturer. (C) This is a general-purpose capacitor liaungany nominal temperature coefficient between —1000 and —5200 ppm/°C, coefficient to be used at option of capacitor manufacturer. Usewith mult ipl ier color of blick.

26

TABLE 3 Color Coding of MIL-C-20 Temperature-Compensating Ceramic Capacitors

Color

BlackBrownRedOrangeYellowGreenBluePurple (violet)GrayWhiteGold

Characteristic*

ppm/°C

0-30-80

-150-220-330-470-750

+100

Letterdesignator

C-H-L-P-R-S-T-U-

A-

Nominal capacitance,pF

First andsecond

significantfigures

0123456789

Multi-plier!

110

1001,000

0.010.1

Capacitance tolerance

For nominalcapacitancesgreater than10PF,%(±)

1{F)2(G)

5<J)

10 (K)

For nominalcapacitancesof lOpFor

smaller, pF(±)

2.0 (G)

0.25 (C)

0.5 (D)

1.0 (F)

* The characteristic is a two-letter symbol identifying the nominal temperature coefficientand the tolerance envelope for the temperature coefficient, respectively. However, the char-acteristic band or spot identifies only the nominal temperature coefficient.

t The multiplier is the factor by which the two significant figures are multiplied to yield thenominal capacitance. The lowest possible numerical multiplier is used to avoid alternate cod-ing; for example 0.5 pF should be green, black, gray not black, green, white.

Significant Jsecondfigures

Characteristic

^Multiplier/ Capacitance' xtolerance

Mil identifier(block)

Inner-electrode terminal

Characteristic

Mil identifier

F i rst\ SignificantSecond/ figures

Multiplier

Capacitance tolerance(a)

Multiplier

Sigmf icant/Second\ \figures ljr'rst

Characteristic^

Capacitance/ tolerance

Mil identifier/{block)

^-Inner electrode terminal

(b)

Fig. 8 Color-code marking of MIL-C-20temperature-compensating capacitors,.(a) Dot coding. (/;) Band coding.

27

oo

TABLE 4 Standard Decade Values (Industry and Military Standards), Preferred Values for Resistors, Capacitors, Zener Diodes

* ±1% ±2%

1.00 1.00 1.001.011.02 1.021.041.05 1.05 1.051.061.07 1.071.091.10 1.10 1.101.111.13 1.131.141.15 1.15 1.151.171.18 1.181.201.21 1.21 1.211.231.24 1.241.261.27 1.27 1.271.291.30 1.301.321.33 1.33 1.331.351.37 1.371.381.40 1.40 1.401.421.43 1.431.45

* ±1% ±2%

1.47 1.47 1.471.491.50 1.501.521.54 1.54 1.541.561.58 1.581.601.62 1.62 1.621.641.65 1.651.67.69 1.69 1.69.72.74 1.74.76.78 1.78 1.78.80

1.82 1.821.841.87 1.87 1.871.891.91 1.911.931.96 1.96 1.961.982.00 2.002.032.05 2.05 2.052.082.10 2.102.13

* ±1% ±2%

2.15 2.15 2.152.182.21 2.212.232.26 2.26 2.262.292.32 2.322.342.37 2.37 2.372.402.43 2.432.462.49 2.49 2.492.522.55 2.552.582.61 2.61 2.612.642.67 2.672.712.74 2.74 2.742.772.80 2.802.842.87 2.87 2.872.912.94 2.942.983.01 3.01 3.013.053.09 3.093.12

* ±1% ±2%

3.16 3.16 3.163.203.24 3.243.283.32 3.32 3.323.363.40 3.403.443.48 3.48 3.483.523.57 3.573.613.65 3.65 3.653.703.74 3.743.793.83 3.83 3.833.883.92 3.923.974.02 4.02 4.024.074.12 4.124.174.22 4.22 4.224.274.32 4.324.374.42 4.42 4.424.484.53 4.534.59

* ±1% ±2%

4.64 4.64 4.644.704.75 4.754 814!87 4.87 4.874.934.99 4.995.055.11 5.11 5.115.175.23 5.235.305.36 5.36 5.365.425.49 5.495.565.62 5.62 5.625.695.76 5.765.835.90 5.90 5.905.976.04 6.046.126.19 6.19 6.196.266.34 6.346.426.49 6.49 6.496.576.65 6.656.73

Values per decade

* ±1% ±2%

6.81 6.81 6.816.906.98 6.987.067.15 7.15 7.157.237.32 7.327.417.50 7.50 7.507.597.68 7.687.777.87 7.87 7.877.968.06 8.068.168.25 8.25 8.258.358.45 8.458.568.66 8.66 8.668.768.87 8.878.989.09 9.09 9.099.209.31 9.319.429.53 9.53 9.539.659.76 9.769.88

192 96 48

±5% ±10% ±20%

1.0 1.0 1.01.11.2 1.21.31.5 1.5 1.51.61.8 1.82.02.2 2.2 2.22.42.7 2.73.03.3 3.3 3.33.63.9 3.94.34.7 4.7 4.75.15.6 5.66.26.8 6.8 6.87.58.2 8.29.1

24 12 6

* ±0.1, ±0.25, and ±0.5%.

TABLE 5 Capacitor Features by Dielectric Type

Type Application Advantages Disadvantages

Paper Blocking, buffering, bypass, coupling, andfiltering at low frequencies

Power-factor correctionContact protectionTiming, photoflash, motor start and run

Readily available in a wide range ofcapacitance and voltage values

Low cost per;i FReliableMedium stabilityExtensive test data

Medium capacitance-to-volume ratioHigh effective resistance at vhf

Film Blocking, buffering, bypass, coupling,filtering to medium frequency

Tuning and timing

Wide range of capacitance and voltagevalues

High IR, low DF, good QStableLowTCHigh voltage

Medium cost per j*F

Mica (dipped) Filtering, coupling, and bypassing athigh frequencies

Resonant circuits, tuningHigh-voltage circuitsPadding of larger capacitors

Low dielectric losses and good tempera-ture, frequency, and aging characteristics

Low ac loss (high Q), high frequencyHighIRLow costExtensive test data, reliable

Low capacitance-to-volume ratio

Glass Resonant circuits, tuningHigh-frequency bypassHigh-frequency coupling

High IRHigh operating temperaturesExcellent temperature stabilityLow ac loss (high Q), high frequencyExtensive test dataReliable

Low capacitance-to-volume ratio

Ceramic(general-purpose

Bypassing, coupling, and filtering tohigh frequency

High capacitancc-to-volume ratioChip style availableLow cost

Poor temperature coefficients and timestability

Susceptible to shock and vibration damagePoor reliability (particularly high-A

commercial types)

TABLE 5 (cont.)

Type Application Advantages Disadvantages

Ceramic(temperature-compensating)

Compensation for temperature variations Temperature characteristic can be closelycontrolled. Stable with time

Available only in low capacitance valuesSusceptible to shock and vibration damageLow capacitance-to-volüme ratio

Variableceramic andglass piston

Frequency tuning Selectable TC (ceramic)HighQ

Susceptible to humidity, shock, and vibra-tion damage

Low-capacitance-to-volume ratioLow capacitance values onlyHigh cost

Tantalum(solid di-electric)

Blocking, bypassing, coupling, and filter-ing in low-frequency circuits, timing,color-convergence circuits, squib firing,photo-flash firing

High capacitancc-to-volume ratioGood temperature coefficientsExtensive test data

Voltage limitationLeakage currentPoor rf characteristicsMedium cost

Tantalum(foil andwet-slug)

Bypassing and filtering in low-frequencycircuits

High capacitance-to-volume ratioHighest voltage for tantalumsLowest leakage currents (slug)Extensive test data

Poor temperature characteristics, particu-larly at low temperature

Susceptible to shock and vibration damage(particularly slug)

Seal lifeMedium to high cost

Aluminumelectrolytic

Blocking, bypassing, coupling, and low-frequency filtering

Photoflash

Highest capacitance-to-volumc ratio ofelectrolytic«

Highest voltage of electrolytic«Highest capacitanceLowest cost per cv unit for commercial

typesHigh ripple capability

Affected by chlorinated hydrocarbonsHigh leakage currentRequires more reforming after periods of

storageMedium to high cost for types with con-

trolled reliabilitySusceptible to dynamic environments

EXPERIMENT 2

INTEGRATOR WITH RESET

Objective: The operation of an active integrator is demonstrated byusing dc and rectangular input signals. For the integrator reset afield-effect transistor Field-effect transistor (FET) is used and itstypical properties are pointed out.

IntroductionThe circuit as shown in Fig. 2.1 performs the time integration of the

input voltage vj:

V0 = - ~ v dtl/ KL* l

vo-oFig. 2.1 Voltage integrator

If a small constant voltage of -100 mV is applied to the input ofour circuit with R = l M and C= 10 nF, the ramp voltage

10io6. io-8 t = 10 t

will be produced. Starting from VQ = 0, the saturation voltage of 10Vwill be reached in 1 second. To restore the initial state, the capacitorshould be discharged. One way to do this is to introduce the n-channelFET 2N3819 as the analog switch (Fig. 2.2). When the FET gate isconnected to the negative power supply voltage -V, drain-to-sourcechannel is nonconductive (R0ff = IO' ohm). When the gate voltage ismade close to zero by grounding the left side of the 10 k resistor, theFET is made conductive (Ron = some 100 R).

10 K

-12Ji_n_ -12

Fig. 2.2 Integrator with reset+ 12

Saturation of the integrator amplifier may be avoided by connectinga large value resistor Rf across the feedback capacitor as shown inFig. 2.3. In this case the integrator response to a dc input voltage

31

vc namely -(Rf/R)Vc . Therefore, with the input grounded an outputvoltage close to zero is achieved. After this modification theintegration of ac signals of frequency f is still correctly performed ifthe relation 2 fRfC 1 is fulfilled. In the opposite limiting case,when 2 fRfC 1 the circuit is an amplifier with the gain of -Rf/Rj.

Fig. 2.3: Integrator with dc resistive feedback

ExperimentAfter assembling the circuit drawn in Fig. 2.2, check the operation

of the integrator with the grounded input. The expected output voltageVQ should be zero. However, the observed voltage tends to slowlyincrease or decrease. Therefore, the exact zero of the integrator shouldbe set by turning the potentiometer and observing the output voltage toget the stable output.

To prove the integration, a small input voltage of the positive ornegative polarity should be applied. The saturation level of VQ iseasily reached. If the voltage is decreasing, the saturation level isobserved at approximately -6V. This effect is caused by the FET whichstarts to conduct if its drain voltage exceeds one half of the gatevoltage which is -12V.

If the rectangular voltage is applied to the input, the expectedoutput voltage is of the triangular form. However, a ramp-steppedvoltage signal is superimposed to the triangular output voltage until theintegration is stopped either by the positive or the negative saturationlevel. This can be explained either by the dc component present in theinput signal or by the input offset voltage instability.

Prove that the integrator becomes stable when 20 M (=10 + 10)resistor is connected across the feedback capacitor. Try to find theminimal frequency of the rectangular input signal where the triangularoutput signal is still undistorted. How much is the term 2 fRjCf inthis case?

32

EXPERIMENTS

UNIVIBRATOR

Objectives. The operation of the positive edge triggered Univibratoris studied. LED drive through a CD 4XXX 1C is considered, and the delay pergate in the CD AXXX family is demonstrated.

IntroductionThe circuit in Fig. 3.1 is the positive edge triggered Univibrator. It

delivers positive pulses of the preset duration and uniform amplitude whenthe input voltage jumps from the low to high state in a sufficiently shorttime.

IN ..II-

IN

OUT

TRUTH TABLE FOR NORX

0011

y0101

z1000

OUT=

Fig. 3.1: Univibrator circuit Fig. 3.2: Univibrator signals

In order to understand the Univibrator operation let us start with theinpuL signal being zero and let us follow the corresponding signalsrepresented in Fig. 3.2. A constant z signal has no influence on the usignal. The u signal is high and y is low. Two low states, x and y resultin high z as seen from the truth table for the NOR gate. However, when theinput, signal jumps from the low to high state, this transition, transmittedthrough the input capacitor, lifts the input voltage x above the thresholdlevel. Therefore z jumps down. This high to low transition of z pushesdown the u voltage changing the y from high to low. When the positive goingpulse at x go down, the low z state is sustained through the y input.

The duration T of the y high state is determined by u which should bebelow a certain threshold voltage. When this voltage has been reached ygoes down, causing the jump in z signal. The positive part of thetransmitted signal, above 12 V, is clamped by the protecting diode insidethe 1C.

The high to low transition of the input signal has no influence on thefurther operation.

33

i. J"o — I — t — K10 n OCD 4001

T

-TWV

Fig. 3.3: Univibrator and LED display schematics

ExperimentsVerify the operation of the circuit (Fig. 3.3) after assembling it,Add external resistors in parallel either to R-^ or to R2» observe

the changes and try to explain them. The output pulse duration T isdetermined by the moment of the intersection between the exponentiallydecreasing voltage u = -VQ e -t'RC, and the NOR gate logical thresholdvoltage, approximately V0/2. Calculate the dependence of the pulseduration T on R and C.

The circuit given in Fig. 3.3 offers additional opportunity to learnsome electronics. How to observe the Univibrator operation by alight-emitting diode (LED)? The current output of 120 /iA, typical for theCD 40 family is too small to drive a LED. Therefore, a transistor amplifieris inserted. During the positive pulses delivered at the Univibratoroutput, the current of 120 yuA flows into the transistor base. If thetransistor current amplification factor of 200 is assumed, the collectorcurrent would be 24 mA. For proper LED operation, about 10 mA is required.Therefore the collector current is limited with the Ik resistor.

This is true for the dc operation. In the case when LED is connectedto the pulses, the average current through it is much smaller, and theproportionally lower light output might be expected.

Try to observe the light output at different pulse rates. The light isnot much less than under the dc operation. With pulse operation of LEDdisplays by strobing, the power consumption is drastically reduced.

It might be interesting to follow the propagation of the Univibratorpulses through gates connected in series. The output signal after thedouble inversion in CD 4001 NOR gate is similar to the input signal, butdelayed. Try to measure the time difference between signals by using thesimultaneous oscilloscope representation of both pulses.

34

EXPERIMENT 4

INVERTING AMPLIFIER

Objectives; The properties of the inverting amplifier are studied. Byits expansion into the summing amplifier with weighted inputs thepossibilities for digital to analog conversion are demonstrated.

Introduction:The operational amplifier, as shown in circuit diagram (Fig. 4.1),

provides the output voltage vo = -(Rf/R^v^ as the response to theinput voltage vj. The majority of the contemporary amplifiers is fullycompensated, and therefore no additional components are needed for stableoperation, irrespective of voltage gain determined by the Rf/Rj ratio.The above formula is of importance in different situations, therefore itsderivation is presented below.

Fig. 4.1: Inverting voltage amplifier

From the already known relation VQ = A (v"1" - v~) follows for thedifferent v+ - v~:

v+ - v~ =Therefore, for large A the difference v+ - v~ tends to zero, for

any finite VQ. In our circuit with v+ = 0, v~ must be also zero.When the voltage vj is applied to the input of the circuit, the

current i^ = v^/Rj will flow into the node point at . The secondcurrent into the node point is the current through the feedback resistorif = VQ/Rf. The third current there is the bias current of theoperational amplifier which is normally very small, 80 nA for 741, and 70 pAfor LF356, for example. According to the Kirchoff law the sum of allcurrents into the node point should be zero, or ij + if = 0, in ourcase. Thus, for VQ follows:

VQ = -(Rf/Rp Vi-

The circuit which has to be assembled according to Fig. 4.2 has twoinputs to apply the signal. For the signal connected to the upper input,the gain is -5,6/20 = -0,28. For the signal connected to the lower inputthe corresponding gain is -0,56.

What can be expected if the same signal, for example the positivesupply voltage, is applied to both inputs? Both output voltages aresuperimposed, and the resulting voltage is the sum of the separatecontributions. This can be proved mathematically as before following theidea that the two input currents must be balanced with the feedback current,i.e. iji + i^2 + if = 0.

35

20k 5K6

Fig. 4.2: Summing amplifier

Exercise.Assemble the circuit shown in Fig. 4.2. Insert OIL 8 socket to have a

way for easy exchange of operational amplifiers. Start with LF 356. Verifythe circuit operation by using at inputs dc supply voltages as well as theperiodic signals from the signal geneator.

Check two bit digital to analog conversion with the positive supplyvoltage as 1 and ground as 0. Setting (0,0), (0,1), (1,0) and (1,1) inputcombination the output voltage will fall in equal steps 0, -vo, -2vo and-3v,o*

The circuit could be modified to perform any multi-bit conversion.Replace LF 356 by LF 357. Now the output voltage oscillates; the

stable operation is achieved only if Rf/Rj<5.Observe the pulse response of amplifiers LF 355, LF 356 and 741. Set

pulse amplitude 1 to 10 v, repetition rate as high as possible, and pulsedurations from 0.5 /as to 10 jus. Very sharp input pulses will be smootheddue to the insufficient amplifier gain at high frequencies. The effect willbe more pronounced if gain Rf/Rj is increased to 100 by replacing thefeedback resistor of 5k6 by a l M resistor.

36

EXPERIMENTA

SIGNAL AMD PULSE GENERATOR

Objective: The signal and pulse generator is produced according toEurostandard to be used in later experiments. It provides rectangular andtriangular voltage up to 10 V peak to peak in the frequency range from 2 to2.103 Hz. From the separate output periodic positive pulses of thevariable amplitude 0 to 10 V, and the variable duration 1 to 1A us of thesame frequency as above are delivered.

Introduction:The triangular and rectangular signal generator can be made by

connecting the discriminator with hysteresis and an integrator in the closedloop (Fig. A.D.

INTEGRATOR 1 i i

^\

Fig. A.I: Triangular and rectangular signal generator

The operation of the circuit can be understood by assuming the lowstate of -10V at the discriminator output. Therefore the integrator outputvoltage linearly grows in time until the discriminator upper transitionpoint is reached. Then the discriminator output voltage jumps into the highstate at 10V approximately. Due to the integration of the positive inputsignal, the integrator output voltage descent linearly until the lowertransition point is reached. After the discriminator output voltage ischanged back to the low state, the cycle is over.

/w & n_nGEN.

JU1 UNIVIBRATOR PULSE AMP.

/W LINEAR AMP._n_TLTL

Fig. A.2: Blocks of the signal and pulse generator

The frequency of the generated signals can be regulated by reducing theamplitude of the rectangular signal before the integration. Small inputamplitude will result in a slowly increasing slope of the generatedtriangular voltage, and a long time will be needed to reach one or othertransition point.

37

The triangular voltage is obtained at the output of the integrator, andthe rectangular at the output of the discriminator. The desired voltageform is selected by the switch S^ for the amplification in the linearoutput stage with the variable gain. In this stage the operationalamplifier is used as a noninverting amplifier.

Having the triangular and rectangular voltage the circuit reading canbe extended to the additional functional blocks (Fig. A. 2). The analogsignals are amplified in the linear noninverting amplifier. For the pulsegeneration the positive edge triggered Univibrator is used, and amplitudeof the generated pulses is controlled by using the pulse output amplifier.

For the noninverting amplifier shown in Fig. A. 3 the relation betweeninput and output signals will be derived. As shown in Exercise 1,"Discriminator", the difference v = v+ must be 0, thereforev~ = v+ As u is the R2/(R1 + R2) part of the output voltage VQ;namely:

v~ = [R2/(Rione can write

v0 = [ ( R! + R2 ) / R2 1By the proper choice of R^ and R2, any amplification without the

signal inversion between 1 and the amplifier open loop gain can be obtained.

Fig. A.3: Noninverting amplifier

The distinguishing feature of the noninverting amplifier is its highinput impedance. This makes it suitable to accept input signals from apotentiometer providing variable gain control. The potentiometer is notloaded and the gain scale is linear.

The already familiar building blocks can be recognised in Fig. A.4.The frequency of the triangular and rectangular signals can be varied intwo ways. Continuous regulation is achieved through potentiometer ?2 inthe range 1:100.

The operation of this system is poorly defined if the rectangularsignal is attenuated more than 100 times. Below these values the amplitudeof the attenuated rectangular signal becomes comparable with the input off-set voltage drift of the integrator. Therefore the lower part end of thedividing potentiometer is separated from the ground by a 100 R resistor.Coarse frequency regulation is achieved by an additional capacitor whichcan be connected in parallel to the 10 nF capacitor in the integrator.

Because the triangular and rectangular signals are not equal inamplitude they are connected to the input of the noninverting amplifierthrough the equalising resistors 5k6 and 15 k. The output noninvertingamplifier with a gain of 2 provides the output signals of amplitudes 10 Vpeak to peak.

38

The positive edge triggered Univibrator activated by the rectangularinput signal and serving for the pulse generation is explained inExperiment 3 "Univibrator". By the variable resistor in place of R2, theoutput pulse duration can be varied. To get the positive pulses from theone-transistor amplifier the Univibrator positive pulses are invertedbefore being applied to the base of the output transistor Trl. Thistransistor is either fully conductive with a large current sink capability,or fully closed. In the latter case the output impedancy is 390 R, thevalue of the collector resistor. In this switched operation, the height ofthe output pulses is determined by the supply voltage i.e. the voltage atthe emitter of the transistor Tr2. Due to the variable voltage on the baseof this transistor, any value for the amplitude of the output pulsesbetween 0 and the supply voltage can be set.

ExperimentsBefore assembling, it is useful to check, the printed circuit board for

the broken lines or for short circuits. Assembling starts with jumpers.During the assembling it is useful to check the operation of the separatestages.

See Fig. A.5 for the component layout.

O H O

Fig. A.4: Signal and pulse generator

The discriminator and the integrator are first assembled, and theiroperation is checked. Then the noninverting amplifier is made andchecked. Finally the Univibrator is assembled and signals at pins 4 and11, CD 4001 are verified.

If the generator will not operate, very probably the careful visualinspection of the soldered board will reveal one or few unsoldered points.It is also useful to check supply voltages at all corresponding 1C pins (12V at pin 7 for both all LF, and pin 14 for DC, -12 V at pin 4 for all LF,and ground at pin 7 for CD).

At last insert all the necessary components into the front plate, fixthem well and join the plate with the front plate with the printed circuit

39

P1ooLO

-V Ooo

xK) xi000

10n

10K1005K612K

P3[;P2[°

OUTVIi oP4o

£0d>enCZ3

O.luCD O. *:C3 ^<=> O

OD 0*00a.o

Ü0i!

Fig. A.5 Component layout

board mechanically using screws and small plastic cubes. Be careful atwiring when connecting the front plate components with the assembled board.The wires connecting the switch S^ should not be parallel in the flatcable; this will cause spikes to appear at the top and bottom of thetriangular signal, due to capacitive coupling.

40

PART 2

POWER SUPPLIES

EXPERIMENTS

RECTIFIER BOARD WITH FILTER CAPACITOR

Objective: Study the basic properties of input capacitor filter stage.

Introduction:This board contains the necessary elements to construct a primaryrectifier and filter circuit to be used in a regulated power supply.The basic relationship between AC and DC voltages and ripple with loadcurrent will be examined.

a. Full Wave Bridge18V 10 VA

4x 1N4007

Full Wave Centre-tap

2 x 1 8 V 10 VA

W 1=9 C 1000 "F' dc t 35V

2x 1N4007

Fig. 5.1: Rectifier circuits

ExperimentAssemble one of the two possible configurations.

Proceed as follows:

A. With no load, measure Vdc and VTCheck the following basic equation:Vdc = 1,41 VT - 0.8 x nn = 1 for Half Wave Centre Topn = 2 for Bridge Rectifier

43

B. Connect a IK load resistor. With a de-coupled oscilloscope, look atthe voltage waveform at the output. Sketch the waveform, indicatingvoltage levels.

C. Switch the oscilloscope to ac coupling. Measure the peak-to-peakripple Vripple pp = . Record also the load current, I2.Repeat for several values.

D. With the results obtained in C, check that

Vripple (peak-to-peak} = K

K = 10 for 50 HzK = 8,3 for 60 Hz

C(uF)

E. For a given load, change the value of the filter capacitor andobserve the effect. Comment on the results.

44

EXPERIMENT 6

AUXILIARY POWER SUPPLY + 15V/100mA.

Objective: To demonstrate the properties of the monolithic voltageregulator.

IntroductionThis simple power supply is intended to be used as a building block for

any application requiring +15 and -15V at 100 mA typically when operationalamplifiers are used.

Two possible versions can be assembled: version a uses four rectifierdiodes and two complementary three-leg regulators: 78L15 for positivévoltage and 79L15 for negative voltage.The b version uses only one type of monolithic regulator, namely 78L15,at the expense of using two bridge rectifiers (or eight diodes).In both cases the basic relations between ac and dc voltage, ripplerejection and regulation capability of the power supply will beexamined.

Version a. 2x18V5VA -W—

— W—L- M —— •

VdcIB

•fB

SJ50035V

500^35V

m

78 L 15

PF

JF

79L15

+ 15

rf.+ 15V/ 100mA

4x JN4007 -15V/100mA

Version b. +15

0-15

Fig. 6.1: Auxiliary power supply + ISV/lOOmA.

45

ExperimentAssemble one of the two possible versions and proceed as follows:

A. Measure the following parameters at no load and full load conditions:

II = 0Lt

11= 100 raALi

VT vdcvo V ripple at A V ripple at B

Comment on the results.

B. Calculate the regulation against load variations. (Take the valuesobtained from A). Compare with the value given in the data sheet.

V% regulation = o x 100

C. Calculate the ripple rejection factor at full load:

ripple rejection = V ripple at AV ripple at B

D. Make a short circuit at the output,current, Isc

Measure the short circuit

46

EXPERIMENT B

REGULATED POWER SUPPLY USING AN OPERATIONAL AMPLIFIER

Objective; This experiment illustrates how a power supply can be builtwith standard components as it works as a complete feedbacked amplifier.

Introduction:The voltage stabilizing loop is determined by the operational

amplifier, power transistor Q^ and resistors Rg, R7 and Rg.

Fig. B.I: Regulated power supply using an operational amplifier

Suggested values:Rl = 330RR2 = 2K2R3 = 820RR4 = 500 R trimmitR5 = 15KR6 = 10KR7 = IK trimmitR8 = IKR9 = 2K2R2 = 5R6/1WRL = 1K/10W w/W/ Pot

QlQ2Q3

1C

Dl

ClCO

BD 6512N39042N 3904

LF356

1N4007

100/35V10/25V

Transistor 0.2 and resistorstype current limiting circuit.

, TSL^ and Rs form a foldback

To understand the action of the voltage stabilizing loop, consider thatunder normal load conditions the current limiter circuit is not operating.0.2 is cut off.

The reference voltage Vg is developed across a reverse biasedbase-emitter junction of a small signal transistor 0.3. A zener diode canalso be used.

Now, let us suppose that the output voltage tends to decrease. Thiswill vause V(_) to decrease and so will the error voltage. This in turn

47

will raise the output voltage of the op-amp making Q^ to conduct more,cancelling in this way the original decreased of VQ.

The foldback type current limiter circuit works as follows: under lowcurrent conditions the drop of voltage across Rs is less than the voltagedeveloped across R3 and R4 which produces a bias at the base emitterjunction of 0.2- For that reason Q2 is cut-off.

The moment at which Q2 starts conducting is when:R = * V + 0.5 V (1)

k is the fraction of output voltage developed across R% and the upperpart of R4 (actually k is adjusted with

As Q2 starts to conduct, it takes the current which previously wentthrough the base of Qj_: the current limiting action takes place. Theoutput current cannot be greater than Imax-

When there is a short circuit at the output terminals the outputvoltage VQ equals zero. From the circuit it is easy to observe that

ISc Rs = 0.7V (2)

as the base current of 0.2 is negligible.

It can be noticed that the short circuit current ISc, is smaller thanthe maximum current IM.

ExperimentThe experiment permits the testing of the proposed circuit verifying

the actions explained above.With the properly selected values for the components, a V/250 mA power

supply can be assembled.As a primary rectifier and filter, a circuit assembled in Experiment 6

of this series of experiments will be used.

A. Adjust R? to obtain 15V at the output voltage Vo.

B. Measure:voVR = depends on the characteristics of 0,3

VA = should be equal to the peak value of VdcVB V0 + 0,6V (at no load) (or Vo + 1,2 V if

a Darlington transistor is used)

C. Adjust the load resistor to have an observable ripple at theinput Vcic- Measure the ripple at the output.

48

V ripple at input =(1)

V ripple at output =(2)

. ., .... (1)ripple rejection = Try =

D. Change the mains voltage using an autotransformer and observe theoutput voltage variation À Vo =. Calculate the regulation againstmains variation

E. Change the load from IL = 0 to full load and observe the outputvoltage variation A Vo . Calculate the regulation against loadvariation.

F. Adjust R4 to obtain IV at VF.

G. Progressively increase the load current monitoring the outputvoltage up to the point when Vo starts to decreaseAt this point measure:

VBEQ2 =k V^Vp =

record IL = Ijj and verify equation (1).

H. Short Circuit the output measuring Isc. Verify equation (2)

I. Plot V-I characteristics

49

EXPERIMENT CREGULATED POWER SUPPLY USING A MONOLITHIC VOLTAGE REGULATOR

Objective; This experiment illustrates the utilization of a monolithicregulator in which the reference, error amplifier and current limiter residein the same package.

Introduction:The LM 723 is a versatile monolithic voltage regulator used in this

experiment to build a 5V/1A power supply mounted onto a Eurocard board.As it supplies ISO mA only, an external power transistor is used to

increase the regulator current capability.For details concerning the operation of the regulator itself it is

advisable to read the corresponding data sheets. In this experiment anauxilliary power supply consisting of a voltage doubler Dj_, €2, D2,C3, R! and D3 provides bias for the LM 723. Resistors R4, P2 andR3 fix the maximum and short circuit current as they determine togetherwith the internal current limiting transistor, a fold back configuration.Resistors R6, P^ and Rj fix the output voltage.

Note that separate wires are used to sense the output voltage. Thistechnique is used in those cases where the load is far from the power supplyand the drop of voltage in the cables are to be compensated. Fig C. 1.illustrates this situation.

100 mV -\ A = 4.8V

LOAD

a) Sensing at the output terminals. The drop of voltage is notcompensated and the load receives a lower voltage.

P.S. V5.2V— o —— = ——

100 mV * r1

100 mV * Sl

V=5V-_____ipumv___* ~-r •-S

b) Sensing is done at the load, where the full voltage is developed. Thedrop in the cables makes that the output terminals are at 5,2V.Fig. C.I: Local and remote sensing for a load located far from thepower supply

ExperimentThe circuit diagram of the regulated power supply is given in Fig. C.2,

the components layout in Fig. C.3

51

IsJ

n

AC

C2.

Ct

XX

Tf

~U—rf>HH V

n n»R7 R8

J)6

Fig. C.2 Regulated power supply with monolithic regulator

ooooooolet Cooooooo

Fig. C. 3 Components layout for power supply

In order to be sure that the building up of the circuit is proceedingproperly, the assembly is done in steps.

A. Connect the transformer, using 11V tap on secondary for 220V and 10Vtap for 240V line voltage. Mount rectifier bridge, diodes D^ D2and 03 and capacitors C^ to C^ and resistor Rj_.Verify V<jc at C$, V^c atare the expected values.

and at 03. Check if they

B. Mount the rest of the circuit. At the output terminals connect thesense lines with wire bridges to the output lines.Increase progressively the mains voltage using a variableautotransformer up to the nominal value. Adjust P^ to get +5V at theoutput terminals. Measure the following parameters:

line regulationload regulationripple rejection

Follow the instructions given in Experiment B of this series.

C. Short circuit protection.Adjust the load resistor to have a current of 1A. Adjust

the current limiting action.Make a short circuit and measure the short circuit current I

to start

SC'

53

D. OPTIONAL: Mount in a separate board the overvoltage protection circuitillustrated in Fig. C.4. Should the output voltage reach the (adjustable)threshold, the circuit triggers and short circuits the output lines, thusdriving the power supply into current limiting or blowing up the fuse incase the pass transistor is short-circuited. In both cases the load isprotected again overvoltages,

Measure the trigger level of the protection circuit by increasing theoutput voltage with P^.

Fig. C.4: Overvoltage protection circuit

Suggested values for the requested power supplyTransformerRF11C 1TlD l, 2, 6D 3C 1C 2, 3C 4C 5C 6C 9P 1, 2R lR 2, 3R 4R 6R 7, 8, 9

pr. 110/220 V, 50/60 Hzfull wave rectifier 1.5A/20 VAC (B 80 C 37000/2200)integrated circuit LM 723 CN with socketDarlington power transistor NPN (BD 651)silicon diodes 60V/1 A (l N 4004)

l W (BZX 85 C 12)0.47

12V

electrolyticelectrolytic 2200 /u/15 Vceramic

zenerdiodecapacitorcapacitor,capacitor,capacitor,capacitorcapacitor, electrolytictrim potentiometerresistor, metal film

metal filmwirewoundmetal film

.1 /u/100 V/u/40 V

resistor,resistor,resistor,resistor, metal film

470 p2.2 /u/25 V100 xu 25 V500 R511 R3 k

1R2, 5Wl K3 K

Suggested values for the overvoltage protection circuit

T 2D 4D 5C 7,P 3R 10R 11R 12, 13, 14

transistor PNP (2N 3906)zenerdiode 5,1 V 0.5Wthyristor 4A/100V (2N 4441)condensor 0.1 /uF/100 Vtrim potentiometer 500 Rresistor 1,5 kresistor l kresistor 100 R

54

EXPERIMENT?

HIGH VOLTAGE POWER SUPPLY

Objective; To analyze a typical circuit used in high voltage powersupply for detector biasing.

IntroductionThe power supply to be assembled and tested produces 900V at

approximately 1 mA. The circuit diagram is on Fig. 7.1. A square waveoscillator feeds a driver stage which is connected to a step-uptransformer. The centre tap of the primary winding is connected to a 12 Vsupply coining from a voltage regulator. Under these circumstances a 440 Vsquare wave is developed in the secondary winding. This ac voltage isrectified in a doubler type rectifier circuit.

lOOOpF.01/1KV

120K1N 400702

CD 4011CD4027

OUT

900V1mA

AK7

1K8

»n„iV

V 5

i1Q

CL C<OUTVref.N'mv.

VCC-7J_

U

4/F/25

1

1; INV

COM.L M 723

Vcc Vc

r*•-Jv

M/2W

ISTif1".01_

11

4C\I

:i 15K

Fig. 7.1:(FROM EXTERNAL SUPPLY)

High voltage power supply

The double circuit works as follows: diode D^ charges capacitor C-^to the peak of the voltage present at the secondary. Between A and B avoltage which is the sum of the dc voltage developed at C^ plus the acvoltage at the secondary winding is in turn rectified by D2 and filteredby C2. The result is that capacitor C2 is charged to the peak value ofthe voltage existing between A and B, that is to say, double of the peakvoltage at secondary winding.

55

The voltage regulator samples the high voltage and adjusts thepotential of the centre tap to compensate for possible variations of thehigh voltage. Potentiometer P permits the final adjustment of the highvoltage.

The oscillator is implemented with a CMOS integrated circuit. Aflip-flop assures a perfectly symmetrical wave at the primary winding of thetransformer avoiding possible circulation of dc current through it.

Note that this is an experimental power supply to illustrate theprinciples upon which a commercial unit is built. For a practicalapplication additional circuits are needed such as filtering networks, highvoltage potentiometer for adjustment of the output voltage, provision forinverting polarity and for output current measurement.

Experiment

A. Assemble the circuit as is indicated in the circuit diagram, Fig. 7.1.

B. Connect an external 15 V power supply and check the following:

the oscillator is running. Measure the frequency of oscillationf = . oscthere is a symmetrical square wave at the flip flop output.the collector of the driver transistors reaches saturation level.vsat = •there is high voltage at the output VQ = . Adjust P ifnecessary.

BE CAREFUL WITH THE HIGH VOLTAGE OUTPUT.

C. - Measure the voltage across the filtering capacitors V^ = and

Reduce the output voltage adjusting P and observe the wave formsat A and at C. Sketch them.Connect a suitable load, (calculate it) and measure the ripple.

When connecting a load, measure the centre tap voltage. Does itchange? Why?

D. OPTIONAL

Add one more multiplying stage. Measure the output voltage.

Using an external generator at the clock input of the flip-flop,try to find an optimum frequency for which the current drawn fromthe voltage regulator is minimum.

56

PARTS

ANALOG CIRCUITS

EXPERIMENT 8

COAXIAL CABLES (AND DELAY LINES)

Objective; The object of this experiment is to measure characteristicparameters of a coaxial cable <RG 58/U) and of a delay line.

Introduction;Coaxial cables are normally used in the interconnection of nuclear

modules. Like any other transmission line they exhibit inductance andcapacitance per unit length. If the load impedance at the receiving end ofa coaxial cable does not have a particular value called characteristicimpedance Z0, a portion of the voltage and current travelling along thecable toward the load will be reflected at the load, resulting in voltageand current waves travelling back towards the generator end of the cable.The output impedance of the generator should also have the value 20 if anyreflection coming from an imperfect impedance match at the receiving end isto be absorbed.

The characteristic impedance is given by the following expression;

-IFL = inductance per unit lengthC = capacitance per unit length

The propagation time istd = L x 7According to the recommendations given in the NIM standard Preferred

Practice, 93 R coaxial cables are used for analog signals. This is sobecause the higher impedance of these cables placed lesser demands onamplifier output current capability and this makes for increasedlinearity in the system. For short cable lengths impedance matchingtermination is not required as reflections do not cause trouble; shortstands for lengths such that the transmission time is much smaller thanthe signal rise time (for example, a 1m cable gives negligible reflectionwith a SO us rise time signal; for most analoge signal cables under 2m donot require termination). For long lengths of 93 R coaxial cable, 91 Ror 100 R (which are standard resistance values) provide adequatetermination.

For fast logic signals, 50 R cable is used and always properlyterminated.

In the case of linear outputs, nuclear modules usually provide twoconnectors, one giving the signal through low source impedance and theother through 93 R. The low impedance output is normally used but if thecable is long and not terminated, reflections and/or oscillation canhappen. In this case the 93 R output is used.

The cable capacitance is also an important parameter to be consideredin some cases, such as in detector-preamplifier interconnection. Toreduce noise, low capacitance at the preamplifier input is desired. The

59

capacitance per unit length is inversely proportional to the ratio ofconductor diameters and directly proportional to the dielectric constantof the material between conductors. The characteristic inductance isdetermined by the same factors. Thus similarly constructed cables withthe same impedance will have the same capacitance per unit length,regardless of the diameter size. Because of their lower capacity 100 Rcables are recommended for detector preamplifier connections.

A comparison of coaxial cables is given:

CableType

Impedance(ohm)

Capacity/Foot(pF)

Outside Diam.(in.)

MatchingConnector

RG-58C/URG-59A/URG-62A/UMicrodoL93-3913

507593

100

29.520.513.5

13.0

0.1990.2420.249

0.132

UG-88/U(BNC)UG-260/U(BNC)UG-260/U(BNC)Microdot32-75

The current capability of the output stage should be checked when acable is terminated; for example a current of 100 mA must be supplied todevelop a 10V signal in a 100 terminated cable.

Experiment:1. Mount a BNC plug to one end of the cable.2. Connect a Ik R resistor to the output of the pulse generator to

increase its output resistance (nominally 50 R) as shown inFig. 8.1. Solder a cable to the resistor and make sure that theground connection to the output connector is as short as possible.Apply a pulse (e.g. 5V, 10 us) to the cable.Connect the probe of the oscilloscope to the input of the cable andmeasure the risetime of the pulse.

T-plug£sHH j-to scope

Fig. 8.1 Schematics of cable experiment, Step 2

Calculate the capacitance C of the cable per unit length (pF/ra)3. Connect a coaxial cable (length ~ 6m) directly to the pulse

generator via a BNC-T piece (see Fig. 8.2). Check the pulse shapeat the cable input (use the probe).

a) with the cable open at the far end (R = oo)b) with the cable shorted (R = 0)c) connect to a preset potentiometer of Ik R to the end and try to

match impedance.

60

T-plug

50R

to scope

Fig. 8.2 Schematics for cable experiment, Step 3

Measure the transmission delay time t<j of the cable (ns/m).Calculate the inductance L (uH/m) and the characteristic impedancefrom the relations and compare the latter with the measured value.

= y LC

d) Observe multiple reflections (at the receiving and sending ends) byrepeating a) and b) with a resistor (220 R) in series with thegenerator output.

4. Delay lines behave like coaxial cables but with much larger valuesof t<j and Z0 (this is due to a comparatively larger value of L).Repeat experiment 3 with a 1 /us delay line (if necessary place a

resistor in series with the potentiometer so that matching may beachieved)»

61

EXPERIMENTS

FILTERING AND DECOUPLING IN NUCLEAR ELECTRONICS

Objective: Demonstrating the effects that may arise in analog circuitswhen power supply lines are not adequately filtered and where no decouplingis introduced between active devices.

Introduction:The amplifier, the circuit of which is shown in Fig. 9,1, is built at a

non-inverting stage with a voltage gain of 23 followed by an inverting stagewith a gain of -18. As there is no power supply decoupling high-frequencyoscillations most probably will occur.

R41K

R2

Fig. 9.1 Circuit diagram of an amplifier stage

ExperimentMount the circuit on the board supplied. Do not use any decoupling.Note that the printed board (Fig. 9.2) is poorly designed.

Fig. 9.2: A possible layout for the amplifier

Look, at output of ICI and IC2 with a scope probe. Use a resistor of300R or so in series with the probe to be sure that no oscillations aredue to probe capacity to ground.Measure the frequency and amplitude of an eventual oscillation presentin the circuit. If so, decide whether dc measurements with a. DVM aremeaningful.If the circuit does not happen to oscillate reduce the gain byshort-circuiting R3 and changing R5 to Ik and repeat step 2.

63

4. Try to eliminate any oscillation by decoupling the power supplies.Observe what happens when (i) the power lines are decoupled at thepoint they enter the circuit by electrolitic capacitors, (ii) when 0.1uF polystyrene capacitors decouple the power lines near the ICI.

5. If no oscillations are present, check the dc voltages with a DVM (use a10k resistor in series with the probe).

6. Check the circuit behaviour with fast signals. If signs of ringing arepresent, observe whether a resistor in series with the input iseffective in reducing them.

7. Observe what happens when you connect a coaxial cable to the output.Repeat the observation with a 100R resistor in series with the output.

64

EXPERIMENT 10

POLE-ZERO CANCELLATION

Objective: analyzing the behaviour of a circuit whose function is thatof clipping a slowly decaying exponential pulse without adding undesiredtails.

IntroductionPole-zero cancellation in nuclear pulse processing is basically

employed to clip a unipolar, exponentially decaying signal, like thatdelivered by a charge-sensitive preamplifier, without adding unwantedtails. Prior to the introduction of pole-zero cancellation into nuclearelectronics, clipping was implemented by RC-differentiators. The clippedsignal was then followed by a tail of opposite polarity which impaired thecounting-rate capabilities of the system (see Fig. 10.1).

SLOWLY DECAYING SIGNALUNIPOLAR

EXPONENTIAL SIGNALAT THE OUTPUT OF APROPERLY ADJUSTED POLE-ZERO CANCELLATION NETWORK

NEGATIVE TAIL

SLOWLY DECAYING SIGNALUNIPOLAR

SIGNAL AT THE OUTPUT OFAN RC DIFFERENTIATOR

Fig. 10.1 Signal shapes observed in a RC differentiator and azero-pole cancellation circuit.

Experiment;To observe the different behaviour of an RC differentiator and of a

pole-zero cancellation network, as far as clipping of an exponentiallydecaying signal is concerned, the following circuit is employed (seeFig. 10.2)

The R^CI differentiator at the input of the buffer-connected LF356amplifier has the purpose of transforming the rectangular signal supplied bythe generator into two exponentially decaying pulses with time constant

65

lOK

OUTFig. 10.2 Diagram for a pole-zero cancellation circuit

Rlcl = 10 A18• Refer to only one of these exponential pulses and makesure that the decay time constant is really 10 jus, by looking with at scopeat point B.

An active RC differentiator is made by combination of the R^ C±network with the LF 356 operational amplifier in the inverting connection,when no shunt resistor is connected across C2-

Fig. 10.3 Shape of the output signal from a pole-zero cancellation circuit

An active RC differentiator is made by combination of thenetwork with the LF 356 operational amplifiers, when no shunt resistor isconnected across C2- Observe that the path from point B to the output isac coupled.

Look then at the shape of the signal at point OUT. The signal shouldlook like the one in Fig. 10.3. The time constant will be slightly lessthan 2 us that is, signal clipping is achieved, but a tail of oppositepolarity is present. Observe also that the decay time constant of the OUTsignal is largely determined by the R2C2 product. For instance, you canreduce R2 to Ik and the output time constant will decrease to «vl yus.

Pass on now to the pole-zero cancellation network. For this purposeconned across C2 the series combination of a 2k resistor and a 10k

66

ten-turn potentiometer. Let R be the value of the resulting resistance.Observe that this resistive path across C2 introduces a dc couplingbetween B and OUT.

Perfect pole-zero cancellation occurs when the time constant determinedby C2 and by the series connection of the 2k resistor and the 10kpotentiometer equals the time constant of the signal at point B.

Look again at the OUT signal by using adequate sensitivity, observe howthe shape of the output signal displayed on the scope changes by changingthe value of the potentiometer (Fig. 10.4).

Adjust the potentiometer to achieve correct pole-zero cancellation anddetermine the exact value of the time constant of the clipped exponentialpulse.

By measuring the values of the total resistance Rs of the seriescombination, of R2 and €2, check that the time constant of the clippedexponential pulse is equal to C2 multiplied by the parallel combination ofR2 and Rs.

Rs TOO SMALL Rs TOO LARGE

TAIL OF THE SAMEPOLARITY AS THESIGNAL

CORRECTPOLE-ZEROADJUSTMENT

TAIL IS REVERSED FROMPOSITIVE TO NEGATIVE

Fig. 10.4 Rs influences the signal shape

67

HINTS FOR LABORATORY WORK

HOW TO MAKE RELIABLE ANALOG CIRCUITS

Designing and building a reliable analog circuit of large bandwidth,say 100 kHz or more, as needed in nuclear electronics is not as simple asyou might believe.

Even in those cases in which the circuit is perfectly designed from thedc point of view, the designer has to fight against several kinds ofdifficulties that can be grouped into two main categories:

A) ANOMALOUS BEHAVIOUR IN ABSENCE OP APPLIED SIGNAL

B) DISTORTION OF THE APPLIED SIGNAL

To category A) belong all the spurious oscillations and the noisegenerated by internal components and pick up of external disturbances aswell.

A common design practice suggests that all the analog circuits shouldbe assembled on a printed circuit board having on one side a GROUND PLANE,according to the drawing of Fig. 1. Active components will be located onthe side of the ground plane, while conductive paths and passive componentswill be soldered on the opposite side.

If a double-faced printed circuit is not feasible, use a single-planeapproach by leaving some GROUND ISLANDS of a few cm^ each.

s« °O s*o£ °0qo J00 ?1 2 Oio

GROUND CONDUCTIVE PATH(LOWER

INSUtATORFig. 1 A printed board for analog circuits

Bad soldering is a common source of spurious oscillations. Payparticular attention to the case in which a connector, for instance a panelBNC female, is directly soldered to the ground plane or to one of the groundislands of your printed circuit board. Use in this case a soldering iron ofsuitable power and make sure that an adequate amount of liquid tin isprovided to safely fix the connector to ground.

69

In the design of a printed circuit board avoid long and thin connectingpaths as they create excessive STRAY INDUCTANCE. From the point of view ofspurious oscillations it is better having short, wide connecting pathsaiming at favouring stray capacitance versus stray inductance. Theconducting paths of the printed circuit board of Fig. 1, in this respect arenot a good example, as they are too long and thin.Never forget, however,that large stray capacitance becomes detrimental to the high frequencybehaviour of the circuit.

Filter the power supply lines as close as possible to the point inwhich they enter your printed circuit board. In series with every supplyline connect a small resistor, 10 to 100R, depending on the currentabsorption you expect in your circuit and then implement a low pass filterusing this resistor and two capacitors in parallel to ground. One of thesecapacitors should be a 10 uF electrolitic, the other one a 0.1 uF ceramicdisc or polystyrene capacitor. The former has the purpose of shortcircuiting to ground the low frequency disturbances, the other will takecare of the high frequency ones.

Never forget that two active elements, for instance two operationalamplifiers in close proximity on the printed-circuit board and supplied bythe same line, most frequently induce each other into oscillation. In thesecircumstances it is advisable to put a capacitive bypass as shown in Fig. 2.

Fig. 2 Preventing oscillations in an amplifier

So, a critical circuit may require more than one filtering group forthe supply lines and the filtering groups should be located in such a way asto interrupt the high frequency path between contiguous active devicesproviding large gain at high frequencies.

Pay attention to the way you connect the pins of an operationalamplifier or of a comparator to the relevant printed circuit points. If thedevice is in the TO-5 can, cut the external leads as short as you can toavoid stray inductance.

If you must introduce into your circuit a grounded-base or emitterfollower connected transistor, most likely it will oscillate. Thisbehaviour is explained by the presence of STRAY INDUCTANCES in the base andcollector leads. Even though you have taken on the precautions to make theconductive paths in the printed circuit board as short as you could, stillthe thin lead of the transistor and the hair-like connection to the chipinside the can may have enough stray inductance to induce high frequencyoscillations.

To remove high frequency oscillations in grounded base and emitter-follower circuits, the precautions shown in Fig. 3 are very useful.

70

x^NFOUOWCft

FOR&WIMGS

COUCCTOfc A MO 6HITT6R

Fig. 3 Eliminating high frequency oscillations

DON'T FORGET THAT IT DOES NOT MAKE SENSE CHECKING THE dc VOLTAGES ANDCURRENTS AS LONG AS THE CIRCUIT OSCILLATES.

Therefore, as soon as a new analog circuit is assembled, connect thescope to the circuit output and turn on power.

IF NO DISTURBANCE APPEARS ON THE SCOPE, YOU CAN START CHECKING THE dcVOLTAGES AND CURRENTS. Remember that, in order to avoid perturbation of thecircuit due to the stray input capacitance of the DVM you employ in thesemeasurements, it is advisable to connect a 4.7k resistor in series with theDVM measuring clips. If all the dc voltages and currents approach theexpected values, then go on applying signal.

IF, HOWEVER, AS SOON AS YOU GIVE POWER YOU OBSERVE ON THE SCOPEOSCILLATIONS, PICK-UP, UNEXPECTED NOISE, START WORKING TO REMOVE THESETROUBLES BEFORE MEASURING THE dc QUANTITIES.

CHECKS TO BE MADE:

ARE ALL THE POWER SUPPLY INCOMING LINES FILTERED?

ARE THERE ACTIVE ELEMENTS WITH NO HF BYPASS ON THE POWER LINES INBETWEEN?

ARE THERE OP-AMPS OR ANALOG COMPARATORS WITH LONG LEADS?

ARE THERE UNNEUTRALIZED GROUNDED BASE OR EMITTER FOLLOWER AMPLIFIERS?

ARE THERE REFERENCE DIODES NOT BYPASSED BY A 0.1 uF CAPACITOR INPARALLEL? THIS MAY EXPLAIN LARGE NOISE CONTRIBUTIONS.

Once you have removed the trouble, go to the next step checking the dcvoltages.

Again, when all the dc voltages are close to the expected values youcan turn the signal generator on and observe the behaviour of the circuit onthe signal.

71

The output signal may show ringing or oscillations, like in Fig. 4.This is a symptom that the bypassing and filtering you have introduced,though effective in removing the oscillations is not yet adequate to thesignal behaviour of your circuit.

Fig. 4 Undesired oscillations

Besides rechecking the bypassing and filtering networks, remember thatsometimes a resistor in series with the input of an amplifier may prove tobe effective in reducing high frequency ringing, Fig. 5.

Fig. 5 Reducing oscillations

Finally, never forget to check that at the side of your circuit thecable employed to couple the signal to other circuits must be properlyterminated on its characteristic impedance.

72

EXPERIMENT 11

BASELINE RESTORATION

Objective; The objective of this experiment is to demonstrate theeffect of baseline restoration in reducing baseline shift at high countingrates. Comparison with ordinary ac coupling will be made.

Introduction:Baseline restoration is a nonlinear operation which has the purpose of

forcing slow tails following a nuclear signal to recover to zero at a fixedslope. Its function is shown in Fig. 11.1. The input signal, which comesfrom an improperly adjusted pole-zero cancellation network is followed by along negative tail.

kPULSE

BASELINERESTORER

PULSE

FRST UNEflR RECOVERYTO

Fig. 11.1 Effect of baseline restoration

At the output of the baseline restorer, the tail is forced by thecircuit to reach the baseline at a fixed slope whose value is determined bythe circuit parameters.

The circuit chosen for this experiment is (Fig. 11.2) )ased upon afeedback circuit which employs a matched pair of diodes working at equalcurrents I. Assume that a positive signal comes in. The capacitor C behaveson the leading edge of the signal as a short circuit. The cathode of D^is pulled positive by a low impedance driving and it turns off. The currentsupplied by Lhc lower generator flows out of the capacitor C, which changesat a rate of -I/C.

When the rectangular signal ends, its trailing edge turns off Ö2,while a current 2I-I = I flows into the capacitor which charges at a rateI/C until the baseline level is reached. The present baseline restorer iscalled symmetric, for the two restoration rates are of equal magnitude butof opposite sign. If the input signal has a negative tail, the action ofthe baseline restorer is identical to the previously described one as longas the slope of the tail has a magnitude lower than I/C.

Experiment:In order to realize the circuit of Fig. 11.1 in the best way, choose

two diodes that are as closely matched as possible. A choice has to be madefrom a batch of diodes using the circuit as shown at the right margin ofFig. 11.2. Fix in the diodes a current of approximately 200 uA, measuretheir forward voltages and select two diodes that differ by less than 20 mVin their forward voltages. Connect them in the circuit of Fig. 11.2. Keep

73

«ptllV^[J2I|1.

10 nFPULSEGENERATOR

•- • •• H y

——— n —— » ——— IL- ± 4F^fi

uCf

|47»

^12V

DVM

Fig. 11.2 Baseline restoration circuitmatching diodes.

At the right: selecting

the pulse generator off and adjust the 20k potentiometer so as to drive thevoltage at point P as close to zero as possible.

Note that: the measurement of the dc voltage on the virtual ground of afeedback operational amplifier requires some precautions, to avoid that thecapacitance of the voltage measuring instrument drives the circuit intooscillation. A simple precaution consists in putting a resistor of a few kin series with the voltmeter probe. Check then the amplifier outputvoltage: it should differ from zero by less than 20 mV.

Once the dc checks have been made, turn on the generator and adjust itso that a signal is delivered with the following characteristics:

Amplitude 2V (to be left unchanged throughout the experiment)width: 10 fispolarity: positive

3repetition rate: 10 pps

ATTENTION: THE FOREGOING MEASUREMENTS REQUIRE THAT THE OSCILLOSCOPEBE dc COUPLED TO POINT P.

Use now a lOx (low capacitance) scope probe to pick-up the signalat point P. Such a signal should look like the one shown in Fig. 11.3.

Use a time scale of 200/is/div, make sure that the baselinecoincides with the oscilloscope zero line as it has to be, if the offsetat point P has been correctly adjusted to zero.

Increase then gradually the generator rate up to 30,000 pps andmonitor the baseline. Check how much it shifts from the position it hasat 103 pps, (Fig. 11.4).

74

topsBRSCLINE

• SLOPE-f 2-IO~Fig. 11.3 Signal shape at point P of the baseline restorer

Increase then gradually the generator rate up to 30,000 pps andmonitor the baseline. Check how much it shifts from the position it hasat 103pps {Fig. 11.4).

-*y t r f \ ———

ZEJtO LIME 1

^ BflSE UNE f

-BaSILINEAT I03pps

t 8RSELIKESHIFT

Fig. 11.A Effect of baseline shift

Plot the baseline shift as a function of the generator rate at thefollowing rates: 1,000 pps, 5,000 pps, 10,000 pps, 15,000 pps,20,000 pps, 25,000 pps, 30,000 pps.

Modify then the circuit in the way shown in Fig. 11.5, leaving thepotentiometer at the same value it had in the previous experiment.Return to the 1,000 pps repetition rate in the generator and observe thesignal at point P with a time scale of 5 /is/cm.

PULSEGENERATOR.

lOnF

Fig. 11.5 Modified input side of the baseline restorer

75

Fig. 11.6 Observation of pulse shape at high amplification

This observation may require a high vertical sensitivity, say 20mV/cm. Pass then to the horizontal scale of 200 us/division and observeagain the baseline referred to the oscilloscope zero line (Fig. 11.6).

2EROBnSE-LINc

ZERO UNE Y

8RSELINE IFig. 11.7 Baseline dependence on count rate

Increase then gradually the generator repetition rate up to 30,000 ppsand measure, as in the previous case, the position of the baseline withrespect to the oscilloscope zero line, Fig. 11.7.

Plot the values of the baseline shift, versus the generator rate at thesame values of rate as before, that is, 1,000, 5,000, 10,000, 15,000,20,000, 25,000, 30,000 pps.

Compare then the rate dependence of the baseline in the two cases,baseline restorer in and baseline restorer out.

It is worth pointing out that the two exercises you have just gonethrough, namely POLE-ZERO cancellation and BASELINE RESTORATION had thepurpose of making you familiar with two ideas that in the history ofNuclear Electronics have to be considered significant steps forward inthe achievement of high rate capabilities.

76

EXPERIMENT DCOMPLETE LINEAR SYSTEM FOR DETECTOR SIGNAL PROCESSING

Objective

The purpose of this experiment is to assemble, put to work andcharacterize a complete linear system for detector signal processing. Theresulting equipment will consist of a low noise charge-sensitivepreamplifier, housed in a metal shielding box, and of a completespectroscopy amplifier. Both units are of professional design and can beused indeed as basic structures, starting from which a home made linearspectroscopy system can be implemented simply by adding more facilities likeselectable time constants and a broader range of gain values.

IntroductionA linear system for detector signal processing consists of a low noise

preamplifier and of a further amplifying and shaping unit, calledspectroscopy amplifier. The latter performs a twofold function. First, itraises the amplitude of the signal delivered by the preamplifier to thelevel required by further processing instruments, like multichannelanalysers. Secondly, it maximizes the signal-to-noise ratio, by enhancingfrequencies in the signal spectrum and depressing the noise frequencies.The amplifier must provide for a stable count-rate independent baseline, forthe signal amplitude is to be measured between peak and baseline. Theamplifier must be able to produce unipolar output pulses while receivinginput pulses with an exponential decay.

The practical work consists of three phases:Assembling and testing the charge sensitive preamplifier.Assembling and testing the spectroscopy amplifier.Connecting the preamplifier to the spectroscopy amplifier andperforming the noise measurements.

These three phases will be described here in three separate sections.

1. Assembling and testing the charge-sensitive preamplifierIn a solid state detector, just as in the case of an ionisation

chamber, the radiation looses its energy in producing charge carriers. Thesum of these charge carriers, the total charge, is the primary informationfrom the detector. This charge across the detector capacity would give riseto a voltage signal. The detector capacity, however, is not constant. Itis proportional to the square root of the supply voltage of the detector.

Therefore preamplifiers are used which are sensitive to the charge atthe input. They convert the input charge to an output voltage. Thus thechanges in the detector capacity no longer influence the amplitude of theoutput pulse. The appropriate circuit consists of a low noise, invertingoperational amplifier with a feedback impedance, parallel connection of aresistor and a capacitor as shown in Fig. D.I.

77

HI

-o out

Fig. D.I Operational amplifier with the feedback

An appropriate internal structure for amplifier A will be describedbelow. The most critical component is the field effect transistor used atthe input; its selection will now be described.

1.1 Selection of the input FETThe noise performances of charge sensitive preamplifiers are determined

to the largest extent by the characteristics of the input field-effecttransistor. The preliminary part of the implementation of acharge-sensitive preamplifier, therefore, aims at choosing out of a batch offield-effect transistors the most suitable unit.

In the normal operating conditions of a charge-sensitive preamplifier,the dominant noise contribution is the thermal noise in the channel of theinput field-effect transistor and to reduce this term as much as possible, afield-effect transistor with a large transconductance gm should beselected.

The transconductance increases as the drain current in the field-effecttransistor is increased. However, it has to be borne in mind that the draincurrent cannot exceed a value, called IDSS» which represents the value ofthe current flowing into the drain when gate and source are at the samepotential.

The selection of the FET for minimum noise operation proceeds asfollows. Making use of the circuit of Fig. D.2, measure the I valuesfor all the transistorjs you have received.

Û I1 ——— "I»'!

5

V r «- > J

(o\

Fig. D.2 Measuring

should be determined by making sure that the drain-to-sourcevoltage lies within +5 and +6V. In this way, each component will becharacterized by its IDSS value. The next step will be the measurement ofthe transconductance gm. For such a purpose the circuit of Fig. D.3 willbe employed.

78

Fig. D.3 A circuit to measure the transductance

In the circuit of Fig. D.3 the feedback loop keeps the source of theFET at 0 V. In this loop the source of the FBI behaves as a very lowimpedance input. The standing current in the FET is set to a value of 0.9IDSS by choosing the resistor R connected between the source of the JFETand the -6V supply according to the relationship:

R 6V0.9 I tk]

DSS

where Ipgg is expressed in mA. Obviously, different values of R willbe required for FETs of different

Connect then a 1 kHz sinusoidal oscillator through a 1 uFdecoupling capacitor and a 10k resistor to the source of the fieldeffect transistor. Adjust the current flowing through the 10k resistoraccording to the following criterion. The peak-to-peak sinusoidalcurrent entering the FET source must not exceed 10% of the standingvalue. Therefore, the amplitude control of the sinusoidal oscillatormust be set so as to meet the previous requirement. In other words, thepeak-to-peak voltage at P^ read with an oscilloscope, divided by 10kmust give a current equal to 10% of 0.9 IDSS» that is equal to0.09IDSS. Let us call this peak-to-peak current iB. Flowing intothe source of the FET, ig modulates the gate-to-source voltage. Readthe peak-to-peak value of the sinusoidal voltage at the output of theoperational amplifier. Let us call this peak-to-peak voltage VG. Theratio ÎS/VQ gives the value of the transconductance.

An example will clarify the whole procedure. Assume an FET for whichthe measurement of Fig. D.2 gives an IDSS of 8 mA. The transconductancewill therefore be measured at 90% of IDSS» that is, at a standing currentof 7.2 mA. A source current of 7.2 mA must therefore be fixed in thecircuit of Fig. D.3. The value of the unknown resistor R is

R = 6V7.2 mA 820 [R]

Having introduced this resistor into the circuit, you know that thestanding source current in the field-effect transistor is 7.2 mA and

79

ooo

T 1 : 2 ft/ 4 A I

r«. Sî>

* R H : -wjjus-t- -jW 0V

Fig. D.4 Preamplifier c ircui t diagram

T 4 ,4 ,5 ,6 :T S -. ir 9 : ZA; ZI o 5

therefore the peak-to-peak value of the 1 kHz sinusoidal current employedfor the gm measurement must not exceed the value

0.1 x 7.2 mA = 0.72 mA.

To fix this current, look at the sinusoidal voltage at P^ andadjust the sinusoidal generator amplitude until the voltage at P± is7.2V. Now you are sure that the current crossing the 10k resistor andentering the source of the FET is 0.72 mA. Pass on now to measure thepeak-to-peak amplitude of the sinusoidal voltage at ?2- Suppose, forinstance, that this peak-to-peak amplitude is 120 mV. Thetransconductance is given by:

120 mV -The measurement of gm has to be repeated on all the units

available and each unit will be characterized by its value of IDSS an<iits value of gm. The FET with the largest gm will be introduced inthe charge-sensitive preamplifier.

1.2 Circuit Description of the PreamplifierWe now refer to the complete circuit diagram in Fig. 0.4. The

preamplifier has two blocks. The first one (Tl - T4) is the chargesensitive loop, corresponding to amplifier A of Fig. D.I; the second (T5- T9> provides voltage gain and a low output impedance. Approximatequiescent values for voltages and currents at several points are shown inthe diagram.

The field effect transistor Tl provides low noise and high inputimpedance to the basic amplifier of the charge sensitive loop; the signalcurrent developed in Tl flows through T2 and the high impedance offeredby current source T3 acting as a load; this determines a high voltagegain in this stage. Resistors R4 and R6 and capacitor C3 avoid highfrequency parasitic oscillations. The value of R3 will depend on IDSS«note that the current entering the current source T3 also passes throughR3; thus R3 may be determined through the relationR3 = 7.6V/(2mA +0.9 IDSS) .

Potentiometer R13 allows the output quiescent voltage to beadjusted to 0V through the application of a quiescent negative voltage ofappropriate value to the gate of Tl.

The feedback impedance corresponding to Cf and Rf of Fig. D.I,is the parallel of C2 and R2; thus the input current is integrated in C2and the corresponding voltage pulse has a decay time constantV = C2.R2 = 220 fis.

The second block is a voltage amplifying stage with the gain defined bythe feedback resistors ratio (R18 + R19)/ R18 =5.7. Transistors TS, T6 andT7 constitute a cascode differential amplifier, R22 being the load resistor;T8 and T9 assure a large output current capability. Feedback make theimpedance at the common node of R24 and R2S practically zero, and R27 isused to match the coaxial cable impedance.

81

1.3 Checks on the Preamplifier and Rise Time MeasurementsOnce the layout of the charge-sensitive preamplifier shown in figure 4

is ready, check the dc voltages in all the circuit nodes and all thecurrents in the branches. Also in these measurements, a resistor of a few kin series with the voltmeter probe is advisable. Compare the values ofvoltages and currents you have found with those written in the circuitdiagram.

If you are sure that the circuit works correctly from the point of viewof the dc condition, introduce it into the special metal box you have beenprovided with. Such a box acts as a shield, reducing the 50Hz pick-up whichotherwise would make measurements very difficult.

You are now ready to begin the analysis of the signal behaviour of yourcircuit. To do this, connect the generator to the test input and fix thefollowing operating condition for the test signal:

shape:polarity:amplitude:repetition rate:pulse width:

rectangularnegative100 mV102 ppsl ras

Look at the output of the whole preamplifier and observe the shape ofthe signal. This should look like the one shown in Fig. D.5.

TEST PULBS

~1

OUTPUT PULSEFig. D.5 Preamplifier output

T fir

3>fT.

Fig. D.6 Decay andrise-time measurement

Measure the decay time constant of the exponential signal at thepreamplifier output and compare the measured value with the product C2.R2 ofthe capacitance and the resistance in the feedback bipole of thecharge-sensitive loop. If agreement exists between the nominal and the realvalues, within the obvious inaccuracy margin due to finite components*tolerances, you can go to the next step, that is, to measuring the risetimeas a function of a capacitance, which simulates the detector, connectedacross the input terminals of the charge-sensitive preamplifier.

82

A set of capacitors ranging from 20 pF to 300 pF is available for thismeasurement.

The measurement has to be performed as illustrated in Fig. D.6. Thedetector simulating capacitor CD is connected in the way shown in thefigure. Raise the generator rate to about 103 pps and measure therisetime of the output pulse, defined between 10% and 90% of the asymp-totic value for CD=0 at first and then for CD = 20 pF, 50 pF, 100 pF,150 pF, 200 pF, 250 pF, 300 pF.

Plot the measured risetime as a function of CD.Connect then the 300 pF capacitor at the preamplifier input and double

C2, that is, increase it from 2.2 to 4.7 pF. Measure the risetime andcompare the value just found with the one found before for Cf = 2.2pF andCD = 150 pF.

If you have finished the risetime measurements, you are ready to takethe next step, which is assembling and checking the spectroscopy amplifier.Charge-sensitive preamplifier and spectroscopy amplifier will then be usedtogether in the noise measurement.

2. Assembling and Testing the Spectroscopy Amplifier2.1 Circuit Description

The amplifier, the circuit of which is shown in Fig. D.7, has threegain and pulse shaping stages, built around ICI, 2 and 3, an active baselinerestoration network built around IC4 and an output buffer, IC5. Pole-zerocancellation is effected at the amplifier input.Gain and Pulse Shaping Stages

The incoming signal is expected to have an exponential decay ofaround = 50 us time constant. To avoid pile-up and other problems thissignal is to be shortened; this is done by active differentiation with atime constant <iif essentially determined by Cl and R3, ^if = 2-2 us-However, to eliminate signal undershoot, a pole-zero concellation techniqueis used; potentiometer R2 is to be adjusted to make Cl x (Rl + R2> =f, thedecay time constant of the input signal. Decay constants from 150 /is to 260^ts can thus be cancelled. (The differentiation time constant is, moreexactly, given by Cl x R3/(R1 + R2); this differs from Cl x R3 by less than2% even if R2 = 0>.

An active integration is also performed around ICI by the feedbacknetwork C2 - R4, with a time constant "^int = 2.2 ;us. When the pole-zeronetwork is adjusted, the gain of the first stage is seen to be 10/e (e =2,78).

The second stage uses the same feedback configuration as the firstone. It performs a t^n^ = 2.2 /is integration and provides for variablegain setting both continuously, by a factor varying between 1 and 2 throughadjustment of potentiometer R6, and in a step, by a factor of 2, by choosingthe feedback network. The maximum dc gain of this stage is given by-R7/R5 = -22; the ac gain is smaller due to the integration time constant.

The third amplifying stage has unity dc gain and performs a doubleintegration with a time constant tjnt = 2.2 /is. The output buffer, whichreceives the signal from the baseline restorer described below is followed

83

00

l/H.

C7 v »1C7u.tr

V*-

4or

1C 1, 2 ; 3, 5 : Lf 356

1C 4 1 LM 31g

Fig. D.7 Spectroscopy amplifier

J•T-

-H2

by R13, a 100R resistor used for impedance matching to a coaxial cable withZ0 = 93R. The output current is limited by IC5 to about 15mA.

Altogether the amplifier performs one differentiation and fourintegrations; all the time constants are equal to 2.2 fis. Thus theamplifier gives a quasi-gaussian shape to an incoming exponentially decayingsignal. This is a very appropriate shape to obtain a good signal to noiseratio in a spectroscopy system.Baseline Restorer

The active baseline restorer works to keep a zero voltage at theinverting input of IC3 (a fast operational amplifier); this node isconnected to the input of the last amplifying stage. The restoration ismade necessary because a capacitor (C7) has been used to cancel the large dcgain of the amplification chain (amplifier plus preamplifier). Signals ofeither polarity whose amplitude exceeds a very small value cut off one ofthe diodes Dl (positive signals) or D2 (negative signals); when this happensC7 is charged with a current of roughly -120 /iA. This has a very smalleffect on the amplitude of the signals, which are of short duration. Byunbalancing the currents in Dl and D2 while there are no pulses present, therestorer is able to keep the value of the voltage at the buffer input veryclose to zero even for reasonably high count rates.Technical Details

As shown in the schematics, all the integrated circuits are connectedto the power line trough RC decoupling networks. This is important to avoidoscillations and interferences among the various circuits. The networksshould be physically close to the 1C, and the capacitor soldered to a goodground line.

Two types of operational amplifiers are used: the LF 356 in theamplifying stages and the LM 318 in the baseline restorer. The LF 356 is anFET input operational amplifier with a gain bandwidth of 5 MHz and a slewrate of 12V//us; it has a low noise input voltage and a typical offsetvoltage of l mV.

The LM 318 is a fast bipolar operational amplifier with a typical slewrate of 70 V/yus and a typical offset voltage of 4 mV. In the presentamplifier it is used as a comparator.

2.2 Amplifier Checking

1. Check for spurious oscillations by looking at the output with a scope.2. Observe the behaviour of the amplifier by checking with a DVM whether

the voltages at the inputs and outputs of the different operationalamplifiers have the expected values. The input to the whole amplifiershould be shorted to ground and approximately 0V will be measured atthose nodes.

3. Connect the charge sensitive preamplifier to the input and use a pulsegenerator to inject a charge pulse in the preamplifier; the output ofthe preamplifier should be a signal of about +0.5V amplitude, veryshort rise time and decaying exponentially with a time constant ofaround 220 yus.

4. Reduce the signal to a level that will give a 5V output signal atmaximum gain; check that the amplifier is not saturated. Observe the

85

signal shape at the output of ICI (one differentiation plus oneintegration), the output of IC2 (two integrations) and of IC3 (fourintegrations). Measure the gain of these stages; check the gaincontrols.

5. Observe the signals at the input and output of IC4; it is seen that,while the (positive) input signal is on, IC4 saturates to the negativerail making D2 conduct all the current that passes through R12 whileRll slowly charges C7.

6. Observe the amplifier behaviour when it is overloaded and compare itsbehaviour to the one observed when the pole-zero cancellation networkis not adjusted.

3. Noise Measurements

With the preamplifier and the spectroscopy amplifier connected togetherand the whole system checked as far as signal behaviour is concerned,observations about noise can be made. Turn the pulse generator off, displaythe noise at the output of the spectroscopy amplifier on the oscilloscopewith an adequately high sensitivity so as to have the noise band covering atleast two vertical divisions.

Observe the noise by gradually changing the horizontal scanning speed,make sure that no 50Hz pick-up is present, that no periodical spikes appearto be superimposed to the noise band, which must look homogeneous. Makesure that the dominant noise contribution, as it ought to be, is the onecoming from the preamplifier. For this purpose, disconnect the preamplifierand terminate the input of the spectroscopy amplifier on 93 R resistor. Thenoise appearing now at the output of the spectroscopy amplifier should beconsiderably smaller than the one observed previously with the preamplifierconnected. If it is so, connect the preamplifier again and start thequantitative noise measurements.

A short explanation about the ways of expressing noise at the input ofa linear amplifier system for radiation detector signals will be anticipated.

Remember that the radiation detectors employed in the energymeasurements deliver a CHARGE which is proportional to the energy releasedby the ionizing radiation in the sensitive region of the detector. Thenoise introduced by the amplifier system can accordingly be expressed as

I) NOISE CHARGE REFERRED TO THE PREAMPLIFIER INPUT

or as

II) WIDTH, EXPRESSED IN UNITS OF ENERGY AND REFERRED TO THE DETECTOROF A HYPOTHETICAL SPECTRAL LINE WHICH IS BROADENED BY THEPREAMPLIFIER.

It has to be borne in mind that both ways express in different unitsthe NOISE CONTRIBUTION of the preamplifier and for this reason thedefinition I is independent of the material employed in detectormanufacturing, either silicon, germanium, CdTe, Hgl2 and so on. Thepreamplifier noise contribution, instead, expressed according to definitionII, would depend on the material the detector is made of.

The preamplifier noise is strongly dependent on the value of thecapacitance CD connected at the preamplifier input to simulate the

86

detector as well as on the shaping implemented by the spectroscopyamplifier. Therefore, before starting the noise measurements, make surethat the set of capacitors you will use to simulate CD have beenaccurately measured.

Now, the way in which the detector current pulse is simulated has to beexplained. Remember that a detector can be thought of as a current source,delivering a known amount of charge, in parallel to a capacitor. Thecapacitor is CD. The current pulse will be simulated in the way shown inthe Fig. D.8. As already pointed out, a small injection capacitor, Cjnj,is provided inside your preamplifier box. One terminal of Cjnj goes tothe preamplifier input, while the other one is soldered to a connector onthe box wall, labelled TEST INPUT.

Fig. D.8 Simulating a current pulse

By applying to the test input a quasi-step signal with a finite slopeon its leading edge, the current flowing through C^nj will therefore be arectangular pulse of width AT, carrying a charge

CinjAyAt

AQ

If Cjnj is known in value and adequately stable, the chargeinjected &Q can be accurately controlled by acting upon the signalamplitude

This method enables the designer to simulate the radiation detectorin a very accurate way. If the generator employed has provision forchanging slope on the leading edge, the measurement can also account forthe finite collection time in the detector, which is simulated by A f •The latter possibility will not be exploited here, for it is useful onlyfor a second-order correction in the noise measurements and thereforewill be forgotten about in what follows.

Become, then, familiar with the detector simulating chargeinjection and set the generator in the following conditions:

REPETITION RATE:PULSE WIDTH:PULSE POLARITY:

1 kHz100 /isnegative

Fix the minimum value of the gain in the spectroscopy amplifier,estimate the charge injected by a 2.2pF injection capacitor when the voltageapplied to it is 20 mV.

87

Pay due attention to the measurement of the input step amplitude andmeasure the amplitude of the signal which appears at the output of thespectroscopy amplifier. The measurement should be performed in thefollowing way.

Use a T-junction connector at the test input of the charge-sensitivepreamplifier. Connect through a coaxial cable the output of the pulsegenerator to one of the inputs of the T connector. Go with a coaxial cable

PULSE PREAMPLIFIER so*SPECTROSCOßXAMPUFIC.RBOARD___

Fig. D.9 Determine the charge sensitivity of the amplifier system

from the other leg of the T connector to the channel-A input of anoscilloscope and terminate there the coaxial cable on its propercharacteristic impedance. As the impedance presented by the preamplifiertest input is very large and purely capacitive, in this way you make afeed-through connection from the generator through the preamplifier to thescope. Use then a probe connected to the channel B of the scope to displaythe spectroscopy amplifier IC3 output. The whole method is illustrated inFig. D.9.

Employ, as typical sensitivities for this measurement:Horizontal 2-5 yus/divChannel A

Channel 6verticalvertical

5 mV/div200 mV/div

88

Adjust the generator amplitude setting to make the amplitude of thestep of channel A equal to 20 mV. This is a convenient value for theforegoing measurements. Note that 20 mV across a 2.2 pF injectioncapacitance generates a charge equal to:

2 x 10 ~2 x 2.2 x 10~12 = 4.4 x 10~14 coulomb or

4.4 x 10~14 _ 1e ..5 .. ,—————— — = 2.75 x 10 electrons1.6 x 10

As a unit of charge injected, remember that a 1 mV signal through a1 pF capacitor gives

—3 —12 —15 1010 x 10 = 10 Coulomb or -^ ———— —— = 6.250 electrons1,6 . 10 19

Return now to the display you have on the scope, with the injectedstep on channel A and the semi-gaussian signal taken at the output of IC3on channel B. Using transparent paper pressed against the display ofyour oscilloscope, sketch the shape of the semigaussian signal and markon it the correct time scale. This will be used as an auxiliaryinformation to determine whether your preamplifier gives comparativelysatisfactory results.

Determine now the charge-sensitivity of your spectrometry system.To do this, measure the peak amplitude vp of the pulse delivered by thespectroscopy amplifier.

The charge-sensitivity of your system will then be the ratio betweenVp and the amount of charge injected at the input. In the presentcase, the charge-sensitivity will be expressed as:

S = ____ g ______ = 23 v / picocoulomb———— —— — —4.4 x 10____ ______c ———— —— —rr — p

v -6S = ____ g ______ = 3.6 x 10 v / electronC ———— —— 5 ——— P

2.75 x 10For instance, if upon injecting 20 mV at the input (do not forget that

the previous relationship assumes an input signal of 20 mV) you findVp = IV, then the charge-sensitivity of your system will be respectively

S = 23V/picocoulomb orcS = 3.6 x 10~ V/electron = 3.6 uV/electron.c

The energy sensitivity of the system depends on the type of detectorthe system is intended to work with. So, in association with a silicondetector, where creation of an electron-hole pair requires 3.67 eV, theenergy sensitivity of the system would be:

S = S / (energy to form a pair) _ r1- —— - 1 ~ or 1 mV/keVEC — *5 • O / 6V 6V

of energy released.

89

If the detector connected to the system is, instead, germanium, where2.97 eV are required to create one electron-hole pair, the energysensitivity of the system would be:

The noise measurement can now be performed and two methods will bedescribed here.

a) Measuring the RMS noise of the amplifier system and refering it to theinput of the whole system.This method has the advantage of leading to a preliminary estimate of the

noise performances of the spectroscopy system in a fast way. It can also besuitably accurate if a true RMS voltmeter, like, for instance, Hewlett Packard3400 A is available (10 Hz - 10 MHz bandwidth). If such a voltmeter is notavailable, a first approximation of the RMS can be made in the following way.

Turn off the pulse generator. On the B-channel of your oscilloscope youwill see the noise band at the output of IC3 . Increase the verticalsensitivity so as to display this band on two divisions.

Reduce the horizontal sensitivity to 10 us/division and increase the beamintensity so as to be able to detect the peak-to-peak amplitude of the noise.Remember that the noise has a gaussian amplitude distribution where thefollowing relationship holds:

™„ T Peak-to-Peak amplitudeRMS valued ————— — ; ———— K —————O . D

In this way you will find a value which represents in mV, the RMS noiseat the output of IC3. The RMS value is related to the full width at halfmaximum (FWHM) according to the expression FWHM = 2.355 RMS value.

To determine the EQUIVALENT NOISE CHARGE referred to the input, thatis, the noise charge which may be considered responsible for the measuredoutput RMS noise, you have just to divide by the charge sensitivity of yoursystem:

EQUIV. NOISE CHARGE = °UtpUt n°iseScThe equivalent noise charge is usually expressed in ROOT MEAN SQUARE

ELECTRONS. If instead you prefer to express the noise in terms of noiselinewidth referred to input, this parameter being frequently referred toas energy resolution, observe that:

FWHM Output noise line = 2.355 RMS output noise.

Then divide FWHM output noise line by the energy sensitivity of yoursystem. The result (FWHM output noise line) SE, usually expressed inkeV, gives the resolution of the system.

b) Measurement employing a multichannel pulse height analyzerThis method requires the pulse generator permanently connected and

consists in displaying on a multichannel analyzer two gaussian linescorresponding to two accurately known amplitude settings of the

90

generator. The preamplifier noise smears the amplitude distribution ofthe pulses and this is the reason why two gaussian distributions areobserved at the output of the amplifier system. The measurementprocedure is as follows: adjust the generator amplitude setting until onchannel A of the scope you read the first reference amplitude which maybe, as previously, 20 mV. Take now the real output of the spectroscopyamplifier, that is, the output of the IC5 buffer with the cablecharacteristic impedance in series, and connect it with a cable to theinput of a multichannel analyzer. Accumulate the resulting gaussiannoise distribution until the curve is well defined, that is, has smallstatistic fluctuations. It is advisable to choose the operatingconditions in such a way that the noise line has a FWHM of at least 10channels. Then stop the accumulation and introduce the second amplitude,which might be 40 mV. Check the amplitude of the generator accurately onchannel A of the scope without changing the vertical sensitivity. Startaccumulating the new gaussian line until it has approximately the samepeak contents as the previous one. Then stop the multichannel analyzerand process the display information, shown in Fig. D.10 in the followingway.

Define by visual inspection the centroid positions of the twogaussian lines and determine the order numbers N^ and N2 of thecorresponding channels. As you know that the difference in the centroidpositions was caused by a difference of 20 mV (40 mV - 20 mV) in thesignal amplitude, and you also know that 20 mV across 2.2 pF simulate anequivalent energy in silicon of 1,000 keV, you can calibrate the energyaxis of your multichannel analyzer, by observing that an input energyvariation of 1,000 keV gives rise to a shift in the spectral line of N2- NI channels. The energy calibration is therefore

1.000 . _,. . Trr —— keV/channel.N2 - NxDetermine now the FWHM of the first and second gaussian curves, and

let i and 2 be their widths in number of channels.The resolution for the first and second gaussian lines therefore is

, keV, FWHM in silicon

, keV, FWHM in silicon

The FWHM in Ge is obtained by remembering that 20 mV across 2.2 pF ingermanium simulates an equivalent energy of 810 keV and therefore thecalibration coefficient would be:

Q-l A-£±ii„ keV/channel.V Nl

PAY ATTENTION: the FWHM should be the same for both spectral lineswithin the statistical fluctuations. If the values of and i>2differ by more than 5%, there is a nonlinearity in the circuit.

Remember that in the noise measurement based upon RMS reading, theoutput from the spectroscopy amplifier has to be taken from IC3, to avoidbaseline restorer induced distortions in the noise line. The measurementwith the multichannel analyzer, instead, is made on the peak of the

91

X

tt

t

it

r Ny

>, ?v /» /\ i

\

> *

Li.cf\ / Fw>M ** v <• *Xfl| •"«•• .a. .o-0**

V\

H*',

*\

\Nz V^

NCWÔ«

Fig. D. 10 Energy resolution displayed on a MCA

waveform resulting from the combination of signal and noise. The signal,accordingly, has to be taken at the true output of the spectroscopyamplifier.

Plan the noise measurement respecting the following steps, to avoidmisuse of the multichannel time and to avoid delaying other groups' work:measure the ENC using the oscilloscope at the values of CD you havealready employed for the risetime measurement, that is:

CD = 0, 20 pF, 50 pF, 100 pF , 150 pF, 200 pF , 250 pF, 300 pF.

Check that the ENC value at CD = 0 is less than 1,000 electronsRMS and that the slope is less than 20 electrons /pF. If your system isbelow the two upper limitations, you can go to the multichannel analyzer.

Determine finally the values of the resolution (FWHM>i for CD =100 pF and (FWHM)2 CD = 200 pF and the slope

(FWHM)2 -100

You should now prepare a complete report on the measurements thathave been made.

92

EXPERIMENT E

TIME INTERVAL-TO-AMPLITUDE CONVERSIOM

Objective: This experiment aims at showing how the linear conversionof a time interval into an amplitude proportional to it can be employed inthe measurement of the time elapsing between two nuclear events,

IntroductionConsider a time interval defined by two nuclear events.

TIME-TO-AMPLITÜDE conversion is the operation which transforms the timedistance between the two events into an amplitude proportional to it. Theamplitude is then converted into a number by an analog-to-digitalconverter. TIME INTERVAL-TO-AMPLITUDE conversion is therfore a preliminarystep to particular kind of TIME DIGITIZING. It is employed whenever thetime interval to be digitized is so short and the resolution required sohigh that direct TIME INTERVAL-TO-DIGITAL CONVERSION is not feasible becauseof the very high clock frequency that would be needed. Besides that, TIMEINTERVAL-TO-AMPLITUDE Conversion may be useful whenever an amplitudedigitizing system is already available and therefore an analog interfacebetween time intervals and signal amplitudes extends in the moststraightforward way the digitizing function to the time variable.

In what follows the two nuclear events will be assumed to beinteractions of nuclear radiations with detectors. The instant ofoccurrence of the two events is defined from the electrical pulses deliveredby the detectors by suitable timing triggers.

It will be assumed that the output signals from the timing triggers areshort pulses: obviously they are delayed with respect to the true nuclearevents, in the sense that the electronically defined time of occurrence ofthe event does not coincide with the actual time of an occurrence of thephysical events. A pure delay, equal for both events, would be of noimportance as the parameters of interest in nuclear experiments is the TIMEDIFFERENCE between events, not their absolute position in time.

In the measurement of time intervals, the pulse which comes earlier iscustomarily referred to as START SIGNAL, while the pulse which comes lateris called STOP SIGNAL.

Time interval-to-amplitude conversion is realised in the followingway. Generation of a linear ramp begins as soon as the START SIGNAL isreceived. The linear ramp stops when the STOP SIGNAL comes in and the valuereached is held for the time necessary for analog-to-digital-conversion.

Depending on the particular experiment, START and STOP may appear onphysically separate lines, like in the case in which they come from timingtriggers associated with two different detectors, or may appear on the sameline. The latter occurs, for instance, in the analysis of the probabilitydistributions of time intervals between couples of events generated in thesame detector. This is the case, for instance, in which the distribution oftime intervals between events is monitored to detect whether the eventsbelong to Poissonian statistics or not.

The principle of TIME INTERVAL-TO-AMPLITUDE CONVERSION is described bythe timing diagrams of Fig. E.I a) and b).

93

sw?

START STAKT LIME

STOP STOP LINIE

OUTPUT LIME J

START STOP STAITT STOP

OUTPUT L/WF

fb)

Fig. E.I: Principle of time interval-to-amplitude conversion1 a> START and STOP signals on two different lines1 b) START and STOP signals on the same line

STA £7

5LOPÎ = 2ab C

Fig. E.2: Example of realization of a TAC

94

The principle of TIME INTERVAL-TO-AMPLITUDE-CONVERSION is implementedby a circuit known as TAG (time-to-amplitude converter). The simplifiedblock diagram of a TAG intended for pulses appearing on separate lines isshown in Fig. E.2.

In the description of the circuit of Fig. E.2 as well as for othercircuit analysis to be made it will be conventionally assumed that theanalog switches are closed when the control voltage VL is at logic levelHIGH and they are open when VL is at logic level LOW.

As to the circuit of Fig. E.2, assume that before the arrival of theSTART pulse the flip-flop has O^ = LOW and Qx = HIGH and thataccordingly S^ is closed and §2 is open.

The monostable multivibrator in the standing state has the Q output atlogic level LOW and therefore 83 is open. In these conditions theconstant current source I is diverted to ground through $2- The resistorR provides a dc path to ground for the leakage currents of the switches S^and S3 and for the bias current out the output buffer, thereby preventingthe voltage across the capacitor C from drifting indefinitely under theaction of these currrents. The value of R must be large enough, 10 megaohmor more to avoid intolerable nonlinearity in the generation of of the linearramp. If the sum of the leakage currents of Sn and 83 and the biascurrent of the output buffer do not exceed IQ"-*0 A, which requires thatthe buffer has a field-effect transistor at the input, the voltage erroracross C would be less than l mV.

The dynamic behaviour of the circuit proceeds as follows. The STARTpulse sets the Q output of the flip-flop to logic HIGH and the Q output tologic LOW thereby diverting the current I into the capacitor C. A voltageramp is therefore generated across C. The linear charging of C stops whenthe flip-flop is reset by the STOP pulse. The voltage reached by thecapacitor at the end of the time interval under measurement is temporarilyheld on C.

The HIGH-to-LOW transition in the flip-flop Q output initiates thefollowing sequence. A time interval, equal to the desired holding time,starts being generated in the delay generator. Once this characteristicdelay has elapsed, the output signal from the delay generator triggers themonostable multivibrator, which at the output Q provides a short positivepulse. The function of this pulse is that of closing the switch 83 thusrestoring the voltage across C to zero. Once the monostable multivibratorrecovers to the standing state, the TAC is ready to process a new timeinterval. The described principle can easily be transferred into thatsuitable for couples of events on the same line by simply replacing theSET-RESET flip-flop configuration with a TOGGLE flip-flop.

It is worth pointing out that a real TAG is somewhat more complicatedthan the circuit diagram of Fig. E.2 would imply. What makes it morecomplicated are the auxiliary logic functions that have to be added toprevent false operation. So, for instance, if a START signal is notfollowed by a STOP signal within a given delay which corresponds to theinstrument full range, the capacitor C must be automatically reset.

A STOP signal not preceded by a start signal must not activate the TAG.Some more elaborate logic decisions may also be needed to improve the

TAC rejection of ambiguous situations.

95

The present exercise is intended to familiarise people with theprinciples of TIME INTERVAL-TO-AMPLITUDE CONVERSION, although accurate inits basic functions, it lacks some of the auxiliary logic decisions.Circuit description

The input section of the TAG differs from the flip-flop structureoutlined in Fig. E.2 for two reasons. One is that to increase theversatility, an input configuration was chosen which not only enables theexperimenter to convert into amplitude a TIME INTERVAL, but also the WIDTHof a PULSE. With this circuit associated with a multichannel analyser thewidth of a rectangular signal can be measured with high accuracy. Thesecond reason why the classical approach based upon flip-flop was abandonedis that in the configuration adopted here, the reset operations after ameasurement are implemented in a much simpler way. The basic circuitdiagram of the TAC is shown in Fig. E.3.

The TAG requires that the START and STOP signals be negative pulses, 10yus long and with a 0.5 V minimum amplitude. The circuit measures the TIMEINTERVAL between the NEGATIVE GOING EDGES of start and stop signals. If thecircuit has to be employed in a real experiment and the timing triggers, aswas assumed so far, deliver very narrow pulses, these pulses must bereshaped by two monostable multivibrators with about 10 /us characteristicduration. For the planned laboratory exercise, this will not be necessary,as the tests will be made using one or two synchronized artificial pulsegenerators, whose widths can easily be adjusted to the required value.

The working principle of the circuit of Fig. E.3 is as follows. Theanalog comparator has the non inverting input biased at 400 mV, while theinverting input is connected to ground via a resistor.

OUT

Fig. E.3 Basic circuit diagram of TAG

96

The start and stop signals are applied to respectively non invertingand inverting input through decoupling capacitors of large value. In thestanding state, therefore, the comparator output is at the logic level HIGHand this keeps S^ open and S2 closed. The switch 83 is open in thestanding state. The current I is diverted to ground and the voltage acrossC remains close to zero thanks to the resistor R in parallel.

When the START signal is received and provided that its amplitudeexceeds the threshold, about 500 mV, the comparator switches. Its outputdrops to logic LOW with the effect of closing 8^ and opening 82 whileS3 still remains open. The current I is steered into C and the linearramp is generated.

When the STOP signal is applied at the inverting input the originalcondition in which the non inverting input of the comparator was at a highervoltage than the inverting one is restored. The comparator output switchesback to logic HIGH, 8^ opens and 82 closes. The current I gets divertedto ground again and C remains charged at the voltage reached when theNEGATIVE GOING EDGE of the STOP SIGNAL was applied.

The delay generator is activated by the LOW-TO-HIGH transition in thecomparator output. At the end of the delay interval, a short positive pulseshaped by the differentiator closes 83 and this resets the charge on thecapacitor. The voltage across C is taken by a low input current buffer andmade available at low impedance for further processing.

The circuit of Fig. E.3 differs from that of Fig. E.2 in the structureof the input section, which employs a comparator rather than a flip-flop;other differences are of minor importance. The linear ramp generation, thecapacitor reset and the output signal buffering are identical in bothcircuits of Figs. E.2 and E.3.

The use of a comparator at the input extends the application of thecircuit to the case in which the width of a pulse, rather than the timeinterval between pulses, has to be converted into an equivalent amplitude.The pulse whose width has to be measured must be sent to the START input andno signal must be sent to the STOP input.

The detailed circuit diagram of the TAC is shown in Fig. E.4.The input comparator is realized with the monolithic circuit K (L710).The second L710, labelled K2 implements the delay generator.

Transistor T2 is the constant generator and 8^, 82, 83 controlits state, enabling or disabling the generation of the linear ramp.

C is the capacitor across which the linear ramp develops when thecollector current T2 is turned ON. The transistor 13 implements thefunction of reset switch. The standing condition of the circuit ofFig. E.4 is the following one.

The output of K! is at logic HIGH, therefore the voltage at node 0 isabout +3V.

Transistor T^ is ON.The voltage at node F is about 2.3 V.The diode 82 is reverse biased.The collector current of Tj^ is 1 mA.This current cannot be entirely supplied by the 8.2 k resistor

connected between the node E and the positive supply voltage. Therefore the

97

STAßT

42V

STOP

~3 -c l- ? 4H/VJnf?

G^- iN^16OUT

£ 2.2k,s

X °-V-O.-JM.F

diode6.6 V.

Fig. E.4: Detailed circuit diagram of TAC.

j^ must be ON. The transistor Ï2 is OFF; the node E is at aboutThe current balance at node E gives:

12 - V,E + I all the currents expressed in mA.8.2

As previously said, VE 6.6 V. Therefore Ip 450 uA. The voltageat node N is about -0.5 V, therefore the voltage at node L is around +3V. The voltage at node I is 0 V and transistor 13 is OFF. The voltageat node H, output voltage is slightly positive. Dynamically the circuitworks in the following way.

The START signal, which must be of a negative polarity, with anamplitude exceeding 0.5 V and a width larger than 10 us switches K^.The output jumps to a slight negative voltage, about 500 mV inmagnitude. As a consequence T^ is turned OFF* because its emitter isclamped to -700 mV by the diode 82- Diode 82 becomes reverse biasedand T2 is turned ON. The emitter current of Ï2 is given by:

12 V - (12 V - 4.7 V) -V,BE = 0.5mA8.2

This current, flowing into C charges it linearly.appears at the output.

A voltage ramp

The HIGH-TO-LOW step which appears at node 0 is transmitted as anegative short spike to the inverting input of &2 by the 47 pFdifferentiating capacitor. This spike has no effect, for it goes on thealready negative non inverting input.

98

Suppose that now the STOP signal, again negative in polarity, morethan 0.5 V in amplitude and more that 10 us in width is applied at theappropriate input. The comparator output quickly switches to the logicHIGH back again. T^ is turned ON, it brings P into conduction and T2goes OFF,

The collector current of T2 stops flowing and C remains charged atthe voltage close to the one stored when the STOP signal was applied.

The spike induced at the inverting input of K2 by the LOW-TO-HIGHstep at node 0 differentiated by the 47 pF capacitor triggers thecomparator K2> which is connected as a monostable multivibrator.A negative rectangular signal, about 3.5 V in amplitude appears at nodeL, which is transmitted differentiated to node I. The negative spike atI has no effect. The positive one drives T3 into heavy conduction,thus discharging C until Tg saturates and the voltage across C is resetto zero. As soon as the driving positive spike on the base of Tß isover, the circuit is ready for a new operation.

The approximate value of standing voltages and currents aresummarized here:

TABLE E.I

NODEABDEFGHILMN0

VOLTAGE400 mV0

7.3 V6.4 V1.8 V0+1 V0+3 V0

500 mV+3V

BranchT CollectorT? CollectorJ Drain

Currentl mA03 mA

The waveforms at various points are sketched in Fig. E.5

99

START

STOPSIGNAL-

O

-Û.5V

+7V

N

f

Fig. E.5 Waveforms at the most significant points

ExperimentConstruct the circuit of Fig. E.4 on the already available printed

circuit board.Once the circuit is ready, check it most carefully before connecting

the power supplies.Connect the power supplies, check all the dc voltages and currents

and make sure that within reasonable inaccuracies due to components'tolerances, they reproduce the values of Table E.I.

Send a negative signal with an amplitude of 0.5 V and a width of 10/us to the STOP input. Nothing must happen in the circuit.Send the same signal to the START input. The trapezoidal signal,with a linearly rising part at the beginning followed by a flattoip and then by a quick recovery to zero must appear at the output.

Check the slope in the linearly rising portion. It must be about 0.5V/yus.

Reduce the duration of the START signal and observe that the finalamplitude of the output signal, node H, must be reduced accordingly.

100

REtRUfJNlM G' G

W i

0 TEIG OUT

START*«• ^^ r** * x^

EJCT.W5IV5 2 STOP-IV

Fig. E.6: Connection of two generators to obtain START and STOP pulses

DELAYLINE

SHORTCABLE

1 rSTOP STAETINPUT INPUT

T A C

>-

AbC(AI P H A)

Fig. E.7 TAC calibration with delay lines and multichannel pulseanalyzer

If everything works correctly, check the linearity of the TAG bysending to the START input ten different values of the START PULSE width.The values of pulse width recommended are:

I/us, 2 /as, 3 ,us, 4 AIS, 5/is, 6 /us, 7/is, 8 /is, 9 /us, 10 /is.

Measure these widths with the highest possible accuracy using the 1/us/div time scale of the scope. Measure with the scope the final amplitudeof the pulse at node H. Plot the output amplitude as a function of theSTART signal. The resulting diagram should be linear.

Having tested the TAG in the PULSE WIDTH measuring mode, you can testit now in the TIME INTERVAL MEASURING MODE.

For this application, use two generators synchronized in the way shownin Fig. E.6 to obtain start and stop pulses and connect them to theappropriate inputs in the circuit.

101

uppe*.START SIGNAL

STOP Sl&WA-L

WPER TRftCESTART S1G-WA-L

LOWER TRftCÊ

OUTPUT

UPPERSTOP

LOWER TR.fVC£OUTPUT

Fig. E.8 TAG waveforms

Check with the scope the waveforms at points 0, E, N, I, H and makesure that they correspond to the ones sketched in Fig. E.5. Test thelinearity again using the already explained method.

Once linearity is checked, calibrate your TAC by using delay lines ofaccurately known delays and a single pulse generator, according to thediagram of Fig. E.7

As the TAC has already been checked for linearity, two values of delayswill suffice for the calibration. Represent on a linear scale the channelnumbers corresponding to the two values of delay. Join the two points soobtained with a straight line. This gives the calibration curve of the TAG.

Go back again to the two synchronized generators of Fig. E.6, fix avalue of delay between start and stop around about 3 AIS and measure itaccurately using the MCA and the previously obtained calibration curve.

The waveforms observed at different points of the TAS are given in Fig.E.8.

102

PART 4

DIGITAL CIRCUITS

EXPERIMENT 12

CORRECT USE OF LOGIC GATES

Objective; Introducing the correct use of logic gates, understandingthe driving requirements and becoming familiar with the characteristics oftwo of the widely employed logic families.

IntroductionAttention will here be limited to CMOS and the TTL families. CMOS has

three main features. First, the power dissipation of a CMOS gate isextremely SMALL in the standing state. Secondly, it can be used by changingin a broad range the voltages that respectively define logic 0 and logic 1.Thirdly, if negligible current is drained out or injected into the gate, theoutput level coincides with the two power supplies.

TTL is important as a family not only because of the extremely broadrange of circuits it makes available to the designer, but also because ithas given origin to a number of subfamilies, like the low power (L), theSchottky (hot carrier diode damped for fast operation), low power Schottkywhich combines the features of the two previous families, the H or highspeed TTL.

Correct use of CMOS and TTL families requires not only a knowledge oftheir characteristic logic levels, but also being aware of the drivingconditions and output current capabilities of the basic gate of eachfamily. This turns out to be especially important when simple interfacesbetween the two families have to be designed.

The basic characteristics of the CMOS family and those of the TTLfamilies are summarized in the following pages.

As you can see, the input of the SN 7400 HAND Gate is connected to thevirtual ground of an operational amplifier, that is, to an almost idealcurrent input. The voltage at the inverting terminal of the operationalamplifier is equal to the voltage set at the non inverting input by thepotentiometer P. By changing the potentiometer setting in steps of 500 mV,determine the behaviour of:

HAND GATE INPUT TO OUTPUT CHARACTERISTICS BY READING WITH A DVMTHE VOLTAGE AT POINTS A AND C.

NAND GATE INPUT CHARACTERISTICS BY READING WITH A DVM THEVOLTAGE AT POINTS P AND B AND REMEMBERING THAT THE INPUT CURRENTOF THE GATE IS GIVEN BY

V - VA BRf

FOR THIS MEASUREMENT, WHEN C GOES LOW, SWITCH THE AMPLIFIER FEEDBACKRESISTANCE TO l M TO BE ABLE TO READ THE SMALL INPUT CURRENT TO THEGATE.

105

Experiment

Construct the circuit as shown in Fig. 12.1.R, = IM

B3-F356

+

— o

A J

T-M-

IIs

74 om

•Î-12V

Fig. 12.1 Using a TTL-IC

Repeat then the experiment with a CMOS NOR gate, by using the newvalues shown in the circuit of Fig. 2.

Rt = 10 M

B

•M2V

3.F356

V

i.1* JH[M-

1PJIOKjf MM74C02

-12V

Fig. 12.2 Using a CMOS-IC

The next step will be interfacing a CMOS inverter with a TIL inverter.Assemble the circuit shown in Fig. 12.3:

-t loV

OUT

Fig. 12.3 Interfacing a CMOS with a TTL inverter

106

Check that when you apply + 10 V, that is, the logic HIGH at the CMOSgate input, the voltage at C^ is +.7 V and the output 0 is at TIL logic1. Apply then 0V, which corresponds to the logic 0, at the input of theCMOS gate and check that point C^ be at about +.2 V. In this case theoutput 0 of the TTL gate should be at about +.2V, which is the TIL logic 0.The transistors, TQ, T]_, T2 realize a non inverting CMOS-to-TTLinterface. It is worth pointing out, in passing, that the T1, T2 pair,connected in the way shown, with the input applied to the base of Tj andthe output taken from C^ realize the basic inverter of the I2L logicfamily, which is characterized by the following levels:

LOGIC 1LOGIC 0 'BE of T,

VCE» SATf TlAssemble now the circuit shown in Fig. 12.4; this is another kind of

CMOS-to-TTL interface and check it as you did before. Does it work like theprevious one? If not, try to explain the reason for the possiblemalfunctioning.

-HOV.

M)O——OUT

Fig. 12.4 CMOS-to-TTL interface

107

EXPERIMENT 13

DIGITAL SETTING OF AMPLIFIER GAIN

Objective; To demonstrate the principle upon which the gain of afeedback amplifier can be digitally preset. The amplifier that will berealized has only two possible values of the programmable gain, and this wasdone for the sake of simplicity. However, the principle can easily beextended to a larger number of gain values,

IntroductionSeveral applications in the field of data acquisition require

amplifiers for which the gain can be preset for instance by a computerinstruction, or more generally, by applying a digital word to the gaincontrol input.

In the present circuit, which is a feedback configuration obtained froman operational amplifier in the non inverting connection, the gain ischanged by switching the feedback return ratio.

A single bit word in this case selects the desired value of the gain.The principle is shown in Fig. 13.1.

The gain selecting bit is applied to the input BQ.Assume BQ. at first at logic 0, BQ = 0V.The transistor T^ will be ON, as the output of the logic driver

SN 7407 is low and the collector current of T^ flowing into diode D±keeps T2 conducting and 13 off. The collector current of Î2 flowingacross the resistor R maintains J2 in the open-circuit condition.Therefore the feedback path around the operational amplifier consists of thefield-effect transistor J^ - 100 K resistor series, connecting theoutput of the amplifier to its inverting input and of a 10 K resistor fromthis input to ground. Neglecting the ON resistance of J, the system has aclosed-loop gain of about 11.

Suppose now BQ raised to logic 1. T^ is turned off and along withT! also diode D1 goes off. The transistor T3 is now ON, and T2 isOFF. As no collector current flows across R, the JFET ^2 becomes a shortcircuit. The gain of the system, neglecting the ON resistance of thefield-effect is determined by the ratio:

R2 R2'v .R2 + R2————-———-———A 2.5

Rl

ExperimentAfter assembling the circuit of Fig. 13.1, check all the dc voltages

at BO = 0V and at BQ = 5 V; if more than one value is shown in thediagram, the one in brackets pertains to BQ = 0V.

109

+ I2V

^

GfllN SELECT!!BIT

Fig. 13.1 Diagram for a digitally preset amplifier gain circuit

If in both cases the values shown in the circuit are reproduced with anacceptable degree of tolerance, send a signal of about 100 mV and check thevalues of the gain, by setting the gain selecting bit to logic 0 and then tologic 1.

Apply then a dc level of 100 mV to the amplifier input and send asquare wave signal passing from OV to + 5V, then again to OV and so forth,with a period of 1 ms. Look at the waveform at the amplifier OUTPUT, andverify that the output is a square wave periodically switching between 250mV and 1.1V.

110

EXPERIMENT F

FLIP-PLOPS. COUNTERS AND DISPLAYS

Objective; Demonstrating the properties of flip-flops and becomingacquainted with their uses in counting circuits; assembling a complete 4digit sealer, with input circuitry and display, using a large scaleintegration counter as a building block..

IntroductionThe SR Flip-flopA SR flip-flop can easily be build from NAND gates as shown in

Fig. F.I. If a positive pulse (corresponding to logic state 1) is appliedto point S the flip-flop is set to state 1 (defined as the state in whichQ = 1); it remains in this state when the pulse ends; further signals onpoint S have no effect on the flip-flop state. If, instead the pulses areapplied to point R then the flip-flop is reset to state Q = 0.

Fig. F.I. Flip-flop constructed from NAND gatesIn most digital circuits it is necessary that flip-flops be allowed to

change state only at certain times, defined by a clock pulse. You caneasily implement an appropriate circuit by a simple modification to theprevious one, as shown in Fig. 2. The S and R inputs are the controlvariables and for reliable operation of the circuit they should bepositioned at the required states BEFORE the Clock (Ck) pulse arrives. Thevalue of the Q output AFTER the n1-*1 clock pulse will be designated byQn+1* ^ou can experimentally verify that the circuit operates accordingto the following table.

Fig. F.2 Controlled flip flop

S

0011

R

0101

Qn+1

Qn01?

•R Q-•CK•S

111

The question mark means that with S = R = 1 the value Qn+i isambiguous, that is, it may either be 0 or 1 depending randomly on which gateis able to respond first; the control S = R = 1 is never to be used.

The JK Flip-flopThe JK flip-flop obeys the following table.J

0011

K

0101

Qn+1

Qn01Qn

•J Q-

K Q

It is seen that this table extends the table of the RS flip-flop (Jcorresponding to S, K to R) by acquiring a definite output whenJ= K = 1, namely Qn+1 = Qn.

You can build a flip-flop obeying the above table by using two SRflip-flops (Fig. F.2) and an inverter; this is shown in Fig. F.3. Thevarious gates respond to low-to-high (from state 0 to state 1)transitions. Because of the inversion of the clock pulse by inverter I,RS-2 responds to a high-to-low transition of the clock pulse. This isillustrated in Fig. F.4.

" S - 1 " S - 2

Fig. F.3 JK flip-flop

Fig. F.4 Pulse sequence in a JK flip-flop

At the low-to-high transition of the Ck pulse RS-1 is actuated, andits state is transmitted to RS-2 at the high-to-low transition of the clockpulse. Such a flip-flop is called a master-slave flip-flop.

112

The T and D flip-flopsThe T flip-flop is a JK flip-flop, subject to the restrictionK = T. Thus, it obeys the following table:

Qn+1

n-D O-

k•KQ-

It is used in counters as described in the experiment below.The D flip-flop is a JK subject to the restriction J= K = D; it

obeys the following table. It is used in shift registers.

01

01

-T Q-

Q-

Counter DisplaysWhen flip-flops are used to build counters it is convenient to be

able to read their contents visually. This may be done with LEDs usingsuitable codes. The simplest from the hardware point of view is to readin a binary code; a LED is connected to the Q output of each flip-flopand is lit when Q = 1.

A most common code pertains to the 7-segment display. If a counteris built as a decade counter the flip-flops are organized in groups of 4and each of these groups counts from 0 to decimal 9; the counter isorganized in a binary coded decimal (BCD) way. The binary information onthe stored number, contained in the values QQ to Qß, must then becoded in such a way that the appropriate LED segments (Fig. F.5) are litto form a number. For example if QQ = Q2 = Qa = 0 and QI = 1(decimal number 2) then the segments labelled a, b, g, e, d are lit.There are integrated circuits which convert from one code to the other(from BCD to 7-segment); we will use them in the experiment to follow.

Fig. F.5 Segments of a LED display

Experiment1. Assemble the circuit of an R-S flip-flop according to the schematics in

Fig. F.2 above and verify its truth table.2. Verify the truth table and observe the time relation between the clock

and output pulses of a 74LS73 or 74C73 master-slave JK flip-flop.

113

3. Assemble the circuit shown in Fig. F. 6. These flip-flops are connectedto form a binary 4-bit counter. Observe its operation by looking tothe clock pulses on channel A and to the various Q outputs on channel B(it may be necessary to slightly adjust the generator frequency toobtain a stable display on channel B if the triggering is made throughchannel A). Draw a time diagram showing what you observe.The gate (74LS10 or 74C10) may be used to clear the flip-flops.Because the Cl input of the 74LS73 is active low, the flip-flops willbe cleared i f A = B = C = l . Thus the counter can be cleared when acertain count has been attained if the inputs A, B, C of the gate areconnected to the appropriate Q outputs. For example, to return to zeroafter the 7th pulse the gate inputs are to be connected to the 22,2^ and 2° flip-flops. The signal out of gate G2 may then go toanother counter, which will count 1 for every 7 clock pulses. Trydivision by other numbers (5 and 10 for example).

svT

Count

2°—

—

j Q

K cT

1_

-

21

1_-

22

1

1_

23

7473 7473

7410

Fig. F.6 Binary 4-bit counter

4. Observe the operation of an integrated 4 bit decade counter, like theTTL 74LS90 or the CMOS 74C90.

5. observe the operation of a BCD to 7 segment decoder by connecting asuitable decoder to a decade (say the 74LS48 if you are using a TTLdecoder or MM74C48 if you are using a CMOS decade).

6. You are now going to assemble a complete four decade counter with a 4digit display. The two main blocks of the counter are an LSIintegrated circuit MM74C925 and a four LED integrated display NSB.Internally the 925 (Fig. F.7) has 4 decade counters, each one connected

to a 4-bit memory (latch); these latches are sequentially connected to asingle BCD to 7-segment decoder by a multiplexing circuit, which also setsthe state 1 to one of four output control lines. The 7 segment output linesare connected to four common-cathode LED digits in parallel, as shown in thecomplete schematics of Fig. F.8. The digit that is lit is the one for whichthe control line is in state 1. The oscillator that advances themultiplexing circuit, and thus the output control lines, is also internal tothe 925 and has a frequency of 1 kHz; to the human eye the digits appear tobe simultaneously lit.

The circuit diagram of Fig. F.8 also shows an input gate to the signalsto be counted and its control (either manual or through a level applied atthe control input) and another gate that may be used to strobe the internallatches of the 925 counter (if unused the latches are always enabled).

114

MM74C925

Reset

«Clock

LATCH sEnable

out

Fig. F.7 Inside a 925

33R 103 102 101 10°

220R

STROBE

Fig. F.8 Four-decade counter

Connect a pulse generator to the count input and open the gate of thecounter. Observe visually and with a scope whether the sealer is counting.

Observe the strobing of the transistors; stop the counter by closingthe gate and observe the segments corresponding to one of the digits bytriggering the scope with the appropriate strobe signal.

Use the strobe input to freeze the display while the sealer is counting.The circuit you have assembled is limited in count rate to about 2 MHz;

if you need a higher count rate capability you may insert a fast decadeafter the input gate, and display that decade independently. The output ofthe decade then goes (directly or inverted as appropriate) to the 925 clockinput.

115

EXPERIMENT 14

VOLTAGE TO FREQUENCY CONVERTER

Objective; The operation of a VCO is studied and the relation betweenthe frequency of the output voltage and the input voltage is measured.

IntroductionA voltage to frequency converter (VFC) is made by connecting the

already existing circuits explained in small exercises (Integrated withReset, Discriminator and Univibrator). The block diagram of the VFC isgiven in Fig. 14.1. When the constant input voltage Vj is applied to theinput of the integrator the resulting output voltage VQ will be:

V0 = -Vjt/rwhere T is the integrator time constant,t = RC.

?vref

INT A/

RESI

4FET

-LL UNI Tl

1Fig. 14.1: Block diagram of a VFC

The voltage Vo is inspected by the discriminator set at Vref .Therefore at the discriminator output, low to high state transition resultswhen Vref is exceeded by Vo. It will be reached in the figure T = <v

By this transition the Univibrator is triggered. In order to get theadequate pulse for the integrator reset (0 for discharge, and -12 V duringthe integration), the Univibrator is operating between the 0 and -12V supplyvoltage. After the time T, the integrator is reset and the Univibratorpulse is finished. Then the integration starts again and the describedcycle is repeated. The higher the input voltage the greater will be thenumbers of cycles per second, i.e. the frequency.

ExperimentConnect circuits into the loop and observe the operation of the VFC

with the applied negative voltage input Vj . Change the reference voltagevref initially set at 5 V and explain results. With the grounded inputthe expected resulting frequency is zero. Set the zero control tr impôt forthe best output voltage.

Explain why you can't use the positive input voltage also. Observesignals at the output of integrator, discriminator and Univibrator and drawthe quantitative pictures (voltage and time marks included) .

Measure the frequency of the output signals at different input voltagesand represent results graphically. Consider the influence of the resetpulse duration on the VFC linearity.

117

EXPERIMENT 15

SAMPLE AND HOLD

Objective: Properties of the sample and hold circuit areillustrated. Some parameters important for its operation are discussed andcompared with the observations.

IntroductionA sample and hold circuit takes samples of the input voltage when the

control pulse is applied and keeps it until the next control pulse arrives.The input - output relation of the circuit is illustrated in Fig. 15.1. Itsoperation is achieved by charging the capacitor C through the analog switchS as illustrated in Fig. 15.2a.. The voltage across capacitor C follows thevoltage VQ switch S is closed and remains constant when open. Of course,the output voltage Vj cannot be used without being changed due to thecurrent taken out from the capacitor during the observation. By selecting alarge C the performance of the sample and hold circuit could be improved.In this case, however, the output voltage V0 could not follow the inputvoltage during the fast sampling due to the finite switch resistance Rsthrough which the capacitor is charged.

vs

V0

r\i ^i !h in ij li:

r/ii1 —ii• —

\V 'ii

iN '-V-j —— r^ —

b)

Fig. 15.1: Sample and hold waveforms

Fig. 15.2: Sample and Holdbasic diagram

To avoid the use of the large capacitor, the voltage follower is added(Fig. 15.2b). When using LF 356 the current taken out from C does notexceed 10~10A, and the output current capability is 25 inA.

It will be interesting to estimate the characteristics of this circuitassuming the 5 V voltage across a 10 nF capacitor with the switch S opened.In this case the voltage drop due to the amplifier bias current taken outfrom the capacitor will be l mV in 1 sec. If the analog switch contained inCD 4066 is used, the corresponding time constant determining the circuittime response will be R2C = 300.10~8s = 3 /is. The sample pulse durationshould not be smaller than 5 RC. This will reduce the relative differencebetween the input and the output voltage at the beginning of the samplepulse to less than 10~ . In our case this amounts to 15 us. Thepractical circuit is drawn in Fig. 15.3.

119

Vg KJK»-CD-1

V|

Signal

IM Li-

!

....... -TI/4CD4O66 ^

*

——— 1£lOn

1.-* S1

_Lci- '/4CD4066 TlOn

•W-i

9&

2

•

3f

^

'"" +7VJ ffHAK

1_ ____ 1

HIMk.^ y .. .4..,,.•Ä^^^— _ t-t 1 ]

\ n IM

4K7|J 1VM -7V ï 79LOÎ

+ 12

°8

—— »O

Fig. 15.3: Sample and hold practical circuitBy the newly introduced components, two improvements are achieved. By

using the second semiconductor switch S2 the influence of the capacitivecoupling of the sampling signal on the output signal is compensated. Inaddition, when switches S1 and 82 are open, the same current is takenfrom the equally valued capacitors C^ and €2, and therefore the effectof the bias current is compensated. For the output voltage drift only thedifference between bias currents, called the offset current is responsible.This makes the output voltage drift in general 10 times smaller.

The operating voltage of the quad analog switch CD 4066 is limited to15 V and therefore the +12/-12 V supply voltages are reduced to 7,5/-7,5 Vby using 3 points voltage regulators 78 L05 and 79 L05. The control inputfor logical switches, also sensitive to voltages beyond the supply voltagerange, is protected by two additional small signal diodes. The CD 4066control signal input connected to the logical low state makes switchesnormally open.

ExperimentsThe printed circuit board should be equipped with a socket for easier

interchange of operational amplifiers LF 356 and LH 318.Connect a sinusoidal signal of few V amplitude and 1 kHz frequency to

the input of the assembled circuit and observe the input and output voltagesimultaneously. Then connect the sample input to the V^ voltage to makeswitches conductive. The output will follow the input voltage but it willremember the input voltage at the moment of dis-connecting the control input from V^. Write the values of 50 sequentialreadings and plot their height distribution. Can you explain the result?What is the expected result if the rectangular voltage is sampled?

Apply periodic pulses of the frequency 1 kHz and duration of 10 us tothe control input and adjust their amplitude to get the adequate logicsignals at the gate of the CD 4066 switches.

Apply a sinusoidal or triangular voltage signal to the analog input andobserve output if the sampling frequency is very close to the signalfrequency. By using this technique the fast signals can be converted intothe slower sinusoidal signals. The observed effect is called thestroboscopic effect. Try to explain it.

Connect the constant voltage to the analog input and observe outputvoltages. Decrease the frequency of the strobed pulses from 1 kHz to a fewHz and compare observations made with LF 356 and LM 318. Estimate the inputoffset currents for both amplifiers.

120

EXPERIMENT G

ANALOG TO DIGITAL CONVERTER (WILKINSON)

Objective: To study the principle of operation of a Wilkinson ADC usedin nuclear spectroscopy.

IntroductionThe function of the ADC in a nuclear system is to convert the pulse

height into a binary number proportional to it.We will deal in this experiment with the Wilkinson type ADC which has

as an outstanding characteristic: an excellent differential linearity.The experimental version of ADC to be studied in the laboratory

converts a D.C. level into an eight bit binary number. The block diagram isshown in Fig. G.I.

O +15V

CONSTANTCURRENTSOURCE

EXTERNALCOUNTER

V______

CHARGE

Fig. G.I: Block diagram of the experimental version of Wilkinson type ADC

The functioning of the circuit is explained as follows:Initially, the analog switches are in the states indicated in

Fig. G.I, that is:Switch A:Switch B:Switch C:

closedopenclosed.

In this way the following situations occur:Capacitor CA is at input potential V|

121

The constant current source makes current i circulate from the +15Vsupply to -15V.At the instant t^, when the conversion process starts, the control

unit changes the state of the switches in the following way:Switch A:Switch B:Switch C:

openclosedOpen

The actions which take place as a consequence of the switches changingare;

Capacitor CA is isolated from the input and connected to theconstant current source.

- The constant current source is disconnected from the +15V supplyand starts a linear discharge of capacitor CA.

At the same time the control unit sends a logic "1" to the three inputAND gate. Observe that the comparator output is also at high level as thecapacitor voltage is positive. As a consequence, the clock pulses entersinto the counter.

Upon reaching the instant t2, when the capacitor is completelydischarged, the comparator output goes to logical "0" and the counter stopscounting.

The number of clock pulses accumulated are proportional to the timeinternal between t^ and ^2 which in turn is proportional to the pulseheight. See Fig. G.2.

'START CONVERSION' "CHARGE"

Vj

Fig. G.2. Timing diagram of the ADC.

To restart the process the "CHARGE" switch has to be operated and thecircuit returns to the initial state being ready to start a new conversionprocess when the "START CONVERSION" switch is pressed.

122

1C 2 =4016 B/4066 B *15V

"START CONVERSION"\— C2, 1000 p F

D22R7 -4K7

R81K

1N914 _J_

ICUCD4011B R9 rr^120K

_TLTLMOOKHZ

TO THECOUNTER

DIRECTOUTPUTO

OPEN COLLECTOR,OUTPUT

2N 3904

100 pFtot» Fig. G.3: Circuit diagram of the experimental Wilkinson ADC

ExperimentA) Assemble the circuit of Fig. 6.3. Connect a sealer to the output.B) UNDERSTANDING THE CONVERSION PROCESS

1. Check that the clock circuit oscillates at 10 KHz approximately.2. Adjust the constant current source to 1 mA.3. Apply a D.C. voltage at the input (Any value between 0 and 10 Volt).4. Press "CHARGE" switch momentarily. Check that CA is charged to the

input voltage.5. Press "START CONVERSION" switch. The counting will start. The result

of the conversion will be shown in the sealer.6. Press "RESET" sealer The content of the counter will be reset to zero.

Repeat the procedure for input values in steps of 0.5V and then plotthe counter content against input voltage.C. OBSERVING WAVEFORMS

1. Disconnect the "CHARGE" and "START CONVERSION" switches and connectpins 1 and 12 of 1C! (4011).

2. Apply a 12V square wave, 100 Hz frequency from an external generator.In this way a repetitive conversion cycle takes place and the different

waveforms can be observed.D. EVALUATION OF INTERNAL PARAMETERS

Using either way of conversion, one-step or repetitive, investigage theinfluence of the magnitude of the constant current source and the clockfrequency in the converted number.

124

PART 5

BASIC INTERFACING CIRCUITS

EXPERIMENT 16

DIGITAL SWITCHES

Objective: Familiarization with switches and debuncing.

Introduction

The three commonly used digital switches are the electrical, the optoand the Hall switches.

Electrical switchesThe two familiar versions are the so-called Single pole single throw

(SPST) and single pole double throw (SPOT) switches shown below.

SPST ——— SPDT

Fig. 16.1 SPST and SPOT

Both of them can be used for the generation of the two possible logiclevels as shown in Fig. 16.2.

+ 5V 4K7 OUT rf5

~ OUTIFig. 16.2 Logic levels generated by SPST and SPOT switches

These switches should never be used as the source of logic pulses, bymomentarily activating them. A mechanical switch is always bouncing afterthe first contact has been made, and one gets an unpredictable sequence ofpulses instead of one.

In the case of an SPOT switch, one can get rid of the bouncing effectwith the use of the following simple circuitry.

In this scheme the two NAND gates form a flip-flop. To set the Qoutput HIGH, one has to ground S. Due to bouncing, the point S getsfloating and grounded repeatedly, but the HIGH state of the output point Qdoes not change. To reset the Q output to LOW, point R has to be grounded.The bouncing of the switch will not influence the low level of the output Qin this case either.

This is the appropriate circuit if one wants to generate not onlystanding logic levels but also a predictable number of pulses. The numberof the activation of the switch here equals to the number of pulsesgenerated.

Opto and Hall SwitchesSwitches are activated manually or mechanically. If you do not want to

interfere manually or you do not want to build complex mechanisms to changea logic level, then you have to use opto or Hall switches.

127

OUT

Fig. 16.3 Simple debouncing circuit

SHUTTER

LAMP I(g) /wwv*

LIGHT

OPTO 1

2SWITCH3

+5V

MAGNET

-CDN S

+5V

HALL

SWITCH

1-2

3

(h1 } OUT

Fig. 16.4 Experimental arrangement to study properties of optical andHall switches

UT

5.H2 »Hs, -«

OPERATEPOINT

OFFj

t'ONI

l !RELEASE'

POINT i_IOO 2OO 3OO 40O 5OO

Fig. 16.5 Hysteresis in development of a switch. X-axis is magneticflux density in Gauss or light flux density in Lux

OUTPUT

COMMON '2

Fig. 16.6 Block diagram of a switch

128

Both are up to date, low cost monolithic integrated circuits with threepins. Two of them are for power supply (GND and +5V), the third is the opencollector output point. The output transistor conducts if the light flux ormagnetic flux density reaches a certain level in the opto or Hall switch,respectively.

Both switches have a built in hysteresis, i.e. the switching point isnot the same for increasing or decreasing excitation which provides forunambiguous or non-oscillatory switching. Hence they might be used not onlyfor level but for pulse generation as well. In addition, the necessarymechanisms to activate such switches are much simpler (a shutter of light orthe proximity of a magnet) than in the case of mechanical switches.

Experiments:1. Check the switching properties of the opto and Hall switches, followingthe diagrams in Fig. 16.4

2. Check their transfer characteristics showing hysteresis (see Fig. 16.5)3. Tape Reader

Read the bit pattern from a punched tape into an 8-bit latch.Use an array of nine opto switches arranged in 0.1" distancescorresponding to the punch positions of a standard 1" paper tape.The functional block diagram of an opto or Hall switch is shown in

Fig. 16.6.o

PAPER OTAPE o

00oOoo

76543S210

0

O PATTERN0 /0 /o- Sprocket Holeo/O0

Fig. 16.7 Arrangement of an opto switch array illuminated by a lampfrom behind the paper tape.

Wire up the circuit shown in Fig. 16.8

INDICATOR LAMPS

74LS374

+5V

EN

STROBE

ENABLE> DISPLAY

STROBE PULSEFROM THESPROCKET HOLE

9X ULN 3330 Y (SPRAGUE )

Fig. 16.8Electronic set upto reada punched paper tape

129

Pull the paper tape below the opto switch array. Pressing the ENABLEDISPLAY button you will see on some indicator lamps the bit pattern beingread last.

4. Flow Meters

There are now inexpensive plastic flow meters on the market containingsmall permanent magnets rotating in front of a Hall switch. Connect one toa counter and blow air with your mouth to check its functioning (Fig. 16.9).

FLOW METER

Fig. 16.9 Demonstration of a Hall switch

5. The Bouncing; of Mechanical Switches

Having a decade counter wired up in the previous experiment you canquickly check the consequences of bouncing and the effect of the debouncingcircuit offered.

Feed the counter with the pulses coming from the circuits shown inFig. 16.10.

-fSV COUNTER COUNTER

4K7

4K7 4K7

Fig. 16.10 Testing efficiency of a debouncing circuit

Activating the switches N times, observe the number of counts displayedin both cases.

130

EXPERIMENT 17

POWER DRIVERS

Objective; Familiarization with high-current drivers as frequentlyused in measurement or industrial control.

Introduction;The outputs of the digital systems are some logic levels.These outputs can never supply (sink or source) more than a few

milliamperes. Such a small current is not enough to activate high powerdevices - relays, ventils, motors - to be controlled by logic or computersystems. One needs some power drivers.

Darlington TransistorsTwo kinds of dc drivers are in use today. The more classic, is the

so-called Darlington pair built by two bipolar transistors as shown inFig. 17.1

IE

Fig. 17.1 Darlington pair

It behaves like a single transistor with beta equal to the product ofthe two transistor beta's.

Darlington transistors are available as single or multiple packages.A typical example for the first is the npn power Darlington 2N 6285

with current gain of 4000 at a collector current of 10 Amps.An example for the Darlington arrays is the ULN 2003A dual in-line

package (Sprague) with seven monolithic devices inside. The devicesfeature open collector outputs and integral diodes for inductive loadtransient suppression. The Darlington transistors are capable of sinking400 mA each and will sustain at least 30V in the off state. The outputsare suitable for use with relays, solenoids, stepping motors, LEDs orincandescent displays and other high power loads.

1. ExperimentActivate an electromagnetic relay (12V, 300 mA) with a ULN 2003A if

the two conditions A and B are met simultaneously, i.e. if both are atHIGH level (Fig. 17.2).

131

H-12V

Fig. 17.2 use of a Darlington array

Substitute the relay with other useful devices (LED, incandescentcar-lamp, etc.). Remember that the seven printing needles of a commonmatrix printer are driven with such a single ULN 2003A 1C.

Power MOSFET transistorPower MOSFET transistors capable of high voltage and current levels

have recently become available. These devices go by names such as VMOSand HEXFET. They can handle surprisingly high voltages and currents.The industry standard IRF 350 device capable of 11 Amps maximum draincurrent, 350 V maximum drain-source voltage and 0.3 ohm maximum onresistance. The power MOSFET is a natural device when interfacing fromlow-power logic such as CMOS.

2. ExperimentDrive a high power device (as a relay, valve or dc motor) with a CMOS

logic gate as shown in Fig. 17.3.

IRF 350

Fig. 17.3 Use of power MOSFET and a CMOS logic gate to drive a powerdevice

Solid State RelaysTo turn on or off very high power (220V, 25 A) ac motors or other

devices, one should use semiconductor relays. They include a triac asthe ac current switch, and the triac is controlled through optocouplersby logic levels.

132

3. ExperimentControl the operation of an industrial (up to 6kW) AC motor by the

output of a logic (later computer) system Fig. 17.4.

SolidStateRelay

IR 2425OPEN

COILECTOROUTPUT

Fig. 17.4 Solid state relay

If you are afraid of high power motors then use any appliance aroundyou (electric lamp, heater, radio, TV etc.)

133

EXPERIMENT 18

DRIVING OF STEPPING MOTORS

Objective: Familiarization with stepper drivers

Introduction:We are going to use a four-phase stepping motor type AMA 12.4

manufactured by SODECO-SAIA with the following specification:VoltageCurrentStepping angleRotation torqueHolding torqueCurrentless torqueMax. stepping frequencyDimensionPrice $ 25.

12 V170 mA (each coil)15°1.5 Ncm3 Ncm0.3 Ncm200 Hz052 x 28 mm

The stepping motor is driven by the excitation of its four coils in aproper sequence. One end of the four coils is common and has to beconnected to the positive pole of a 12 V power supply whose negative polehas been grounded.

To drive the motor the other end of the coils should be consecutivelygrounded by the use of switching transistors (Darlington, MOSFET's) oneby one or - to achieve some higher torque-two by two.

Let us denote the coils according to the Fig. 18.1.

Fig. 18.1 A stepping motor

BLACK BLACK YELLOW

To drive the motor clockwise first for instance CO has to be excited(i.e. the wire of yellow colour grounded) then, Cl, C2, C3, CO, Cl, etc.To drive the motor coounter clockwise the sequence of coil excitations isas follows: CO, C3, C2, Cl, CO, C3, etc.

The subject of the following experiments is the construction ofsimple logic systems for the generation of the above sequences.

135

For a given stepping motor requiring 12 V supply each coil takes 170mA to be fully excited. This current is too high to be sourced or sunkenby a TTL circuit. The maximal sink current of an open collector TTL gateis 16 mA. It is not enough to provide the nominal torque, but anyhow themotor will rotate nevertheless. Hence at the beginning we shall usesimple open collector TTL circuits for the driving of the motor and willapply only later the appropriate and powerful Darlington transistors.

Experiment1. Stepper driver logic

To generate the proper switching sequences required by a steppingmotor one has to build a two-stage binary counter and simply decode itscontent as shown below in Fig. 18.2.

Cj

L J

k 1CÄi_

1 1Ci

L _J

C0

L

Vm-+5V

SteppingMotor

§!QoStepping Pulses

_n__n__TL

Fig. 18.2 Generating the switching sequence for a stepping motor

With only VM = +5V motor supply and with only TTL drivers thestepping motor will just rotate.

CLK

7474

CWDIRECTION

Fig. 18.3 Controlling the direction of stepping motor turns

136

One can change the direction of the rotation by connecting CLK1 to QOinstead of QO with a jumper. But such a change needs manualintervention. We do not like that, because it does not allow itself tobe automated (a computer cannot change the position of a jumper).

We can insert, however, a simple logic scheme in place of the dottedbox in the middle as shown in Fig. 18.3.

After substituting the jumper by this circuit then some controller(computer) easily can send a HIGH level to the DIRECTION INPUT to getclock-wise rotation or a LOW level to get counter clockwise rotation.

The sequence of clock pulses led to the CLKO input might be generatedeither manually or by a controlling (computer) system. The number ofpulses will define the rotation angle. With the given motor and with theuse of this scheme, 24 clock pulses generate a full resolution (one step= 15°).

Experiment2. The use of high current drivers (Fig. 18.4)

|STEPPING[MOTOR

ULN 2003ADARLINGTON ARRAY

AA A(SPRAGUE)

Fig. 18.4 Use of a Darlingtonarray to drivea stepping motor

7408

Keep the logic circuit built before, but change the 7403 OC NANDgates with 7408 AND gates. Do not connect their outputs directly to themotor coils but amplify each line first with a Darlington transistor.These Darlington transistors can sustain higher voltages, hence one cannow apply VM = +12 Volt to the motor to get its full torque.

Experiment3. Stepping motor controllers

Use the dedicated circuit UCN 4202A to control and drive the steppingmotor. This 1C contains the simple logic circuit studied before and thepower transistors as well (Fig. 18.5).

STEPPING MOTOR •nay

CLKDIRECTIONSTOP

Fig. 18.5 Controllinga stepping motor witha dedicated 1C.

15

137

EXPERIMENT 19

TRISTATE BUFFERS AND BUSES

Objective; To demonstrate the use of tristate buffers

Introduction:In more advanced digital systems (for example, in computers), the

signal lines - called bus lines, i.e. the simple wires used for theconnection of the various subsystems - can be fed with logic levels bymore than one device, but - and this is the point to remember well -never simultaneously.

To achieve this, all the outputs to be connected to the common buslines have to be let through some special enabling/disablingtransmitters, called tristate buffers (Fig. 19.1).

BUS LINE

THREE STATE |_

BUFFERS l^//.ti 9—V

SUBSYSTEM

SQ

Fig. 19.1 Tristate buffers arrangement

Because the bus lines are shared, we always have to have a controller- in computer systems it is an intrinsic part of the processor - whichcontrols the various possible transmitters, enabling only one of them tobe active. The others should be in disabled states, meaning that theiroutput float, as if they were connected to the common signal line throughsome insulator. This insulator is in fact a semiconductor element builtin the tristate buffer, which is controlled in such cases to behave likea break, effectively like an insulator. Alternatively, being enabled, itbehaves like a conductor.

Note, that TS (tristate) buffers are required only if one writes(transmits) to the bus. No similar precautions are needed if a deviceonly reads the state of the bus. In the dedicated computer components(microprocessors, memory) the tristate buffers are built in on themonolithic device itself. But separate TS buffers are required if youconnect (interface) some external devices to the system.

The tristate buffer is a special digital component whose output inits disabled state is neither LOW, nor HIGH (as would be expected from awell behaved digital output) but floats, as if it were insulated or inother words in a high impedance state. Due to this third state is calledsuch a special transmitter is called tristate or TS buffer.

139

The quad-TS buffer type 74 LS 125 to be used in this experiment isshown below in Fig. 19.2.

+-5VI

74LS12514 13

+5V

12 11 10 9 8

3 |4 |S |6 7

SPST

74 LS 12 5390R-dDn

EN

Fig. 19.2 A typical quad-three state buffer

Experiment 1Using digital switches and LED indicators, verify that the output of

a TS buffer follows the input if enabled (EN = LOW).

Then disable the TS buffer (EN = HIGH) and check that the output canbe brought HIGH or LOW by connecting it to +5V or GND through a l Kresistor.

Experiment 2

Connect together the outputs of all the four TS buffers (Fig. 19.3).Enable only one of them, and check that this and only this one determinesthe logic level on the common bus line

BUS LINE

H H/H /L

Fig. 19.3 Connecting three state buffers to a bus line

Experiment 3Build a logic circuit to assure, that only one of the TS buffers is

active.

140

o __I °uiu

3Eg0<-tcu.

+ 5V

TRISTATE BUFFERS

Al5_

12

14

uf"

INDICATOR LED

ADDRESS DECODER

74 LS I38J8

ADDRESS REGISTER & COUNTER.,AT THE SAME TIME

74 1 93

COUKT UP INCREMENT ,

COUNT DOWN DECREMENT |

>±£—— LOAD AN

PARALLEL INPUT TO BE AN ADDRESSI I I

Fig. 19.4 Use of three state buffers

Keep in binary form the address of the device to be selected in aregister (74 193 up/down counter register) and use a decoder (74 138which guarantees that only one of its outputs becomes asserted. Use theoutputs of this decoder to address (i.e. select for data transmission)that TS buffer which corresponds to the given address.

Using a counter (74 193) in this experiment as an address registeryou have more freedom to change its content. You can load in a newaddress parallel (from e.g. an array of switches) or you can simplyincrement or decrement its content (i.e. the current address).

By the way, this address register has the same role in thisexperiment as the PROGRAM COUNTER (PC) has in a computer where itscontent becomes incremented after the execution of each instruction orloaded with a new address in the case of JUMP and CALL instructions.

141

EXPERIMENT 20

SHAFT ENCODERS

Objective; To demonstrate how to use digital systems for physicalmeasurements.

Introduction:The most elementary physical observable is the length, or distance,

or displacement. If we learn how to design digital systems to measurethe momentary value of such a variable, then we can measure the value ofany other physical variable, assuming that it lets itself be transformed- with some appropriate device called transducer - to a displacement.

The temperature can be transfored with a bimetal as a transducer, theforce with a spring as the transducer, the electrical current and voltagewith a moving coil meter as a transducer. We shall be in a position tomeasure any physical quantities if we solve the problem of measuring thedisplacement itself digitally.

It is not a narrow-minded objective! Remember: we want to measureeverything digitally. Which means automatically, because if a quantityappears once in a digital form, then it easily lets itself be read - orloaded rather - into a register and into a computer from there. Thus notonly you personally - with your visual, mental, physical and other humanability - but the computer will be the one that can derive consequencesof the measured quantity and can interfere in the process of eventswhenever the measured value of a variable requires that. Of course therequirements will be given always by you, now in the role of a programmeror even as a systems designer - but the dull procedure of monotonousmeasurements, visual readouts, arithmetical comparisons (judgement on thenecessity of intervention) all will be done ceaselessly and tirelessly bythe computer. And we can relax at last. The duty to tranlate thedisplacement into a sequence of digital pulses, is the task of shaftencoders.

ABSOLUTE SHAFT ENCODER

The absolute shaft encoder is a transparent disc with a sequence ofcodes painted on it (Fig. 20.1). One code stretches radially across theconcentric extends predefined tracks and the consecutive ones are shiftedangularly as shown below (here with binary codes on four tracks)

If we apply four optoswitches arranged radially at radiicorresponding to each track, then we can read out the angular position ofthe disc right in digital form (or representation) if the disc isilluminated from behind.

There is, however, an intricate problem you would encounter at oncetrying to use this trivial binary coded disc for real measurements. Youwould notice some striking uncertainties in certain readouts. To explainthat, let us choose that position of the disc when the array ofoptoswitches is showing the binary code 0111. Rotating the discclockwise, the next readout should be 1000. But unfortunately it willnot be, at least not unambiguously, because when the array is crossing

143

14

13

11

10

6 g Fig. 20.1 Shaft encoder

the line which separates the codes 0111 and 1000 almost anything canhappen. If, for example, the optoswitch corresponding to the MSB (mostsignificant bit) is a little bit more sensitive than the rest of them,then it could switch over to 1 earlier than the other ones switch over to0. Hence in this example for a short period of the motion, we can easilyobtain the bit pattern 1111 instead of the expected 1000, i.e. 15 decimalinstead of 8 after the value 7. That would be a serious shortcoming ofour device, which we would not in any case tolerate.

To solve the problem one should use the more tricky GRAY code insteadof the trivial binary one on the disc. In the case of the GRAY codesystem, only a single bit changes the bit pattern proceeding from oneposition in the disc to the next one. Hence the uncertainty can never bemore than +1 position, which is anyway tolerable.

CODEBINARY

0 1 2 3 4 5 6 7 8 9 A B C D E F

1

n\ ^\L_J

GRAY

B2

Fig. 20.2 Binary and Gray code systems

144

The two code systems are shown stretched out into a linear format inthe Fig. 20.2.

Having agreed upon the better suitability of the GRAY code systems,the question remains as to how we should interpret its readings, i.e. howcould we transform its bit patterns to the ones corresponding to thebinary code systems we were used to.

Logic networks implemented by digital gates help again, as nowadays -due to their permissive low prices - in almost everything.

Using a proper network of exclusive - OR (EOR) gates the task iseasily solved as shown in the Fig. 20.2, below the pictorial code systemsreferred. By the way, another network of EOR's is shown on the left sideas well, for the reverse transformation by which one can implement thatlogic algorithm which generates the GRAY code sequences from the binaryrepresentation of the natural numbers.

Experiment1. Wire up the logic network as shown in Fig. 20.2 using two 7486

quad-EOR 1C's and connect it to the outputs of the 8-track GRAY codeencoder. Connect a LED array to the outputs of the EOR gates toindicate the angular position of the shaft encoder in the usualbinary form.

2. Fix a pulley on the shaft and throwing a string over it with someloads at both end simulate the control rod position measurement of anuclear reactor. Keep in mind that the reading of the binary outputswill be carried out with a computer in a later experiment.Notice that the pulley is a transducer which transforms the lineardisplacement of the rod to the angular displacement of the shaftencoder.

3. Find out and build on another transducer which - after some refine-ment perhaps - can be useful in your everyday work.

INCREMENTAL SHAFT ENCODER

An absolute shaft encoder uses many precisely aligned optoswitches -therefore its price is not low enough.

One can more easily afford a so-called incremental shaft encoderwhich includes only one (or two) optoswitches pointed to the single trackof a simpler disc. Along the single track of this simple disc there areequidistant opaque and transparent stripes. Rotating the shaft pulseswill be generated in the optoswitch. Connecting a counter one candigitally follow the rotation of the disc.

But this device is not able to distinguish between the two possibledirections of the rotation. The content of the counter connectedincreases always irrespective of the direction.

To distinguish between the two directions - and control an UP/DOWNcounter accordingly - one needs a second optoswitch shifted along thetrack with a quarter grid length. You can follow on a time diagram theoutputs of the two switches called A and B for the cases of the twodirections:

145

I GR.D II LENGTH I

UP DOWN

t tA B

t tA B

Fig. 20.3 Signal sequency depends on direction of movement

Notice the relevant difference, namely that at the positive goingedge of the signal B, the other signal A is:

HIGH if the grid moves UP LOW if the grid moves DOWN.Hence the logic circuit which can control the UP/DOWN pin of a

bidirectional counter looks like this as shown in Fig. 20.5.

Fig. 20.4 Control of UP/DOWN counter

2. ExperimentUsing the UP/DOWN Counter type 74 193 build and check with an

incremental encoder the following circuit given in Fig. 20.5.

•UP COUNT

74193DOWNCOUNT

C

B

7400

Fig. 20.5 Circuit to experiment with an incremental encoder.

146

PART 6

INTERFACING

EXPERIMENT 21

OUTPUT PORTS

Objective; Familiarization with the design and application ofcomputer output ports.

IntroductionIf we want to use our computer - apart from other chores - as a

controller of various external equipment, first of all an INTERFACE hasto be built from which the wires carrying signals (i.e. bit patterns,e.g. codes for commands) can be led to the equipment to be controlled.

A universal computer has not any specific connector for your allconceivable and unique equipment. However, if it really is a universalcomputer (and not some kind of desk calculator) then it must have atleast one multipin connector through which one can be connected to thesystem bus which is in fact an extension of the pins of themicroprocessor itself.

The interface is a specific logic device to be built by us (now inthe role of a system designer) through which the computer (or rather itssystem bus) can be connected to the specific equipment to be controlled.

The simplest version of an interface is an output port. The outputport is a registrer (usually 8 bit wide) whose inputs are hookedpermanently to the data lines (Data Bus) of the computer and the outputsto the external equipment to be controlled. That is all. Almost.

KLUh-Q.SOU

BUSCONNECTOR

RD

JQRQMRQ

A14A15

GND

CONTROL LINES

ADDRESS BUS

(16)

> a

DATA BUS______| (8)

T

OCTAL LATCHOR FLIP FLOP

•-9-

111

(0

£

DO

Qj QOHVn n *EXTERNAL WORLD

STROBE

Fig. 21.1 System bus of a computer

149

The only complication which needs some circuit design comes when weare going to generate a LOAD (or STROBE) pulse for this register. Thenthe relevant question is: what time or rather at which condition shouldwe load the quickly varying content of the databus into our register.The right answer is: then and only then if the computer executes an OUTinstruction inserted in the code sequence by some purpose.

The full format of an OUT instruction isOUT PORT ADDRESS, DATA

If the processor executes this instruction, then (and only then)does it put out the DATA specified in the instruction on the DATA Bus,the PORT ADDRESS on the ADDRESS Bus and in addition it asserts two of itsdozen control lines. One of them is IORQ(Input/Output Request) by whichit informs the external world that the address currently on the systembus should be interpreted by_ the I/O devices (and not by the memory).The second of them is the WR (Write) line by which it informs theexternal world that onto the DATA Bus the processor enables someinformation (DATA in our example) through its internal tristate buffersand the external device addressed should strobe in that data.

Hence first the simultaneous occurrence of IORQ and WR~ has to bechecked. A simple OR gate (74 LS 32) can be used for this job whoseoutput signal will be called OUT.

Then the PORT ADDRESS (assigned arbitrarily to the given port by us,now in the example is 3) should be decoded to obtain a signal called AS(Address Select).

And at last these two signals OUf and AS* should be combined in an ORgate to generate the necessary STROBE signal. The positive goingtrailing edge of this pulse will finally load the DATA into our octalregister. This register is called an output port because its outputs areaccessible by any external device.

EP r*ölW uj l imil 'sL

CONTROLDATA ADDRESS

OCTAL REGISTER

T - - - - --< r

Fig. 21.2 Connecting a computer with a data register

If you find this address decoding a little bit cumbersome - comparedto the simple task of generating the signal AS in the case of addressmatching - then you are right. But one can simplify this task wheneverthe number of the external devices do not exceed sixteen, i.e. the numberof the separate address lines used for port addressing.

150

In such cases we can assign such addresses to the various ports - inthe binary representation of which only one of the address lines has a 0value while all the others are 1's. The sixteen possible addresses -looking trivial in binary but rather strange in decimal representation -are as follows.

BINARY1111 1111 1111 11101111 1111 1111 11011111 1111 1111 1011

HEXAFFFEFFFDFFFB

DECIMAL655346553365531

0111 1111 1111 1111 7FFF 32767

Notice that sixteen 1's in a binary register amounts to 2 -1. Ifthe j-th position is zero, then we have to subtract its contribution 2^to get the content of the register: (216-1)-2J.

The program which tabulates these specific numbers permitted forport addressing without any decoding circuit is given below.

10 LET20 FOR30 PRINT40 NEXT

ALL1 = 2* 16 - 1J = 0 TO 15J, ALL1 - 2 t JJ

If these are the sixteen possible addresses we agreed upon to beused only for port addressing, the the STROBE generating circuit - andthus the whole output port - becomes much simpler than before, namely

ADDRESS CONTROL

with port address FFFB - 65531 ,06) (10)

Fig. 21.3 Output port

EXPERIMENTS

The interface circuit shown in Fig. 21.3 has to be built using twointegrated circuits only (74 LS 32, 74 LS 374) and 12 wiresaltogether (including the common ground) to implement an output porthere with port address 65531.Check the functioning of this port by connecting a LED array to theoutput pins PQ-PJ and running the following simple BASIC program.10 LET PORT ADDRESS = 65531 3020 INPUT "A NUMBER PLEASE"; DATA 40

OUT PORT ADDRESS, DATAGOTO 20

151

3. Change the first line of this program to read10 LET PORT ADDRESS = 65527

and run again. There will be no effect to your input activity onthe external device (now LED's), because the current PORT ADDRESS(=65527) does not match with the address decoded by the interface(65531).

Change the wire from A£ to Aß and your system should output theDATA again.

4. Connect to P0 the control input of a semiconductor relay (IR 2425)and insert a 220V ac lamp in its output circuit. Run the followingprogram.

10 LET PA = 6552715 LET D = 020 LET D = D + 130 OUT PA, D35 PAUSE 2540 GOTO 20

5. Leave the previous HW (hardware) setup intact and program a lightscheduler (at Tl ON, at T2 OFF, at T3 ON etc).

6. Change the lamp with an ac motor or with any applicances around youto schedule its function.

7. Connect to the output pins PO-P3 of the output port the inputs of anULN 2003 A Darlington array, and drive the 4 coils of a steppingmotor with the following program.

10 LET PA = 6552720 FOR J = 0 TO 325 LET D = 2 t J30 OUT PA, D35 NEXT J40 GOTO 20

Then make the following change

20 FOR J = 3 TO 0 STEP -1

Let both versions of the program run, observe the direction of therotation.

8. Write a BASIC program to drive the stepping motor with N steps inany direction.

9. Get rid of the motor and Darlington array, and use the output portto enable and disable an external counter built by TIL 306 1C1s asshown in Fig. 21.4.

152

OUTPUT PORT•4

74 LS 374

12

PULSES TO BE. COUNTE 3

TIL 306 COUHTEiyklSPLAY

\

/ 1u1M«1

15 7

1

nLJ

'i«M15

Fig. 21.4 Driving gin external counter through an output port

Run the following program to enable the counter for T sec10 LET PA = 6552720 OUT PA, 030 INPUT "TIME OF MEASUREMENT"; T40 OUT PA, 150 PAUSE 50 * T60 OUT PA, 070 PRINT "END OF COUNTING"80 GOTO 30

153

EXPERIMENT 22

INPUT PORTS

Objective; Familiarization with the design and application ofcomputer input ports.

IntroductionIf we want to use our computer - besides other chores - to test the

state of some external equipment to decide on the necessity of some kindof interference via the output ports, or to read the result of somemeasurements for prompt or later uses (data collection, data logging)then we need input ports.

The input port is a tristate buffer (usually 8 bit wide) whoseoutputs are connected permanently to the data bus of the computer. Theinput lines of this buffer are connected to the external devices to sensethere the current binary levels. These external binary levels may notreach permanently the databus, therefore the tristate buffer is disabled.

It should be enabled only for that moment when the processorexecutes an IN instruction expecting the external data to appear on thedatabus which it will read at the same time from this bus.

At that specific time - or to be more correct, in that specificcycle of the execution of the IN instruction - the PORT ADDRESS will besent on the ADDRESS BUS and two of the control lines will be asserted.One of them is IOR<J (Input/Output Request) informing the external worldthat the current address on the system is for a specific I/O device (andnot for the selection of a specific memory cell). The other one is theRD (Read) line informing the external world that from the given addressthe processor is going to read the data supplied.

Hence the logic circuit needed is very similar to that one used inthe case of the output port (Fig. 22.1). The difference is that now atristate buffer (and not a register) is activated and that instead of theWR line now the RD line is combined into the similar decoding logic.

D A T AADDRESS CONTROL

5V

DIR

18 17 16 15 14 13 12 11

TRISTATE BUFFER

74 US 245

If5 6 7 8

aa

P7 P6 P5 P4 P3 P2 P1 P0

EXTERNAL WORLD

INPUT PORT

with port address FFFB - 655310«) do)

Fig. 22.1 Input port

155

EXPERIMENTS

1. Build the input port shown above the AS being connected to A2.Hence the port address is now PA = (216 - 1) - 22 = 65533.

2. Connect a switch array to the 8 input points of the port and run thefollowing BASIC program changing the switch pattern.

10 LET PA =2* 16 - 1 - 2 * 220 COSUB 10030 GOTO 20

100 LET D = IN PA110 PRINT D120 RETURN

3. Modify the previous program to get a new output on the screen onlyif a change occurred in the input. The new program lines needed:

15 LET DP = 0 : REM DP = DATA PREVIOUSLY READ105 IF D = DP THEN GOTO 100115 LET DP = D

4. Connect the output points of a shaft encoder to the input port andrun the previous program to follow the rotation of the shaft.Using a pulley and string make measurements of displacement bycomputer.

156

EXPERIMENT H

MEASUREMENT OF PHYSICAL QUANTITIES BY COMPUTER

Objective: Demonstrate how to interface an ADC to a computer

IntroductionTo measure the value of an analog physical quantity one has to

design a proper transducer which transforms this quantity to aproportional voltage level. The transformation should not necessarily belinear because doing the measurements by computer its calculating abilitymakes feasible any kind of correction.

Having the analog voltage level one can use an ADC (Analog DigitalConverter) to get the digital binary representation which can be read bya computer.

Most of the monolithic ADC's produced these days are designed foruse with microcomputers. This means, that they have built in tri statebuffers, hence one can connect their outputs directly to the data bus.These buffers become enabled if the ADC gets a LOW pulse from thecomputer.

The 8bit ADC type ADC 0801 with a conversion time of 100 ,us hasdifferential inputs so they can be used easily with measuring bridgesallowing higher accuracies

CONTROL

O

MEASURING BRIDGE

ANALOG PORT

with port address FFFB ~ 65531(18) (10)

Fig. H.I Analog port

157

EXPERIMENT

1. Build the analog interface shown in Fig. H.I.2. Rotating the potmeter R^ run the following program to make a ploton the screen and log the data

10 LET PA = 2 * 1 6 - l - 2 t 220 DIM M(IOO)30 FOR j = 1 TO 10040 OUT PA, 050 LET D = IN PA60 PLOT 2 * j, 070 DRAW 0, D * 150/25580 LET M (j) = D90 NEXT j

3. Append the next few lines to the previous programme to query yoursimple database or familiarize with data retrieval.

100 INPUT "WHICH CHANNEL, PLEASE?"; c110 PLOT 2 x c, 160120 DRAW INK 2; 0,6130 PRINT AT 0,5; PAPER 6; INK 0; c, M(c)150 GOTO 100

4. Replace R^ with a termistor, heat it with a match then let it coolduring the run of the previous program.If the range of your instrument is not acceptable then adjustpotmeter RQ. The voltage at point 9 should be half of the fullscale voltage requested.

158

EXPERIMENT K

COMPUTER CONTROL OF NUCLEAR MEASUREMENT

Objective: Automate with a computer routine or dangerous measurements.

IntroductionIn a typical nuclear measurement one makes repeated readings of

radiation intensity, i.e. lets one or more counters count for a certain timeinterval, then changes something (sample holder, position of a detector)with the help of a motor and lastly plots and evaluates the collected data.

With the sufficient knowledge acquired up til now, we can easily buildthe interface required for this project. It is shown in Fig. K.I.

D A T A A D O R E S S C O N T R O L

18 3 4 17 14 7 8 13

OCTAL INPUTTRISTATE BUFFER

OCTAL OUTPUT REGISTER

74 LS 374

FROM DETECTOR

ENABLE COUNTING

, STEPPINGI MOTOR

PULSES TO BE COUNTED

CONTROL OF NUCLEAR MEASUREMENTwith port address FFFB —65531

(16) (10)

Fig. K.I Interface for a nuclear experiment

Experiments1. Wire up the circuit shown with WIRE WRAP tool on a EURO BE (Bread Board)

159

2. Check the counters first connecting them to a detector and running theprogram below.

10 INPUT "MEASURING TIME (in sec)"; T20 LET PA = 2 t 16 - 1-30 DIM D(20)40 FOR j = 1 TO 2050 OUT PA, 2 t 660 OUT PA, 2 t 770 PAUSE T x 5080 OUT PA, 090 LET D(j) = IN PA100 PRINT j, D(j)110 NEXT j

REM Clear CountersREM Enable countersREM Wait for. T secREM Disable CountersREM Store dataREM Print result

3. Check if you can rotate the motor by ALPHA degrees CW or CCW running theprogram below.

200 DIM M(4) :REM Initialize motor210 FOR k = 1 TO 4 :REM Load in the stepping sequence220 LET M(k) = 2*(k-l) : REM 1,2,4,8 will be stored in matrix M.230 NEXT k

240 LET i = 1250 LET d = 1 :REM End of initialization (d = direction

of motor)300 INPUT "HOW MANY DEGREES?"; ALPHA

310 LET d «• ALPHA/AB S ALPHA320 LET S = ABS (ALPHA/15)

330 FOR j = 1 to s340 GOSUB 500 :REM Calls for one step350 NEXT j360 GOTO 300

500 LET i = i+d : REM Make one step510 IF i>4 THEN LET i = 1520 IF i<l THEN LET i = 4530 OUT PA, M(i)540 RETURN

4. Combine the two programs properly to make a complete measurement controlprogram with a nice colour plot at last.One hint you would never find out alone: when you have the motor

connected then copying lines 50, 60 and 80 into the final version you alwayshave to add the current value of M(i) to the data output as in

50 OUT PA, 2 t 6 + M(i)

A last hint: by changing the value of d by d = -1 x d you can reversethe motion of the motor to drive it to the initial position after acomplete run.Happy debugging.

160

PART?SPECIAL PROJECTS

SPECIAL PROJECT I

GEIGER MUELLER RATEMETER

Objective; To assemble and test a simple ratemeter to be used witha Geiger Huiler counter.

IntroductionThe mean count rate of pulses with random distribution, which takes

place in the case of signals coming from nuclear radiation detectors, canbe measured with integrated type ratemeters, displaying the count rate byanalog representation.

The circuit (see Fig. I.I) is composed of a simple high voltagepower supply for biasing the GM counter and an integrator circuit todevelop a voltage proportional to the count rate.

The high voltage power supply is similar to the one described in thePower Supply series of this manual.

The ratemeter works as follows: each time the GM delivers a pulse,the one-shot circuit is triggered and produces a pulse having astandardized width (approx. 780 us) and 15V amplitude. A current pulseis injected into the operational amplifier feedbacked as an integratorcircuit. In equilibrium state, that is to say at constant count rate, aconstant voltage is developed at the output of the operationalamplifier. (The feedback resistor RF can be selected as Rj_, R2 orR3.)

V0 = i . RF (1)

Being i the current circulating through RF which has to be equalto the average injected current iav

'av = IT ' *W « C (2>4

where: V is the height of the pulse (15V)tw the width of the pulse (780 us)r the count rate.

From (1) and (2) results

V RF (3)0 -v • fcw • R; •rObserve that C^ does not appear in the expression of V0 but itsvalue has to be such that the time constant RpC^ is much greater than

the inverse of the count rate 1/rIn our case three different values of RF can be selected with a

switch in order to get three different scales:V. = 10V at 1000 pps then R_ = 8K2U J?VQ = 10V at 100 pps RF = 82K

and Vrt = 10V at 10 pps R_ = 820K0 r

163

o>-PULiO)

<0

•fHO)

(VA-p

Ll60cd

•i-i•O•P•i-tao•HO

60•rHta

164

These values are obtained considering that according to equation (3)

v . tw10 x 10

1r

R_ =I:

15 x 780 10

8,5 108 . -

-6lr

An analog meter indicates the count rate by measuring theoperational amplifier output voltage.

Assembling instructionsThe circuit diagram for the 6M ratemeter is given in Fig. I.I, the

suggested components layout is seen in Fig. 1.2.

IC3

C7

IC1

dJR18

ID IC2

LM317

V QT

l——IC10

TR1

Fig. 1.2 Component layout for the Geiger Müller Ratemeter

A. RatemeterMount on the monostable and operational amplifier and relatedcomponents.Using an external pulse generator apply negative pulsesthrough Cy.

- Check that at the monostable output the pulses produced have awidth of 780 ps and that the amplitude is 15V.

165

Check that the output voltage changes with frequency.Adjust R]^ to get the proper full scale indication for eachrange.

B. High Volta&e Supply- Mount on the printed circuit board the oscillator, flip-flop,

transistors Q^ and 0,2, transformer and voltage regulator.

- Check the frequency of oscillation, and that transistors Q^and Q2 reaches saturation.

- Check that the voltage and centre tap of the transformer can beadjusted by means of R-j.Mount the rectifiers and the high voltage components.

Measure the range of high voltage adjusting R7.

C. Geiger Müller CounterConnect the GM counter to the printed circuit board (don'tforget to ground the cathode of the counter).Observe the pulse shape at the input of the monostable circuit.Observe the output voltage indication for different intensity ofradiation.

166

SPECIAL PROJECT 11

SINGLE CHANNEL ANALYSER

Objective; Single channel analyser (SCA) is assembled using theprefabricated PCB and tested. Signal forms have to be measured and drawn inthe real voltage and time scale to complete the documentation.

Introduction:The SCA is a device providing the output pulse of the constant

amplitude and duration if the input accepts the pulse greater thansmaller than V} + V2.

and

The described single channel operation can be achieved by observinginput pulses with two discriminators, set at V^ and V^ + V2. If theV^ is exceeded by the input pulse then one shot providing the out- putpulse is activated. If V^ and V^ + V2 are both exceeded theactivation of the one shot is prohibited. The voltage V-± is calledusually the level, and voltage V2 is referred to as the channel width.

For more detailed operation of the SCA, Fig. II. 1 showing the SCA blockdiagram and Fig. II. 2 showing the signal forms should be used.

PI P2V1 AM 1

?

IN

TVOLTAGESOURCE

.+ DIFFER.AMPLIF.

lvfl.

V

J

2

•

Ur'r't HLEVELDISCRIM

ZEROLEVELDISCRIM

FLIP FLOP

ONE SHOT1

ONE SHOT2

OUT

Fig. II.1 SCA block diagram

Instead of comparing the input signal Vj with Vlt the voltage V^is subtracted from the input signal in the differential amplifier. Theresulting voltage is compared with zero in the ZERO LEVEL DISCRIMINATOR.This comparison of the resulting voltage is made in the UPPER LEVELDISCRIMINATOR set at V2. This gives answers if the incoming pulse isgreater than V^ + V2.

With respect to the height of the input pulses three different caseswill be considered.

In the first case the input pulse (Fig. II.2a) is smaller than V^.The resulting voltage does not exceed zero (Fig. II.2b). Neither the ZEROLEVEL DISCRIMINATOR nor the UPPER LEVEL DISCRIMINATOR set at V2 areactivated.

167

input pulses

diferential amplifier

zero level discrim. | | |1upper level discriminator !

one shot • n;

one shot 1trig, of one shot 2 !

i i

R S f f - Q

one shot

output

1 1:i ii2

t

n[1

n

t)Fig. II.2 Signal Forms

In the second case the resulting voltage exceeds zero but does notexceed V2 level of the upper level discriminator. The ZERO LEVELDISCRIMINATOR is activated (Fig. II,2c). By 1 -0 transition of the zerolevel discriminator output pulse (Fig. II.2c) the ONE SHOT 1 is triggered(Fig. 2e). Its positive going pulse is transmitted through 2-input AND gate(Fig. 2i) because the Q output of the RS flip-flop is 1 (Fig. II.2g).Finally, by 1 0 transition of the negative going ONE SHOT 1 output pulse(Fig. II2f) the ONE SHOT 2 is activated (Fig. II.2g). However, its positivegoing pulse intended for the RS flip-flop reset is meaningless.

In the third case the input pulse is greater than Vj_+V2. Afterbeing shifted down in the DIFFERENTIAL AMPLIFIER for Vx the pulseampllitude is still exceeding the V2 level. Therefore both discriminatorsare activated (Fig. II.2c and II.2d). First, by the positive going pulsefrom the UPPER LEVEL DISCRIMINATOR (Fig. II.2d) the RS flip-flop is set,resulting in Q = 0 state (Fig. II.2g). Then, as in the previous case, theONE SHOT 1 is triggered (Fig. II.2e) by the 1 0 transition of the ZEROLEVEL DISCRIMINATOR (Fig. II.2c). The pulse from the ONE SHOT 1 is stoppedin AND gate due to Q = 1 state at one input of AND gate. By the end of theONE SHOT 1 pulse the ONE SHOT 2 is triggered (Fig. II.2h). The producedpulse resets the RS flip-flop (Q = 1; Fig. Ilg).

168

The detailed SCA scheme is shown in Fig. II.3.

+12r,IC5

S

1/2 IC5

Fig. II.3 Scheme of SCA

The SCA input stage (ICI) is a differential amplifier with differentinput sensitivities. To the inverting input with the amplification factor 1the reference voltage V^ from potentiometer PI is connected. This voltagecan vary from 50 mV to 5V. The smallest voltage 50 mV is determined byresistor R6, and the biggest voltage 5V is the voltage of the voltage sourcewith IC7. By the voltage drop across R6 the threshold voltage of 100 mV forinput pulses is introduced. Through two RC filters R5, C4 and R7, C5voltages Vi and V2 are decoupled.

Pulses to be analysed are applied to the noninverting input of ICI.They are attenuated by a factor of 2 determined by the proper ratio ofresistors Rl, R2, R3 and R4; and shifted down for V^. By adjusting thecapacitor C3 made of two twisted wires the optimal pulse response of theinput stage is achieved. For this purpose rectangular input test pulses ofa few us have to be attached to the input.

Through the described attenuation the input pulses normally swingingbetween 10 an - 10 V are reduced to + 5V in height. This is the normaloperating range for fast differential comparators IC2 and IC3(SN 72710). In order to avoid interference, each 710 is supplied with itsown Rd filter at supply lines.

The negative edge triggered ONE SHOT 1 accepting signals from IC2 isformed from 2 NAND gates of 7AL200. Capacitor CIO and resistor R16 arechosen to provide an output pulse of the duration of 1 us. As the outputpulse at pin 8, IC4 is negative going, an inverter is added.

In the positive edge triggered ONE SHOT 2, two NOR gates from 74L201are utilised and the DC voltage at input pins 11, 12IC5 is reduced to 2.5Vby the resistor dividing network R17 and R18. The reliable triggering bythe negative going pulses of the amplitude 3.5V obtained by the

169

Suggested Components

ClC2C3C4C5C6C7C8C9CIOCllC12C13C1ACIS

PI Ik,P2 Ik,

P3 10

Tr 1,Dl ZR

1C 1,1C 2,1C 4,1C 5

lOOnlOOntwisted wires0.22 u0.22 u100 n100 n100 n100 n4.7n1 n10 p47p0.22u0.22 u

ten turnsten turnsk, trim pot

Tr 2 BC 2124.71C 7 LF 3561C 3 SN 527101C 6 SN 74LSOO

SN 74LS02

RlR2R3R4R5R6R7R8R9RIORllR12R13R14R15R16R17R18R19R20R21R22R23R24

3kIk56k56k33 R15 R33 R470 R100 k100 R100 R470 R100 k100 R100 R360 R5kl5klIk556 k100 k6k86k815 k

differentiation of l 0 transition of pulses from the previous stage, isassured in this way.

In order to make the operation of SCA independent of the supply voltagewhich may vary from crate to crate the internal reference voltage is used.The 4.7V reference voltage provided by ZR 4.7 (Dl) is increased to 5 V inthe noninverting amplifier with IC7 by using the proper R 20/P3 resistanceratio. Transistor Trl is added to increase the current output capability ofthe voltage source.

Transistor Tr 2 connected as the emitter follower provides -5V for 710drive.

Equipment1. Assemble the single channel analyser board, according to the wiring

diagram (Fig. II.3). The component layout diagram (Fig. II.4) will beuseful.

2. Apply the pulses from a pulse generator, and observe the shape and thetiming of the signals at the testing point a - i.

3. Try different shapes of the input pulse and record the response of thesingle channel analyzer,

170

r -iOUT IN

15 CZ33K r"""»1K i——l

0.1uO>0.1 ud>

pi P2

o o o c c c ) oM- p

56K

6K8CZ3 10°K

_6K8JZZ> O••••—*• nr^mBC212

15KCZ3

0.22p

Up ,22u10K

470 ——

100 0.1p 100 470

A

U%/100K

0.1p______ ^0.22p ( ______

(j f| | SN74LSOO ^ (j }[SN71LS02|{SN74LSQQ SN74LSOO

°'22

5K15K1

_iFig. II.4 SCA component layout; with test points (a ,b,c . . . )

4. Complete diagram in Fig. II.3 by inserting the observed pulse shapes atthe appropriate points.

171

SPECIAL PROJECT III

SCALER-TIMER

Objective; To design, construct and test a simple sealer-timer, usinga contemporary approach.

Introduction;This sealer is developed as a part of an integral measuring system for

low cost scintillation counting. To describe briefly it counts and displaysthe input pulses up to predetermined time which is set by present switches.

It has six decade cascaded counters which can accept up to 1 MHz countrate and displays current count with seven segment LED displays.

Accurate time base is provided by quartz crystal.Start, stop buttons allows the user to interact with the counting

process at any time.The input is prepared to accept positive TTL logic level pulses.At power-up module is ret automatically.The PCB401-2 board is designed to interface sealer timer (PCB401-1) to

the printer with RS 232 interface standard.Technical Specifications;Input : - front panel BNC connector

- DC coupled- 50 input impedance (if Rl is inserted)- accepts positive TTL (Low + 0,8v)- logic level pulses (High + 2v>- maximum ± 50 V- minimum pulse width 25 ns

Start : - push button to activate the accumulation: - push button to terminate the accumulation: - two digit thumbwheel switches to preset the time- X.10Y (seconds)- mimimum presetable time interval is one second

Mode : - toggle switch to select single or recyling of thepreset counting operation

Display : - six digits max. lO+^-l countsPower consumption: : - min. 15V, max. 80mAPhysical sizes : - double with Eurocrate modulePrinter out : - frontpanel CANON 25 pin connector.Functional Circuit Description;As indicated in the block diagram Fig. III.l, the module has six main

functional blocks. A time base generator, control logic, time, counter,input shaper and finally as a second board (PCB401-2) an interface toprinter.

173

STOP S3

I N

POINTER.

JHTERFRCÊ

Fig. III.l Sealer-timer block diagram

021M* I

-IWFC9 T

j« t»a.< i ^ \ , iVlH"«>

( C6l5_r\ o,<>fnH5V'|^jLrSW T«

STOP

a_ ,>"saRfcya„\ b

1 —————— O O ————— -T _

xiow -l- /Si. A<Minv6

5

p6

«K.JRÎO

rrr

PßlVJT

••-ko s sz^. ' 4013re R a

j-

ia 5

34%

-"•U TK,D S

24,tfc<04* a

R

« 19 1

a . '^«i H

.TCix

Fig. III.2 Control logic and time base generator

Quartz crystal drive Zl is an oscillator and a divider 1C 32,768 kHzoscillator frequency is divided down to 2 Hz and made available at pin 3.To obtain 1 Hz time base Z3 is employed as 1: 2 divider.

Control logic (see Fig. III.2) consists of a sequencer, power up resetcircuitry and flip-flops to control the process. The sequencer is builtaround the Z2 (4017 decade counter 1C) which is responsible for producingsequences. The control logic circuitry is reset either at power up orpressing the stop button. That initializes the 22, Z3 and Z4 flip-flops andthen the sequencer is prepared to start. If the start push-button ismomentarily pressed, Z3 changes a state and enables the 22 to advance withpulses coming from the time base generator Zl/1. Z2.2 sends a pulse toreset the timer 1C (Z7) to load its registers with the value fo the frontpanel preset time switches. Then Z2/7 activates Z4/11 FF. The output ofZ4.12 goes low to inhibit pulses reaching Z2 to advance. In the meantimepreparing the second half of Z4 to be set with the TCLK pulse tosynchronize. The positive going edge of TCLK sets the Z4/3. The outputZ4/1 switches to high. This reaches to timer (Z7) and counter Z6 (seeFig. III.3) after a short delay of R19 and C8 and inversion of Z5 as anenable command (INH).

When the preset time is passed, the timer (27) sends back an EQUALpulse to clear two Z4 FF's. Then the sequencer continues to advance. Thesequencer Z2/10 produces a PRINT pulse to printer interface (PCB401-2).Then if the EEC-MAN switch (SI) is closed, reset is activated via Z5 toreturn the sequencer 22 to the initial state and reset of Z3 to be ready forthe next START.

If SI is open, this means RECYCLE. Then Z2 advances until step "9" andreturn to "0" and the above-mentioned cycle repeats.

Preset time switch values are transferred to internal comparisonregisters of the timer Z7 at the beginning of every cycle. The decimalthumbwheel switch selects the power (O Y S) and the BCD thuumbwheelselects the multiplication factor (O X 9).

Z7 counts up with TCLK to keep the elapsed time of accumulation andgenerates EQUAL pulse to indicate preset time is reached.

The counter Z6 receives pulses via Tl and the pulse shaper from the INBNC and displays the current count. T2...T7 are digit driver transistors.Z6 supplies output for the printer interface.

The printer interface board PCB401-2 is subject to future developmentto have a print-out of the sealer-timer unit.

Assembling Instructions;1. Check the printed board PCB401-1 to see whether any shorts exist due to

poor etching of the board during PCB process.2. Insert the jumpers as shown in Fig. III.4.3. Insert all the components except 1C's (be careful: the pin

configuration of Tl 2N3904 is different).

4. With a grounded soldering iron, place the 1C*s properly and then solderthem.

176

2>x\NW8T>a 03

Fig. III.3 Shaper, timer and counter

00

ij'tfejat^î-Aa JV-£«--V-jTrhM. & T«-• rt rt ws

*2-U U1'?o ^9 a"1 * ^ MW

«12»

Fig. III.4 Component layout

S. Connect the cables to the displays and front panel switches (seeFig III.5).

n nû

ri/./

nu

nu

nû

l l l l I

I -to ?c6Uoi_iX

Xe

Fig. III. 5Sealer-Timer 401 display board

6. Do not forget to connect a cable between the wiper of the decimalthumbwheel switch to the wiper of the BCD thumbwheel switch.The pulse identification chart (Fig. III.6) will be useful.

start button pressed

Z2/3 1Ready to count

RESET

LOAD REG(Z2/4)

ACCUMULATE(Z2/7)

PRINT(Z2/10)

INH

EQUAL

TCLK

n 12 V

1

n

1

n , ,

1

n

1

0

1

0 . .....

1

0

n

timer *counter

/I I

counts \,

•\\ timer sends a p\ ^- —— ~~ to indicate ores)if time is reached

Isr

Pig. III.6 Pulse identification chart

179

S C A L E R / T I M E R

o

siRT

S

OA-U1

RECYLE

MANUAt-O

ON^

OOFFSINGLE

TIME PRESET

0

ï op

oINJl

X.10Y

r^ o

PROG.

>

PR1„

ER

O,--\

**J0

Fig. III.7 Front plate inscriptions

7. If you wish to finish your construction, so that the timer-sealer canbe plugged into a EURO-crate, you can prepare the front platesaccording to Figs. III.7 and III. 8.

Testing1. Connect + 15V supply to the board.2. Connect an oscillator to IN BNC, adjust it to 1 kHz. Set the preset

switches to 1.0 = 1 second.3. Then RECYCLE-MANUAL switch to RECYCLE position.4. Then the display should count up, stop momentarily and display 1000

then recycle. This is a full test off the module.

Miscellaneous Notes:1. At the input of the sealer the resistor Rl was shown with dotted

lines. Inserting Rl depends on the user's demands.2. After inserting 7 segment displays and soldering the cables to fix the

display to the front panel. First glue the red transparent filterpiece. Then glue the holder pieces (made out of wood or plastic) tothe displayboard. Finally glue them all on to the front panel.

3. Do not forget to fix the back side connector with screws.

180

f*v

0te

vc

r-f

^

_

JLTCN

JL

î

u

V

5ri33

UK a

5,3J — 15

li1

1

. «>3 .

;-13 —

i

,_..^

. 1t

03

0

01 1

1iii

06,51Y^L>

- - -«

-"11

06,503 ._ /T\/y «

i

06,5

©'I

3--06,5

—— 22,6 ———

r 010"\x

t~ ~

— 17 _

— —— 24

33

o

1

1

^ -

ii- - -

i

-10,6-

03

ïO

. 9

03

i l

03,5

l

—

,5

?

-8 -

13,5-

3 s

ines

Fig. III.8 Front plate drilling plan

4. Cable connections between PCB 401-1 to Decimal thumbwheel switch isindicated on the board as 1, 2, 3, 4, 5, 6. They should be connectedrespectively to 0, 1, 2, 3, 4, 5. terminals of the decomal thumbwheelswitch.

181

SPECIAL PROJECT IV

MICROCOMPUTER EXTENSION; HP-SMP BUS CONVERTER

Obiactive: To demonstrate the design, construction and operation of aconverter providing connection between the internal bus of a microprocessorsystem (Hewlett-Packard 5036A) and a SMP bus (Siemens).

IntroductionThe HP-SMP converter has been designed for the Hewlett Packard

microprocessor lab extension. The conversion to the widely used SMP busfrom Siemens is made to provide flexibility for using SMP cards. Theconverter provides four bus connectors for additional SMP cards like memoryextension and serial connection. It can also serve as a motherboard for astandard SMP microcomputer i.e. replacing the HP kit by a CPU card fromSiemens.

The lists of signals available on the HP-bus and the SMP bus are givenin Table IV.1.

The compatible signals on the SMP bus are:*RESET and ÏNTRBoth the Reset and the Interrupt signal are active high on the HP-bus,so they are inverted and made active low for the SMP-bus.

*MMIOThe memory mapped I/0(MMIO) signal is generated by a four input NANDgate using address bits 12 - 15 as input. It is then provided to theSMP bus through a buffer.*MEMRD, MEMW, IOWR, IORDThejse signals are generated for the SMP bus using the 8085 signalsIQ/M, NWR and NRD available on the HP-bus. When IO/M is low MEMRD orMEMWR is generated depending on whether NRD or NWR IS LOWRESPECTIVELY. Similarly for IO/M high IORD or IOWR is generateddepending on whether NRD or NWR is low respectively.«ADDRESS LinesThe address lines AO - A15 are buffered on the bus converter so thatthe HP bus is not loaded by the connected circuits.

*DATA LinesThe data lines are connected through an 8 bit bus transceiver. Thedirection of the data transfer is governed by the signal NRD. NRD lowmeans data flow from the SMP bus to the HP bus and for NRD high fromthe HP to the SMP bus.

*ENABLEThe ENABLE signal is active low and is generated by a NOR gate on theaddress bits 14 and 15. The memory extension works from HEX address

This experiment was prepared by Dr. 6. Brandenburg and Mr. A. Shaftab, atKFA Jiilich GmbH; the work was sponsored by the Government of the FRG.

183

P1B

HP-BUS

B READY

C RESIN

D *2TTLE HOLD

J NINTAK INTR

M RESETOUT

P HLOAW SOD

Buffer

ROYIN

RESIN

CLOCKOUTHOLDÏNTÂ

1STRlSTT

HLDA

SOD

12 c-Mp-i

— — SMPaL

-inrâ'7 . <"MPi

—— SMPa19 -IIP

15 SMPa13 SMPr

P1B

R NRO

S IO/M

T NWR

Decoder

MEMRD

MEMWR

IÜRDIOWR

—— S.SMPa10 -Mpbnrd

30 SMPc30 ,..„

M'\ra

P1A (1-15) ADDRESS SMP-BUS

P2B

NRD

(1-B)<fDATA )' r

DIRTX/RXBuffer

1

PIA

13ENABLE

MMÏB

SMP-BUS

Fig. IV.1 HP-SMP converter block diagram

4000 to FFFF and the enable signal is low in this range. However thememory mapped I/O is only available for the addresses FOOO to FFFF.

*RST 5.5The RST 5.5 is a signal used to initiate the serial I/O (seedescription of 8085 for detail). On the SMP bus RST 5.5 is active lowso it is inverted and fed to the HP bus. The RST 5.5 is used withwired And function on the standard SMP bus connector hence at the inputof the inverter a pullup resistor is connected.

*PowerThe jumper pins are provided on the bus converter to connect +5V, +12Vor 15V power from an external supply. When the +5V supply is to beprovided from the HP kit the jumper J^ has to be inserted. The HPkit power supply can supply a maximum of 1.75 A. The HP kit drawsnearly 600 mA and the bus board draws about 226 mA. Hence thecurrent-drawn by additional cards on the bus converter must not exceed1 A.

184

U D C : B K 3B K R N D Y 8 < C O - 2

F I L E : B0221 D O B : 001

n

5

n

sn

Lg7 lcmC2G

-< pa I- n

L2U

C2E]IM ianQJGnz:

n

Si

n

sn

s

n

n

g

n

ŒI3

CED

aoamjm_icnnŒ5H

n

n

ŒZDrr?~i[QD

10in

HHEB ^__

11 | H1A

-In* H1B

PIAP1B

25000 Fig. IV.2 HP-SMP bus: components arrangement on the board

ooo\

HP-BUSP1B

READY

RESET IN

SMP-BUSi

CLKOUT

-15V m-5V 12

•———Bl

HOLD

NINTA

INTRRSTS.5

RESET OUT

SIL

HLDA Vcc -I

NRO

10/M

NWR

SOD

HP-BUSP2A

DO01

03

05

07

LS162

U8

LS323

Aus U7

JL,

U8 AVcc

LS245

U10

DIR EN1

-Vcc

LS165

U8

Vcc.

Fig. IV.3 Converter circuit diagram 1

Reset

HEMRDRESINHEHW

ROYIN

OBOHLDADB1HDTPOB2ISTDB3

DB<.IRTÄ

.DBS

DBt

DB7

ÏOW

-«10

-•16

-«20

-•22

-«24

126

-•28

• 30•»32

SNMMS

00-o

»jws LSI?i« ————— LC>2 — i ——

"I '\^^ T

3« ——————————————— £>* ———— j ———————UTO ,

^ * L^SI —————————————— MS^ ———— 4 ———————

U1 "61 ——————————— £>2 ———————— 1 ———————

7B ________ Lj>J ——— —————U2 ^

t • ———————— ^^ —————— —————

9> ———————————— LfSi ——— —————U2 "

n m ————— ü- ^ ————— ——— i

11 • —————————— MV ——— —— iU2 *^

« • ——————————— *- ^ ———————— T—l _,1

13« ———— • —————————— Lf>^— 'U3 *^ ' ——

H • ———— — i ———— C>-i ————— l

15 • ———— — -* —————— 4^ ———— ———————U3 »^

-Î-XLS20 U3-— 1,6 JV«

1— --i- P 9 V^ t

1 f3[J»i —— , Vcc

S ** K

f»

AttMAUA1AKA2AB

A3

A4

AS

Ai

A7

AI

SliLA?

AH

AH

ONO.12V

§

f

»

S

.

«v i,•-•Nomenclature

jH Symbol U indicates 7<.hundred series Ic's

—— 9 Symbol Vcc indicates .5V—— »T

M.^^^^^^^

__^-^«

^_^

"""""wfl^^^^^

?°-«13L ^* Ppwtr Ccfvwcfiwic

•* J1 Close« Pow«r from HP-Bus— €1 J1 OH" Ext»rn»t Powtr

• 17 P3 GNO Externat— • P^ »SV

• n PS -5V-Hi Pi »15V

•21 P7 -1SV—m Pi »«v_«23 M -«V

B7S »ttV -12V »«V -SV -1SV- • f d l » d B » •

• Z7 Jn J_cio .je« Je» j£?* T*i »lüu "T»i *Tîiu »TVi•» 1 1 i 1 1

-£31

r**V [lOn Jlpn [lOn |lOn J^

"ÏÏ1 "ÏÏ2 "JC3 let "ÏÏ.7u

GND B-i— 1 1 l l"

• Fig. IV. 4 Converter circuit diagram 2^

TABLE IV.l

A. SMP BUS CONNECTOR PIN ASSIGNMENT

Pin No.

1234567891011121314151617181920212223242526272829303132

ROW A

-15V-5VDACK3LK85DHASTBRESETALEHEHRRESINMEMWDREQ3RDYINBUSENDBODACK2DB1DREQ2DB2INTDB3

DREQODB4INTADBSCAENDB6CADSTBDB7EOFIOW

+15V+5V

ROW C

-12VM(GND)OSCMHIOA12AOA13AlA14A2A15A3SODA4

DACK1A5

DREQ1A6

DACKOA7——A8

RST5 . 5A9

RST6 . 5A10RST7 . 5AllTRAPIORM(GND)+12V

188

B. HP BUS CONNECTOR PIN ASSIGNMENT

PIAPin No. Signal

PIBPin No. Signal

12345678910111213141516171819202122

AOAlA2A3A4A5A6A7A8A9A10AllA12A13A14A15——————————

ABCDEFHJKLHNPRSTUVWXYZ

ALEREADYRESET INCLKOUTHOLDSISO

NINTAINTR

RST 5.5RESET OUT

SIDHLDANRD10/NMNWRNALEVASODSTEP+5VGND

"——" indicates free pins

189

C. HP BUS CONNECTOR PIN ASSIGNMENT

P2A P2BPin No. Signal Pin No. Signal

12345678910111213141516171819202122

DODlD2D3D4D5D6D7OUTOOUT1OÜT2OUT3OUT4OUT5OUT6OUT7———————+5VGND

ABCDEFHJKLHNPRSTUVWXYZ

————————

————

INOINIIN2INSINAINSIN6IN7——___——

+5VGND

'——" indicates free pins

190

The signals READY, RESETIN, 02TTL, HOLD, NINTA, RESETOUT, HLDA, SOD,are identical on the two busses so they are directly wired through. Toindicate the signal states the address and data lines are connected toLEDS. They are lit on a high signal. MMIO is indicated by a LED which islit up at MMIO low. The input/output enable signal (ENIO) in the addressspace 4000 to FFFF is also indicated by a LED which is lit up at ENIO low.Fig. IV.1 shows the block diagram of the bus converter.

ExperimentAssembly The following is the assembly description with reference to thecomponent layout on the board shown in the Fig. IV.2 and the circuitdiagrams IV.3 and IV.4. The layout has been drawn as seen from thecomponent side. Following are a few tips for the students to support theassembly.

*A11 the soldering should be neat, there should be no splashes ofsolder and cold soldering must be strictly avoided.*HP connectors should be mounted with pin 1 on the top edge ofhe connector. The component side has connections 1-22 and on thesolder side there is A - Z. The connectors should be orientedaccordingly. Before soldering all the pins make sure that the boardcan easily be mounted on the HP kit.*The SMP connectors should be mounted with pin 1 towards the topside and column A on the left side.*A11 the integrated circuit sockets should be mounted with pin 1facing the HP connector.

*The LEDs for address and data lines should be placed so that theanode (normally the longer leg of LED) is connected to the line fromthe 1C pins generating signals. The LEDs for ENIO and MMIO have to beplaced with the cathode side connected to the leg of the chipgenerating the signal.

Warning:Take care in soldering that the components do not get overheated.

All capacitors are of value 10 nF, all dual in line array resistorsare of l K and pin 16 is common. R3 is 680 R and the rest are 1/4 WIK resistors.

191

Test ProgramsKey in the following program and starting from location 0800 run the

program with hardware step. Watch for write signals on the kit. When it ishigh you should look at MMIO, ENIO, Address and Data LEDs and compare itwith the expected results. Exit each program by pressing the RESET key.* Address lines test:

The program sets the address bits in four patterns which check all theaddress lines for high and low states.0800 32 STA FFFF ; all address LEDs high.0801 FF0802 FF0803 32 STA AAAA ; alternate LEDs high

start with low.0804 AA0805 AA0806 32 STA 5555 ; alternate LEDs high

start with high.0807 550808 550809 32 STA 0000 ; all address LEDs low.080A 00080B 00080C C3 JMP 0800 ; repeat from location

0800080E 00080F 08

Test Memory Happed I/O signal:The program sets the address LEDs by executing STA instructionsrepeatedly. Bits 12 - 15 are set one by one. Note that the MMIOsignal comes only after the four most significant bits are high.The program repeats itself after setting MMIO.0800 32 STA OFFO0801 FO0802 OF0803 32 STA IFFO0804 FO0805 IF0806 32 STA 3FFO0807 FO0808 3F0809 32 STA 7FFO080A FO080B 7F080C 32 STA FFFO080D FO080D FF080E C3 JMP 0800080F 000810 080811

192

Test Data Lines, Date transfer to the SMP bus is disabledThe program tests if all the data lines are correctly connected to theinput of the transceiver U10. The patterns to be set on the LEDs aresuch that all the lines are checked for high and low state. The datastored at address 0950 - 0953 contains the patterns. The data is notenabled to passto the SMP bus as the addresses always keep bits 14 and15 low.080008010802080308040805080608070808O808;080A080B080C080D080E080F

081008110812081308140815081608170818

0819081A

Data for0950095109520953

3A500932OFOF3A510932

OFOF3A520932

OFOF3A530932OFOFC3

0008

PatternsFF55AA00

LDA

STA

LDA

sta

LDA

STA

LDA

STA

JMP

0950

OFOF; all data in LEDs high.

0951

OFOF

0952

OFOF;

0953

alternate LEDs high startwith low.

alternate LEDs highstart with high.

OFOF; all data in LEDs low.

0800; repeat from location0800.

193

Test Data lines, Data transfer to the SMP bus is enabledIn the above program change address with STA instructions to CFOF andrun the program again, then the data are transferred to the output ofU10.

Suggested Components1. Bus driver 7417 32. Data Transceiver 7ALS245 13. NOR Gate 74LS33 14. 4 input Nand Gate 74LS20 15. 2 input OR Gate 74LS32 16. Inverter 74LS16 17. 16 Pin Dual in Line Resistors Beckman* 898-1-1K 48. LEDs9. Bypass Capacitors

(or other 10 nF Ceramic Capacitor)10. Help points11. Resistors IK/Ohm 412. HP Connectors Nr-HP-1251-2680 2

HP-HLMP 6205 3410 nF Red Cap 4

13. SMP Connectors IEC-603-2-C096M equivalentDIN 41612, page 4, for example(AMP C143-012A-965)64 or 96 pin

14. Printed Circuit Board KFA ZEL/NE 464 1Note: The 1C 7417 is available of normal Schottky type only.DIN = Deutsche Industrienorm* Dual in line array pin 16 common.

194

SPECIAL PROJECT V

MICROCOMPUTER EXTENSION: SERIAL I/O BOARD

Objective; To assemble and test a board permitting a serial connectionto an I/O terminal, RS232 compatible, or for a 20 mA current loop.

IntroductionThe described board is a serial I/O board with standard Eurocard

dimensions. It is functionally compatible with the SMP bus computersystems. The design objective has been to use the simplest ICs available onthe market. Both RS232 and 20 mA current loop compatible terminals can beconnected. The baud rate can be selected by a switch array on the board.

Specifications

1. Baud rate2. Data3. Input/OutputA. Controls5. Clock6. Temperature7. Relative humidity8. Serial connection9. Input power10. Standard Eurocard

110 to 9600 Baud8 bit asynchronousTTLRST5.5, MMIO, MEMRD, MEMWRSingle TTL clock0 - 5 5 deg operatingup to 90% with no condensationRS232 and 20 mA current loop compatible+5V, +12V & -12V100 mm x 160 mm

The communication with a computer can be made through deviceshandling the data in parallel or serial format. When the I/O unit is tobe located close to the CPU, parallel transfer of data ii the choicebecause it is faster. However, when the I/O unit might be placed at adistance from the computer like terminals - the serial I/O is a betterchoice. In this case only one line is required for data transfer alongwith control lines. The speed is normally not as important for such kindof communication. This simplifies the transceiver circuit for remotelinks through cables or via Modems (modulators/demodulators). The serialconnection may use synchronous or asynchronous mode for datacommunication.

This experiment was designed by Dr. Brandenburg and Mr. A. Shaftab inKFA Jiilich GmbH; the work was performed with the support of theGovernment of the FRG.

195

Synchronous Mode. The rate of data transfer in synchronous mode isdetermined by the clock of the peripheral. Once the transfer of a characteris triggered its output is generated or received at the clock frequency.Sync characters are included in the data stream. The receiver hunts for thecorrect sync pattern and when it is matched the data transfer is allowed.This is illustrated in Fig. V.l.

1BIT INTERVAL

CLOCK SIGNAL

DATA SIGNAL

TYPICAL • «ITSYNC PATTERN

PIRST DATA BIT '

Fig. V.l. Signal sequence in synchronous mode.

Asynchronous Mode. For asynchronous data transmission each characterhas a start bit leading it and stop bits following it. The data can betransmitted asynchronously at the preset frequency. At the receiver sidethe start bit also signals the beginning of a character and the receiverdoes not need to hunt for a special bit pattern. This is shown in Fig. V.2.

STOP ELEMENT STOP CLEMENT

i . . nOHE • «ITCHARACTER(I1MIM«)

START OHE 0 »ITELEMENT CHARACTER

(•••«••O«!

Fig. V.2. Signal sequence is asynchronous mode.

ooCQ

o_

VDATA

RESETCLK

C/ÏÏRD"

RST5.5

A

RxRDY

TxRDY

R x C

UART8251A

TxDRxO

D5RDTRCTSRTS

RS232/

20mA Loop

Fig. V.3 SMP Serial I/O Board

196

8251A/S2657PROGRAMMABLE COMMUNICATION INTERFACE

Synchronous and AsynchronousOperation

Synchronous 5-8 Bit Characters;Internal or External Character Synchro-nization; Automatic Sync Insertion

Asynchronous 5-8 Bit Characters;Clock Rate—1,18 or 84 Times BaudRate; Break Character Generation; 1,1Vi, or 2 Stop Bits; False Start BitDetection; Automatic Break Detectand Handling

Synchronous Baud Rate — DC to 64KBaud

• Asynchronous Baud Rate — DC to19.2K Baud

• Full Duplex, Double Buffered, Trans*mitter and ReceiverError DetectionFraming

Parity, Overrun and

• Fully Compatible with 8080/8085 CPU

• 28-Pin DIP Package• All Inputs and Outputs are TTL

Compatible• Single + 5V Supply• Single TTL Clock

The Intel9 8251A IB the enhanced version of the Industry standard, Inter* 8251 Universal Synchronous/AsynchronousReceiver/Transmitter (USART), designed tor data communications with Intel's new high performance family ofmicroprocessors such as the 8085. The 8251A Is used as a peripheral device and Is programmed by the CPU to operateusing virtually any serial data transmission technique presently In use (Including IBM "bl-sync"). The USART acceptsdata characters from the CPU In parallel format and then converts them Into a continuous serial data stream fortransmission. Simultaneously. It can receive serial data streams and convert them Into parallel data characters for theCPU. The USART will signal the CPU whenever It can accept a new character for transmission or whenever It hasreceived a character for the CPU. The CPU can read the complete status of the USART at any time. These Include datatransmission errors and control signais such as SYNOET, TxEMPTY. The chip Is constructed using N-channel silicongate technology.

DATA•US

•UFFIM

CIK.crtJTO«m

CONTROLlOQIC

MOOf MCOM?not

INTfANAIOAT» HI K

TRANSMITeurrtR

TRANSMITCONTHOl

.T.I o.C

o,C

NICEIVf

I» PI.fl.f)

«n

«cc^CBt>C

R>nr>v

«z]4

S

6

t 8281 A*4

iniii?13M

?J

tt

K

7»

7?

7170

18U

t*

15

3o,3c\,3 v<t3RTÖ

3ÔTS3 «TS35553 «rsf t3d-

3 »•!•3 T.IMPTv

3053 SVNOf T/HO

3 t.wnv

ntcfivtCONfBOl

Fig. V.4. USART Specifications.

197

The serial I/O board has been designed to operate on a standard SMPbus. It handles data characters from the bus in parallel format andsends/receives serial data from the I/O port. An option to switch to RS232or 20 mA current loop connection is available. The desired connections canbe made by wire wrapping on jumper pins. Fig. V.3. shows the block diagramof the circuit.

Address Decoder. A specific address is assigned to the serial I/Oboard. This can be set by the switch array SWI which is compared with bits2 - 9 of the address requested for I/O. Bits 10 - 15 are to be high, bits12 - 15 are high to select MMIO, bits 10 and 11 are not used for addressselection. Bit 0 is used to select data or control/status for the 8251A,high on it indicates control and low signals the data. The bit 1 is leftopen for future use. When the address sent to the board is correct a CS(Chip Select) is generated for the USART 8251A.

Universal Synchronous-Asynchronous Transceiver (USART) 8251A. Fordetailed description refer to the specifications available in data catalog.A brief description to introduce the USART is presented here. Fig. V.4shows an overview of the functional behaviour and the pin configuration.The 8251A can be used flexibly to suit different input/output connections tothe CPU. Before it starts to handle the data a set of control words arewritten into it, which define its functional behaviour. The control wordswill program baud rate, character length, number of stop bits, synchronousor asynchronous operation, even/add, parity etc. The mode instruction andcommand instruction used for our serial connection are described in thefollowing.chapters.

Mode Instruction. The 8251A is used in asynchronous mode so that theuser can choose the options shown in Fig. V.5.

o.

EP PEN

BAUD RATE FACTO«

SYNCMODE (1X1 I «XI (MXI

CHARACTER LENGTH

BITS

1

BITS BITSt

«ITS

PARITY ENABLE' 1 • ENABLE 0 • DISABLE

EVEN PARITV GENERATION/CHECK1•EVEN 0 - OOO

NIMMER OF STOP BITS

INVALID JIT1*

BITS BITS

(ONLY EFFECTS T«. Rx NEVERREQUIRES MORE THAN ONESTOP BIT)

Fig. V.5. Mode Instruction Format.

198

EH m RTS ER S8RK DTR T«EN

ü TRANSMIT ENABLE1 > truMi0 • dnabte

DATA TERMINALREADY __"hifh" wi« lore« DTRoutput to ttto_____

RECEIVE ENABLE1 - «ruMt0 * diufcfe

SEND BREAKCHARACTER1 • loten T»D "low"0 "norm») op*rltion

ERROR RESETI - rMt *rro» flagi

F-E.OE. FE

REQUEST TO SEND"hich" «rill for» RTSoutput to «ro

INTERNAL RESET"hifh" rtturm 82S1A toMod* Instruction Foimit

ENTER HUNT MODE*1 * «mbl« tMrch foi SyncCturKttn

1 (HAS NO EFFECTIN ASVNCMOOEI

Fig. V.6. Command Instruction Format.

We have used the value (4E) Hex for defining the mode which means thatthe baud rate for the serial I/O shall be 16 times less than the clockfrequency at pin 20, a data character will be of 8 bits, parity will bedisabled only one stop bit will be used. The mode instruction can be loadedafter the USART has been reset.

Command Instruction. The command instruction controls the actualoperation of the selected mode. The desired command word can be selectedwith reference to Fig. V.6. When C/D is high on pin 12 the control wordwhich will provide the operating information for data handling can bewritten into the USART.

We have used (27) Hex as the command word which means that transmitterand receiver are enabled, "data terminal ready" and "request to send"signals are set low.

Status Word. The status word of 8251A can be read by the CPU with C/Dset high by a read instruction. It contains status information about thedevice connected to it. The meaning of the bits in the status word areshown in Fig. V.7.

199

OSR SVNDET FE OE PE T.EWfTV R.ROY T.ROY J

No«!

SAME DEFINITIONS AS I/O PINS

PARITY ERRORThi PE lit« it Mt «iMn • (Mrttv•rvor n dvttctad. 1C is nMt byItM E R bit öl th« CommandInitfuction PE doM not inmbilopwalionof th*82S!A

OVERRUN ERRORThe OE fl*9 n (*t «ton th* CPUdoM not raad a character betörtin« not am bKomo ••wtabltIt is itMl by IlM E R bit of Ih«Comnund Intlruclion OE do«tnol inhibit optrMMMt of th* 82S1Ahov»lvn. th« prrnotMly owfrunchatacltr n lo«l

FRAMING ERROR (Aiynconly)Th< FE llig n itt Mhwi * vüidStop bit K nol dMKttd M th«•nd of «v«ry ch*r«ct«r M u r««ctby th« E R bit ol th« CommandImtruclton f E do«» not inhibitth« op«rilKMi of the 82S1 A.

DATA SET READY Indien«that in« OSR » 9t l »to kvtl.

Fig. V.7 Status Read Format.

Baud Rate Generator. The baud rate generator provides the timing clockfor receiving and transmitting characters through USART. Different baudrates can be selected by a combination of switches from the array SW2.Table V.I shows the possible combinations. Note that a 1 on a switchcorresponds to "ON" state.

Table V.l. Selecting baud rate.Switches Baud Rate01234567

0000000010000000110000001110000011110000111110001111110011101010

9600480024001200600300150110

200

The clock, available on pin 5 of U9 is 16 times faster than the actualbaud rate as the USART has been configured to divide by 16 internally. Thechips U4 - U6 (74161) count to 15 from the binary number set at pins 3,45,6 initially and then set the overflow bit 15. A low at pin 9 loads all thechips inputs to start the counting. Pins 3 - 6 of U4 are tied to ground soit always divides the input frequency by a factor of 16. The binary numberset on switches 0-3 determine the dividing factor by U5 and switches 4-7determine the factor for U6. When an overflow on all the three chips occurspin 8 of IC8 goes low giving one clock pulse to flipflop U9 and loads thecounter chips again to divide the input frequency by the same cummulativefactor and then the next timing pulse is issued. The counting in U5 isenabled by bit 15 of U4 and in U6 it is enabled by bit 15 of U5. Hence thecounters divide the input frequency successively.

20 mA Current Loop Every cable has a finite ohmic resistance per unitlength. For long cables the input voltage signal may drop considerablybefore reaching the receiver end due to resistance of the cable. Hence thedistance between the terminal and the computer has to be limited for voltage

Connectors

Opto-Coupler

'-12V

(active) (passive)

Fig. V.8. Operation principle of a 20 mA current.

driven connection. The twenty mA loop is useful when we have to place theterminal at a greater distance. The current loop couples withnormal TTLcircuits on the two sides through opto couplers. The driver side of theloop provides 20 mA current irrespective of the voltage drop on the cable.This ensures a good quality of the signals. The device at the currentdriver side is called "active" and that at the receiver side is termed as"passive". The principle is illustrated in the Fig. V.8. The 20 mAconnection needs two pairs of wires one for input and the other the output.

On the serial extension board both RS232 compatible and 20 mA currentloop compatible terminals can be used. By the help of jumpers the board canhandle the terminal in active or in passive mode.

Fig. V.9.A shows active transmitter and V.9.B shows the activereceiver. Fig. V.10.A shows passive transmitter and V.10.B shows passivereceiver.

201

(A)

Connector

USART SIDE TERMINAL SIDE

Connector

TERMINAL SIDE -12V USART SIDE

Fig. V.9 (A) Active transmitter, (B) Active receiver.

The data is transmitted through both 20 mA current loop and the RS232driver. For 20 mA loop proper jumpers have to be added as shown in Fig.V.10.A and V.10.B. For the receiver besides these an additional jumper J5is provided on the board to distinguish between RS232 and 20 mA loopsignal. If the jumper is open the RS232 connection is enabled and if it isclosed 20 mA current loop is connected to pin 3 of USART (RxD signal).

Selectable Modes on the BoardThe serial I/O board is normally RS232 compatible with the jumpersopen. To use with 20 mA current loop jumpers have to be added.To make the use of the board flexible, all the necessary signals areprovided on the help points near the SMP connector. Their layout isdescribed below.REST Pin 1REST Pin 2REST Pin 3REST Pin 4REST Pin 5REST Pin 6PI Pinl

INTRST 5.5RxRDYRST 6.5RST 7.5TRAPTRDY

202

(A)

Connector

(B)

USART SIDEI-12V

»5V

33

TERMINAL SIDE

Connector Ç i1 (Î333V

TERMINAL SIOE I-12V USART SIDE

Fig. V.IO.(A) Passive transmitter, (B) Passive receiver.

* When using the board with normal ASR33 TTY use 110 Baud rate and setthe jumpers to make the board active receiver and transmitter (refer toFig. 9A & B).

* Connect pin 4 and 5 of the V24 connector by a jumper. Note that thetest programs set RTS signal with the command word.

* Board address can be selected by switch array SW1 (refer to section3.22) e.g. for FD20 set switch 8 and 4 to "OFF" others to "ON".

* Baud rate can be selected by switch array SW2 (refer to section 3.3.7)e.g. for 9600 bauds all switches are "OFF" for 110 bauds switches 1, 2,3, 5, 7 are "ON" and switches 4, 6, 8 are "OFF".

203

ExperimentAssemblyThe following is the assembly description of the serial I/O board with

reference to the component layout in Fig. V.ll and circuit diagramsFig. V.12 and V.13.* The soldering should be neat, there should be no splashes of solder and

cold soldering must be avoided.* All the integrated circuits should be mounted with correct orientation

i.e. pin 1 facing the SMP connector.* The switch arrays should be mounted so that they are off when pressed

towards the edge of the card,* The diode and transistor should be placed with correct orientation

indicated on the board.All the resistors are to be 1/4 Watt rated exept R5, R7, R8 and R9which should be of 1 Watt rating.

* All bypass capacitors should be red caps of 10 nF or ceramic capacitors.* Normally the I/O device interrupts the CPU via the RST 5.5 signal

however jumper pins have been provided near the SMP connector to enablea user to select any of signals from RST 5.5, RST 6.5, RST 7.5, Trapand INT for this purpose.

UDC: BK3BKRNDY8.CO-2

FILE: B0228 DOB: 004

Fig. V.ll Components layout

204

10 12 14 16 18 20 22 24 26 26 30 32

»5V

11 13 15 17 19 21 23 25 27 29 31Symbol 2 indicates 74hundred series It'sSymbol Vcc indicates <5V

Fig. V.12. Circuit diagram 1.

K)O

. X I

Vcc1K 0

i

4 9152MHZ

Note All Jumpers open for RS232 Connection»12V Supply is required for 75188

»5V—Vcc for all othersConsult the manual for Baud rate selection and

For 20mA current loop

-12VFig. V. 13. Circuit diagram 2.

* The board is RS232 compatible when all jumpers Jl, J2, J3, J4, and J5are open. To make it work with 20 mA current loop select the jumpersas described in the chapter "Functional Description".

* When used on the HP-SMP bus converter +12V supply has to be provided inaddition to the +5V supply from the HP bus.

* Check the setting on switch arrays to select correct address and baudrate.

* Plug in the board and check that ail ICs are connected to power andground and then run the test programs as described later.

TestsAfter the board has been assembled step by step testing of the board

has to be done.1. Dismount the USART chip and plug in a temporary connection between pin

3 and 19 in the socket of the USART. Mount the serial I/O card on thebus board and connect it to a terminal. Type a character on the keyboard. Observe the output on the display. If it displays thecharacter typed, it makes sure that the connection between the terminaland the serial I/O board is correct otherwise check the input/outputlines for the USART to the connector etc.

2. Mount the USART chip and set the switches on the board to select theaddress (FFOO)* of the board and the baud rate to match the terminalattached.

3. Check on all ICs that power and ground are available on the correctpins.

Note: The RESET key available on the HP kit is not the same as thehardware reset. The user presses the RESET key to halt aprogram at the current location. A second push on it bringsthe HP kit to initial state (U LAB UP).On power up a hardware reset pulse resets the USART on theserial I/O board. Then two consecutive words mode and commandwords are written in it which define its operatingconfiguration. To initialise the USART again at a later stage,a data word with reset bit set is written in it. After thatthe mode and command words may be written. Hence, the testprograms in sections 4 to 6 should be run from location 0805just after power up. Later on the programs have to be run fromlocation 0800.

4. Key in the transmitter test program, the board address used in thiscase is (FF01) Hex. KRun the program in instruction step mode firstand then run it from location 800.The program is in a loop, sending the character "U" to theterminal. If the character stream is being received at the printerthe transmission side of the board is functional - if not we shouldcheck it.

207

Key in the test program for serial extension board to operate inreflect mode i.e. characters typed in at console are received byUSART and then sent to the printer. If this happens the USART boardis functional otherwise check.Key in the program for serial extension test routine to send allASCII characters. The ASCII characters shall be printed in rows often characters if the board is functional.

Transmitter Test0800080108020803080408050806080708080809080A080B080C080D080E080F08100811081208130814081508160817

3E403201'FF2101FF364E36277EIFD2OC082B365523C3OC08

MVI

STA

LXI

MVI

MVI

MOVRARJNC

OCXMVI

INXJMP

A, 40

FF01

H.FF0101

M,4E

M,27

A, M

080C

HM, 55

H080C

;set the reset bit in data;send reset data to USART

;send mode word to USART

;send command word to USART;read status word of USART;test TxRDY bit

;send character "u" to printer

; repeat from address 800

»Switches 1 - 6 ON switches 7 & 8 OFF in SWI

208

0000A DDR0800O80208050807Ö80A080B080D080E080F081008110814081708180819081A081D081E0821

HEX3E323E21773E777EIFIFD23A47

7EIFD27832C3

CODE40014E0127

OE00

1800OE

FFFF

08FF

08FF08

BEGIN'

NEXT.

NEXT1,

** ** #*»*»*•*»» -M-** -s-» ##»*»»•*#•<(••*<• •*•*•*•«• -s-» •##•«-» - •*•* «*TEST PRÜGRAM FOR SERIAL EXTENSION BOAKu•»•CHARACTERS ARE READ FROM KEYBOARD AND REFLECTED ON PRINTER•»•MODE WORD FOR DART (INTEL 8^53 A) 316 < CF HEXA5 SETS IT TO•»BAUD RATE 1&XCLOCK AND ACCEPT 8 BIT CHARACTERS«•COMMAND WORD FOR UART (8251 A > 47 SETS THE BITS FOR«•REQUEST TO SEND -RECEIVE ENABLE, DATA TERMINAL READY AND TRANSMIT«ENABLE UART BOARD ADDRESS IS F FOO»TO EXIT PRESS RESET KEY ON HP KIT**»»»*»***»**»»*•»••«••»•*•»••!*-•?••«•-»••«••«•»! H-* * .!•**••>( W**-**-*« #•»•-«•>-!<•»»*••»-•«• *-•**•)>ÖRQ 4000

*****

MVI5TAMVILXIMOVMVIMOV

A,100177401A, 116

.RESET USART B251A

LOAD MODE WORDH,177401-SET ADDRESS IN REGISTERS HM,A ,MOVE MODE WORD TO UARTA,47 ,LOAD COMMAND WORDM,A ,MOVE COMMAND WORD TO UART

#*#•»•*#*#•»•*#*•**•»####*»WAIT LOOP f"OR KEYBOARD CHARACTER******MOVRARRARJNCLDAMOV

A,M ,READ STATUS WORD

NEXT ,IF CARRY BIT IS 0 CHECK STATUS AGAIN177400 ,READ ONE CHARACTER FROM KEYBOARDBiA ,SAVE IT IN B REGISTER

»»»»»»»»»»»»»»»»»»•»»»OUTPUT CHARACTER TO PRINTER***********MOVRARJNCMOVSTAJMPEND

A,M ,READ STATUS OF UART

NEXT1 ,IF CARRY BIT IS 0 READ STATUS WORD AGAINA,B ,RECALL CHARACTER FROM E REGISTER177400 ; OUTPUT THE CHARACTER TO PRINTERNEXT ,READ NEXT CHARACTER

0000ADDR HEX CODE0800 3E 400802 32 01 FF

21 01 FF3E 4E

0805oaoaoeoAO80B080D

080E 7£080F l F0810 IF0811 D2 OE 08

08140816081°081AoaiB081E08200823082408250828082A082D082F0830

083308360837083A083DOS3EOS3F0842084508480849084C084E

3E32

^EIFD23E327EIFD23E323E2F323A3C32CA

7EIFD23A323C32

06B8

2100

19OD00

23OA00

10

O4

04

0419

3D0000

007D

OF

08

FF

08

FF

OF

OF

OF08

08OFFF

OF

084F DA 33 080852 E 50853 CE 10 000856 CD 10 OO0859 E i085A C3 OE 08

0001

TEST ROUTINE FOR SERIAL EXTENSION 0^ HP KITASCII CHARATER SET IS PRINTED UN THE PRINTERTHROUGH THE SERIAL EXTENSION TO TEST THE CÜNNEC I IONAND THE PRINTERQRG 4000*# ***•*•»***•»••* -fHHHm-*-* *«•**#*» &-* *•*•!! «#•»-* •MVI A, 100STA 177401 , RESET USART S251A

LXIMVIMOVMVIMOV

H,A,M,A,

177401116A ,47

INITIALISE THE SERIAL PORT

H. A

WORD.TRIGGER THE TEST ON ANV, KEY FROM TERMINAL

MOV A, MRARRARJNC WORD•»•a--* •»•&•* •»•»#•« a *#•»#*# *•»*•«•»•»#»*****#•»• •»• •»••*•*• **•,•(•**•»-•»•»*•*•» -a **#<MVI A, 41 .STORE FIRST ASCII CHARACTER AT OFOOSTA 7400

SEND

,SEND CR TO PRINTER

PRINT

MOV A, MRARJNC SENDMVI A,15STA 177400**#***•#*«*****"«••« **»»*»***•«•*•*•»•»* «•#**«»*******#*****•»••>MOV A,MRARJNC PRINT .SEND LF TO PRINTERMVI A,12STA 177400

, INITIALISE COUNTER AT OF04

LOOP

SEND1

MVI A,20CMASTA 7404* *•»#*****#*** **•*#* *•»#•» ««****•»«•»****•«**•»***#•****•*****LDA 7404INR ASTA 7404 ,IF TEN CHARACTERS HAVE BEEN SENTJZ SEND - ,SEND CR AND LF•»**» ****#**•»****#*•*•»**•***«**»*•***•»*****•»-•***#**-iHHHHHMOVRARJNCLDASTAINRSTA

A, M

SEND174OO1774OOA7400

SEND CHARACTER TO PRINTER FROM OFOO

,SET NEXT CHARACTER IN OFOO**#*##*#*«*-> »•»#•» ****«»**»****»*#**•*****•*•***•»****#**•'MVI B,175 .COMPARE WITH LAST ASCII CHARACTERCMP B

JCPUSHCALLCALLPOPJMPEND

LOOPH2020HWORD

IF SMALLER GO TO NEXTPUSH H L REGISTERS ON STACK

POP H L REGISTERS FROM

210

Wire wrap versionThe present exercise can be performed also using the wire wrap

technique.After an electronic circuit has been designed on paper the first

practical version is prepared with the wire wrap connections. Then itsfunctional behaviour is tested. In this way the designer can easily makealterations in the circuit to suit the practical requirements. Finally theprinted circuit board is prepared. To give an experience of thisintermediate state in circuit design to the students the serial I/O board isalso prepared for wire wrapping.

EXAMPLE:

Z7

WIRE WRAP CONNECTION LIST:

Comp. Pin27 é27 4-C<=> 2-£7 10e<r 1/?il 7-RID l

Comp. Pin?7 5"&iO 2.27 42-7 l|

<*Nh

CTL. 2-C.TL )

Comp. PinK 10 1C6 t^•7 V37 11

Comp. Pin

K n iC.S \

Comp. Pin

RU i

Fig. V.14. Example of a connection list

211

All the components are placed at the same positions as on the actualboard and the connections have been deleted. +5V and GND are made availableon the help points on the edges of the board. +12V and -12V connections aredirectly wired to the pin 1 and pin 14 of Ull. The following procedure isrecommended for the students to wire wrap the circuit.1. Place wire wrap sockets for all the components taking care that they

are correctly oriented. The pins of the components have been markedfor ease.

2. Prepare a connection list for wire wraping according to the circuitdiagram. A connection list has been prepared as an example for aportion of the circuit, shown in Fig. V.14.

3. Wire wrap the connections using the wire wrap gun. Take care that:* The wires are neither too tight nor too loose.* The wires do not pass tightly around a wire wrap pin of any

component as this may cause an erroneous connection to thatpin.

4. Place the components in the sockets. See that the orientation iscorrect.

5. Check that the power and ground are available to all ICs.6. Test the board by using test programs described for the soldered

version of the board

HEX-ASCII TABLE

00010203040506070809OAOBOCÖDOEOF1011121314

NULSONSTXETXEOTENQACKBELBSHTLFVTFFCRSOS!OLEDC1 (X-ON)DC2 (TAPE)DCS (X-OFF)DC4 (TAPC)

282C2D2E2F303132333435363738393A3B3C3D3E3F

+'_

/0123456789

i<=>9

565758595A585C5D5E5F606162636465666768696A

VWXYZl\lA (Î)- M\

abcde1ghiJ

15161718191A181C1D1EIF202122232425262728292A

NAKSYNETBCANEMSUBESCFSGSRSUSSP!"#S%&/

()*

404142434445464748494A4B4C4D4E4F505152535455

®ABCDEFGH1JKLMNOPQRSTU

6B,6C6D6E6F707172737475767778797A7B7C7D7E7F

klmn0

PqrstuvW

X

yz{l\-DEL

(ALT MODE)

(RUB OUT)

Adr - 16 bit address

212

COMPONENT LIST FOR SERIAL I/O BOARD

COMPONENT QTY TYPE COMP NAME

74L50374LS0474L26674LS161

74LS0274LS2074LS74

8251 ASN75188SN75189

74LSOO

1223

1111111

DSS 108 (100 mA) 2BC184C 1IN914 14N28 2IEC-603-2-C096M 1equivalent DIN 41612,page 4, for example(AMP C143-012A-965)64 or 96 pinRS232 connector 14,9152 MHz HC18U 1single in line 2array resistors1/4 W resistor 71/4 W resistor 21/4 W resistor 21/4 W resistor 110 nF capacitors 12100 pF capacitors 11/8 W resistor 11/8 W resistor 11/8 W resistor 11/8 W resistor 2Printed circuit board 168 pF capacitor 1

NAND gate open collector

inverterexclusive NOR

4 bit binary synchronouscounter

NOR

4 input NAND

f l ip flopUSART

RS232 line driverRS232 line receiver2 input NAND

8 switch array

NPN transistor

Diode

opto coupler MOTOROLA

SMP connector

AMP 205858 - 18222crystalnine pin IK R88

l K560220330red caps or ceramicceramic

2 K120 K3.9 K4.7 K

KFA, ZEL/NE 466

ceramic

Z17ZI, Z16Z2, Z3Z4, Z5, Z6

Z7

Z8Z9Z10ZUZ12Z13SW1, SW2TRIDIZ14, Z15SMPA, SMPB, SMPC

V24CTLRAI, RA2

R1,R2,R10,R11,R12,R14,R15R5, R9R7, R8R3

C5R13R16R4, R6R17, R18

C17

DIN = Deutsche Industrienorm

213

SPECIAL PROJECT VI

MICROCOMPUTER EXTENSION; MEMORY

Objective: To construct and test a SMP memory board, designed toextend the capability of a Hewlett-Packard microprocessor learning system,and to demonstrate the structure and functioning of a complete memory.

IntroductionThe exercise is to be performed in several steps; each is described

separately, including the introductory remarks. The memory board is to beconnected to the SMP bus converter and Hewlett-Packard MicroprocessorLaboratory. The static RAM 6116 was selected for design of the memory,because its pin functions are compatible with the EPROM 2716. Thus thememory board can be used either with RAM or with EPROM, or with both.

Step 1: Assembling the memory boardExperiment 1

Refer to the block diagram, Fig. VI.1, wiring diagram, Fig. VI.2 andcomponents plan, Fig. VI.3.

Place the components in the correct position on the printed circuitboard. The positions are named. The positions can also be checked byusing the component plan.Make sure that components are mounted properly and at the correct pinposition, then solder them.Check every soldering point to be correct i.e. no coldjoint, no excesssoldering.

AIMS

MEMW

Fig. VI.1 HP.kit extension memory: block diagram

This experiment was prepared by Dr. G. Brandenburg and Mr. V. Srisaman, KFAJlilich GmbH; the work was sponsored by the Government of the FRG.

215

Vcc Vcc

.5V'——p

ill' .

•~i T7" "UND J

, .»« . .v»AÜ ——————

.-»AU ——————, »AS ——————

»m** —————,6»M! ——————:<.»*? —————um** —————

.2 0»A7 ————————

i»«**« •**UB44 —————

:'2»*2 —————c lo»Aj —————————, „AIv M AU

t 0MFR1Ï)

,„.«153 ————

Cl-: r0 !

Vcc i

lo-n _L( _t_

Vcc -3s;9

VCC -T

23

s

6789

F.'liS

12 U<t

j »SEL-TTVü—^•^MSM,.»•23 —————,I.«B2 ————————

,:*23 —————,,»£ —————,2*^ ———————„_36

,j.«E —————

-^

n- r^7-

y |20

U2LS2t5

~r———— [20

11}

LS245

U3

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T\4*-L" i V 1jiyu ,i7i

Sl32

a l 12 7 Ï «— *"7 K 9 t 9 7 ,, -1

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u LJ'°: ' LS138 ,2 vl ß 1 J «.3 0^.

2 4 2 H 2 „ ^

* r^ r1 ^— -13 11« _[8 16 Jl

- ————— 1 Vcc Vcc

n

- ——————————— JZfi —————— ( 1V- Lü A«11 " A».2" ' ——————— }- A7

7 At3 A. M1-M*

" ' II

ff.

RU2

U'X U7»l 6 PN1«11 T

12 ttt 1tt 115 1If

1l

16 | 5 2716/6116

"• • ' ' A".n 7 !:RU1 ' ———————————————————— A0

L cm | --„WS-/VPPirV.8 l «n,,, i

^ 2L)>^ i n n oLS03

\

U1152^,5

111213UISW

sv,

n

t 7 aiIS

uU1.-.1

W 17

/

/

/

/

/

/

/

/

/

/

/

/

5;

" .3 >*— l

12J

-HJLS30

/--

/^

±N ll -KJin

BERNDY3,CO-2UDC: BTÎ3 FILE: B0222

Fig. VI.2. HP-kit extension memory: circuit diagram Fig. VI.3 Components layout

Step 2; Address decodingIntroductionThis memory board has a capacity of 16K when populated with full memory

chips (Schips: 2k each) and the board can have a starting address from 0 tothe maximum capacity of the (SMP) BUS (64K) in 4K step. The startingaddress can be set by using switch SI as indicated in Table V.l. Alsonotice that uLab has the free memory address space from 4000H for extensions.

TABLE VI.1 STARTING ADDRESS

Switch Setting1 2 3 4offoffoffoffoffoffoffoffonononononononon

offoffoffoffononononoffoffoffoffonononon

offoffononoffoffononoffoffononoffoffonon

offonoffonoffonoffonoffonoffonoffonoffon

StartingAddress04K8K12K16K?OK24K28K32K36K40K44K48K52K56K60K

Hex0000100020003000400050006000700080009000AOOOBOOOCOOODOOOEOOOFOOO*

*- I/O MAP spaceI/O Map will be described later.

The address decoding is shown in Fig. VI.4

A buffer is used for reducing the bus load of internal board circuits.Subtracter is a hardware arithmetic subtracter which subtracts the startingaddress from the bus address and provides the internal base address. Theborrow output from the subtracter will indicate that the address is lowerthan the starting address of the board and it is used to disable thedecoder. Also two higher MSB outputs from the subtracter are used todisable the decoder if the resultant address is higher than the capacity ofthe board. Only three bits are used for decoding.

An example is shown where the address is lower than the startingaddress of the board. Let us assume starting address of 4000H and a busaddress of 2000H.

217

STARTADDRESS SW.

ENABLE/DISABLE

INTERNALADDRESS

Fig. VI.4 Address decoding circuit

ENABLE/DISABLE

INTERNAL J .ADDRESS

DECODER

U6

7U.S138

?W111213V»15

—— Cr- —— O —

—0——&-

— o-— o-

10111213141516

\}

BADR

to Memory Chips

Fig. VI.5 Chip select circuit

Bus address 0010 0Start address 0100 0Output from subtracter 1 1110 0

The results from the subtracter contains the borrow which indicatesthat the board is not selected. The borrow output will disable the decoder.

Now an example where the bus address is higher than the boardcapacity. Let us use the same starting address and a bus address of BOOOH.

Bus address 1011 0Start address 0100 0Output from subtracter 0 0111 0The second MSB will disable the decoder.Memory chip selectAnother circuit on the board is the chip select switch, Fig. VI.5The task of this circuit is to provide a board addressed signal. Only

when the chip select switch is enabled (closed) for the corresponding memorychip. This means that the board can be used for any capacity which ismultiple of 2K (capacity of a memory chip).

218

The BADR is the output signal from this circuit, which indicates thatboard is addressed. It is gated by the MMIO signal to provide BSEL which isused for enabling the data buffer. The BSEL signal indicates that thisboard is selected.

Table VI.2 Chip select switch

1OffOnOnOnOnOnOnOnOn

2OffOffOnOnOnOnOnOnOn

3OffOffOffOnOnOnOnOnOn

4OffOffOffOffOnOnOnOnOn

5OffOffOffOffOffOnOnOnOn

6OffOffOffOffOffOffOnOnOn

7OffOffOffOffOffOffOffOnOn

8 Board CapacityOffOffOffOffOffOffOffOffOn

02K4K6K8K10K12K14K16K

Memory Happed I/O

MMIO is a bus signal of the SMP Bus. In the standard SMP Bus the topmost 4K memory address space is used for I/O addressing. The SMP Busprovides the MMIO signal to indiace that the address is in the memory mappedI/O address space. In our case this signal is created by the bus convertercircuit.

Experiment 2Objective: In this experiment, the address decoding operation will be

observed with an oscilloscope while the uLab is running a short programwhich addresses the memory board.

Use the uLab to check Write/Read data operation.1. Set the starting address of the memory board to 16K. (What is the

correct switch setting?)2. Set the chip select switch to enable only the first memory chip.

(What is the correct switch setting?)3. Mount the board in the SMP socket of the bus converter.4. Turn on uLab and check the supply voltage on the memory board. It

should be 5V. + 10%.5. The display should show uLAB UP, if it does not press RESET.6. Fetch address 4000 and store data 55.7. Fetch address 4000 again and observe that the data read out is 55.8. Try to store another data, maybe AA, FF, 00, etc., and also try

another address.

219

Observe addressing with an oscilloscope.1. Key in the following program:

CONTENTSADDRESS080008010802080308040805

LABELSLOOP:

INSTRUCTIONLDA 400

JMP LOOP

COMMENTS; Memory Address

; Repeat

2. Connect the scope's probe channel A to BSEL (board select)point.

3. Set input to 2V/Div. Set the sweep speed to 10 us/div andtrigger on channel A.

4. Run the program entered in step A. Verify that the display issimilar to Fig. VI.6.

Fig. VI.6 Addressing waveform.

Step 3: Control signal circuitIntroductionThreee control signals are received by the board which control its

operation namely:- MEMR- MEMW- MMIO

MEMR is a bus control signal which controls the read dataoperation. It is a negative logic signal. This signal is normally high;

220

when it goes low the data from the proper memory address must be put onthe data bus.

MEMW is a bus control signal whih control the write data operation.It is a negative logic signal. This signal is normally high; when itgoes low the memory device which is addressed must read data from the busand store the new received data.

MMIO is a bus status signal. It is normally high; when it goes lowthe bus address is within the memory mapped input/output region.

The circuit for the internal control signals is shown in Fig. VI.7.

74LSOO

MEMR

MMIO

7M.SOO

\\———READ

7M.SOO74LS03

WRITE

Fig. VI.7 Control Circuit

MEMR is inverted and gated by MMIO to provide the /READ signal.Like MEMR, MEMW is performed by a similar circuit but the /WRITE signalis provided by an open collector gate. The open-collector gate is usedfor compatibility with EPROMS in place of RAMs. EPROMs from somemanufacturers send interfering signals through the Vpp pin, while thatpin in case of a RAM is used for /WR signal.

Experiment 3This experiment allows the observation of the operation of control

signals with an oscilloscope.1.a)b)c>d)

2.ADDRESS080008010802080308040805080608070808

Connect the oscilloscope as follows:Channel A to WRITE point.Channel B to BSEL point.Trigger on channel A.Set both input channels to 2 V/div and the sweep speed to1 jas/div.Key in the following program:CONTENTS LABELS

LOOP:INSTRUCTIONSTA 4000

LDA 4000

JMP LOOP

COMMENTS; Write operation

; Read Operation

; Repeat

221

Fig. VI.8. Write Operation

Fig. VI.9 Read operation

This program will perform, write and read operations with thememory board. The microprocessor repeatedly executes thisshort loop, such that Read and Write operation can be observedby an oscilloscope.

3. Run the program.4. Adjust the trigger level until a stable display is obtained.

See Fig. VI.8.5. Connect the oscilloscope channel A to the READ point.6. Observe the read operation, Fig. VI.9.

222

Step 4: Diagnostic programIntroductionThe software which is used for testing the hardware is typically

called DIAGNOSTIC program. Refer to Practical Microprocessor Lesson 13Section A Software Design Procedure, should be familiar with this and thefollowing section.

Consider a practical diagnostic test program which should consist ofthe following parts:

1. Clear all memory locations that will be tested.2. Check that every memory location was cleared.3. Write a check pattern to each location, each time check all

other location that they have not been altered. Then clear andcheck the next location.

Fig. VI.10 shows an example of the flowchart of a clear memoryroutine.

START )

Loop throughall locations ————

| Write zero |

~"ï"~"~~( end loop )

( END )

Fig. VI.10 Clear memory routine

Experiment AWhen hardware parts are designed it is normal that the diagnostic

program for checking this hardware should be written.Write diagnostic software1. Write a flowchart for the entire program. Try to make it clear.2. Choose specific registers for each function.3. Write a program which follows the flowchart.Test the board1. Key in the written program.2. Specify the wanted test region. (Test only the first memory chip.)

3. Run program.

223

4. If program is not running properly, "debug" it and repeat theprocedure.

5. Disable the second memory cycle with the chip select switch,6. Specify test region for first and second memory chip.7. Verify that the program shows an error for the address of the

second memory chip.8. Run program to test the entire board.

PROBLEM SOLUTIONS

Experiment for Step 21. Switch setting for starting address 16K (or 4000 H) is:

SW1-1 OFFSW1-2 ONSW1-3 OFFSW1-4 OFF

2. Switch setting for the selection of first memory chip is:SW2-1 ONSW2-2 OFFSW2-3 OFFSW2-4 OFFSW2-5 OFFSW2-6 OFFSW2-7 OFFSW2-8 OFF

3. Assembled test programADDRESS CONTENTS LABELS

LOOP:080008010802080308040805

3-A0040C3_0008

Experiment for Step 31. Assembled test program

INSTRUCTION

LDA 4000

JMP LOOP

ADDRESS080008010802080308040805080608070808

CONTENTS3200403A0040C3_0008

LABELS INSTRUCTIONLOOP: STA 4000

LDA 4000

JMP LOOP

COMMENTS

; Memory address

: Repeat

COMMENTS; Write operation

; Read operation

; Repeat

224

Experiment for Step 4A.3.1 Entire program flowchart is given in Fig. VI.11Program for memory testing by using HP uLAB (Step 3).

SMP TEST XMACRO 8085 16-JUN-83 13: 57TABLE OF CONTENTS3 37 DEFINE PARAMETERS4- 64 RAM TEST ROUTINE5- 77 CLEAR MEMORY6- 102 MEMCHECK7 147 RAM TEST OK8- 165 ERROR DISPLAY

PROBLEM SOLUTION

( START ')V___________/

I Loop all location |-

| Write zero |

( end loop )| Loop all location |

———TT Error TT

DATA:0^>———(End loopj

, IL1EL1I

( end loop \

I Beep |

Store display buf ferwith "No Error"

Loop inf ini te |-

Scan display |

( End loop )

Fig. VI.11 Complete program flowchart

225

PROBLEM SOLUTION

Program for memory testing by using HP uLab.

mri

mi

-) u>l K LÜ

>0 ÜJ Z^ h- M

UJ I- >r 3 >• <in < o D: * _ico a « o o a.o < E u>œ a. »- ui s: »- v«01 E o tn Qa LU u uj uia: z »- cc i v- ceo •-< < o o< U. E Ui Z Z (E•c. LU < _J uj < cex en a ce o r tr ui-

UJz i^ «r N ft N na o -o i*, o * <o

H U.(na i i i i i iUJ O «f r» «0 N GOi- ua. nr <U) V-

226

SMP TEST XMACRO 8083 16-JUN-83 13:57 PAGE 2CROSSMACRO 8089

1 .TITLE SMP TEST23 J4 )3 ) AUTHOR: V. SRISANANe>7 : DATE: 11-MAY-838 i9 J VERSN =• 110 ;11 i PROGR.NAME: MEMMTST.MAC12 ;13 >14 ;13 j DESCRIPTION:16 i PROGRAM TEST FOR HP_EXTENSION IAEA PROJECT17 ) KFA 2EL-NE ...18 ;19 i COMMANDS:20 ;21 ; ASSEMBLY PARAMETERS:22 ) NONE23 ;24 ,- SUBROUTINES:23 ; NONE26 )27 ; WARNINGS:28 J NONE29 ;30 ;31 i MODIFIED:32 >33 i3433

K>N>-J

toto SMP TEST XMACRO 8085DEFINE PARAMETERS

3738394041424344454647 004000484950 00540O51525354 00002055 00071056 00075137 00003058 0020605960 OO576061 00577262

16-JUN-83 13:57 PACE 3

0800

OBOO

.SBTTL DEFINE PARAMETERS«««»ft***********************************************************

USER PROGRAM AREARESTART LINKSUSER DATA STORAGE AND STACKMONITOR USED AREA

6116 RAM

;1;i

ii ******

MEMSIZiiDISBUF

H0800 -HOAEF -HOBOO -HOBB1 -*********- Hoaoo» HOBOO

HOAEEHOAFFHOBBOHOBFFt*****-; 2K:

i GLOBAL DEFINE» HP UTILITY ROUTINE

001001C801E900180430OBFOOBFA

BEEPSOSDCDSTDMDELB» HPUDSPDDSPj

»mmmat

HOOIO ;H01C8 iH01E9 iH0018 iH0430 >

BUFFER AREAM

aHOBFO iHOBFA t

BEEP, CAN BE CALLED BY RST_2 COMMANDSCAN DISPLAY SEGMENTSDISPLAY CHARACTER DECODERSTORE DISPLAY MESSAGEVARIABLE DELAY SUBROUTINEUNDECODED DISPLAY BUFFER ADDRESSDECODED DISPLAY BUFFER ADDRESS

SMP TEST XMACRO 8085 16-JUN-83 13:57 PACE 4RAM TEST ROUTINE

64 SBTTL RAM TEST ROUTINE6566 l PROGRAMM START POINT676869 OOOOOO 0000 ORG H080070 004000 0800 TSTRAM:71 i72 004400 0900 START - H090073 004402 0902 COUNT » START +274 004404 0904 PTTRN - COUNT +275 s

toto

toWoSUP TESTCLEAR MEMORY

XMACRO 8085 16-JUN-83 13:57 PAGE 5

777879SO8182838485868788899O919293949596979899100

. SBTTL CLEAR MEC-004000004003OO4004O04O07004011004012004013OO4O16004017

004022OO4025004026004031004032O04O33004036004037004040004043004044

052353052066043015302005302

052353052257276302043015302005302

002OOO000

O07007

002000

210

032032

OllOil

O10010

OilOil

01O

O1OO10

0800O803080408070809080A080BOBOE080F

0812081508160819081A081B081E081F082008230824

2AEB2A3623ODC205C2

2AEB2AAFBEC223ODC205C2

020000

0707

0200

88

1A1A

0909

0808

0909

08

0808

CLRMEM: LHLD COUNT jXCHGLHLD

CLRLP: MVIINXDCRJNZDCRJNZ

ii CHECK FOR

LHLDXCHGLHLDXRA

CLCHKL: CMPJNZINXDCRJNZDCRJNZ

i

STARTM, 0HCCLRLPBCLRLP

MEMORY CLEARCOUNTSTARTAMERRORHCCLCHKLBCLCHKL

;;ii

t

i

1

;i

ii

i

LOAD COUNTTO DESTART ADDRESS TO HLCLEAR 1 LOCATION POINT BY HLPOINTER TO NEXT LOCATIONTEST IF LOOP FINISHED

NO: LOOP AGAIN

LOAD COUNTSTART ADDRESSCLEAR ACCCOMPARE MEMORY DATAIF ERROR, DISPLAY ERROR ADDRESSTEST IF LOOP FINISHED

SMP TESTMEMCHECK

1021031041O91061071081O911011111211311411911611711811912O12112212312412312612712812913O131132133134139136137138139140141142143144

004047004O92OO4O93004094004037OO4060OO4O63004064OO4069004070004071004072004079004076004O77004102004103004104004 1O7O04110OO4113004116004117OO412OOO4123OO4124OO4123OO4130004133004134004137OO4142OO4143004144004143OO4146OO4191004192

XMACRO 8085 16-JUN-83 13:57 PACE 6

. SBTTL); DE - ADR) HL - ADR2

0521191O40323330720223O30921191040522972763020430193020093023031732793021722743O2072226302303022023301019302009302

002

OOO004

002

000

116

O76076142

210

210O04210102

060060

Oil

OilOil

Oil

Oil

010

O10010010

010

010Oil010010

010010

0827082A082B082COB2F083008330834083908380839083A083D083E083F08420843084408470848084B084E084F08900893089408330838083BOS9C083F086208630864086908660869086A

2A4D442AEB3A12C32A4D442AAFBEC223ODC209C2C37BBDC27ABCC23A96C2C31213ClODC209C2

02

0004

02

00

4E

3E3E62

88

88048842

3030

09

O909

09

O9

08

0808OB

08

O8090808

08O8

iLHLDMOVMOVLHLDXCHO

LP1: LDASTAXPUSHLHLDMOVMOVLHLDXRA

LP2: CMPJNZ

ELP2: INXOCRJNZDCRJNZJMP

NTZERO: MOVCMPJNZMOVCMPJNZLDASUBJNZJMP

CLP1: STAXINXPOPDCRJNZDCRJNZ

MEMCHECK

COUNTC,LB,HSTARTPTTRNDBCOUNTC,LB,HSTARTAMNTZEROHCLP2BLP2CLP1A- ELERRORA, DHERRORPTTRNMERRORELP2DDBCLP iBLP1

i

i

i

i

i

t)

i

t

)

9

i

i COUNT -> BC

i LOOP ADR -> DE.<ADR> <- TEST PATTERNLOOP ADR2

.LOOP ADR2 - SAD.EAD

..IF <ADR2>#0

...RAM ERROR

.IF ADR2=ADR

..IF <ADR2>#PATTERN

...RAM ERROR

..<ADR> <- OEND LOOP

toSMP TESTRAM TEST OK

14714814915015115215315415515615715815916O161162163

004133004136004161004163O04164OO4166004167004171004172OO4174004175004177004200004202004205

XMACRO 8085 16-JUN-83 13: 57 1

327041066053066053066053066053066053066315303

377 013253243367206257257310 001202 010

086D086E0871087308740876O8770879087A087C087D087F088008820885

D721362B362B362B362B362B36CDC3

FFABA3F786AFAFce82

OB

0108

DISPOK:

. SBTTLRSTLXIMVIOCXMVIOCXMVIDCXMVIDCXMVIDCXMVICALLJMP

RAM TEST2 ;H, DDSP+5M, HAB ;HM, HA3 )HM, HF7 ;HM, H86HM, HAFHM, HAF iSOS ;DISPOK ;

OKCALL"N"IIQII

II II

II P II

"R"11 R "SCAN

BEEP; POINTER TO DECODEDi NO ERROR MESSAGE

DISPLAY SEGMENTSCONTINUE

DISPLAY DIGIT

SMP TESTERROR DISPLAY

XMACRO 8085 16-JUN-83 13:57 PACE 8

165166 004210167 004213168 OO4214169 O04216170 004217171 OO4220172 004221173 004222174 004223175 OO4224176 004225177 004226178 004227179 004230180 004231181 OO4232182 004235183 004236184 004237185 004240186 OO4241187 OO4242188 004244189 004245190 004246191 004247192 004251193 004252194 004253195 004256196 004261197 004262198 004265199 00427020O202

021106016257051027051027051027051O27022033015362170007OO7007007346022033170346022327001315OO53O2315303

365 013003

216 010

017

017

200 020351 001256 010060 004252 010

0888OB8BOB8C088E088FOB90089108920893OB94OB950896089708980899089A089D089EOB9F08AO08A108A208A408A508A6OBA708A908AA08AB08AE08B108B208B508B8

OOO001

11 F5 OB ERROR:46OE 03AF ERRLP:291729172917291712IBODF2 BE 087807070707E6 OF12IB78E6 OF12D7 DISBP:01 80 10 DISLP:CD E9 01 DISP:O5C2 AE 08CD 30 04C3 AA 08

iOOOl

. SBTTLLXIMOVMVIXRADADRALDADRALDADRALDADRALSTAXDCXOCRJPMOVRLCRLCRLCRLCAMISTAXDCXMOVAN ISTAXRSTLXICALLDCRJNZCALLJMP. END

ERROR DISPLAYD, UDSP+5B.M ;C, 3 ;AH i

»H ;

HHDD ;C jERRLP tA. B ;

HOF iD jD jA. B ;HOFD2 ;B. H 1080 ;DCD ;BDISPDELB ;DISBP ;

; POINTER TO DISPLAY BUFFERGET READOUT DATASET 4 DIGITS COUNT DOWNCLEAR ACCSHIFT MSB OF ADDRESS INTO CTHEN INTO A4 TIMES

STORE DIGITPOINTER TO NEXTCOUNT DOWN DIGITMORE DIGIT GO BACKGET FIRST DIGIT

MASK 4 BITSTORE ITPOINTER TO NEXT LOCATION IN BUFFERNEXT DIGIT

CALL BEEPSET DELAY TIMINGDISPLAY MESSAGE

FLASHINGAGAIN

tou>u>

toOJ SMP TESTSYMBOL TABLE

XMACRO 8085 16-JUN-83 13:57 PAGE 9-1

ABBEEPCCLCHKLCLP1CLRLPCLRMEMCOUNTCYDDCD. ABS.ERRORS

- 000007» OOOOOO=» O00020- OOOO01OO4032004142O04007OO4000

- OO4402- OOOOOO- 000002- OOO751OO4273OOOOOODETECTED:

DDSP -DELS -DISBPDISBUF-DISLPDISPDISPOKE -ELP2ERRLPERRORH -

0000010

005772O02060004252005400OO4253O04256004202OO0003OO4102004216O04210000004

VIRTUAL MEMORY USED: 10450 WORDS < 41 PAGES)DYNAMIC MEMORY: 19748 WORDS < 75 PAGES)ELAPSED TIME: 00:00:16C3MEMTEST,CDMEMTEST-MEMTEST

HAB - 000253HAF » 000257HA3 - 000243HF7 - 000367HOBFA - OO5772HOBFO - 005760HOBOO - 005400HOF - 000017HO010 » OO002OH0018 « 000030HO1C8 - OOO710H01E9 - 000751

H0430 =H0800 =H0900 =H1080 =H86LLP1LP2MMEMSIZ=NTZERO

002060004000004400010200000206OOO005004060004076000006004000004116

PRPSW »PTTRN -SDSSNSPSTART -STDM -TSTRAMUDSP -ZE »

000003000006O04404000710000002OO0006004400OOOO3O004000005760000001

MEMTEST CREATED BY MACRO ON 16-JUN-83 AT 13:57SYMBOL CROSS REFERENCESYMBOLBEEPCLCHKLCLP1CLRLPCLRMEMCOUNTDCDDOSPDELSDISBPDISBUFDISLPDISPDISPOKELPSERRLPERRORLP1LP2MEMSIZNTZEROPTTRNSDSSTARTSTDMTSTRAMUDSP

VALUE- 000020004032004142004O07004000

- 004402« 000731» OO5772* 002060004252

- 005400004253004256OO4202OO4102004216004210004060004076

» OO4000004116

- 004404« O00710» 004400* 000030OO4000

« 005760

REFERENCES#3-54#5-936-127

#5-81#5-78#4-73#3-56#3-61#3-58#8-193#3-50#8-194#8-195#7-161#6-122#8-1695-94#6-112#6-120#3-476-121#4-74#3-55#4-72#3-57#4-70#3-60

5-97#6-1385-844-748-1957-1498-1988-199

8-1977-1626-1378-1816-1306-1426-124#6-1286-1127-1614-73

8-166

5-995-865-78

6-1336-1446-126

6-1345-80

PAGE 1CREF V01

5-89 6-107 6-115

6-136 #8-166

5-91 6-110 6-118

to

Hints on trouble-shootingRun a program to clear all the memory locations. Read back all thelocations. If all locations contain a zero proceed to test number 2.However, if all locations read a 1 it means that a bus driver isdisabled. Take a scope and check on pin 19 of in. Also check all thechip select signals.

Run a test program to write a bit pattern 10101010 to all the memorylocations. Read back all locations. If same data is there proceed totest number 3. If not, then check the logic signals on the board. For

Contents ofMemory

Second Run

255,. 511,.

Address

766,no)Fig. VI. 12 Checking the memory

example you read 00101010 always. It shows that the two highest bitsare probably short circuited. To locate the chip on which this shorthas occured switch off the memory chip one by one (use switch array S2)and run the program until you locate it. If the error is not locatedon any memory chip it indicates that the short circuit is on the driverside.

3. For a thorough checkup of the memory run a program which writes a datawith the ramp pattern. As shown in the diagram the first location hasa zero the second a one and so on up to location 255 (decimal) whichhas data word 255 in it. Read back all the memory locations and verifythat the pattern was successfully written. For a second run shift thepattern by one i.e. on location 0 a 1 is stored and so on. Verify inthe same way and proceed for a second run.

Hints to use test Programm from EPROM

Normally the students are supposed to key in the test program in the HPkit. However one may load the program in an EPROM and put it on a socket ofmemory board also. One such program has been loaded on the EPROM suppliedwith the memory board. A small program starting from location 0 on the chiprelocates the following test program to start from location 0800. Hence theprogram can test all the 16K memory. Following are the hints for a user.

1. Plug the EPROM in the socket M8.

2. Set the board address BOOO i.e. on SW1 switches 1,3 and 4 are ON andswitch 2 is OFF. Set all the switches on SW2 ON.

3. Fetch address E800 and press RUN key. The test program is relocated inthe HP kit's RAM area starting from location 0800.

236

4. Store the following data:LOCATION DATA

0900 00 START-ADDRESS low byte0901 BO START-ADDRESS high byte0902 FF END-ADDRESS low byte0903 B7 END-ADDRESS high byte090A AA PATTERN (AA, 55, FF etc.)

Note: The memory area to be tested has to be selected by giving appropriateaddress limits as given in the example above.

5. Run the program from location 0800. The memory area between start andend addresses shall be checked by writing and reading the test patternin every location. If the test is successful the u-lab gives a beepand displays "no Err". If the program sees an error in reading orwriting data pattern the display blinks "Err". If the program sees anerror in reading or writing data pattern the display blinks the addressof the memory location in error +1 and gives a beep. The test programneeds execution time of the following order.

2k memory 1.5 minutes4k memory 5 minutes6k memory 25 minutes

Step 5 Installation informationThis chapter contains instructions for installing the ZEL-NE 465 add-on

memory. Please read the entire chapter before attempting the installation.This chapter is organized in three parts as follows:

Pre-InstallationInstallationCheckout of memory card.

1. Pre-installation

Prior to installationm check for compliance with the requirements asfollows:

1. Adequate number of slots for boards2. Adequate power supply capacity for all units3. Adequate equipment for checkout

VoltmeterOsciloscopeField engineer tool kit (soldering iron, screw driver, etc.)

2. InstallationCheck all parts when received, inspect for any damages. Do not apply

power to any unit which has been damaged.

Check all power pins with a voltemeter before plugging the board intoits slot. The pins marked GND in table 2.1 should read zero volts and thepins marked +5V in Table 2.1 should read +5 volts +5%.

237

For SMP bus connector pin assignment refer to Special Project IV.Check starting address switch (SI) for the appropriate starting

address. See Table VI.2.Check chips select switch (S2) for the used memory chips. See Table

VI. 3.

Table VI.2. Address dip switch setting

StartingAddress04K8K12K16K20K24K28K32K36K40K44K48K52K56K60K

-1Switch SI-2 -3 -4

OffOffOffOffOffOffOffOffOnOnOnOnOnOnOnOn

OffOffOffOffOnOnOnOnOffOffOffOffOnOnOnOn

OffOffOnOnOffOffOnOnOffOffOnOnOffOffOnOn

OffOnOffOnOffOnOffOnOffOnOffOnOffOnOffOn

Table VI.3. Chip select switch setting

Switch S2 Memory chips Address-1-2-3-4-5-6-7-8

MlM2M3M4M5M6M7M8

StartStart +Start +Start +Start +Start +Start +Start +

2K4K6K8K10K12K14K

Insert the board into its slot and apply power,checkout procedure.

Checkout of Memory Card

Then proceed to the

After installation a complete on-line test should be run. The memorydiagnostics will provide an adequate check on the memory board. Howeverdiagnostics should also be run on all other components of the system. If afailure occurs, refer to the next chapter of this manual (Theory ofoperation and maintenance).

Step 6; OperationThis chapter describes the inputs and outputs, operation flow charts

and timing diagrams.

238

Inputs and outputs. The ZEL-NE 465 receives three inputs from the SMPBus: /MEMR, /MEMW, /MMIO, address and write data. It returns read data.

SIGNAL NAME

/MEHR

/MEMW

/MMIO

DATA 0-8

ADRESS 0-15

INPUT/OUTPUT

Input

Input

Input

Input/Output

Input

DESCRIPTION

This signal is low to indicate aread cycle.This signal is low to indicate awrite signal.

This signal is low to indicatethe I/O page.Data is transferred between thememory and the SMP Bus processoror 8 bidissectional data lines.The processor supplies 16address inputs. They are usedas follows :

AO-10 Internal chip addressA11-A15 Card and chip select

Modes of operation. The ZEL-NE 465 is operating in one of threemodes: READ (non-destructive), WRITE and standby. Normally it will be instandby mode until it receives a read or write signal from the bus.

Read cycle. Read cycles are determined by the status of the /RDcontrol line. When /RD goes low the data stored previously at the addressspecified by the address inputs will be transferred to the output data buslines. The contents of the memory will not be altered.

Write cycle. Write cycles are determined by the status of the /WRcontrol line. When /WR goes low, the data on the input bus will be writteninto the address specified by the address inputs. The contents of the restof the memory will not be altered.

Standby mode. When the board is not addressed it will go into standbymode and wait for the next control cycle.

Timing Diagram. The timing diagrams are shown in Pig.VI.13 and Fig.VI.14t cycle --------

Validaddressand MMIO

MEMR

I/™"™\____

|<- t rdl ->D out ————————————————— <

Read Cycle TimeOutput Enable to Output ValidChip Disenable to Output in High

|<- t o/~V.-

trctoetohz

hz ->\/

12010050

ns min.ns max.ns max.

Fig. VI.13 Read Timing Diagram

239

t cycleValidaddressand MMIO

xxxxxxxxxxxxxxx<- t dw -> | <- t dh ->

XXX

MEMW

D in

Write Cycle Time tc 120 ns min.Data to Write Time Overlap tdw 40 ns min.Data Hold from Write Time tdh 10 ns min.

Fig. VI.14 Write Timing Diagram

Board addressing. The block diagram on Fig. VI.1. shows two sets ofaddress lines coming from the SMP BUS. The first set (AO-A10) is used fordevice addressing. The second set (A11-A15) is used for board addressing.See logic schematics. This address line is buffered by U2 and U3. Addresslines A11-A15 are sent to adder and decoder for memory device addressing U5and U6 and the outputs of the decoder are sent through switch S2 to enableeach memory device and then to the U7 "or" gate, the output signal from this"or" gate indicates that the board is addressed and gated by /MMIO todisable the board when it is in memory mapped Input/Output space. Theoutput signal is used to enable the data buffer Ul.

Device addressing. As discussed in the previous section, address linesAO-A10 are brought onto the memory board from the SMP Bus to the buffers U2and U3. The outputs of these buffers AO-10 are sent to the memory devicesfor device addressing.

Timing and control. Since this memory board uses static memory devicethere is no critical timing circuit, every control signals control the boardfunction directly.

OPERATION

There are 3 control signal lines: /MEMR, /MEMW, /MMIO. /MEMW isbuffered by gate U4 and U5. The gate U5 is an open-collector gate which isused because in case the board is populated by EPROMs, EPROMs from somemanufacturers send interering signals through the Vpp pin, while this pin incase of RAM is used as /WR sdignal pin, therefore the open collector gatehas to be used to isolate this interferation. /MEMR is also buffered bygate U4 and gated by the /MMIO signal to diable the read function if theboard is in MMIO space. The output from gate U4 and pin 8 is sent to memorychip M1-M8 pin 20 and the data buffer pin 1 to control the direction of thedata flow.

Data transfer. The Data transfer logic uses the TRI-State buffer Ul.The "enable" of this buffer is controlled by the board addressing logic.The direction of the data transfer is controlled by the READ signalgenerated from the /MEMR and the /MMIO control signal.

240

Step 7; MaintenanceEquipment needed for testing and maintaining the memory card is listed

below:1. Oscilloscope2. Voltmeter3. P.E. Tool kit - soldering iron, wires, etc.4. Diagnostic Programs

If any problem arises, the following general procedures should beobserved:1. Check the power supply and make sure it complies with the

specifications.2. Make sure the card is properly mounted in its connector.3. Check for obvious causes of failure, such as faulty connectors, loose

wires, etc.4. Check the inputs to the memory. I/O connections are listed in the

table "Interface Pin Assignments".5. Run diagnostic tests and check for a failing memory chip as described

below.

After running the diagnostics, the error mode must be defined. Thethree most likely problem areas are:

1. Memory devices2. Address selection and buffer circuit3. Data buffers

The following procedure is recommended for isolating a failing memorychip.1. Run diagnostic programs to isolate the failing address and data bits.2. Determine on which board the failure has occured.3. To identify the failure on that board down to a particular memory

device, the on board address is derived by taking the memory addressand subtracting the starting address from it. The result divided by 2Kis the number of the failing memory device.In many instances the error indicates that more than one memory

location or address fails. In these cases the problem will not be caused bya single memory device but more likely will be part of the circuitry whichaddresses or controls the memory board. This section will aid in findingand solving problems in the addressing circuitry.

Board addressing is described in detail in the section "Operation ofboard addressing" and this section should be reviewed before going furtherinto troubleshooting. The most probable cause of failures will be fromincorrectly set switches. Problems involving adderessing sometimes may becaused by improper seating of board or by corrosive build-up on contacts.

241

Some problems, however, will be due to a failing chip. In this instance itis best to use the diagnostic error outputs to gather information fordetecting and isolating the problems.

Data buffer failures will show up on diagnostic error outputs as adata-bit being incorrect in all addresses, if the failure is on a singlegate. If the complete chip fails, then the failure will show up as an alldata bit error.

242

PARTS

DATASHEETS

LM78LXX Series

Voltage Regulators

LM78LXX series 3-terminal positive regulators

general descriptionThe LM78LXX series of three terminal positive regu-lators is available with several fixed output voltagesmaking them useful m a wide range of applicationsWhen used as a zener diode/resistor combination replace-ment, the LM78LXX usually results in an effectiveoutput impedance improvement of two orders of magni-tude, and lower quiescent current These regulators canprovide local on card regulation, eliminating the distribution problems associated with single point regulationThe voltages available allow the LM78LXX to be used inlogic systems, instrumentation, HiFi, and other solidstate electronic equipment Although designed primarilyas fixed voltage regulators these devices can be usedwith external components to obtain adjustable voltagesand currents

too high for the heat sinking provided, the thermalshutdown circuit takes over preventing the 1C fromoverheating.

features• Output voltage tolerances of ±5% (LM78LXXAC) and

+ 10% (LM78LXXC) over the temperature range

• Output current of 100 mA

• Internal thermal overload protection

• Output transistor safe area protection

• Internal short circuit current limit

• Available m plastic TO 92 and metal TO 39 lowprofile packages

The LM78LXX is available in the metal three leadTO 39 (H) and the plastic TO 92 (Z) With adequateheat sinking the regulator can deliver 100 mA outputcurrent Current limiting is included to limit the peakoutput current to a safe value Safe area protectionfor the output transistor is provided to limit internalpower dissipation. If internal power dissipation becomes

voltage rangeLM78L05LM78L06LM78L08LM78L10

5V6V8V

10V

LM78L12LM78L15LM78L18LM78L24

12V15V18V24V

connection diagrams

Metal Can Package Plastic Package

Order Numbers - Order NumbersLM78L05ACHLM78L06ACHLM78L08ACHLM78L10ACHLM78L12ACHLM78U5ACHLM78L18ACHLM78L24ACH

LM78L05CHLM78L06CHLM78L08CHLM78L10CHLM78L12CHLM78L15CHLM78L18CHLM78L24CH

LM78L05ACZLM78L06ACZLM78L08ACZLM78L10ACZLM78L12ACZLM78L15ACZLM78L1BACZLM78L24ACZ

LM78L05CZLM78L06CZLM78L08CZLM78L10CZLM78U2CZLM78L1SCZLM78L18CZLM78L24CZ

See NS Package H03A See NS Package Z03A

245

IO4*.o\

absolute maximum ratingsInput Voltage VQ = 5V to 8V

V0 = 12V to 18VVO = 24V

Internal Power Dissipation (Note 1)Operating Temperature Range

30V35V40V

Internally Limited0°C to «-70'C

Maximum Junction TemperatureStorage Temperature Range

Metal Can (H Package)Molded TO-92

Lead Temperature (Soldering, 10 seconds)

-65°C to*150°C-55° C to+150°C

300° C

00XX

0LM78LXXC electrical Characteristics (Note 2) Tj = 0 Cto+125"C, lo = 40mA, C|N = 0.33^F,Co = (unless noted)

LM78LXXC OUTPUT VOLTAGEINPUT VOLTAGE (unit» otherwise noted!

PARAMETER

VQ Output Voltage(Not« 41

AV0 Line Regulation

AVQ Load Regulation

-}VQ Long Term StabilityIQ Quiescent Cuffem

•ilQ Quiescent Cu"«nt

Change

Vn Output Noise Voltage

•*v,N^VOUT

Input Voltig«Required to Maintain

Line Regulation

CONDITIONS

Tj • 25 C1 mA |Q 70 mA Of

1 mA •' IQ •- 40 mA jnn _WIN

Tj 25 C

Tj 25 C 1 mA IO 40mA

Tj = 25 C 1 mA ' IQ . 100mA

Tj - 25 C

Tj- 125 C

Tj « 25 C 1 mA-_ IO 40mA

Tj • 25'' C

Tj . 25 C !Note3if - 10 H/ - 10kH;

1 = 125 Hi

Tj . 25 C

5V10V

MIN TYP MAX

46 5 54

45 55

I7< V|N v. 201

10 150

'8 •; V IN-_ 20118 20C

17 < V|N < 201

5 3020 60

123 6

55

0?1 5

i8< VIM < 201

40

40 60

(8< VIM < 18)

7

6V11V

MIN TYP MAX

55 6 65

54 66

185- V IN 211

10 15019- V|N- 211

18 200

( 8 5 - - ViN-^211

6 3522 70

IS3 6

55

021 5

(9-: VIN< 211

50

38 58(9< VIN< 19)

83

8V14V

MIN TYP MAX

7 36 8 8 64

72 88

(10 5' VIN •; 23l

12 150(11 • VIN 231

20 200(10 5- VIN^ 23l

8 4025 80

203 6

55

021 5

(II •_- VIN< 231

60

36 55(12 < VIN< 23l

105

10V17V

MIN TYP MAX

92 10 108

90 11

(13 • V|M<_ 25l

16 175

114 <: VIM'' 25l25 225

(13 < VIN'_ 25l

9 4527 90

223 6

55

021 5

(14-; VIN < 251

70

36 53114 <-. VIM< 251

13

12V19V

MIN TYP MAX

11 1 12 129

108 132

114 5< V|M< 271

20 200I16< VIN< 271

30 250114 5< V|N<27)

10 5030 100

243 65

6

021 5

(16 < VIN 271

80

36 52115-r VIM< 25l

145

15V23V

MIN TYP MAX

138 15 162

135 165

(18 < VIM < 301

25 250120 < VIN < 301

30 300I18< V|N<30)

12 7535 150

3031 65

6

021 5

(20 -C VIN < 301

90

33 49185CV|N<285)

18

18V27V

MIN TYP MAX

166 18 194

162 198

(2l 4 < VIN < 331

27 275

122 < VIN < 33)32 325

121 4 < VIN < 33)

15 8540 170

4531 65

6

021 5

(22 < VIN < 33l

150

32 46(23 < V|N<33)

21 4

24V33V

MIN TYP MAX

22 1 24 25 9214 264(28 < VIN < 381

30 300(28 < VIM < 381

35 350127 5 < VIN < 38)

20 10040 200

563 1 65

6

0215

(28 < VIN < 381

200

30 43(29 < VIN < 35)

275

UNITS

V

V

V

mV

V

mV

V

mV

mV

mV/1000 hr«mA

mAmA

V

*"V

dBV

V

Not« 1: Thermal resistance of the Meial Can Package (H) without a heat sink is 15&C/W junction to case and 14(TC/W junction to ambient Thermal resistance of the TO-92 package n 180°C/W junction toambient with 04" leadf from a PC board and 160&C/W junction to ambient with 0 125" lead length to a PC board.Not« 2: The maximum steady state usable output current and input voltage are very dependent on the heat sinking and/or lead length of the package The data above represent pulse test conditions with functiontempératures as indicated at the initiation of testNot* 3. Recommended minimum load capacitance of 0 01;iF to limit high frequency noise bandwidthNot* 4: Th* temperature coefficient of VQ^T is typically within '001% VQ/"C

absolute maximum ratings

Input Voltage VQ = 5V to 8VVO = 12V to 18VVO = 24V

Internal Power Dissipation (Note 11Operating Temperature Range

30V35V40V

Internally Limited0"C to +70"C

Maximum Junction Temperature 125'CStorage Temperature Range

Metal Can (H Package) -65" C to +150°CMolded TO 92 (Z Package) 55°C to +150* C

Lead Temperature (Soldering, 10 seconds) 300°C

LM78LXXAC electrical characteristics (Note 21 Tj = o"cto+i25"c. 033/^.00 (unless noted)

LM78LXXAC OUTPUT VOLTAGEINPUT VOLTAGE luntoi othtnuiM nolMI

PARAMETERVQ Output Voltage

INol«4l

AVQ L in« Regulation

•iVQ Load Regulation

.WQ Loog Te»m Stability

IQ Qui«cent Current

.IIQ Qu'ncent Current

Chjncf

V„ Output None Voltage

•iVIN

•IVOUT n'W'' R"~''""

Incut Voltage

Required to MaintainLin* Regulation

CONDITIONSTj 25 Ct mA • IO • JO mA

1 m A - IQ • 40 mA anrt

VMIN ' VIM'' VH«AXTJ • 25 c

Tj 25 C 1 m« • IQ' 40mA

Tj 25 C 1 mA IQ' 100mA

Tj 25 C

Tj 125 C

1 mA (Q- 40mA

VMIN' VIM- VMAX

Tj - 25 C (Note 3iI - 10 H/ 10 liH/

1 • I?OH/

Tj ' K C

5V10V

MIN TYP MAX

48 !> -i24 76 5 25475 525

(7- V IM- 70i

10 5418 VIM ?0i

18 7517 V|N- 20>

5 30?0 60

1?

3 54 7

0 t10

18 VIM 201to

47 6?(8- VIM 161

7

6V11V

MIN TYP MAX

5 75 6 6 ?66 1 635 7 6 3(S3- VIM- 2»

10 68(9- VIN ?"

18 90183- V,N 71.

6 3522 '0

15

3 64 7

0 1

- 1 0(9 VIM 2i i

50

45 60

19 V IM- 'Si

83

8V14V

MIN TYP MAX7 7 8 8 376 8476 84( 1 0 5 - VIM ?3'

1? 85HI VIM ?1

20 100il05 VIM 33

8 402b 80

20

3 54 ?

0>

1 0ut VIM ?3

60

43 57112- V IM ' 23

105

lov17V

MIN TYP MAX

96 10 10495 10595 105"25- VIM 25i

16 105•13 VIM 25>

?5 140' 1 2 5 V IM- 25

9 4527 90

22

3 54 7

0 (1 0

•13 VIM 25i

70

41 55H3 V , M - 25i

125

12V19V

MIN TYP MAX

11 5 12 125114 126114 1261 1 4 5 - VIM- 271

JO 110116- V IM- 271

30 1801 1 4 5 - VIM- 27i

10 50 •30 100

24

3 54 ?

0 f1 0

i t 6 - V IM- 27180

40 54H5- VIM v 25>

145

15V23V

MIN TYP MAX144 15 15614 25 15 761425 1575

11 7 5-- VIM •'SOi

25 140120- VIM" 301

37 2501 1 7 5 - VIN 30i

1? 7535 150

30

3 1 64 7

0 »1 0

(20- VIM^ 30l

90

37 51I185'_, VIN< ?85i

175

18V27V

MIN TYP MAX17 3 18 18 717 1 189171 189

120 7 -- VIM -- 33l

35 190'?! • V IM" 33l

45 275120 7 ' V,M-_ 33i

15 8540 170

45

3 1 54 7

0 11 0

IÎ1 v VIM-. 331

ISO

3« 48(23 •_ VIM-; 33i

207

24V33V

MIN TV» MAX23 24 2622 8 J5 222 8 25 2127- VIM' 38i

50 200128' V IM" 38.

60 300127 •_ VIM:; 38'

20 '0050 200

56

3 1 54 7

011 0

128- VIM • 381

200

34 45129-.- VIM •> 351

27

UNITS

V

V

V

V

mV

V

mVV

mV

mV

mV 1000 hn

mA

mA

V

UV

OBV

V 00ExC/>

(flK)•fe.-vl

Not» 1: Thermal rejulance of the Meial Can Package |H) without a heal sink is 15 C.W junction to case and 140 C-'W junction to ambient Thermal resistance ol the TO-92 package is 180 C/W function toambieni with 04" leads from a PC board and 160'C/W junction to ambient with 0 125" lead length to a PC boardNot* 2: The maximum steady state usable output current and input voltage are very dependent on the heat sinking and-Or lead length of the package The data above represent pulse test conditions with junctiontemperatures at indicated at the initiation of testNot« 3: Recommended minimum load capacitance of 0 OlwP to limit high frequency none bandwidthNot« 4: The temperature coefficient of VQUT " typically within -001% Vo/°C.

LM78LXX Series

typical performance characteristics

Maximum Average PowerDissipation (Plastic Package)

0125 LEAD LENGTHFROM PC BOARDWITH 72 CM H£AT SINK

04 LIADLENGTHFROM PC BOARDFREE AIR

i 0125 LEADLENGTH— I ~~ FROM PC BOARD

FREE AIR

15 10 45 ED

AMBIENT TEMPERATURE I C)

Maximum Average PowerDissipation (Metal CanPackage)

j; 10aa: 05

01

NO HEAT SINKt

WITH 30 C/W HEAT SINK

15 30 45 60

AMBIENT TEMPERATURE ( C)

Peak Output Current

0 5 10 15 20 25 30

INPUT OUTPUT DIFFERENTIAL (V)

Dropout Voltage Ripple Rejection

0 5

0 25 50 75 100 125

JUNCTION TEMPERATURE ( CI

RIPP

LE R

EJEC

TIO

N Id

B)

OO

^

0>

CO

C

0

D

0

0

C3

C

VN 10VV0u, ' 5VIOUT 40 itTA '25 Cl l 11 I

A

1

-

*<<

D 100 H 10k

FREQUENCY IHil

s

10

10

50

1 0

O S

Output Imp«

:V,N 10V •

' 'OUTTA 2

————

—— __

5 C1 ————Coui

»dance

Cn,

„F TANTALUM

y_/

,T *1

:/=

r ———

10 100 Ik I Ok 100k IM

FREQUENCY IH;)

Quiescent Current Quiescent Current

36

3 4

3 230

2l

2 6

24

Z ?20

I

~

1

L

?»

——

•—— • f-^f

-

f~— ——— i—— •

V0

ICHTj

P—— • ^ «••

UT * 5V .,, 40mA

2S Ci i

10 15 20 25 3

INPUT VOLTAGE (VI

33323l

302 9

2 l2 7

2 6

? d

—

XX—

X

v,*VOL'ou

X

10V, 5V

r • 40

———

X

nA —

- ———

X25 SO 75 100 125 150

JUNCTION TEMPERATURE ( C)

248

LM78LXX Series

equivalent circuit

LM78LXX

typical applications

INPUT ——-—A .—— LM7ILXK - . * • OUti

„. J_ °"° JL a-—r—

•R*4«tfH tf A« ftfubtM it to<4li4 IM trwn ito powtf Mpplv I'll«

VOJT 'SVIiV/fll • I0IBI

&V/R1 • >IQ !M4(ttuUiiM (L,l - HRI ' RD'RII U. «l LM7IIM1

Fixed Output Regulator Adjustable Output Regulator

249

LM78LXX Series

typical applications (con't)

'out - IV71/HM • (u

.1 10 ' t S mA o»t» tint ind \oti chtn

Current Regulator

A Q Voui • W AT 400 MA

iinilsum•'Hcjrtinh 01

••Qptiorul 1mp<0vn itppJ* rffvtnort ind lunucnl mponi*

L oit RctulihDit 0 6% 0 _ lt _ îiO mA »utwd with I0h - SO T

5V. 500 mA Regulator with Short Circuit Protection

O WOUT- i S V A T l D O m A

C4001.,F

-V IN > -20V |

*Solid linului

H--— H

Lx-

h ——— l

-N

IMIIL15H

CI

C2-2 M

oi-IN4]19 A

LM320H IS

1 '

___

___

•x

u, • IWAIIMmA

• 15V, TOO mA Dual Power Supply

It if'Suljd tinraiumVoui • V0 . SV. Rl • (-V,„/I0 iumotl

V„„, SV IR2/R4I loi (R2 • Rll (R« • RS\

AOSVDulpu l wiflcoi(npon4lolR2'R4} 01 IR] /R4I-D9

Variable Output Regulator 0.5V - 18V

250

LM79XX Series

Voltage Regulators

LM79XX Series 3-Terminal Negative RegulatorsGeneral DescriptionThe LM79XX series of 3 terminal regulators is availablewith fixed output voltages of -5V, -5.2V, -6V, -8V,-9V, -12V. -15V, -18V and -24V. These devicesneed only one external component — a compensationcapacitor at the output. The LM79XX series is packagedm the TO-220 power package and is capable of supplying1.5A of output current.

These regulators employ internal current limiting safearea protection and thermal shutdown for protectionagainst virtually all overload conditions.

Low ground pin current of the LM79XX series allowsoutput voltage to be easily boosted above the preset

value with a resistor divider. The low quiescent currentdram of these devices with a specified maximum changewith line and load ensures good regulation in the voltageboosted mode.

Features• Thermal, short circuit and safe area protection

• High ripple rejection

• 1.5A output current

• 4% preset output voltage

Typical Applications;15V, 1 Amp Tracking Regulators

•v„,O

Variable Output

O VDU, Ml»

SOUO •TANTALUM

t

3LMlt

,, Li

2

Rl

R?

JL

-t 1„Fi — SOLID

TANTALUM

'Improves transient response and ripple rejectionDo not increase beyond 50iiF

O COMMONVOUT = VSET

/R1 + R2\

\ R2 /

Performance (Typical)

(-15)Load Regulation at -il|_ ' 1 A 40 mVOutput Ripple, CIM = 300ÛMF. IL = 1A lOCVVrmsTemperature Stability 50 mVOutput Noise 10 Hz < f < 10 kHz 150pVrms

O V«,, (-I1SW

1+15)2 mVlOOMVrms50 mV150,uVrms

Select R2 as followsLM7905CTLM7905.2CTLM7906CTLM7908CTLM7909CTLM7912CTLM7915CTLM7918CTLM7924CT

soon300IÏ300S247QU470127500Ik1.2k2.5k

•Resistor tolerance of R4 and R5 determine matching of (*•) and ( — ) outputs* 'Necessary only if raw supply filter capacitors are more than 3" from regulators

Fixed Regulator Dual Trimmed Supply

JL-lic,.- - p^mruT O • «> LM79XXCT

O '50V

-<3 OUTPUT

"Required if regulator is separated from filter capacitor by more than 3".For value given, capacitor must be solid tantalum. 25/jF aluminum electro-lytic may be substituted.

t Required for stability For value given, capacitor must be solid tantalum.25pF aluminum electrolytic may be substituted Values given may beincreased without limitFor output capacitance in excess of 100>iF. a high current diode frominput to output (1N4001. etc I will protect the regulator from momentaryinput shorts.

251

toC/l Absolute Maximum Ratings

Input Voltage(Vo = 5Vto18V)(VO = 24V)

Input-Output Differential5V to 8V)9Vto 18V)24V)

-35V-40V

25V30V35V

Power DissipationOperating Junction Temperature RangeStorage Temperature RangeLead Temperature (Soldering, 10 seconds)

Internally Limned0°Cto-H25°C

-65"Cto+150°C230° C I

Electrical Characteristics Conditions unless otherwise noted IOUT = 500 mA, CIN =2.2#F. COUT = IA<F. 0°C< Tj< -H25°C. Power Dissipation < 15W.

PART NUMBEROUTPUT VOLTAGEINPUT VOLTAGE lunle» otherwise specified)

PARAMETER

VQ Output Voltage

AVQ Line Regulation

AVQ Load Regulation

IQ Quiescent Current

A|Q Quiescent Current

Change

Vn Output Noise Voltage

Ripple Re/ection

Dropout Voltage

'OMAX Peak Output Current

Average TemperatureCoefficient o<Output Voltage

CONDITIONS

Tj = 25°C5mA< <QUT< )A-P< 15W

Tj = 25°C. (Note 2)

Tj = 25 C. (Note 21

5mA< lQUT< 1 5A

250 mA< lQUT< 750mA

Tj = 25 C

With Line

Wi'h Load 5 mA IQUT 1 1 A

TA = 25 C. 10H/^f< 100 H;

f = 120 Hi

Tj = 25 C IOUT - 'A

Tj = 25 C

IOUT = BmA.0 CT Tj^ 100 C

LM7905C-5V-10V

MIN TYP MAX

-48 -50 -52-4 75 -5 25

(-20< V|N<-7)

8 50(-25 < V|N< -7)

2 15<-12< V|N< -81

15 1005 50

1 2

05( 25 < VIN-_' 7)

05

125

54 66( IS^V iM^ 8)

1 1

22

0 4

LM7905 2C-52V-10V

MIN TYP MAX

-50 -52 54-495 -545

(-205^ V|N< -75)

7 501 25 < V IN< -75)

2 15( -125- : V|N-.' -85)

15 1005 50

1 2

051 25-:V|N'. 75)

05

130

54 66( 1 8 5 - VIM-' 85 )

1 1

2 2

04

LM7906C-6V

-11VMIN TYP MAX

-575 -60 -625-57 -63

(-21 < VIN< -8)

5 60( -25 < V|N^ -8)

2 20( 13-: V|N< -91

15 1205 60

1 2

05( 25 < VIM< 81

05

150

54 66

( 19<V|N< *

1 1

22

04

LM7908C-8V-14V

MIN TYP MAX

-77 -80 -83-76 -84

(-23 < VIM < -10 51

6 80( -25< VIM< -105)

2 30

( -17< V|N<-11)

15 1605 80

1 2

051 25 < VIM< -105)

05

200

54 661 2 1 5 - VIM-' 'I 51

1 1

2 2

04

LM7909C-9V-15V

MIN TYP MAX

-865 -9 -935-855 -945<-24< V|M<"-11 5)

6 80( -26< VIN< 11 5)

3 30<-18< V|N<-12>

15 1705 80

1 5 3

05<-25< V|N< 11 5)

05

225

54 66( 225< VIN< -125)

1 1

2 2

-06

UNITS

VVV

mV

V

mV

V

mV

mV

mV

mA

mA

V

mA

MV

dBV

V

A

mV/'C

Electrical Characteristics '«' 'oui '-»o0 "1/v . COUT • i»>' . o c •_ n • 1 5W

PART NUMBEROUTPUT VOLTAGEINPUT VOLTAGE (unless otherwise specified)

PARAMETER

VQ Output Voltage

-W0 Line Regulation

AVg Load Regulation

IQ Quiescent Current

^lQ Quiescent CurrentChange

Vn Output Noise Voltage

Ripple Rejection

Dropout Voltage

'OMAX pMk Output Current

Average TemperatureCoefficient ofOutput Voltage

CONDITIONS

Tj = 25 C

5mA< lQUT< 1A 'P< 15W

Tj = 25"C. (Note 2)

Tj = 25 C, (Note 2)

5mA< lQUT< 1 5A250 mA < IOUT < 750 mA

Tj = 25 C

With Line

With Load.5mA<louTS'1A

TA = 25 C. 10Hz<f< lOOHz

f = 120 Hz

Tj = 25 C. lQUT= 1A

Tj = 25 C

IOUT = 5mA.0 C<T j< 100"C

LM7912C

-12V-19V

MIN TYP MAX

-115 120 12 5-114 126

( -27<V|N< 145)

5 80( 30 < V|N<; 14 5)

3 30

(-22 < VIN< - 16)

15 2005 75

1 5 3

05(-30< V|N<-14 5)

05

300

54 70(-25< V|N<-15)

1 1

2.2

-08

LM7915C-15V-23V

MIN TYP MAX

144 150 156

1425 1575( 30-_' VIN< 175)

5 100( 30-: VIM:: 1751

3 50

( 26<r VIN'' 20)

15 2005 75

1 5 3

05

(-30< V|NrT "17 5)0 5

375

54 70

( 30< VIN< 175)

1 1

2 2

-1 0

LM7918C-18V-27V

MIN TYP MAX

173 180 187

171 189

( 33^ VIM^ 21)

5 100( 33-^ VIN •'_ 21)

5 50(-30^ VIM £ -24)

15 2405 100

1 5 3

0 5(-33 ^ VIM <_ -21)

05

450

54 70(-32 < VIM < -22)

1 1

2 2

-10

LM7924C

-24V-33V

MIN TYP MAX

-23 -24 -25

-228 -252

( 38< VIN^ -27)

5 150(-38 < V1N^ -27)

6 75(-36 < VIM^ -30)

15 2405 100

1 5 3

0 5( 38 < VIM < -27)

05

600

54 66

(-38< VIM< -28)

1 1

2 2

-1 0

UNITS

V

VV

mV

V

mV

V

mV

mV

mA

mA

V

mA

^vdB

V

V

A

mV/'C <oXX(/><D

(0<J\10

Nott 1: For calculations of junction temperature rise due to power dissipation, thermal resistance junction to ambient ("j^l is 50 C'W (no heat smkl and 5 C/W (infinite heat sink)Not« 2: Regulation is measured at a constant junction temperature by pulse testing with a low duty cycle Changes in output voltage due to heating effects must be taken into account

LM79XX Series

Typical Applications (Continued)High Stability 1 Amp Regulator

«out 10

Load and line regulation < 0.01% temperature stability < 0 2%t Determines Zener current

t tSolid tantalum•Select resistors to set output voltage. 2 ppm/"C tracking suggested

Preventing Positive Regulator Latch-Up Current Source

.v„ _i/ 1H340 Y — . —\ J Dl^v^_^/ 1N41'<— fi-i

< ! RlS in

COM —————— 4 ———————— —————

Ji, IJfl ? | 6 mA

v», — y IM»»*» y — • —

R1 and D1 allow the positdelayed relative to - V I M

+

4-

•Voui

Let i

r) —— !S,-F À

1 - i - <>1 ' r-- — IR.

- "' ' i , 1 1 • 1 - -L IMOQ1 1 ! Ï F •*• °°T II' ™" ^ "

r1] fsr --«-r L JI ! CURRENT ()

- ^ i A -1-.- "^•- .AN, T• *" \ 1 output

-Vo,,. \v___x/

ve regulator to "start-up" when WIN isand a heavy load is drawn between the ey

outputs Without Rl and 01. most three terminal regulators will not "lf)UT = 1 mA + ^—star t with heavy (01 A- 1 A) load current flowing to the negative ^ 'regulator, even though the positive output is clamped by D2

' R2 is optional Ground pin current from the positive regulator flowingthrough R1 will increase *VQ(JJ ^ 60 mV if R2 is omitted

-T ————————— I11

c,'_L± 1!5, F — y- |'o 1 —————— • ——————

1 Ui ^ 11 f^.^"' -

v,„ — i-H IMI90SC1 U-i ———— i

\^__^X

\f-"\{A

— cz— JS-F

Light Controllers Using Silicon Photo Cells

-v 1 i ' I L 1 -1 1 i A5! _ « v - i s v | | S IM» »U H X

(?Ji«i»R.o, ei. !* ««'«> L>| , > iïrCURRENT ^ f ,„,„ J ' x V JMAX,UR«O»

1 •' " T T C ' "^ " rilBRTMT1 1 Cl* --".«' CURRt'"1 J- »^-p ./i ^x r-

-A^/LM,,«crU- .-.,, 1

'Lamp brightness increases until i| = IQ ( » 1 mAI + 5V/R1.t Necessary only if raw supply f i l ter capacitor is more than 2"

from LM7905CT

Connection DiagramsTO 3 Package

Order Numbers: OUTPUTLM7905CK LM7912CKLM7905.2CK LM7915CKLM7906CK LM7918CKLM7908CK LM7924CKLM7909CK

See NS Package KC02A

•Lamp brightness increases until i| = 5V/R1 d| can be set aslow as luA)

t Necessary only if raw supply fi l ter capacitor is more than 2"from LM7905CT

TO 220 Package Order Numbcn:LM7905CT LM7912CT

output LM7905.2CT LM7915CT»"UT LM7906CT LM7918CTCNO LM7908CT LM7924CT

LM7909CTSee NS Package T03B

254

LM79XX Series

Schematic Diagrams-5V through -8V

V,N0

-9V through -24V

v,N0

255

LM79LXXAC Series

Voltage Regulators

LM79LXXAC Series 3-Terminal Negative RegulatorsGeneral DescriptionThe LM79LXXAC series of 3-terminal negative voltageregulators features fixed output voltages of --5V, -12V,-15V, -18V and -24V with output current capabilitiesin excess of 100 mA. These devices were designedusing the latest computer techniques for optimizingthe packaged 1C thermal/electrical performance. TheLM79LXXAC series, even when combined with a mini-mum output compensation capacitor of 0.1 A<F, exhibitsan excellent transient response, a maximum line regula-tion of 0.07% VQ/V, and a maximum load regulation of0 01% VQ/mA.

The LM79LXXAC series also includes, as self protectioncircuitry safe operating area circuitry for output transis-tor power dissipation limiting, a temperature independentshort circuit current limit for peak output currentlimiting, and a thermal shutdown circuit to preventexcessive junction temperature. Although designed pri-marily as fixed voltage regulators, these devices may be

combined with simple external circuitry for boosted and/or adjustable voltages and currents. The LM79LXXACseries is available in the 3-lead TO 92 package

Features

• Preset output voltage error is less than ±5% over load,line and temperature

• Specified at an output current of 100 mA• Easily compensated with a small 0.1 pF output

capacitor• Internal short circuit, thermal and safe operating area

protection• Easily adjustable to higher output voltages• Maximum line regulation less than 0 07% Vgyy V• Maximum load regulation less than 0.01%• TO-92 package

Typical Applications Connection Diagram

Fixed Output Regulator TO-92 Plastic Package (Z)

Cl* •— -0 3 3 W F — r—

VINO ——— é —— LM79LXXACZ

"!". r?»*

I n

i

-VOUT

GNO

Required if the regulator is located far from the power supplyfiller A 1 »jF aluminum electrolytic may be substitutedRequired for stability A 1 p? aluminum electrolytic maybe substituted

Adjustable Output Regulator

CI —0.33 p F —

J

— <

LS=„

05ACZ

LRt

J_

— C2— 0.1 yF

-VO = -5V - (5V/R1 + IQ) • R2,5V/R1 ,• 3 IQ

OUTPUT

INPUT

BOTTOM VIEW

Order Numbers

LM79L05ACZ LM79L18ACZLM79L12ACZ LM79L24ACZLM79L15ACZ

See NS Package Z03A

256

Absolute Maximum RatingsInput Voltage

VQ = -5V to-18VVQ = -24V

Internal Power Dissipation (Note 1)

-35V-40V

Internally Limited

Operating Temperature RangeMaximum Junction TemperatureStorage Temperature RangeLead Temperature (Soldering. 10 seconds)

0 C to +70 C+125°C

-55 Cto+150 cC300°C

Electrical Characteristics (Note 2) to + 125"C unless otherwise noted

OUTPUT VOLTAGEINPUT VOLTAGE (unie» otherwise noted)

PARAMETER

VQ Output Voltage

-IVo Line Regulation

.iVQ Load Regulation

AVg Long Term Stability

IQ Quiescent Current

-llQ Quiescent Current Change

Vn Output Noise Voltage

•iVlNaVQ

Input Voltage Requiredto Maintain LineRegulation

CONDITIONS

T, = 25 C IQ = 100mA1 mA< |Q< 100mA

VMIN< VIN< VMAX1 mA< lo<40mA

VMIN< VIN < VMAXT, = 25°C. lQ= 100mA

VMIN< VIN < VMAXT, = 25 C, IQ = 40mA

VMIN < VIN < VMAXT, = 25'C1 mA< |Q< 100mA1 mA < IQ < 40 mA

|Q= 100mA

IQ = 100mAT, - 125°C, |Q = 40mA

1 mA< |Q< 100mA1 mA< lQ<40mA|Q= 100mAVMIN < VIN < VMAXT, = 25°C. |Q= 100mA

f = 10Hz-10kHz

T, = 25°C, lo= 100mAf = 120 Hz

T, - 25°C|Q= 100mAIQ * 40mA

-5V-10V

MIN TYP MAX

-52 -5 -48-5 25 -4 75

(-20 < V|N<-7 5)-5 25 -4 75

(-20 < VIM < -7)

60(-25*: VIN < -7 3)

60(-25 < VIN < -7)

5030

20

2 65.5

030 1025

(-20 < VIN < -7 5)

40

50

-73

-70

-12V-17V

MIN TYP MAX

-125 -12 -115-126 -114

(-27 < VIN < -14 8l

-126 -114(-27 < VIN < -14 5)

45(-30< VIN < -14 6)

45l-30< V|N<-14 5)

10050

48

2 655

030 1025

(-27 < VIN < -14 8)

96

52

-146-14 5

-15V-20V

MIN TYP MAX

-156 -15 -144-1575 -1425

(-30< V|N<-18)-1575 -1425

(-30 < VIN < -17 5)

45(-30 < VIN < -17 7)

45(-30<V|N<-175)

12575

60

2 65 5

030 1025

1-30 < VIN < -18)

120

50

-177-175

-18V-23V

MIN TYP MAX

-187 -18 -173-189 -171

(-33 < VIN < -21 11-189 -171

(-33 < VIN < -20 7)

50(-33 < VIN < -20 8l

50(-33 < VIN < -20 7)

15085

72

2 655

030 1025

(-33 < VIN < -21 1)

150

49

-208-207

-24V-29V

MIN TYP MAX

-25 -24 -23-25 2 -22 8

(-38 < VIN < -27 4)-25 2 -22 8

(-38 < VIN < -271

60(-38 < VIN < -27 11

60(-38 < VIN < -27)

200100

96

2 655

0301025

(-38 < V,N<-274)

190

46

-27 J-27

UNITS

V

mV

V

mVV

mVmV

mV/1000 hr

mA

mA

mAV

XV

dB

V

(D£X

O

(0

(D*K)l/l Not* 1 Thermal resistance, junction to ambient, of the TO 92 (2) package is 180 C/W when mounted «nth 0 40 inch leads on a PC board and 160 C/W when mounted with 0 25 inch leads on a PC board

Nott 2 To ensure constant function temperature, low duty cycle pulse testing is used

LM79LXXAC Series

Typical Performance CharacteristicsMaximum Average PowerDissipation (TO-92) Peak Output Current

° 04

15 30 45 60 75

TA - AMBIENT TEMPERATUBE CC)

Dropout Voltage

I 25 50 75 100 125

T, - JUNCTION TEMPERATURE ( C]

02 ———

£ 015 hrf=ec. \f= \]T" 01 1——

Ê 10 005 V ———

It 1 ———

Tr (

V

c

25 C

-5V0

^

JT = H

• Tr2

Ss\

O m V

i C

s^^v

0 5 10 15 20 25 30

INPUT-OUTPUT DIFFERENTIAL (V)

Ripple Rejection

I 20

100 Ik 101.

FREQUENCY (Hî)

100k

Short Circuit OutputCurrent

025

02<

£ 015

0 005

VOUT =

0 -5 -10 -15 -20 -25 -30 -K

INPUT VOITAGE (VI

Output Voltage vs.Temperature (Normalizedto 1V @ 25°C)

i oto

0 25 50 75 100 1»

T, - JUNCTION TEMPERATURE ( C)

Quiescent Current

-5 -)0 -n -20 -25 -30 -35

INPUT VOLTAGE (V)

Output Impedance

S oi

V O U T - - S VVm.-10VIOUT"50mA

T A - 2 5 C" O l n F

ALUMINUMS?

10 100 U 10k 100k IM

FREQUENCY (Hi)

Typical Applications (continued)t15V, 100 mA Dual Power Supply

JVOUT' ISV* 100mA"IN j-v_j2DV^^^^

GNDO— 1

-350-

[-— 022

— C3r— 033

LM78L15AC 1 ——— •— OVOU

uf

„f

— » — C2ÎOOluF

! 0M0,„F

LM79115AC ——— •— Q-VO '-15V » 100mA

258

LM79LXXAC Series

Schematic Diagrams-5V

-12V through -24V

259

LM117/LM217/LM317

Voltage RegulatorsLM117/LM217/LM317 3-terminal adjustable regulatorgeneral descriptionThe LM117/LM217/LM317 are adjustable 3-termmalpositive voltage regulators capable of supplying in excessof 1.5A over a 1.2V to 37V output range. They areexceptionally easy to use and require only two externalresistors to set the output voltage. Further, both lineand load regulation are better than standard fixed regula-tors. Also, the LM117 is packaged in standard transistorpackages which are easily mounted and handled.

In addition to higher performance than fixed regulators,the LM117 series offers full overload protectionavailable only in IC's. Included on the chip are currentlimit, thermal overload protection and safe area protec-tion. All overload protection circuitry remains fullyfunctional even if the adjustment terminal isdisconnected.

features• Adjustable output down to 1.2V• Guaranteed 1.5A output current• Line regulation typically 0.01%/V• Load regulation typically 0.1%• Current limit constant with temperature• 100% electrical burn-in• Eliminates the need to stock many voltages• Standard 3-lead transistor package• 80 dB ripple rejection

Normally, no capacitors are needed unless the device issituated far from the input filter capacitors in whichcase an input bypass is needed. An optional outputcapacitor can be added to improve transient response.The adjustment terminal can be bypassed to achievevery high ripple rejections ratios which are difficultto achieve with standard 3-termmal regulators.

Besides replacing fixed regulators, the LM117 is usefulm a wide variety of other applications. Since the regu-lator is "floating" and sees only the input-to-outputdifferential voltage, supplies of several hundred voltscan be regulated as long as the maximum input tooutput differential is not exceeded.

Also, it makes an especially simple adjustable switchingregulator, a programmable output regulator, or byconnecting a fixed resistor between the adjustment andoutput, the LM117 can be used as a precision currentregulator. Supplies with electronic shutdown can beachieved by clamping the adjustment terminal to groundwhich programs the output to 1.2V where most loadsdraw little current.

The LM117K, LM217K and LM317K are packaged instandard TO-3 transistor packages while the LM117H,LM217H and LM317H are packaged in a solid Kovarbase TO-5 transistor package. The LM117 is rated foroperation from -55°C to +150°C, the LM217 from-25" C to +)50°C and the LM317 from 0°C to +125°C.The LM317T and LM317MP, rated for operation over a0°C to +125°C range, are available in a TO-220 plasticpackage and a TO 202 package, respectively.

For applications requiring greater output current inexcess of 3A and 5A, see LM150 series and LM138series data sheets, respectively. For the negative comple-ment, see LM137 series data sheet.

LM117 Series Packages and Power Capability

DEVICE

LM117LM217LM317LM317TLM317M

PACKAGE

TO-3

TO-39

TO-220TO-202

RATEDPOWER

DISSIPATION

20W

2W

15W7 5W

DESIGNLOAD

CURRENT

1 5A

05A

1 5A >05A

typical applications

1.2V-25V Adjustable Regulator Digitally Selected Outputs 5V Logic Regulator withElectronic Shutdown*

VOUTV|(,JV-35V

al—improves transientresponseNeeded if device is far from

filter capacitors

/ R2\"VOUT=1 25V 1 +— I

INPUTS

*Sets maximum lMm output * 1 2V

260

LM117/LM217/LM317

absolute maximum ratingsPower Dissipation Internally limitedInput-Output Voltage Differential 40VOperating Junction Temperature Range

LM117 -55°Cto+150°CLM217 -25"C to+150"CLM317 0"Clo+125°C

Storage Temperature -65°C to + 150°CLead Temperature (Soldering. 10 seconds) 300°C

preconditioningBurn-In in Thermal Limit 100% All Devices

electrical characteristics (Note!)

PARAMETER

Line Regulation

Load Regulation

Thermal Regulation

Adjustment Pin Current

Ad|u$tment Pin Current Change

Reference Voltage

Line Regulation

Load Regulation

Temperature Stability

Minimum Load Current

Current Limit

RMS Output Noise. % of VQUT

Ripple Refection Ratio

Long Term Stability

Thermal Resistance, Junction to Case

CONDITIONS

TA « 25"c, 3v < VIN - VOUT < 40v(Note 21

TA « 25"c. 10 mA < IOUT < IMAXVOUT < 5V, (Note 2)VOUT >5V. (Note 2)

TA - 25"C. 20 ms Pulse

10mA<lL<lMAX

2 5 V < (V|N- VOUT»:' 40V

3'_'(V|N VOUT' < 40V. (Note 3)

10 mA <_ IOUT < 'MAX. p _ PMAX3V < V'IN - VOUT < 40V, INote 2)

10 mA < IOUT ^ 'MAX- (No1e 2|

VOUT < 5VVOUT > 5vTMIN< T (<TMAXVIN VOUT - 4ovVIN VOUT < 15V

K and T Package

H and P Package

VIN- VOUT = «vK and T PackageH and P Package

TA • 25" C. 10H»<I< 10 kH/

VOUT-- 10V. M 120 HZCADJ* IQMF

TA- 125"C

H PackageK Package

T PackageP Package

LM117/217

MIN

1 20

1 505

66

TYP

001

50 1

003

50

02

1 25

002

2003

1

35

2 20.8

04

0.07

0003

6580

0.3

122.3

MAX

002

1503

007

100

5

1 30

005

501

5

1

153

LM317

MIN

1.20

1 S05

66

TYP

001

501

004

50

02

125

002

2003

t

35

2208

0.4007

0003

6580

03

12234

12

MAX

0.04

250.5

007

100

5

t 30

0.07

701 5

10

1

153

UNITS

%/V

mV

%

%/W

HA

*A

V

%/V

mV

%

%

mA

AA

A

A

%

dBdB

%

°C/W°c/w°c/w°cw

Nott 1: Unie» otherwite specified, these specifications »pply 55°C < T, < +150°C (or the LM117. 25"C < T, < -M50°C for the LM217 and0 C '. T, ••_ *125'C for the LM317. VIN-VQUT ' SV and IQUT ' 0 1Afor th« TO-5 and TO-202 packages and IQUT " 0 5A for the TO-3 pack-age and TO 220 package Although power dissipation n inrtrnaMy limited, these specifications are applicable for power dissipations of 2W for theTO 5 and TO-202 and 20W for the TO-3 and TO-220. IMAX is 1 SA for th* TO-3 and TO-220 package and 0 5A for the TO-S and TO-202 puckaoeNot* 2: Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage due toheating effects are covered under the specification for thermal regulation.Not* 3: Selected devices with tightend toleranc* inference voltagt available.

261

LM117/LM217/LM317

typical performance characteristics (K and T Packages)

Load Regulation Currant Limit Adiuitmant Currant

-75 -50 -25 0 25 50 75 100 125 ISO

TEMPERATURE ( CIII 20 M 4«

INPUT OUTPUT DIFFERENTIAL IV!

(0

3

œ 50

35

7-75 -SO -25 0 25 50 75 100 125 150

TEMPERATURE I C)

Dropout Voltage Temperature Stability Minimum Operating Current

-75 -50 -25 0 25 50 75 100 125 150

TEMPERATURE! C)

12(0

1240

I 2 M

1 220

\

-N-\

75 50 -25 0 25 50 75 100 125 150

TEMPERATURE« C)

0 10 20 M 4«

INPUT-OUTPUT DIFFERENTIAL (VI

Rippl» Rejection Ripple Rejection Ripple Rejection

0 5 10 15 20 25 M 35

OUTPUT VOLTAGE (V)

100

g 60

40

/IS"r

I t -«

„ AOJ " "»' ^'" *

""t"—*.^XpAOJ"0

*~^

•HUTI\V2

\

\\

>k

\

10 mA15V "

i C _

Ks.10 IM Ik 10k IHk IM

FREQUENCY (HJ)

001 01 1

OUTPUT CURRENT (A)

Output Impedance Lin« Transient Response Load Transient Response

II IN II Ilk IMk IM

FREQUENCY [Hi)

1 S

S s 1J

SI .ssg •t- <

-15

«S il<""

M ! I ICL • itif. CAOJ B HP

i i \CL-I .CAOJ-«

IL • 50 nA

11 II M

TIME Lvil

40

262

LM117/LM217/LM317

application hintsIn operation, the LM117 develops a nominal 1.25Vreference voltage, VREF. between the output andadjustment terminal. The reference voltage is impressedacross program resistor R1 and, since the voltage is con-stant, a constant current \] then flows through theoutput set resistor R2, giving an output voltage of

VOUT — + 'ADJR2

«OUT

FIGURE 1.

Since the lOO iA current from the adjustment terminalrepresents an error term, the LM117 was designed tominimize IADJ an<^ make it very constant with lineand load changes. To do this, all quiescent operatingcurrent is returned to the output establishing a mini-mum load current requirement. If there is insufficientload on the output, the output will rise.

External Capacitors

An input bypass capacitor is recommended. A 0.1/jFdisc or IfiF solid tantalum on the input is suitable inputbypassing for almost all applications. The device is moresensitive to the absence of input bypassing when adjust-ment or output capacitors are used but the above valueswill eliminate the possibility of problems.

The adjustment terminal can be bypassed to ground onthe LM117 to improve ripple rejection. This bypasscapacitor prevents ripple from being amplified as theoutput voltage is increased. With a 10pF bypass capa-citor 80 dB ripple rejection is obtainable at any outputlevel. Increases over 10pF do not appreciably improvethe ripple rejection at frequencies above 120 Hz. If thebypass capacitor is used, it is sometimes necessary toinclude protection diodes to prevent the capacitorfrom discharging through internal low current pathsand damaging the device.

In general, the best type of capacitors to use are solidtantalum. Solid tantalum capacitors have low impedanceeven at high frequencies. Depending upon capacitorconstruction, it takes about 25pF in aluminum electro-lytic to equal 1//F solid tantalum at high frequencies.Ceramic capacitors are also good at high frequencies;but some types have a large decrease in capacitance atfrequencies around 0.5 MHz. For this reason, O.OI iFdisc may seem to work better than a 0.1pF disc asa bypass.

Although the LM117 is stable with no output capa-citors, like any feedback circuit, certain values ofexternal capacitance can cause excessive ringing. Thisoccurs with values between 500 pF and 5000 pF.A IfjF solid tantalum (or 25/^F aluminum electrolytic)on the output swamps this effect and insures stability.

Load Regulation

The LM117 is capable of providing extremely good loadregulation but a few precautions are needed to obtainmaximum performance. The current set resistor con-nected between the adjustment terminal and the outputterminal (usually 240J7) should be tied directly to theoutput of the regulator rather than near the load. Thiseliminates line drops from appearing effectvely in serieswith the reference and degrading regulation. For exam-ple, a 15V regulator with 0.05ÎÎ resistance between theregulator and load will have a load regulation due toline resistance of 0.05ft x l|_. If the set resistor is con-nected near the load the effective line resistance will be0.05Œ (1 + R2/R1) or in this case, 11.5 times worse.

Figure 2 shows the effect of resistance between the regu-lator and 240fZ set resistor.

«s—VW-»— VOUT

S 240

FIGURE 2. Regulator with Line Rnituneein Output Lftd

With the TO-3 package, it is easy to minimize the resis-tance from the case to the set resistor, by using twoseparate leads to the case. However, with the TO-5package, care should be taken to minimize the wirelength of the output lead. The ground of R2 can bereturned near the ground of the load to provide remoteground sensing and improve load regulation.

Protection Diodes

When external capacitors are used with any 1C regulatorit is sometimes necessary to add protection diodes toprevent the capacitors from discharging through lowcurrent points into the regulator. Most 10uF capacitorshave low enough internal series resistance to deliver20A spikes when shorted. Although the surge is short,there is enough energy to damage parts of the 1C.

When an output capacitor is connected to a regulatorand the input is shorted, the output capacitor willdischarge into the output of the regulator. The discharge

263

LM117/LM217/LM317

application hints (con't)current depends on the value of the capacitor, theoutput voltage of the regulator, and the rate of decreaseof VIM In the LM117, this discharge path is througha large junction that is able to sustain 15A surge with noproblem This is not true of other types of positiveregulators For output capacitors of 25pF or less, thereis no need to use diodes

The bypass capacitor on the adjustment terminal candischarge through a low current junction Discharge

occurs when either the input or output is shortedInternal to the LM117 is a 50S2 resistor which limits thepeak discharge current No protection is needed foroutput voltages of 25V or less and 10/jF capacitanceFigure 3 shows an LM117 with protection diodesincluded for use with outputs greater than 25V andhigh values of output capacitance

D2 protects against C2

FIGURE 3 Regulator with Protection Diodes

schematic diagram

264

LM117/LM217/LM317

typical applications (con't)

Slow Turn-On 15V Regulator Adjustable Regulator with ImprovedRipple Rejection

High Stability 10V Regulator

iT

l""' 1MII7 VIB__.

VINAl

C2<M„F

>j TS RIs ?«<

> ———— I— WV— • ^1 Rî I<• R2 S ^ 1

>" 2NMOÏI ———— r» ———— 1> ? > , -y +J_C)f XT-S75,.

r I T .FII< -r-°'

:«««» T01" , i TH-FXp

-1 ——— I ———————— —————

, LmI •

T°'"f i— C3 ~ „"N I ,F'

——— . ———————— . ——————— - J^<<

VOUTu

—tk IMI

R3:»'

^ RI< "C SX1

«J

•«»

R2

'Solid tantalum ~-

'Discharges CI il output is shorted to ground

High Current Adjustable Regulator

3 IMUiSINPABAllH

0 to 30V Regulator Power Follower

"in-

! ————————————— -\ f~ ————————————— I """Y ••<R!

«i Ss» IMI:J" 1i— VW—*- v,„ vou

ADJ

_ CI

1 ———— I———<FU __< 1?» J ^ l"'l»?

I• X I O . f ' T 3

. / _i± c? 1i« xp,..f-

ïiï— t- V|" VOIJT ~t— VOUT3iV »DJ I

> R1

S in— — ci ———— ,,

T°'"f k_ „ /? 3k

1 —————— 1 >— VOU, ^

, —————————————— (__

~ r /- -^ iMin. _ - t c 3 " A "V

/^-N.«MV , ————— 1

>S R3> 6BO

r 'Solid tantalum

Minimum load current - 30 mAtOptiona -improves ripple reaction

SA Constant Voltage/Constant Current Regulator

MJ4U?

C2 — -1 —— CURRINT S-' SolIM »F — i — ADJUST,. • . " S I!

1 ' ZbDd ' 3"RI t »3l H 1 0J3 "'""

— J— CI^ ~^ 1WF

VOUT - ..... _ -<- - . . - - - - - - -- OU"UI

tiIN»4)J

R4(M

-M-->fr!<Dl 03

IN«S? UO*

-IV T

T 1 ?V »V

* , ' I8»f r 7^

H F { . TLMMU

!1 s«Ci n.- >2»«

'>rF ]m< », 11 *" 1• -vw 7 i

M \* +0 -15V H, V* — *— C»

VOlT»CE-> ^T^ >*>•'ADJUST [ [

10V

_l_n '— . — o i.t

Y^INfUT —— V*/S( —— —— 1». s*

10k

40V

IM195

I OUTCUT —— 054

LMIIJ «01AOJ

( t" — -

t —

<<

1A Current Regulator

LMiir

IN • V,N VOUT _T AOJ

Cl— 1 —,.,-J-

krT

LOAD

1.2V-20V RegulatoMinimum Program C

IMIl»

IN — v,, VOUT _^_AOJ 1

|

L

r withurrent

-VflUt*

;rt,|.* Solid tantalum'Lights in constant current mode Minimum load current * 4 mA

265

LM117/LM217/LM317

typical applications (con't)

Htgh Gain Amplifier Low Cost 3A Switching Regulator

Solid Tantalum

"Core- Arnold A-254168 2 60 turn»

4A Switching Regulator with Overload Protection

3 IM19S IN P A R A L L E L

Precision Current Limiter

Solid Tantalum

"Core Arnold A-254168-2 60 turns

VIN VOUT

*08U < Rl < 120JJ

Tracking Preregulator

R2720

V I N -

1ADJ

VIN VO U T

-ci-01 . F

Rl240 LMIU

VIN VOUT

AOJ

R3120

?* jyouipui"-/? AOJUSI

High Volug« Regulator Adjusting Multiple On-Card Regulatorswith Single Control *

VIN — VINA

VOUTu — t — voul v,N —

>îi

VINA

VOUT3J

— VOUIT VIH — VIN VOUTAOI

11J

—VOUT'

R2> U

All outputs within ! 100 mV^Minimum load-10mA

266

LM117/LM217/LM317

typical applications (con't)AC Voltage Regulator

mm

Adjustable 4A Regulator

——— [VIN VOUT1 AOJ

A"V

1

AOJ '

M

<I20

__ 1 «Vp,~l "";. ;-uo / \ - 7i-

IM3I7

12V Battery Charger

IM31J BS"

VIN ——— Km vOUTL_l A j r

*RS— sets output impedance ofUse of RS allows low chargingcharged battery.

50 mA Conttant Curren

IM317H

«IN ———— «1« "OUT -AOJ

1

connection diagrarr

ITO-3 Steel)Metal Can Package

»OIUSTMENI /O \L V|N

\ XCASJ is

BOTTOM Vit«

Order Number:LM117K STEELLM217K STEELLM317K STEEL

See NS Package K02A

^ t _i_S »O "y" z«»

S »2

/ R2\:harger ZQUT = RS I1 + — 1 sv T

rates with fully \ R1 /

t Battery Charger

24

" T^

r- —— 11 0.2

— — IM31J ——— \VV— '

LM117

- — JVIN "OUT -f-VVVH1 AOJ

j* i^100 :-1 2NMOS , ^ <K>.

'<r'~

Current Limited 6V ChargerLM3I7

V|M ........ VIM «OUT 4». . .0 30V ADJ T

{240

i 4.SV TO »V

•51

»

1

H- TrT— i *•^ "Sets peak current (0.6A for 1 fl)

IS

ITO-39» (TO-220) (TO-202)Metal Can Package Plastic Package Plastic Package

f^Y" f O «{CASEISOUTFUT ."' '";

Order Number:LM117HLM217HLM317H

See NS Package H03A AOJ —— —

»0

1

«J -——

- — v,»

" Fl

O•^ — V

1 If

L-VOUT«OUT VIEN

Order Number:LM317T

See NS Package T03B

Order Number:LM317MP

Se« NS Package P03A

267

LM137/LM237/LM337

Voltage RegulatorsLM137/LM237/LM337 3-Terminal AdjustableNegative RegulatorsGeneral DescriptionThe LM137/LM237/LM337 are adjustable 3 terminalnegative voltage regulators capable of supplying in excessof -1 5A over an output voltage range of —1 2V to•37V These regulators are exceptionally easy to apply,requiring only 2 external resistors to set the outputvoltage and 1 output capacitor for frequency compensation The circuit design has been optimized for excellentregulation and low thermal transients Further, theLM137 series features internal current limiting, thermalshutdown and safe area compensation, making themvirtually blowout proof against overloads

The LM137/LM237/LM337 serve a wide variety ofapplications including local on card regulation, programmable output voltage regulation or precision currentregulation The LM137/LM237/LM337 are ideal complements to the LM117/LM217/LM317 adjustable positiveregulators

Features• Output voltage adjustable from -1 2V to -37V• 1 5A output current guaranteed, -55°C to +150°C

Line regulation typically 0 01%/VLoad regulation typically 0 3%Excellent thermal regulation, 0 002%/W77 dB ripple rejectionExcellent rejection of thermal transients50 ppm/°C temperature coefficientTemperature independent current limitInternal thermal overload protection100% electrical burn inStandard 3 lead transistor package

UM 137 Sériai Packages and Power Capability

DEVICE

LM137LM237LM337LM337TLM337M

PACKAGE

TO 3

TO 39

TO 220TO 202

RATEDPOWER

DISSIPATION

20W

2W

15W7 5W

DESIGNLOAD

CURRENT1 5A

05A

1 5A05A

Typical Applications

Adjustable Negativ* Voltage Regulator

-VIN- VIN LM137/LM337

ADJ ^«0«

VOUT, -VOUT

-VOUT = -1 25V (1 +R2

TC1 = 1 iif solid tantalum or 10 pF aluminum electrolytic required for stability*C2 = 1 MF solid tantalum is required only if regulator is more than 4" from

power supply filter capacitor

268

LM137/LM237/LM337

Absolute Maximum RatingsPower DissipationInput-Output Voltage DifferentialOperating Junction Temperature Range

LM137LM237LM337

Storage TemperatureLead Temperature (Soldering, 10 seconds)

PreconditioningBurn-In in Thermal Limit

Electrical Characteristics

Internally limited40V

-55°Cto+150°C-25°Cto+150°C

0°Cto+125°C-65°Cto+150°C

300° C

100% All Devices

(Note 1)

PARAMETER

Line Regulation

Load Regulation

Thermal Regulation

Adiustment Pin Current

Adiustment Pin Current Change

Reference Voltage

Line Regulation

Load Regulation

Temperature Stability

Minimum Load Current

Current Limit

RMS Output Noise. % of VQUT

Ripple Reiection Ratio

LonjTerm Stability

Thermal Resistance. Junction to Case

CONDITIONS

TA = 25°C. 3V < |V|N-VouTi < *OV(Note 21

TA • 25°c. 10 mA < IOUT < IMAXIVQUT|< 5V. (Note 2]|VQUTi>5V, (Note 21

TA - 25"C. 10ms Pulse

iOmA< IL < IMAX2 5V < |V|N-VoUTi < 40V. TA = 25°C

TA = 25°C (Note 3]3 < |V(N - VOUTI < 40V. (Note 3)

10 mA < IOUT < 'MAX. P < ?MAX

3V<IV|N-VQUT. <40V. (Note 21

10 mA < IOUT '_' 'MAX. (Note 21

IVQUTl < 5V

iVQUTl 5 5V

TMIN<TJ<TMAX|V|N-VOUTI<40V|V|N-V0UTI<'OV

IV|N-VOUTl<15V

K and T PackageH and P Package

K and T PackageH and P Package

TA-25X 10Hz< f< 10kHz

VOUT = -10V, f- 120 HZCADJ= IO/^FTA- 125°C. 1000 Hours

H PackageK PackageT PackageP Package

LM137/LM237MIN

-1.225-1 200

1.5

0.5

66

TYP

001

15

0.3

0.002

65

2

-1.250-1.250

002

20

03

06

2.51.2

2208

040.17

0003

6077

0.3

122.3

MAX

0.02

25

05

002

100

5

-1.275-1 300

005

501

53

1

IS3

LM337MIN

-1 213-1.200

1.505

66

TYP

001

15

03

0003

65

2

-1 250

-1 250

0.02

2003

06

2.51 5

2.208

040 17

0003

6077

0.3

122.3412

MAX

004

50

1 0

004

100

5

-1 287

-1 300

007

701.5

106

1

15

3

UNITS

%/V

mV

%

%/W

PA

£*A

V

V

%/V

mV%

%

mAmA

A

A

A

A

%

dB

dB

%

"C/W°c/w°c/w"c/w

Not« 1. Unless otherwise specified, these ipecificalions apply -55"C < T, < +150"C for the LM137, -25°C < Tj < +150°C for the LM237 and0°C < T, < +125°C for the LM337; VIM - VQUT " 6V- and 'OUT * 0.1 A for the TO-5 package and TO-202 package and IQUT " 0 5A for th«TO-3 package and TO-220 package. Although power dissipation is internally limited, these specifications are applicable for power dissipations of2W for the TO-5 and TO-202 and 20W for the TO-3 and TO-220. 'MAX " 1 -5A for ""> TO-3 and TO-220 package and 0 SA for the TO-S packageand TO-202 package.Not* 2' Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle Changes in output voltage due toheating effects are covered under the specification for thermal regulation Load regulation is measured on the output pin al a point 1/8" belowthe base of the TO-3 and TO-5 packages.Not« 3. Selected devices with tightened tolerance reference voltage available.

269

LM137/LM237/LM337

Schematic Diagram

O»OUT

Thermal RegulationWhen power is dissipated in an 1C, a temperaturegradient occurs across the 1C chip affecting the individualICcircutt components. With an \C regulator, this gradientcan be especially severe since power dissipation is large.Thermal regulation is the effect of these temperaturegradients on output voltage (in percentage output change)per Watt of power change in a specified time. Thermalregulation error is independent of electrical regulation ortemperature coefficient, and occurs within 5 ms to 50 msafter a change in power dissipation. Thermal regulationdepends on 1C layout as well as electrical design. Thethermal regulation of a voltage regulator is defined as thepercentage change of VgUT- per Watt, within the first10 ms after a step of power is applied. The LM137'sspecification is 0.02%/W, max.

0.1%

In Figure 1. a typical LM137's output drifts only 3 mV(or 0.03% of VOUT = -10V) when a 10W pulse isapplied for 10 ms. This performance is thus well insidethe specification limit of 0.02%/W x 10W = 0.2% max.When the 10W pulse is ended, the thermal regulationagain shows a 3 mV step as the LM137 chip coolsoff. Note that the load regulation error of about 8 mV(0.08%) is additional to the thermal regulation error.In Figure 2. when the 10W pulse is applied for 100ms,the output drifts only slightly beyond the drift in thefirst 10 ms, and the thermal error stays well within0.1%(10mV).

0.1X

10 n«

LM137,VQUT = -

1L = OA-.0.25A-»OAVertical sensitivity, 5 mV/div

FIGURE 1

LM137,VOUT = -10V

VIN-VOUT - -40VIL = OA-0.25A-OAHorizontal sensitivity. 20 ms/div

FIGURE 2

270

LM137/LM237/LM337

Connection Diac

TO-3Metal Can Package

ADJUSTMENT / O\. VOUT

\ /CASE IS

\ o / ""UI

BOTTOM VIEW

Order Number:LM137K STEELLM237K STEELLM337K STEEL

See NS Package K02A

jrams

TO-39Metal Can Package

—— ADJUSTMENT

«- OUTPUT

—— INPUT

CASE IS INPUT

JO-220Plastic Package

' 0 '; i

BOTTOM VIEW

Order Number: »OJ —— _LM137HLM237HLM337H

See NS Package H03A f

«•* —

VINRONT view

TO-202Pltttic Package

-VIH

-VOUT

Typical Applications (continued)Adjustable Lab Voltage Regulator

The 10/jF capacitors are optional to improve ripple rejection

Current Regulator

VIN 1.250V(CURRENT 'OUT ~ —rr~IOUTPUT " '* "0.8Î7 < R1 < 120ÎI

'OUT

Negative Regulator with Protection Diodes

r±

When C|_ is larger than 20pf. D1 protectsthe LM137 in case the input supply is shorted

**When C2 is larger than 10 pf and — VQUT is

larger than —25V, D2 protects the LM137 incase the output is shorted

Order Number:LM337T

See NS Package T03B

VOUT

FRONT VIEW

Order Number:LM337MP

See NS Package P03A

—5.2V Regulator with Electronic Shutdown*

*Minimum output ^ —1.3V when control input is low

Adjustable Current Regulator

4^VOUT

'OUT

'OUT

-VW-H '

l ~ '

.(^L\ 115% adjustable

High Stability -10V Regulator

271

LM137/LM237/LM337

Typical Performance Characteristics (K steei.Kc and T Packages»

Load Regulation Current Limit

5 - 1 2o-14

-75 -51-2S | 25 SO 75 100 125 150

TEMPERATURE I°C)

0 10 20 30 40

INPUT OUTPUT DIFFERENTIAL (V)

Adjustment CurrentId

< 75t-

fctCa" 65

-75-50-25 0 25 50 75 100 125 150

TEMPERATURE CO

Dropout Voltage Temperature Stability

-75-50-» 0 25 50 75 100 125 150

TEMPERATURE ("CI

1J70

1.260

1250

1.240

Minimum Operating Current

-J5 -50 -25 0 25 50 75 100 125 150

TEMPERATURE! C)

9 10 20 30 40

INPUT-OUTPUT DIFFERENTIAL IV)

Ripple Rejection Ripple Rejection Ripple Rejection

102

RIPP

LE R

EJEC

TI

» fi :

• [S,""N

l/ -500mA"l- 120 Mi

T, - «°CI

-«AI

— C

-6V

J"

\DI"•-»-•

fcF.

"i •• •iM^M

RIPP

LE R

EJEC

TIO

N (t

»}

S

o

S

S

Î

l -U -2l -M -40

OUTPUT VOLTAGE (V)

Output Impedance

II 100 1k tOt 100k IM

FREQUENCY IHz)

^

CAI

VIN'VOUTIL .5(T . -JS

--^

j-O

-15V• -IOV10mA°C

x

O\ >\

x^V

s >03

VIN--.VOUT-

1-120T, • 25°

1 1 1

W II!CADJ"10.,F

CAOJ

15V-10V

Hi ^cHill

•0

OUT

PUT

VOLT

AGE

DEV

IATI

ON

(V)

»

0

0

0

0s»

o

Ki

*

a>

•

INPU

T VO

LTAG

ECH

ANG

E (V

)

ow

e»

0 100 Ik 10k 100k IM 001 O.t 1 It

FREQUENCY IHi) OUTPUT CURRENT (A)

Line Transient Response Load Transient Response

bvAB

KLI CADJ~fn —

— — Vrji

Jl'_

•0

±• 10pF

50 it25 CIcF

A

1V

\

UJ

S> o.-i z ny

OUTP

UT V

O0

CURR

ENT

(AI

QEV

tATI

Ûi

i i

ii

* —

o

o

a

On

04

jn

O<

jt

J»

ra

O

f*T^L

^

k CAOJ"

.C»

v-V

IN-T,

If

0

NzhIfcF

N- - ISVJUT'- 'l>50m= 25 C

i*~v-«

\0 10 20 30 40 S 0 10 20

TIME M TIME lull

i/t

^

30 4

272

LM723/LM723C voltage regulator

LM723/LM723C

Voltage Regulators

general descriptionThe LM723/LM723C is d voltage regulator designed primarily for series regulator applications Byitself, it will supply output currents up to 150 mAbut external transistors can be added to provideany desired load current The circuit features extremely low standby current drain, and provisionis made for either linear or foldback current limiting Important characteristics are

• 150 mA output current without external PUSStransistor

• Output currents in excess of 10A possible byadding external transistors

• Input voltage 40V max

• Output voltage adjustable from 2V to 37V

• Can be used as either a linear or a switchingregulator

The LM723/LM723C is also useful in a wide rangeof other applications such as a shunt regulator, acurrent regulator or a temperature controller

The LM723C is identical to the LM723 exceptthat the LM723C has its performance guaranteedover a 0°C to 70°C temperature range, instead of•55'C to H25°C

schematic and connection diagramsDual In Line Package

Hvt 11 t,t 1'ul

Order Number LM723N or LM723CNSee NS Package N14A

Order Number LM723J or LM723CJSee NS Package J14A

Metal Can PackageCUKHCNT

equivalent circuit*

NON INVENTING

Nett Pin 5 cortMCltd tt e»MT Of VII*

Order Number LM723H or LM723CHSee NS Package H10C

"ICUKKI«

IIMII SENSE

Pin numbers refer to metal can package

273

LM723/LM723C

absolute maximum ratingsPulst Voltage from V' to V" (50 ms)Continuous Voltage from V' to V~Input Output Voltage DifferentialMjximum Amplifier Input Voltage (Either Input)Maximum Amplifier Input Voltage (Differential)Cufrenl from V?Current from Vn E F

Internai Power Dissipation Metal Can {Note 1)Cavity DIP (Note 1)Molded DIP (Note 1)

Operating Temperature Range LM723LM723C

Storage Température Range Metal CanDIP

Lead Temperature (Soldering. 10 sec)

50V40V40V

7 5V5V

25mA15 mA

800mW900 mW660 mW

-55°Cto+125°C0°C to + 70°C

-65° C to *150"C-55"Cto<125"C

300"C

electrical characteristics (Note 21

PARAMETER

Line Regulation

Load Regulation

Ripple Rejection

Average TemperatureCoefficient of Output Voltage

Short Circuit Current Limit

Reference Voltage

Output Noise Voltage

Long Term Stability

Standby Current Dram

Input Voltage Range

Output Voltage Range

Input Output Voltage Differential

CONDITIONS

VIN = 12V to V,N = 15V

-55°C<TA<-H2S°C

0°C < TA < +70° C

V,N - 12V to V,N - 40V

IL = 1 mA to IL = 50mA

-55°C<TA<H25°C

0°C<TA<= + 70°C

f ' 50 Hz to 10 kHz, CREF - 0

f = 50 Hi to 10 kHz, CREF = 5 u'F

-55°C<TA<+125°C

0°C < TA < +70°C

R s c = 10U, VOUT = 0

BW = 100 Hz to 10 kHz. CREF = 0

BW = 100 Hz to 10 kHz. CREF = 5pF

I L -0 . V , N -30V

LM723

MIN

695

95

20

3.0

TYP

01

02

.03

74

86

002

65

7 15

20

2 5

0 1

1 3

MAX

0 1

03

02

0.15

0.6

015

7 35

35

40

37

38

LM723C

MIN

6.80

9.5

20

30

TYP

.01

0 1

.03

74

86

003

65

7 15

20

25

0 1

1 3

MAX

0 1

0.3

05

0.2

0.6

015

750

4 0

40

37

38

UNITS

%VOUT

%VOUT

%VOUT

%VOUT

%VOUT

%VOUT

%VOUT

dB

dB

%/°C

%/°c

mA

V

„Vrms

;jVrms

VIOOOhrs

mA

V

V

V

Note 1 : See derating curves for maximum power rating above 25°C.Note 2: Unless otherwise specified, TA = 25°C, V|N = V* = Vc = 12V, V~ = 0, VOUT = 5V,l|_ = 1 mA, RSC - 0, GI = 100 pF, Cp^p = 0 and divider impedance as seen by error amplifier< 10 kfi connected as shown in Figure 1 Line and load regulation specifications are given for thecondition of constant chip temperature Temperature drifts must be taken into account separatelyfor high dissipation conditions.Note 3: LI is 40 turns of No 20 enameled copper wire wound on Ferroxcube P36/22-3B7 pot coreor equivalent with 0.009 in air gap.Note 4: Figures in parentheses may be used if R1/R2 divider is placed on opposite input of error amp.Note 5: Replace R1/R2 in figures with divider shown in Figure 13.Note 6: V must be connected to a +3V or greater supply.Note 7: For metal can applications where V£ is required, an external 6.2 volt zener diode should beconnected m series with

274

LM723/LM723C

maximum power ratingsLM723

Power Dissipation vsAmbient Temperature

1000

IN700

- MO

300

200too

DIP

TOS\sNs

TjMAX-ISfl-CRT M - l«rC/W(TORTM-'*»°C«<OINO HEAT SINK

\\s1

5)_1

N\'s-

\^

-SS -25 0 25 SO 75 IM 125 ISO

TA AMIIENT TEMPERATURE CC)

LM723CPower Dissipation vsAmbient Temperature

1000IM100700

* 'MJ MO

' 400100200100

- T O S

-L \.s\s

TjMAX-125'CRT M -125°C/W(TORTM-ISS"C/W(OIFNO HEAT SINK

^5•->

5lI

-SS -25 0 25 50 75 100 12S 150

TA AMBIENT TEMPERATURE CCI

typical performance characteristicsLoad RegulationCharacteristics withCurrent Limiting

- «S

•

8;-«»i -"P<a -OISuUJOC

-02

-025

- VOUT'*SV V,H«*12V

^.-rtttr0 5 10 IS 20 25 30

OUTPUT CURRENT <mA)

Current LimitingCharacteristic«

12

1«

01

0 6

0 4

0.2

—

—

-T. -1

T

T

A '

A '

———

26- 1

-SS'

Vo,RX*v

*

c-

C'

JT-

— «_i

V V,N

\

~

••1

-

2V

0 20 40 «0 10 100

OUTPUT CURRENT (mA)

Line Transient Response

Load RegulationCharacteristics withCurrent Limiting

Load & Line Regulation vsInput Output VoltageDifferential

OUTPUT CURRENT (mA)

Current LimitingCharacteristics vsJunction Temperature

Standby Current Drain vsInput Voltage

-50 0 SO 100 ISOJUNCTION TEMPERATURE! C)

Load Transient Response

10 20 30 40 SO

INPUT VOtTAGE (V)

Output Impedance vsFrequency

V,*-«12VVoui-'SVt • t mA

TA - 25-C

11-40

IS 25 35 45

TIME U)

10

01

011

VINRfCT A -IL-

--

X)

«12V - -

25 C50mA -

— ? '-^

,

C L ' 0

/

U 10k 100k

FREQUENCY (Hil

IM

275

LM723/LM723C

TABLE I RESISTOR VALUES (ki2) FOR STANDARD OUTPUT VOLTAGE

POSITIVEOUTPUT VOLTAGE

•30

•36

»50

• 60

•90

• 12

• 15

• 28

•45

»75

APPLICABLEFIGURES

(No» 4)

1. b. 6. 9.12(41

1. 5. 6.9.12(41

1. 5.6.9.12(4)

1.5.6.9.12 (4)

2. 4. (5. 6.12.91

2. 4. (5. 6.9. 12)

2. 4. (5. 6.9. 121

2. 4. (5 69 12)

7

7

FIXEDOUTPUT

!5X

HI

4 12

357

2 15

1 15

1 B7

4 8 7

787

21 0

357

357

R2

301

365

499

604

7 15

7 15

7 15

7 15

48 7

78 7

OUTPUTADJUSTABLE; 10% INott 5)

R1

1 B

1 5

75

05

75

20

33

56

2 2

2 2

PI

05

05

05

05

1 0

1 0

1 0

1 0

10

10

R2

1 2

1 5

22

2 /

2 1

30

30

2 0

39

68

NEGATIVEOUTPUT VOLTAGE

•100

• 250

-6 INule6)

9

12

-15

-28

-45

-100

-250

APPLICABLEFIGURES

/

1

3.1101

3. 10

3. 10

3. 10

3. 10

8

8

8

FIXEDOUTPUT

•5%

Rl

3 5 7

3 5 7

357

348

3 5 7

365

357

3 5 7

3 5 7

3 5 7

R2

102

255

243

536

845

11 5

243

41 2

976

249

5% OUTPUTADJUSTABLE

:10%

Rl

22

2 2

1 2

1 2

1 2

1 2

1 2

2 2

2 2

2 2

PI

10

10

05

05

05

05

05

10

10

10

R2

91

240

75

20

3 3

43

10

33

91

240

TABLE II FORMULAE FOR INTERMEDIATE OUTPUT VOLTAGES

Output» from +2 to +7 volts[Figure* 1. 5.6.9. 17. (41)

R2VOUT * IVRE* X f^VRj'

Output* from +7 to +37 voU»I figure* 2. 4. (5,6.9. 12)!

Rl * R2VOUT * lV«Ef X - -p-j — |

Output« from «4 to +250 volt»IF.yurt J\

VOUT-!^ X R^-rRJ-LR3.R4

Outputt from -6 to -250 voluI Figures 3. 8. 10!

Van Rl • R2VOUT 'I " x - „ , - - ! . R3- R4

Current Limiting

, VSlNit

'••'«"- R«"

Foldback Currtnl Limiting

, .VOUT R3 VsaNst IR3» R4I'«~""1 Rsc f l4" * FtsTÏÛ ——— '

IS-OBT CKT • 1 "s"c" X — fli— |

typical applications

., 11 M .w-ima1"—••TYPICAL XRFORMANCE

tin »ndiiw Ont^i v«tut> ivllM fU|»ht>M I.W*, • JV) It «V

M «AI l i mV

T .T"

RI R2 TVnCALFERFOfUUNCE

FIGURE 1. Basic Low Voltag« Regulator(VOUT - 2 to 7 Volt»)

«•!• U • m /ft} '•< "«»Mill U«f«n«<t *rtt Ktfiltut Out*« VilUfi IIVIm fUcJiti» </.V,K • 3VI II «V

MWllcwvMMtcM«. l,* R,»*», (al,. • M «AI 4 l «V

FIGURE Z. Basic High VolUg« Regulator'VOUT • 7 to 37 Volts)

•1 N.iHin ,iMirx

(i

•[ t

nnr

-Tm*\

TYPICAL ft RFORMANCEh»*MO«tf.tV>i»* -IfVUM Bipilrti. I&VM -IV) t mV

• IM «AI t »V

TVrtCAirCRFORMANCE

LIM R>»4iüo. (:,V,K • 3V) l » «V. IAI IS »V

FIGURE 3. Negativ« Voltage Regulator FIGURE 4. Positive Voltage Regulator(External NPN Paa Transistor)

276

typical applications(con't.)LM723/LM723C

- l« IM (

Cl• rftw

f T?TYPICAL PERFORMANCE

FtofulltHl Output Voltl|> »5VLin«Rf|iitittonlÄV„,-3V) O S m VIwd Refutation (AlL * 1AI 5 mV

FIGURE 5. Positive Voltage Regulator(External PNP Pais Transistor)

f Tf-TYPICAL PERFORMANCE

Rtluliud Ogtput Volât« «5Vlin» Rtfnlition teV,N -3V) OS mVLoid Rtplition |alt • 10 mA) 1 mVShort Cirtutt Current 20 mA

FIGURE 6. Foldback Current Limiting

TYPICAl PERFORMANCERtplattd Output Votai» »50VIm RtfuMon toV,N • 20V) 1S mVloof Rtfiilltion (alL • SO mAI JO mV

FIGURE 7. Positive Floating Regulator

TYPICAL PERFORMANCERtfuhtH- Output VolUf «5VLint R«fiiUjtion(ÄV„,-30V) 10 »VLot« Rtfulttiin lilt • IA) M mV

FIGURE 9. Positive Switching Regulator

1r

;«i

>«i

'

•'c 1 IIV

*J)«

»

„ 1-

"*"1 tlliiHK

t

—

UT;;JT'""

IM

SLtfUtl

TYPICAL PERFORMANCErtVoftjfi -IXV

lin Rtiulition |AVIN • 20V) 30 mVLori Rtfulnion lalt * 100 mA) 20 mV

FIGURE 8. Negative Floating Regulator

, .rCl —

II 1«

: :

,M

. I,,

il»!îic tl

u

JÇ«

—

,.,

— « -Cm ,

tt

mur

~~~i?;

1*-rr;I"

TYPICAL PERFORMANCERtffutattd Output Vottogr -1SVImt Rt|ul>tion lûV,N - 20V) 1 mVL«d Rtfulition taL * 2A) B mV

FIGURE 10. Negative Switching Regulator

••

..,

i«u) ,l»UK "

Cl

* 1 It».*

J•1

1 è- "••?--W^ — OmcK.-*«i

TYPICAL PEAFORMANCER^ulitt« Output Voltifi «SVlin Rtfilition (ùViN -3V) 0 S mVloid B»|«lit»n (alt • SO mA) IS mV

FIGURE 11. Remote Shutdown Regulator withCurrent Limiting

Nat» Current hnwl trammel mjv WMttf for dmttovm if current

r

TYPICAL PERFORMANCER>l»liud Output Volute <SVLiiMRi|ul«i°n(AV,,,-10V) OSmVLMd Rl|ul«ion (AlL • 100mA) 1 S mV

FIGURb 12. Shunt Regulator FIGURE 13. Output VoltageAdjust (See Note 5)

277

LF111/LF211/LF311

Voltage ComparatorsLF111/LF211/LF311 voltage comparatorsgeneral descriptionThe LF111, LF211 and LF311 are FET input voltagecomparators that virtually eliminate input current errors.Designed to operate over a 5.0V to ±15V range theLF111 can be used in the most critical applications.

The extremely low input currents of the LF111 allowsthe use of a simple comparator in applications usuallyrequiring input current buffering. Leakage testing, longtime delay circuits, charge measurements, and highsource impedance voltage comparisons are easily done.

Further, the LF111 can be used in place of the LM111eliminating errors due to input currents. See the "appli-cation hints" of the LM311 for application help

advantages• Eliminates input current errors• Interchangeable with LM111• No need for input current buffering

connection diagrams*Metal Can Package Flat Package

NOTE P.nSconnected10P V IE f t

NOTE Pm4 connected to cair

Order Number LF111H, LF211H Order Number LF111F. LF211Forl_F311H orl_F311F

See NS Package H08C See NS Package F10A*Pm connections shown on schematic diagramand typical applications are for TO 5 package

schematic diagram and auxiliary circuitsAlANCt SlftOif IMANCE

Dual-ln-Lme Package

__ - BALANCE1 STROBE

Noie Pin & connected to bottom ot picktoe

TOP VIEW

Order Number LF111D, LF211Dor LF311D

See NS Package D14E

Offset Balancing

Strobing

'IncitBUt typictl common m«tfiIII« lion 7 OVItf t« llV/ve.

Increasing InputStag« Current*

278

LF111/LF211/LF311

absolute maximum ratings

Total Supply Voltage (V84)Output to Negative Supply Voltage (V74)Ground to Negative Supply Voltage (V14)Differential Input VoltageInput Voltage (Note 1)Power Dissipation (Note 2)Output Short Circuit DurationOperating Temperature Range

LF111LF211LF311

Storage Temperature RangeLead Temperature (Soldering, 10 seconds)

LF111/LF211

36V50V30V

±30V+ 15V

500 mW10 seconds

-55°Cto-H25°C-25°C to +85°C

-65°Cto+150°C300° C

LF31136V40V30V

±30V±15V

500 mW10 seconds

0 C to +70 C-65°Cto-H50°C

300° C

electrical characteristics (LFin/LF2H) (Note3)

PARAMETER

Input Offset Voltage (Note 4)

Input Offset Current (Note 4)

Input Bias Current

Voltage Gain

Response Time (Note 5)

Saturation Voltage

Strobe On Current

Output Leakage Current

Input Offset Voltage (Note 4)

Input Offset Current (Note 4)

Input Bias Current

Input Voltage Range

Saturation Voltage

Output Leakage Current

Positive Supply Current

Negative Supply Current

CONDITIONS

TA = 25° C. Rg

TA = 25°C, VCM = 0 (Note 6)

TA = 25°C, VCM = 0 (Note 6)

TA =25°C

TA = 25°C

VIN < -5-0 mV. IOUT = 50 mA. TA = 25°C

TA - 25°C

V,N >5.0 mV, VOUT = 35V. TA = 25° C

Vs = ±15V. VCM = ° <Note 6)

VS = ±15V. VCM =0 (Note 6)

V* >4.5V, V~ = 0VIN < -6-0 mV. IS1NK < 8.0 mA

V,N > 5.0 mV, VOUT = 35V

TA = 25°C

TA = 25°C

MIN

40

-13.5

TYP

0.7

5.0

20

200

200

0.75

3.0

0.2

2.0

5.0

*14

0.23

0.1

5.1

4.1

MAX

4.0

25

50

1.5

10

6.0

3.0

7.0

130

0.4

0.5

6.0

5.0

UNITS

mV

pA

PA

V/mV

ns

V

mA

nA

mV

nA

nA

V

V

^A

mA

mA

Not« 1: This rating applies for s 15V supplies. The positive input voltage limit is 30V above the negative supply. The negative input voltage limitis equal to the negative supply voltage or 30V below the positive supply, whichever is less.No»« 2: The maximum junction temperature of the LF111 is +150"C. the LF211 is t110"C and the LF311 is +85°C. For operating at elevatedtemperatures, devices in the TO-5 package must be derated based on a thermal resistance of +150"C/W, junction to ambient, or +45° C/W, (unctionto case. For the flat package, the derating is based on a thermal resistance of «185' C/W when mounted on a 1/16 inch-thick epoxy glass board withten. 0.03-inch-wid», 7-ounc« copper conductors. The thermal resistance of the dual-in-line package is » 100"C/W. junction to ambient.Not« 3: These specifications apply for Vg " '15V, and the Ground pin at ground, and -55°C v T/^ ^, + 125"C lor the LF 111. unless otherwisestated With the LF211, however, all temperature specifications are limited to 25"C < TA < +85'C and for the LF311 0"C <- TA •_ *70' C Theoffset voltage, offset current and bias current specifications apply for any supply voltage from a single 5 0V supply up to > 15V suppliesNott 4: The offset voltages and offset currents given are the maximum values required to drive the output within a volt o< either supply with a1.0 mA load. Thus, these parameters define an error band and take into account the worst case effects of voltage gam and input impedance.Not* S: The response time specified (see definitions) is for a 100 mV input step with 5.0 mV overdrive.Not* 6: For input voltages greater than 1SV above the negative supply the bias and offset currents will increase-see typical perlormance curvesNot* 7: Do not short the strobe pin to ground, it should be current driven at 3 to 5 mA.

279

LF111/LF211/LF311

electrical characteristics (LFSID (Note3)

PARAMETER

Input Offset Voltage (Note 41

Input Offset Current (Note 4)

Input Bias Current

Voltage Gam

Response Time (Note 5)

Saturation Voltage

Stiobe On Current

Output Leakage Current

Input Offset Voltage (Note 4)

Input Offset Current (Note 4)

Input Bias Current

Input Voltage Range

Saturation Voltage

Positive Supply Current

Negative Supply Current

CONDITIONS

TA = 25°C. Rs < 50k

TA = 25°C, VCM = 0 (Note 6)

TA = 25°C. VCM = 0 (Note 6)

TA - 25"C

TA = 25"C

V.N < -10 mV, IOUT = 50 mA. TA = 25" C

TA = 25°C

VIN > 10 mV. VOUT - 35V, TA ~- 25"C

Rs <50k

Vs = ±15V. VCM =0 (Note 6)

Vs = ±15V. VCM = 0 (Note 6)

V+ >4 5V, V" = 0VIM < -10 mV, ISINK < 80mA

TA -- 25"C

TA = 25"C

MIN TYP

20

50

25

200

200

0 75

30

02

1 0

30

H4-135

023

5 1

4 1

MAX

10

75

150

1 5

10

15

04

7 5

50

UNITS

mV

pA

pA

V/mV

us

V

mA

nA

mV

nA

nA

VV

V

mA

mA

Noi« 1: This rating applies for il5V supplies The positive input voltage limit is 30V above the negative supply The negative input voltage limitis equal to the negative supply voltage or 30V below the positive supply, whichever is less.Not« 2: The maximum junction temperature of the LFlt l ts +160 C. the LF211 is MIO C and the LF311 is «85 C For operating «»t elevatedtemperatures, devices in the TO-5 package must be derated based on j t net mot lesistance of * 150 C/W, junction to ambient, or * 45 C/W. junctionto case. For the 1lat package, the derating is based on a thermal resistance of M85 C/W when mounted on j 1/16 inch thick epoxy glass boaid withten, 0.03 inch-wide, 2-ounce copper conductor The thermal resistance of the dual in line package is +100 C/W, junction to ambientNow 3: These specifications apply fo/ Vg - ' 15V and 55 C *_ TA •_ M25 C for the LF111, unless otherwise stated With the LF21 1. however,all temperature specif icat ions are limited to 25 C ^ T/^ ^ +85 C and for the LF3110 C < T^< *70 C The of fset voltage, of fset current and biascurrent specifications apply for any supply voltage from a single 5,0 mV supply up to * 15V suppliesNot« 4: The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with a1.0 mA load. Thus, these parameters define an error band and take into account the worst case ef fects of voltage gam and input impedanceNot« 5: The response time specified (see definitions] is for a 100 mV input step with 5 0 mV overdrive.Not« 6' For input voltages greater than 15V above the negative supply the bias and of t sel eu n en t s will mer ease-see typical performance curvesNot« 7: Do not short the strobe pm to ground; it should be current driven at 3 to 5 mA.

typical applications

SQUARE» WAVE

OUTPUT'

• T T L 01 OH linoui ol two

100 kHz F re« Running Multivibrator Cty»t»l Oscillator

280

LF111/LF211/LF311

typical performanceInput Bias Currentvs Common Mode

aa

o-

= U • «25- C =

V~ 4.0 1.0 12 16 20 24 21

INPUT COMMON MODE VOLTAGE (V)

Input Bias Currentvs Temperature

10,000

1.000

100

s

1l.O

-55 -35 -15 5.0 25 4S 65 IS 105 125

TEMPERATURE ft)

Transfer Function

NORMAL OUR,.- 1.0k

- v**-5«V

EMITTEFOLIO»OUTPUTRL -W

,.

tR

)

TPUT

rl ////

V §xIVj]

^v.T,

V

-30•25 C_

-1.« -0.5 I 0.5 M

DIFFERENTIAL INPUT VOLTAGE (nVI

Response Time for VariousInput Overdrives

V

Response Time for VariousInput Overdrives

0.2 0.4 O.I O.ITIME bn)

Output Saturation VoltageO.I

16

"M

TA--»°C-

~~*&-9>

I 1« 21 N 4» MOUTPUT CURRENT («At

Response Time for VariousInput Overdrives

1.« 2.t 3.1 4.1

Response Time for VariousInput Overdrives

t.O 2.0 3.0 40

Supply Current

t 10

-H -K -11 U 2l 4t U M IM 11t

TEMPERATURE CCI

Output Limiting Characteristics Supply Current

u «OUTPUT VOLTAGE (V)

« ( 5.0 II 15 21 25 MSUPPLY VOLTAGE (V)

Leakage Current«

» 4l K U IN inTEMPERATURE CO

281

LF111/LF211/LF311

typical applications (con't)

TRIANGULARWAVCOUTFUT

10 Hz to 10 kHz VolUgt Controlled Oicillitor

Inpul - S O V H j t o S O k H lOutput- lOkHjtolMkHl

Frequency Doubler

>

*\ii »;;

^H&

Zero Crossing Detector Driving MOS Switchv • -tn

Zero Crossing DetectorDriving MOS Logic

•Input poterrty « ftvcnH MfcmMint p* 1 M Mtpvl

Driving Ground-Referred Load Comparator and Solenoid Driver

282

typical applications (con't)

LF111/LF211/LF311

. jxft »rVl "•s, I *

Switching Power Amplifier

«trtxiict

Switching Power Amplifier

nimon

H« «•>!*_< In*. *

Relay Driver with Strobe

to Mnt tfikcv

TTL tnterltct with High L*val Logic

T IM_

Positiv* Pnk D*t*ctor

•S»M ttinii»«

Negativ* P«k D*t*ctor

Using Clamp Oiodn to Improve Response

283

LF155/LF156/LF157 Series

Operational Amplifiers/Buffers

BI-FET TechnologyLF155/LF156/LF157 Series MonolithicJFET Input Operational AmplifiersLF155, LF155A, LF255, LF355, LF355A, LF355B low supply currentLF156, LF156A, LF256. LF356, LF356A, LF356B wide bandLF157, LF157A, LF257, LF357, LF357A, LF357B wide band decompensated (AvM.w = 5)MIN

General DescriptionThese are the first monolithic JFET input operationalamplifiers to incorporate well matched, high voltageJFETs on the same chip with standard bipolar transistors(BI-FET Technology). These amplifiers feature low inputbias and offset currents, low offset voltage and offsetvoltage drift, coupled with offset adjust which does notdegrade drift or common-mode rejection. The devicesare also designed for high slew rate, wide bandwidth,extremely fast settling time, low voltage and currentnoise and a low 1/f noise corner.

Advantages• Replace expensive hybrid and module FET op amps• Rugged JFETs allow blow-out free handling compared

with MOSFET input devices• Excellent for low noise applications using either high

or low source impedance—very low 1/f corner• Offset adjust does not degrade drift or common-mode

rejection as in most monolithic amplifiers• New output stage allows use of large capacitive loads

(10,000 pF) without stability problems

• Photocell amplifiers• Sample and Hold circuits

Common Features(LF155A, LF156A, LF157A)

• Low input bias current• Low Input Offset Current• High input impedance• Low input offset voltage• Low input offset voltage température

drift• Low input noise current• High common-mode rejection ratio» Large dc voltage gain

Uncommon Features.

30 pA3 pA

1 mV3(UV/°C

0.01 pAA/Hz100 dB106 dB

LF155A LF156A LF157A UNITS(AV=5)'

• Internal compensation and large differential inputvoltage capability

Applications• Precision high speed integrators• Fast D/A and A/D converters• High impedance buffers« Wideband, low noise, low drift amplifiers• Logarithmic amplifiers

• Extremelyfast settlingtime to0.01%

• Fast slewrate

• Wide gainbandwidth

• Low inputnoise voltage

4

52.5

20

1.5

125

12

1.5

5020

12

AJS

V/jusMHz

n V A/Hz

Simplified Schematic•vcc

-L S

c*IDpF

Hh!>-

i^

r

^n

-(Y:..

n

—M ——

161-oOUT

C - 2 pF on LF157

284

LF155/LF156/LF157 Series

Absolute Maximum Ratings LF155A/6A/7A LF155/6/7

Supply Voltage »22V *22V

Power Dissipation IPd at 25 CIand Thermal Resistance (0|A> INote 1)

T|MAX(H and J Package) 150 C 150 C

(N Package)(H Package) Pd 670 mW 670 mW

fl,A 150 C/W 150"C/W(J Package) P<j 670 mW 670 mW

H,A 140 C/W 140 C/W(N Package] Pd

»|ADifferential Input Voltage '40V »40VInput Voltage Range (Note 2) *20V »20V

Output Short Circuit Duration Continuous ContinuousStorage Temperature Range 65 C to 1150° C 65 Cto+150°CLead Temperature (Soldering lOsecondsl 300 C 300 C

LF355B/6B/7BLF255/6/7

LF355B/6B/7B»22V

115 C100 C570 mW150" C/W570 mW140 C/W500 mW155 C/W•40V»20V

Continuous

65"C to+150 C300 C

LF355A/6A/7ALF355/6/7

»18V

115 C

100 C570 mW

150° C/W

570 mW140 C/W

500 mW155° C/W

•30V«16V

Continuous

5' C to * 150 C300" C

DC Electrical Characteristics (Notes)SYMBOL PARAMETER CONDITIONS UNITS

VOS

-WQS

_iTC

vo

VCM

CMRR

PSRR

Input O f f se t Voilage

Average TC of Input

Offset Voltage

Change in Average TC

with VQS Adjust

Input Orfsel Curient

Input Bias Current

Input Resistance

Laige S gndl Voltage

Gdltl

Output Voltage Swing

RS 50" TA 25 COver Temperature

RS 50"

RS 50<2 (Note 4|

T| 25 C (Notes 3~5T"

TI THIGHTj 25 C (Noies 3 5)

TJ < THIGHTj 25 C

Vs 15V TA 25 CVQ MOV RL 2kOver Temperature

Vs -15V RL 10k

Vs M 5V R L 2k

Input Common Mode

Vol'age Range

Common Mode Rejection

Rat o

Supply Voltage RejectionRat o

M 5V

(Note 6) dB

AC Electrical Characteristics = 25°cSYMBOL PARAMETER CONDITIONS

LF155A/355A

MIN MAXLF156A/356A

MIN MAX

LF157A/357A

MINUNITS

SR

GBW

CIN

Slew Rate

Gam Bandwidth

Product

Settling Time to 0 01%

LF155A/6A Ay - 1LF157A Ay 5

(Note 7]

Equivalent Input Noise

Voltage

Equivalent Input

Noise Current

Input Capac tance

«S 100Ï2f 100 HJf- 1000 Hi

I 100 Hzf - 1000 Hz

1Û

40

15

V/jjsV/us

nV/x/Hz

nV/\/H7

pF

285

LF155/LF156/LF157 Series

DC Electrical Characteristics (Note 3)

SYMBOL PARAMETER CONDITIONS UNITS

VOS

ATC/.}VOS

IDS

IB

AVOL

VCM

CMRR

PSRR

Input Offset Voltage

Average TC of InputOffset Voltage

Change in Average TCwith VQS Adjust

RS = sou. TA - 25"cOver Temperature

RS = 50U

RS = 50<2. <No1e4|

Input Offset Current

Input Bias Current

T, - 25 C. (Notes 3 5IT i< THIGHTj = 25"C, (Notes 3. 5)TJ< THIGH

Input Resistance

Large Signal VoltageGam

Output Voltage Swing

Tj - 25 C

Vs= ' 15V. TA' 25"C

VQ = '10V, R|_' 2kOver Temperature

Vs= J15V. RL= 10k

VS= *15V. RL = 2k

Input Common Mode

Voltage Range

Common Mode Rejection Ratio

Supply Voltage ReiecRatio

'15V

(Note 6}

DC Electrical Characteristics TA = 25°c. vs

PARAMETER

Supply Current

LF155 A/155,LF2S5.

LF355A/35SB

TYP

2

MAX

4

L F 355

TYP

2

MAX

4

LF156A/156.LF256/356B

TYP

5

MAX

7

LF356A/356

TYP

5

MAX

10

LF157A/157LF257/357B

TYP

5

MAX

7

LF357 A/357

TYP

5

MAX

10

UNITS

mA

AC Electrical Characteristics TA = 25°c, vs

SYMBOL

SR

GBW

CIN

PARAMETER

Slew Rate

Gam Bandwidth

Product

Settling Time to 0 01%

Equivalent Input Noise

Voltage

Equivalent Input

Current Noise

Input Capacitance

CONDITIONS

LF155/6 AV= 1.LF157 AV = 5

UNITS

286

LF155/LF156/LF157 Series

Notes for Electrical CharacteristicsNote 1 The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated byambient temperature, TA The maximum available power dissipation at any temperature is P<j = (T|M/\x ~" A^'jA or tne 25 C P<JMAX- which-ever is lessNote 2' Unless otherwise specified the absolute maximum negative input voltage is eciual to the negative power supply voltage

Note 3: Unless otherwise stated, these test conditions apply.

Supply Voltage, Vg

TATHIGH

LF155A/6A/7AL F 155/6/7

±15V < Vs< !20V

-550C<TA<+125°C+ 125°C

LF255/6/7

i15V <V S < 120V

-25° C< TA< +85° C+85° C

LF355A/6A/7A

±15V < Vs < !18V

0°C <T A < +70°C+70° C

LF355B/6B/7B

115V < Vs i20V

0°C< TA < +70°C+70°C

LF355/6/7

VS = 515V

0°C < TA < +70°C+70° C

and VQS, IQ and IQS are measured at VQ^ = 0Note 1. The Temperature Coefficient of Ihe adjusted input offset voltage changes only a small amount 10 5(iV/ C typically) for each mV ofadjustment from us onginal unadjusted value Common mode rejection and open loop voltage gain are also unaffected by offset adjustmentNote 5 The input bias currents are junction leakage currents which approximately double for every W C increase m the junction temperature, TjDue to limited production test time, the input bias currents measuied are correlated to lunction temperature In normal operation the junctiontemperature rises above the ambient temperature as a result of internal power dissipation, Pd Tj = TA + <-)jA Pd where <-JjA is the thermalresistance from junction to ambient Use of a heat sink is recommended if input bias current is lo be kept lo a minimumNote 6 Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with commonpracticeNote 7 Settling time is defined here, for a unity gam inverter connection using 2 kii resistors for the L F155/6 It is the time required for the errorvoltage (the voltage at the inverting input pin on the amplifier! to settle lo within 0 01% ot its final value from the time a 10V step input is appliedto the inverter For the LF157, Ay = -5, the feedback resistor from output to input is 2 kil and the output step is 10V (See Settling Time TestCircuit, page 91

Typical DC Performance CharacteristicsCurves are for LF155, LF156 and LF157 unless otherwise specified.

Input Bias Current

-55 -25 5 35 K M 125

CASE TEMPERATURE CCI

Iriput Bias Current

-55 -25 5 35 15 it 125CASE TEMPERATURE CO

Input Bias Current

-to -s « 5 inCOMMON MODE VOLTAGE IVI

Voltage Swing Supply Current Supply Current

PEAK

TO

PEA

K O

UTPU

T SW

ING

(VI

s s

s

i

i"TA'25 C

S

/

/

/

/

/

1 10 15 2l

SUPPLY VOLTAGE ('VI

Negative Current Limit

gsl

0 5 10 IS 20 25 31 35OUTPUT SINK CURRENT (mA)

SUPP

IV C

URRE

NT (

«AI

„

K» «*»

*

~~~-~-~-

--^_— —.— •— •

TC • -55 C-1

T c -25 C

ÏC'

L

125 C

>I55

5 ID 15 20 25

SUPPLY VOLTAGE (-VI

Positive Current Limit

0 5 10 15 20 25 30 35 40OUTPUT SOURCE CURRENT (m«!

''^

X

sx

^x

^

/fe1:-

s%TC

L

h•12

15i

i'C

i^C

7

0 5 10 l> 20 25SUPPLY VOLTAGE ('VI

Positive Common-Mode InputVoltage Limit

o ».ÏI

II 1«

5 10 15 20

POSITIVE SUPPLY VOLTS IVI

287

LF155/LF156/LF157 Series

Typical DC Performance Characteristics (Continued)

Negative Common Mode InputVoltage Limit

-5 -10 -15 -JO

NEGATIVE SUPPLY VOUS (V)

Open Loop Voltage Gain

S tO IS 20SUPPIV VOLTAGE f 'V I

Output Voltage Swing

VS - *15VTA -25'C

0 10 10OUTPUT LOAD RL(kS!)

Typical AC Performance Characteristics

Gam Bandwidth Gam Bandwidth Normalized Slew Rale

-55 -15 -15 5 25 45 K K 1K 125TEMPERATURE ( C)

-55 -H -15 t 25 45 «5 K 105 125TEMPERATURE CCI

-SS-35 -IS 5 K 45 «5 IS 105 125

TEMPERATURE TO

LF155 Small Signal Pulte Response,+1

LF156 Small Signal Pulse Responsi LF157 Small Signal Pulse Response,Ay

TIMEIOSvt/DIV) TIMEI05«s/OIVI TIME 10 1 „s/OIVI

LF155 Large Signal Pulse Response,Av-+1

LF156 Large Signal Pulse Response,AV-+I

LF157 Large Signal Pulse Response,Ay" +5

TIMEd .s/OIVI TIMEd.s/OIV) TIME (05 l/DIV)

288

LF155/LF156/LF157 Series

Typical AC Performance Characteristics (Continued)

Inverter Settling Time Inverter Settling Time

a

-10

10

s0

-5

1 -10

I -.5U

-20

-25

ID

7 §

s s

s ;

IBP) OliV

ti N01L33r3H

3QQ

IN f,

Q iu

S 01

1

> 24

1 2"

$ 16

g W=i

=1

o

1 mvV^lmV> \

0 05 10 5

SETTLING TIME U>

Bode Plot

^ÇA

-f

1

pH--Mn

. ———— **r* ——

H

1 1

i.

l -Sx-- -

5 '^-=> ^

10 0.1 1 10

SETTLING TIME M

Bode Plot^T,

- 75 10 ^----JUS —— 5J> RH(

' SU \ V i-o 0 —— — -* -±t

25 = r ( iiîr l, s = "5 |f- -25 5 5 -15 —— —--414

30 « „ ï.

3 25 r -H^^ -» ::: -rtyJ1 -100 35 _ P^.J -I?& <n 1 111

iSE. VS - '15V J5

^ ^ -___ - . 25

s;:::: °25—— — _ J!(- .75

- !- -100u—— _ _ - - . ! -125

10 100 I 10 100FREQUENCY IMHi FREQUENCY (MH,)

Common-Mode Rejection3atia Power Supply Rejection Ratio

^X;>s

\S

iribi/l

V S - -15VR L » 2 k

v T A - 2 5 C

\s \\ \F1"\ N

^

IUU ^^

X^\6n ———————— X_

NEGATIVSUPPL

1 M

S £? n

LF155T A ' Z 5 C

V— VS - I5V-\ POSITIVE\ SUPPLY

>3v \V\1 100 Ik 10k 100k IM 10M '» 100 1k 10k 100k IM

FREQUENCY IHil FREQUENCY (Hi)

Indistorted Output Voltage Swing n Equivalent Input Noise Voltage

1 4-^-.3

-LFISsJL..

———44 W* — pulLl

-14 \>\^\- -iA^

i i .;;jj -! . Mill

JI.I- 4-U • V S . - 1 5 V•tt R l -2k- f W T A . Z S C-ll»v"-J l 1XDIST

^Plf

^ \ A V = ^

IJV r i i^ i Tjt'NfcJ j

, '^Skr>h Til

5' 140 -• - I

10 - - t - • • I

BO -... _k Ä40 - -LF I66 /7S W-

- - • • ' ' i K

TA " 25 C II il

i luiIB lllfl[| 1 lu

_ . . t ...ffl

" F" 15 "" lr~" ili iims inn9 ni

101 100k IM IOM Si 10 100 tk 10k

FREQUENCY (H, FREQUENCY (H.)

110

I 90z

70

50

30

100

10

Open Loop FrequencyResponse

\V^^vs\^o>

N\svIF15

^ —

-vs

-LFI

*\

V^

- -is

-56

S\S^V

^v

10 100 III 10k 100t IM IOM

FREQUENCY (Hil

Bode Plot

LFIS7' VS- -15V

20

15105D

-5-10-15-20

— GAIN

K

1007550

- So Sm

-U 5-50 o

~" I-100 ö

-125-150-175

10

FREQUENCY IMHil

Power Supply RejectionRatio

—^v. \\

N,

——— L

__ ME

N'S

S.. \\ v

h"CATIVE

T A - 2 5 ' C^VS- -1SV

!w POSITIVE SUPPLYN. 1- F I56/7

Nv

"\S

SUPPLY

\\

\Ls\ sX

vsX

S.\\s

100 1k 10k 100k IM 1DM

FREQUENCY (Hil

Equivalent Input NoiseVoltage (Expanded Scale)

T A - 2 5 C _Vc- -15V

Ik

FREQUENCY IHi)

289

LF155/LF156/LF157 Series

Typical AC Performance Characteristics (Continued)

Output Impedance Output Impedance Output Impedance1000

Ik IM 100k IM 10M

FREQUENCY (Hi)

Ik tOk 100k IM IM

FREQUENCY (Mi)

i 10

H 10k 100k IM 10M

FREQUENCY |Hi)

Detailed Schematic0-»cc

*C"2pFon LF157

Connection Diagrams (Top views)Metal Can Package (HI

NC

Order NumberLF155AH LF156AH LF157AHLF155H LF156H LF157HLF255H LF256H LFZ57HLF3S5AH LF356AH LF357AHLF355H LF356H LF357H

See NS Package H08C

Not» 4: Pin 4 connected to caw.

Dual-ln-Line Package (N or J)

IAIAIICE ——

INPUT •

TJ

Order Number LF355N. LF356Nor LF357N

See NS Package N08B

290

LF155/LF156/LF157 Series

Application HintsThe LF155'6/7 series are op amps with JFET inputdevices These JFETs have large reverse breakdownvoltages from gate to source and drain eliminating theneed for clamps across the inputs Therefore laigedifferential input voltages can easily be accomodatedwithout a laige increase in input current The maximumdifferential input voltage is independent of the supplyvoltages However, neither of the input voltagps shouldbe allowed to exceed the negative supply as this willcause large currents to flow which can result in adestroyed unit

Exceeding the negative common mode limit on eitherinput will cause a reversal of the phase to the outputand force the amplifier output to the correspondinghigh or low state Exceeding the negative common modelimit on both inputs will force the amplifier output to ahigh state In neither case does a latch occur sinceraising the input back within the common mode rangeagain puts the input stage and thus the amplifier m anormal operating mode

Exceeding the positive common mode limit on a singleinput will not change the phase of the output howeverif both inputs exceed the limit, the output of theamplifier will be forced to a high state

These amplifiers will operate with the common modeinput voltage equal to the positive supply In fact, thecommon mode voltage can exceed the positive supply byapproximately 100 mV independent of supply voltageand over the full operating temperature range Thepositive supply can therefore be used as a reference onan input as for example m a supply current monitorand/or limiter

Precautions should be taken to ensure that the powersupply for the integrated circuit never becomes reversed

Typical Circuit ConnectionsDriving Capacitive Loads

in polarity or that the unit is not inadvertently installedbackwards m a socket as an unlimited current surgethrough the resulting forward diode within the 1C couldcause fusing of the internal conductors and result in adestroyed unit

Because these amplifiers are JFET rather than MOSFETinput op amps they do not require spenal handling

All of the bias currents in these amplifiers are set by FETcurrent sources The diain currents for the amplifiers aretherefore essentially independent of supply voltage

As with most amplifiers, care should be taken with leaddress, component placement and supply decoupling inorder to ensure stability For example, resistors from theoutput to an input should be placed with the body closeto the input to minimize "pickup" and maximize thefrequency of the feedback pole by minimizing thecapacitance from the input to ground

A feedback pole is created when the feedback aroundany amplifier is resistive The parallel resistance andcapacitance from the input of the device (usually theinverting input) to ac ground set the frequency of thepole In many instances the frequency of this pole ismuch greater than the expected 3 dB frequency of theclosed loop gam and consequently there is negligibleeffect on stability margin However, if the feedback poleis less than approximately six times the expected 3 dBfrequency a lead capacitor should be placed from theoutput to the input of the op amp The value of theadded capacitor should be such that the RC timeconstant of this capacitor and the resistance it parallelsis greater than or equal to the original feedback poletime constant

LF157 A Large Power BW Amplifier

»out

A/\7i«« vy ^y

is adjusted with a 25kpotentiometerThe potentiometer wiper isconnected to V1"For potentiometers withtemperature coefficient of100 ppm/ C or less theadditional drift with adjustis - 0 5 nW C/mV ofadjustmentTypical overall dr i f t 5 /W/C (05 u\lf C/mV of

ad) l

L _ _ J"LF155/6 R -5k

LF157 R - 1 25k

Due to a unique output stage design these amplifiers have the ability to drive large capacitive loadsand still maintain stability CLIMAX) 0 n' ^

Overshoot _ 20°o

Settling time lts) 5 us

For distortioh £ 1% and a 20 Vp pVQUT swing, power bandwidth is500 kHz

291

LF155/LF156/LF157 Series

Typical Applications

Settling Time Test Circuit

2k. O.I*—vw

10V

0

2k. OIS•400. DIX

o • vw * ' -

'-T-T r•IOV.fl . lSJ -±

-15V O

«l 2N«i6 • Settling time is tested with the LF155/6 connected100 of t °UT as un''V 9a'n inverter and LF157 connected for

Av = -5• FET used to isolate the probe capacitance• Output = 10V step• Ay = -5 for LF157

LF355

Large Signal Inverter Output. VQJJT (from Settling Time Circuit)

LF356 LF357

2M!/DIV tus/DIV

Low Drift Adjustable Voltage Reference

vo u t - iov

= '0.002%/ CAll resistors and potentiometers should be wire-woundP1 : drift adjust

Use LF155 for» Low lg» Low drift* Low supply current

292

LF155/LF156/LF157 Series

Typical Applications (Continued)Fast Logarithmic Converter

Klut

• Dynamic range: 100 pA < I, < 1 mA(5 decadesl. IVQl - 1V/decade

• Transient response. 3 MS for AI, • 1 decade• CI, C2. R2. R3: added dynamic compen-

sation• VOS adjust the LF156 to minimize quiescent

error• Rj: Tel Labs type Q81 + 0.3%/°C

- log V.R. Ir

R2 - 15.7k, RT - 1k, 0.3%/°C (for temperature compensation)

Precision Current Monitor

• Vo = 5R1/R2(V/mAof ls)• R1, R2. R3 01% resistors• UseLF155for

* Common-mode range to supply range» LOW IQ» Low VQS* Low supply current

8-Bit D/A Convertir with Symmetrical Offset Binary Oparation

MM LAB15V II U 11 H BS >( 17 M

TnTiîtT»îiï«TioTnTHvREf-nvo—WV^1

• RI, R2 should be matched within i0.05%• Full-scale response time: 3 MS

EO+9.920+0.040-0.040-9920

B1

1100

B2

1010

B31010

B4

1010

B5

1010

B6

1010

B7

1010

B81010

COMMENTS

Positive Full-Scale(+) Zero-Scale{-) Zero-ScaleNegative Full-Scale

293

LF155/LF156/LF157 Series

Typical Applications (continued)Wide BW Low Noise, Low Drift Amplifier

C!

Power BW IMAX ~ 240 kHz2*Vp

• Parasitic input capacitance C1 - 13 pF forLF155. LF156 and LF157 plus any additionallayout capacitance) interacts with feedbackelements and creates undesirable high frequencypole To compensate add C2 such that R2C2 ~R1C1

Boosting the LM56 with a Current Amplifier

i l k

V*

' 01>.f

l\ 'o

'OUT(MAX)

TTmA Iwill drive RL _ 100SH

0 15——y V/jjs (with CL shown)

No additional phase shift added by the current amplifier

3 Decades VCO

Isolating Large Capacitive Loads

vout

• Overshoot 6%• ts 10 us• When driving large C(_, the VQUT slew rate deter

mined by C|_ and IQUTIMAXI

IOUT 0023 —— V/us = 0 04 V/us (with CL shownl

C[_ 05

Low Drift Peak Detector

• By adding 01 and Rf, VQ^ = 0 during hold mode Leakage ofD2 provided by feedback path through Rf

• Leakage of circuit is essentially ID ILF155, LF156) plus capacitor leakage of Cp

• Diode D3 clamps VQLIT ^^' *° ^IN~^D3 to improve speed andto limit reverse bias of D2

• Maximum input frequency should be <s. 1/2nRfC02 whereCrj2 1S tne shunt capacitance of D2

Non Inverting Unity Gain Operation for LF157ni

R1C ;1

R1 =

(2n) (SMHzl

R2 + Re

AV(DC)

'-3 dB *

Inverting Unity Gain for LF157

Vr (R8*R7)f —-t—————— . 0< VC< 30V. 10 H; <- f < 10kHz

18 VPU R8R1IC - ^ - - -R1, R4 matched Linearity 0 1% over 2 decades 3dB

294

LF155/LF156/LF157 Series

Typical Applications (Continued)High Impedance, Low Drift Instrumentation Amplifier

«15V

VOUT

ft1)VOUT " — —— + 2V <V|pg common-mode < V+

• System VQS adjusted via A2 VQS adiust• Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier

Resistor array RA201 (National Semiconductor) recommended

Fast Sample and Hold

JFET SWITCHESIfI113I

SW1 ORAH0114

N"

• Both amplifiers (AI, A2) have feedback loops individually closed with stable responses (over-shoot negligible)

• Acquisition time TA, estimated by:

TA 2RQN.VlN.ChlSr J

provided that:

VIN < 2nSr RON Ch and TA >

If inequality not satisfied: TA

'OUT(MAX), RON is °f swi

20mA• LF156 developes full S, output capability for VIM > 1V• Addition of SW2 improves accuracy by Putting the voltage drop across SW1 inside the feedback

loop• Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2

295

LF155/LF156/LF157 Series

Typical Applications (Continued)High Accuracy Sample and Hold

VOUT

• By closing the loop through A2, the VQUT accuracy will be determined uniquely by AIMo Vgs adjust required for A2

• TA can be estimated by same considerations as previously but, because of the addedpropagation delay m the feedback loop (A2) the overshoot is not negligible

• Overall system slower than fast sample and hold• RI.CC additional compensation• Use LF156 for

* Fast settling time* Low VQS

High Q Band Pass Filter

IpF

VOUT

By adding positive feedback (R2)Q increases to 40fBP = 100 kHz

VOUT

Clean layout recommendedResponse to a 1 Vp p tone burst300 MS

High Q Notch Filter

VOUT • 2R1 = R = 10 MH2C = CI = 300 pF

• Capacitors should be matched to obtain high Q• 'NOTCH = 120 Hz, notch = -55 dB, Q ^ 100• Use LF 155 for

* Low IB* Low supply current

296

LM118/LM218/LM318

LM118/LM218/LM318 operational amplifiersgeneral descriptionThe LM118 series are precision high speed opera-tional amplifiers designed for applications requiringwide bandwidth and high slew rate They featurea factor of ten increase in speed over general purpose devices without sacrificing DC performance

features" 15 MHz smdll signal bandwidth• Guaranteed 50V//jis slew rate• Maximum bias current of 250 nA• Operates from supplies of ï5V to ±20V• Internal frequency compensation• Input and output overload protected• Pin compatible with general purpose op amps

The LM118 series has internal unity gam frequencycompensation This considerably simplifies its appli-cation since no external components are necessaryfor operation However, unlike most internally

compensated amplifiers, external frequency compensation may be added for optimum performanceFor inverting applications, feedforward compensation will boost the slew rate to over 150V/pisand almost double the bandwidth Overcompensation can be used with the amplifier for greaterstability when maximum bandwidth is not neededFurther, a single capacitor can be added to reducethe 01% settling time to under 1 /^s

The high speed and fast settling time of these opamps make them useful in A/D converters, oscillators, active filters, sample and hold circuits, orgeneral purpose amplifiers These devices are easyto apply and offer an order of magnitude betterAC performance than industry standards such asthe LM709

The LM218 is identical to the LM118 except thatthe LM218 has its performance specified over a-25°C to+85°C temperature range The LM318 isspecified from 0°C to +70° C

schematic and connection diagrams

Flat Package

) CQMKMATI0* I

Mital Can Package* Dual-ln-Line Package

*Pm connections shown on schematic diagramand typical applications are for TO-5 package

Order Number LM118H. LM218Hor LM318H

Sa« NS Package H08C

Order Number LM118J 8,LM218J8or LM318J8

See NS Package J08AOrder Number LM318NSee NS Package N08B

Order Number LM118F or LM218FSee NS Package F10A

Dual-In Line Package

CMMMAT1M1

Order Number LM118J, LM218Jor LM318J

See NS Package J14AOrder Number LM118D, LM218D

or LM318OSee NS Package 014E

297

LM118/LM218/LM318

absolute maximum ratingsSupply VoltagePower Dissipation (Note 1)Differential Input Current (Note 2)Input Voltage (Note 3)Output Short-Circuit DurationOperating Temperature Range

LM118LM218LM318

Storage Temperature RangeLead Temperature (Soldering. 10 seconds!

±20V500 mW±10 mA

+ 15VIndefinite

-55°Cto+125°C-25° C to +85° C

0°C to +70° C-65°Cto+150°C

300°C

electrical characteristics (Note 4)

PARAMETER

Input Offset Voltage

Input Offset Current

Input Bias Current

Input Resistance

Supply Current

Large Signal Voltage Gain

Slew Rate

Small Signal Bandwidth

Input Offset Voltage

Input Offset Current

Input Bias Current

Supply Current

Large Signal Voltage Gain

Output Voltage Swing

Input Voltage Range

Common-Mode Rejection Ratio

Supply Voltage Rejection Ratio

CONDITIONS

TA = 25°C

TA = 25"C

TA = 25°C

TA = 25°C

TA = 25°C

TA = 25°C. VS = ±15V

VOUT= ilOV. R | _ > 2 k £ 2

TA = 25"C. Vs = ±15V.Av = 1

TA = 25"C. Vs= 115V

TA = 125"C

Vs = ±15V, VOUT = ilOVR L > 2 k J 2

Vs = ±15V. RL = 2 k S >

V$ = '- 15V

LM118/LM218

MIN TYP MAX

2 4

6 50

120 250

1 3

5 8

50 200

50 70

15

6

100

500

4.5 7

25

t12 ±13

±11 5

80 100

70 80

LM318

MIN TYP MAX

4 10

30 200

150 500

05 3

5 10

25 200

50 70

15

15

300

750

20

±12 ±13

+ 11 5

70 100

65 80

UNITS

mV

nA

nA

Mil

mA

V/mV

V.Vs

MHz

mV

nA

nA

V,mV

V

V

dB

dB

Note 1: The maximum junction température of the LM118 is 150"C, the LM218 a 110'C. and the LM318 is 110"C. For operating at elevatedtemperature*, devices in the TO-5 package must be derated based on a thermal resistance of 150 C/W. junction to ambient, or 45' C/W. junctionto case. For the flat package, the derating is baser! on a thermal resistance of 185°C/W when mounted on a 1/16 inch-thick epoxy glass board withten, 0.03 inch-wide, 2 ounce copper conductors The thermal resistance of the dual-in-line package is 100' C/W. (unction to ambientNot« 2: The inputs are shunted with back-to-back diodes for overvollage protection. Therefore, excessive current will flow if a differential inputvoltage in excess of IV is applied between the inputs unless some limiting resistance is used.Not« 3: For supply voltages less than > 15V, the absolute maximum input voltage is equal to the supply voltage.Not« 4: These specifications apply for i5V < V$ < 120V and-55°C < TA < +125"C.(LM118>.-25"C < T^ < +85°C (LM218). and 0"C < TA< +70' C (LM318I. Also, power supplies must be bypassed with O.lpF disc capacitors.

298

LM118/LM218/LM318

typical performance characteristics LMHS, LM2is

Input Current Voltage Gain Power Supply Rejection

-SS -36 -15 5 25 45 ES 15 105 125

TEMPERATURE I C)

10 16

SUPPLY VOLTAGE I V)

£>~j

IM

10

BO

20

0

-20

POSITIVE SUPPLY

r NEGATIVE SUPPLY

T» • n c

100 tk 10t. 100k IM 10M

FREQUENCY (Hi]

Input Noise Voltage Common Mode Rejection Supply Current

10 100 Ik 10k 100k

FREQUENCY (Hi)

120

2 100

o

UJ

UJ

i 60

1 40

I 2°U

0

Rs - 2 kllT . - 2 5 C —

100 tk I Ok 100k 1M IOM

FREQUENCY (Hi)

S 10 IS

SUPPLY VOLTAGE I V)

Closed Loop OutputImpedance

10 100 Ik 10k 100k IM

FREQUENCY IHi)

Current Limiting

T, •125 C

S 10 IS 20 26

OUTPUT CURRENT ImA)

Input Current

-too

I IT * > 2 5 C -

-01 -01 -04 -«2 0 02 04 0« 01

DIFFERENTIAL INPUT (VI

Unity Gam Bandwidth Voltage Follower Slew Rate Inverter Settling Time; a

s 2

:CHH» M

J.OIM

O

1 "

1 10

1_

<.s

1

-V

V

= ' i

^-

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299

LM118/LM218/LM318

typical performance characteristics LMHB, LM2is

Large Signal FrequencyResponse

05« IM 2M 5M 10M 20M 50M

FREQUENCY (H!)

Open Loop FrequencyResponse

> 10 -•oz | ..51 * "3 j

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n . .

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10 100 Ik 10k 100k 1M IOM 100M

FREQUENCY (Mil

Large Signal FrequencyResponse

t'

-Vy

——

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fRIOUtNCY (Mil

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—*tt-L

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1 01 03 0

TIME [„i

0

— (

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UTPU1

-- -

T» -25 CVs 15V

5 07 0

typical performance characteristics

Input Current200IM

-,„BIAS

OFFSET

« 10 20 30 40 M 10 70

TEMPERATURE TO

Voltage Gam Power Supply Rejection

10 15

SUPPLY V O L T A G E ! V)

10k 100k IM 10M

FREQUENCY (Hi)

Input Notse Voltage Common Mode Rejection

100 1k 10kFREQUENCY [Hi)

100k

Supply Current

100 It 10k 100h IM

FREQUENCY (Mil10 IS

SUPPLY VOITAGEI V)

âoo

LM118/LM218/LM318

typical performance characteristics LM3is (Cont'd)

Closed Loop Output Impedance Current Limiting Input Current

IOJ

u tn1

ac

| 10°

| to1

Z3

1

AV

^

— •» ——

« 1000/

s

Vs- 15VTA -25 C

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r

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n

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TA

15V

—••S

•70 C

-25 C-

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——

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! «u= -200

-400

-EDO

i— V

\\I

0 100 Ik 10k 100k IM 0 5 10 15 20 25 -01 -06 -04 -02 0 02 04 tl 0

FREQUENCY (Hi) OUTPUT CURRENT ImAl DIFFERENTIAL INPUT (V)

Unit Gun Bandwidth

0 10 20 30 40 50 60 70

TEMPERATURE I C)

Voluge Follower Slew Rate

0 tO 20 30 40 50 60 70

TEMPERATURE ( C)

Inverter Settling Time

|

003 Ot 03 1

TIME M

Large Signal Freque )cyResponse

05M IM 2M it» 10M 20M 50M

FREQUENCY (Hi)

Open Loop FrequencyResponse

' 112 --

> 10 --u>z 1 - 1B 1r- fi _ _1a.»—3 .

U - .

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1

"l

VNr»,™s

T*Vs

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CV

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Voltage Follower PulseResponse

10 100 Ik 10k 100k IM 10M 100M

FREQUENCY (Hi)

Large Signal FrequencyResponse

Open Loop FrequencyResponse Inverter Pulse Response

I«

12

to

1

6

4

2

01M

t-'n-"

•\\

TV

FEEOFt

V.

A

s-

1 125 C

15V

IRWARO

IM IHM 30M

FREQUENCY (Hi)

r ""too

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*-

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UT

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'KC• '15V

-20 —————————————————————— -.„ ———————————————————————tooM 1» 100 Ik 10k 100k IM 10M IOOM -01 01 03 05 07 0

FREQUENCY (Hi) TIME W

301

LM118/LM218/LM318

auxiliary circuits

•bltnct atom Mcttsary fot

Feedforward Compensation for GreaterInverting Slew Rate*

'Sin. .«dunlin,OTO to 0 IX fat itOVnipch»i|irtlOOm

Compensation for MinimumSettling* Time

Offset Balancing

j

•*————*— ouiruiFI,T

Isolating Large Capacitive Loads Overcompensation

typical applications

*D» mt Harftmn it vott»f«(R1 > S kll)

Fast Voltage Follower *

rFast Summing Amplifier

1« .»ui—V^-Ai

rDifferential Amplifier

Four Quadrant Multiplier

302

typical applications (con't)

LM118/LM218/LM318

tNIU 1 r ____!••» TT

SAMPIE

Fast Sample and Hold

fROMSWUCHlS

•OplioniJ - Rctfueti Htuitu Hmt

O/A Converter Using Ladder Network

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D/A Converter Using Binary Weighted Network

IWK '.

»1,1 "•:

Fast Summing Amplifierwith Low Input Current

«, ; _L_ ci" f T""" "L|-""

1———I R1 • R2- - 4 - C I - C Z

10V-14mA bulb ELDEMAIIE9

1Z . R 2 C 1

Wem Bridge Sine Wave Oscillator

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••* "i

Instrumentation Amplifier

303

LM710/LM710C

LM710/LM710C voltage comparatorgeneral descriptionThe LM710 series are a highspeed voltage comparators intended for use as dn accurate, low leveldigital level sensor or as a replacement for operational amplifiers in comparator applications wherespeed is of prime importance The circuit has adifferential input and a single ended output, withsaturated output levels compatible with practicallyall types of integrated logic

The device is built on a single silicon chip whichinsures low offset and thermal drift The use ofa minimum number of stages along with minoritycarrier lifetime control (gold doping) makes thecircuit much faster than operational amplifiers insaturating comparator applications In fact, the low

Voltage Comparators

stray and wiring capacitances that can be realizedwith monolithic construction make the device difficult to duplicate with discrete components operating at equivalent power levels

The LM710 series are useful as pulse height discnmmators, voltage comparators in high speed A/Dconverters or go, no go detectors m automatic testequipment They also have applications in digitalsystems as an adjustable threshold line receiver oran interface between logic types In addition thelow cost of the units suggests it for applicationsreplacing relatively simple discrete componentcircuitry

schematic" and connection diagrams

-4» * *

it ' 01

Metal Can Package Dual tn Line Package

feOCO*Mn ON

Order Number LM710Hor LM710CH

See NS Package H08C

Order Number LM710Nor LM710CN

See NS Package N14A

typical applications Line Receive With IncreasedOutput Sink Currant

Schmitt Trigger

Level Detector With Lamp DriverPulse Width Modulator

AAA__

-MIL•Pm connections shown are for metal can

304

LM710/LM710C

absolute maximum ratingsPositive Supply VoilageNegative Supply VoltagePeak Output CurrentOutput Short Circuit DurationDifferential Input VoltageInput VoltagePower Dissipation

TO 99. (Note I)Flat Package. (Note 2)

+ 14V-7V

10mA10 seconds

•5V

300 mW200 mW

Operating Temperature Range TWIN *MAXLM710 -55"Cto t!25"CLM7IOC O C « o t ? 0 ' C

Storage Temperature flange -65"C to »150"CLead Temperature {Soldering, 60 seconds) 300 C

electrical characteristics (Note 3)

PARAMETER

Input Offset Voltage

Input Offset Current

Input Bias Current

Voltage Gain

Output Resistance

Output Sink Current

Response Time

Input Offset Voltage

Average Temperature Coefficient

of Inpul Offstt Voltage

Input Offset Current

Average Température Coefficient

of Input Offset Current

Input B'as Current

Input Voltage Range

Common Mode Rejection Ratio

Differential Input Voltage Range

Voltage Gain

Positive Output Level

Negative Output Level

Output Sink Current

Positive Supply Current

Negative Supply Current

Power Consumption

CONDITIONS

RS < 200U. VCM = ov, TA - 25"cVOUT - i 4v. TA - 25°cTA - 25"cTA ' 25"C

TA - 25"C

VOUT • o. TA <=• 25"c

AV|N> 10 mV

TA " 25°C, (Note 4)

RS < 200S2. VCM - OV

TMIN < TA < TMAXR S <50SZ

TA • TA MAXTA • TA MIN25"c < TA < TMAXTMIN i TA-_25'cTA " TMINV~ = -7V

RS < 2oon

-5 mA < IOUT < 0VIN > 5 mV

V|N> 10 mV

VIN 5 5 mVV|N> 10 mV

VIN > 5 mV. VOUT • oTA' 125'C

TA • -55"C

V|N> 10 mV. VOUT '0O ' C < T A < *70"cVIN > 5 mVVIN "• 10 mV

VIN > 5 mVVIN> 'O mV

IOUT • oVIN > 5 mVV|N> 10 mV

LM710

MIN TVP MAX

06 20

075 30

13 20

1250 1700

200

20 25

40

30

30 10

025 3018 70

50 2515 75

27 45

i50

80 100

i50

1000

2.5 32 40

-10 -05 0

05 1.71 .0 2.3

5.2 90

4 6 7 0

90 150

LM710C

MIN TVP MAX

1 6 50

18 50

16 25

1000 1500

200

1.6 25

40

65

5.0 20

7575

15 5024 100

25 40

•50

70 98

•50

800

2.5 32 40

- 1 0 -05 0

05

52 90

46 7.0

150

UNITS

mV

^A

uA

11

mAmA

ns

mV

„vrc

uA

uA

nA/'C

nA/"C

*A

V

dB

V

V/V

V

vvv

mAmA

mA

mA

mA

mA

mA

mWmW

Not« 1: Rating applie» força« temperatures to 125°C for LM710 and to 70° C for LM710C; derate linearly •i5.6rnW/°C torombient temptrt-tor« above 106°C.Not« 2: Derate linearly at 4.4 mW/°C for ambient temperatures above 100°C.Not« 3: These specifications apply for V* • 12V, V~ • -6V, -55°C < TA < +125*C for LM710 and <fC < TA < +70°C for LM710C unl«»iotherwise specified. The input offset voltage and input offset current (see definitions) are specified for a logic threshold voltage of 1 8V at -55°C,1.4V«t25°C, and IV« 125°Cfor LM710and 1.5VatO°C. 1.4V at 25°C and 1.2V at 70°C for LM710C.Not« 4. The response time specified (see definitions) ii a 100 mV input step with S mV overdrive (LM710) or a 10 mV overdrive (LM710C).

305

LM710/LM710C

typical performance characteristics

Transfer Function Voltage Gain Voltage Gain

-50 -30 -10 10 30 iOINPUT VOLTAGE (mVI

Input Bias Current

-75 -50 -25 0 25 50 75 100 125

TEMPERATURE ("O

Response Time ForVarious Input Overdrives

0 20 40 SO M 100 120TIME (ni

Output VoltageLevel

-50 -24 0 25 50 75 100 I2STEMPERATURE CO

1700

Ul

S 1500o

1400

1300-7

20

3

10

X

0-;

30

20

: 0

-10

0

-50

[ -100

35

|30

JE

u

I»t-

1"t o

-7

XsV* • 12V

N- . -6 0V

VA k

\

N-50 -25 0 25 50 75 100

TEMPERATURE I°CI

Input Offset Current

\

Nss\^

VV

V

' 17V• -60V

'

12

~

5 -50 -25 0 25 50 75 100

TEMPERATURE I°O

Response Time ForVarious Input Overdrives

ai

I0n20 n

m:JJN

^

v^

%-- 2„- !S-s

OmVOmV

^5

V •V "

-T. •

k

12V-60V2S°C

3000

2500

| 2000UU*

5 1500o

1000

5005 1

i

10

^ B

Z g

ŒŒ

U

&

2

125

0 20 40 60 tO 100 120TIME Irai

Output SinkCurrent

~~S ^- ••»• =»

5 -SO -25 0

^

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0 11 12 13 1POSITIVE SUPPLY VOLTAGE IV)

Supply Current

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GA IVE

-04 -02 0 02 04

INPUT VOLTAGE (V)

Common Mode PulseResponse

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POW

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306

LM741/LM741A/LM741C/LM741E

Operational Amplifiers/BuffersLM741/LM741A/LM741C/LM741E operational amplifiergeneral descriptionThe LM741 series are general purpose operationalamplifiers which feature improved performanceover industry standards like the LM709. They aredirect, plug-in replacements for the 709C, LM201,MC 1439 and 748 in most applications.

The amplifiers offer many features which maketheir application nearly foolproof: overload pro-

tection on the input and output, no latch-up whenthe common mode range is exceeded, as well asfreedom from oscillations.

The LM741C/LM741E are identical to theLM741/LM741A except that the LM741C/LM741E have their performance guaranteed overa 0°C to +70°C temperature range, instead of-55°Cto-H25°C.

schematic and connection diagrams (Top views)

>Hn

:"• i

TH.iIM i

0» Oll

._ ' WftnNULL

! 1 K *

r i1 MK

! 'Oil OUVr

1 —— LSi

; \ •'« ;

01)

"— c! Hit

H

DM

Metal Can Package Flat Package

Net*. PM 4 c*UMCtt4 u MM.

Order Number LM741H. LM741AH,LM741CHorLM741EHSee NS Package H08CDual-1 n-Lint Package

WVIftlMC WfUT I

MMWVtltTUtt IWurf

Neu hu S ceitMttté1 te eettem et BKkefe

Order Number LM741F or LM741AFSee NS Package F10ADual-in-Lin« Package

u

Order Number LM741CN or LM741ENSee NS Package N 08B

Order Number LM741CJor LM741EJSee NS Package J08A

Order Number LM741CD, LM741O,LM741AO or LM741EOSee NS Package D14E

Order Number LM741CN-14See NS Package N14 A

Order Number LM741J-14, LM741AJ-14LM741CJ-14 or LM741EJ-14

Sea NS Package J14A

307

LM741/LM741A/LM741C/LM741E

absolute maximum ratings

Supply VoltagePower Dissipation (Note 1 )Differential Input VoltageInput Voltage (Note 2)Output Short Circuit DurationOperating Temperature RangeStorage Temperature RangeLead Temperature

(Soldering, 10 seconds)

LM741A

±22V500mW

±30V±15V

Indefinite-55°Cto+l25°C-65°Cto+150°C

300° C

LM741E

±22V500mW+30V±15V

Indefinite0°Cto+70°C

-65°Cto+150°C300° C

LM741

±22V500 mW

±30V±15V

Indefinite-55°Cto+125°C-€5°Cto+150°C

300° C

LM741C

±18V500 mW

+ 30V±15V

Indefinite0°C to +70°C

-65°Cto+150"C300°C

electrical characteristics (Note3i

PARAMETER

Input Offset Voltage

Average Input OffsetVoltage Drift

Input Offset VoltageAdjustment flange

Input Offset Current

Average Input OffsetCurrent Drift

Input Bias Current

Input Resistance

Input Voltage Range

Large Signal Voltage Gain

Output Voltage Swing

Output Short Circuit

Current

Common ModeReaction Ratio

CONDITIONS

TA = 25°CRS<ioknRs<5onTAMIN <TA< TAMAXRS<50S!RS< 10kf2

TA • 25°C. Vs • ±20V

TA - 25°CTAMIN <TA< TAMAX

TA • 2S°cTAMIN <TA< TAMAXTA - 25°C, Vs - ±20VTAMIN < TA < TAMAX.Vs - ±20V

TA • 25°CTAMIN < TA < TAMAXTA- 25°C, R L > 2 k S iVs = ±20V. VQ- 1 15VVs- t!5V. VQ- ±10VTAMIN '_- TA < TAMAX.R L > 2 k S 2 .

Vs- J20V, VQ« ±15VVs- *15V.V0- 110VVs- ±5V. VQ - ±2V

Vs - ±20VRI_ > 10 kuR L > 2 k S 2Vs' 115VRL> 10kSÎRL>2kn

TA - 25° cTAMIN < T A< TAMAXTAMIN < T A< TAMAXR S < lOkSi . VCM= '12VRS < 50 k!2. VCM = '12V

LM741A/LM741EMIN TYP MAX

08 30

40

15

±10

30 3070

05

30 300210

1 0 6005

50

32

10

•16•15

10 25 3510 40

80 95

LM741MIN TYP MAX

10 50

60

!15

20 20085 500

80 500I 5

03 20

•12 113

50 200

25

*12 *14»10 ±13

25

70 90

LM741CMIN TYP MAX

20 60

7 5

±15

20 200300

80 50008

03 20

«12 ±13

20 200

IS

±12 ±14

±10 ±13

25

70 90

UNITS

mV

mV

mV

mV

uV/'C

mV

nA

nA

nA/°C

nAWA

MflMQ

V

V

V/mV

V/mV

V/mV

V/mV

V/mV

VV

V

V

mAmA

dB

dB

308

LM741/LM741A/LM741C/LM741E

electrical characteristics (con't)

PARAMETER

Supply Voltage RejectionRatio

Transient ResponseRise TimeOvershoot

Bandwidth (Note 4)

Slew Rate

Supply Current

Power Consumption

LM741A

LM741E

LM741

CONDITIONS

TAMIN < TA < TAMAXVs~ ±20Vto Vs = î5VRS<BOÎÎRs<10kîî

TA - 25°C. Unity Gam

TA = 25°C

TA - 25°C, Unity Gain

TA - 25°C

TA - 25°CVs - ±20VVs- ±15VVs - ±20V

TA" TAMINTA - TAMAXVs = ±20V

TA • TAMINTA - TAMAXV$ = 115V

TA= TAMINTA • TAMAX

LM741A/LM741EMIN TYP MAX

86 96

025 0860 20

0437 15

03 07

80 150

165135150150150

LM741MIN TYP MAX

77 96

035

05

17 28

50 85

60 10045 75

LM741CMIN TYP MAX

77 96

035

05

17 28

50 85

UNITS

dBdB

US

%

MHz

V/;«

mA

mWmW

mWmWmWmWmW

mWmW

Note 1. The maximum junction temperature of the LM741/LM741A is 150°C, while that of the LM741C/LM741E is 100°C. For operation atelevated temperatures, devices m the TO 5 package must be derated based on a thermal resistance of 150°C/W junction to ambient, or 45°C/Wjunction to case The thermal resistance of the dual-in-line package is 100°C/W junction to ambient For the flat package, the derating is based ona thermal resistance of 185°C/W when mounted on a 1/16 inch thick epoxy glass board with ten, 0 03 inch wide, 2 ounce copper conductorsNote 2: For supply voltages less than ! 15V, the absolute maximum input voltage is equal to the supply voltageNote 3: Unless otherwise specified, these specifications apply for Vs = ±15V, -65°C < TA < +125°C (LM741/LM741 A). For the LM741CVLM741E. these specification! are limited to 0°C < TA < +70°C.Note 4: Calculated value from BW (MHz) = 0 35/Rise Timers)

309

54/74 FAMILIES OF COMPATIBLE TIL CIRCUITSPIN ASSIGNMENTS (TOP VIEWS)

QUADRUPLE 2-INPUTPOSITIVE-NAND GATES

00

positive logicY = AB

SN6400 (Jl SN7400 (J. N)SN54HOO (J) SN74HOO (J. N)SN54LOOIJ) SN74LOOIJ, NISN54LSOO (J. Wl SN74LSOO IJ. NISN54SOO (J, W) SN74SOO (J. N)

QUADRUPLE 2 INPUTPOSITIVE NANO GATESWITH OPEN COLLECTOR OUTPUTS

01

positive logic:Y •= AB

SNS401 (J) SN7401 (J, N)SN54LS01 U. W) SN74LS01 (J, NI

46 «A GNO 38 3A 3Y

SN5401 IWISN54H01IW)SN54L01 (T)

SN54H01 (Jl

7A 28 31 GND

SN74H01 (J. N)

QUADRUPLE 2 INPUTPOSITIVE NOR GATES

02

positive logic:Y- Â+B

SN5402 (J)SN54L02 (J)SN54LS02 (J. W)SN54S02 (J. W)

SN7402 (J. N)SN74L02 (J, N)SN74LS02 (J, N)SN74S02 (J, N)

4Y 48 4A GND 38

SN5402 4W)SNS4L02 (T)

QUADRUPLE 2 INPUTPOSITIVE NAND GATESWITH OPEN COLLECTOR OUTPUTS

03

positiv« logic:Y- ÂB

DSaSN5403 (J) SN7403 (J, N)SN54L03IJ) SN74L03(J. N)SN54LS03 (J, W) SN74LS03 (J, N)SN54S03 (J. Wl SN74S03 U. N)

310

54/74 FAMILIES OF COMPATIBLE TTL CIRCUITSPIN ASSIGNMENTS (TOP VIEWS)

HEX INVERTERS

04

positive logic

6A 6Y i>A J>Y 4A

t>J fcj

SN5404 (JlSN54H04 (J)SN54L04 (J)

SN7404 (J. N)SN74H04 (J. NISN74L04U, N)

SN54LS04 U, W) SN74LS04 (J, NISN54S04 (J, Wl SN74S04 (J, N)

1A 2Y 2A VCC 3A 3Y 4A

SN5404 IWISN54H04(W)SN54L04 (T)

HEX INVERTERSWITH OPEN-COLLECTOR OUTPUTS

05

positiv» logic.Y - Ä

1Y 2A ZY 3A 3Y GND

SN5405 (J)SNS4H05 (J)

SN7405 (J. NISN74HOS (J, N)

SN54LS05 (J, W) SN74LS05 (J, NISN54S05 U. W) SN74S05 !J. NI

1Y ÇA 6Y CND iY tA 4Y

hJA ?Y 2A VCC 3A

SN5405 (W)SN54H05 (W)

HEX INVERTER BUFFERS/DRIVERSWITH OPEN COLLECTORHIGH VOLTAGE OUTPUTS

06poutiva logic.Y - Ä

1A IV 2A 2Y 3A 3Y GND

SN5406 U, W) SN7406 (J. N)

HEX BUFFERS/DRIVERSWITH OPEN-COLLECTORHIGH-VOLTAGE OUTPUTS

07positive logic

5

4^TJïïU^]_[Tj4iï}_j7]_fTi_LTNJ LTxl LTxJ

'{/"] [£>' d/"iljiijijji±n]jiij~iirJN5407 U. W) SN7407 (J. N)

QUADRUPLE 2-INPUTPOSITIVE-AND GATES

08poittiv* logicY- AB nlllinitlifliTlirLir

IA Ift IY JA 78 2Y GNO

SN5408 (J. W) SN7408 U, N)SN54LS08IJ. Wl SN74LS08U. N)SN54S08IJ.WI SN74SOB(J. NI

311

54/74 FAMILIES OF COMPATIBLE TTL CIRCUITSPIN ASSIGNMENTS (TOP VIEWS)

QUADRUPLE 2-INPUTPOSITIVE-ANO GATESWITH OPEN-COLLECTOR OUTPUTS

09

YCC *B 4A *v 38 3A 3Vi ou^vu^Tim

Y = AB ZA 76

SN5409 (J. W) SN7409 (J. N)SN54LS09 (J. W) SN74LS09 (J, N)SN54S09 U. W) SN74S09 (J. NI

TRIPLE 3-INPUTPOSITIVE-NAND GATES

10positive logic:Y = ABC

Vcc 1C W X 38 3A 3VVcc 1C

rO^U»

;.iLL

fcUBL

SN5410U) SN7410 (J, N)SN54HXOU) SN74H10 (J, N]SN54L10IJ) SN74L10U. NISN54LS10 (J.W) SN74LS10IJ. N)SN54S10U.WI SN74S10U. NI

1C 3V X GND 38 3A K

IB 1Y Vcc 7V

SN5410 (W)SN54HKHW)SN54L10IT)

TRIPLE 3-INPUTPOSITIVE AND GATES

11

positive logic:Y = ABC

SN54H11 (Jl SN74H11 [J, N)SN54LS1HJ.WI SN74LS11 (J. NISN54S11 (J, W) SN74S11 (J. N)

'<- JV K l,NI) tu (A H.

1A 18 IV VCC 7V ?A 70

SN54H11 1W)

TRIPLE 3-INPUTPOSITIVE NAND GATESWITH OPEN-COLLECTOR OUTPUTS

12

positive logic:Y- ABC

SN5412U, W) SN7412IJ. N)SN54LS12IJ, W) SN74LS12 U, N)

DU AL 4 INPUTPOSITIVE NANDSCHMITT TRIGGERS

13

positive logic:

Y = ABCO

VcC !O 2C NC 2Ü 2A ?Vpguagim-

3ÄO1A IB NC 1C 10 IV UNO

SN5413U.W) SN7413 (J. N)SNS4LS13U. W) SN74LS13U. N)

NC~No internal c

312

54/74 FAMILIES OF COMPATIBLE TTL CIRCUITSPIN ASSIGNMENTS (TOP VIEWS)

HEX SCHMITT-TRIGGERINVERTERS

14

pojitivo logic:Y = A

Vcc 6A 6V S

_j H |__j 1) [_| W |_J

1 ^"1

l( J

r

A 6

TU"

u>

P

V 4

'M

L>o'

&

A 4Y

1 |_| 1 |_

1

^J

1A IV JA ÎV JA 3V ONO

SN5414U.W) SN7414<J, NISN54LS14 (J. W) SN74LS14 U, N)

TRIPLE 3-INPUTPOSITIVE-AND GATESWITH OPEN-COLLECTOR OUTPUTS

15

positiv« logic:Y = ABC

SN54H15U. W) SN74H15(J,NISN54LS15U.W) SN74LS15IJ, N)SN54S15U, W) SN74S15U.NI

HEX INVERTER BUFFERS/DRIVERSWITH OPEN-COLLECTORHIGH-VOLTAGE OUTPUTS

16

positiv« logic:Y = A

SN5416 (J. W)

CND

SN7416 (J. N)

HEX BUFFERS/DRIVERSWITH OPEN-COLLECTORHIGH-VOLTAGE OUTPUTS

17

positiv« logic:Y - A

VçC «A 6Y SA 6V 4A

3A XV GND

SNS417 U. W) SN7417 U. N)

DUAL 4-INPUTPOSITIVE-NAND GATES

20

positiv« logic:Y-ÄBCD

CND 7V ?D K

ID IV GND

SN5420 (J) SN7420 (J, N)SN54H20 (J) SN74H20 (J. N)SN54L20 (J) SN74L20 (J, N)SN54LS20 U. W> SM74LS20 {J, N)SN54S20 (J. W) SN74S20 U. N)

1A IV NC VcC NC 2A

SN5420 (W)SNS4H20 (W)SNS4L20 (T)

NC — No int«rnal connection

313

54/74 FAMILIES OF COMPATIBLE TTL CIRCUITSPIN ASSIGNMENTS (TOP VIEWS)

DUAL 4 INPUTPOSITIVE AND GATES

21

positive logic:Y- ABCD

Vcc 20 2C NC 28 2A ?Y

A IB NC 1C ID 1Y GND

SN54H21 (J) SN74H21 U.N)SN54LS21 (J, W) SN74LS21 (J, N)

IO 1C IB GNU ?V 2U 2C

ij J " "II'jiiTunAnzn-JT:IV NC Vcc NC 2A ?B

SN54H21(W)

NC —No internal connection

DUAL 4 INPUTPOSITIVE NAND GATESWITH OPEN-COLLECTOR OUTPUTS

22

positiv» logic:Y = ABCD IA IB NC 1C ID W CND

SN5422 U. Wl SN7422U. NISN54H22 (J) SN74H22 (J, N)SN54LS22 (J, Wl SN74LS22 (J. N)SN54S22 (J. Wl SN74S22 (J. M)

ID IC IB GND

lA IV NC Vcc NC 2A 2ti

SN54H22 (Wl

NC—No internal connection

EXPANDABLE DUAL 4 INPUTPOSITIVE-NOR GATESWITH STROBE

23positiv« logic:1Y 1B+1C-HD)+X2Y = 2G12A+2B+2C+2D)

X - output of SN5460/SN7460

SN5423 (J, W) SN7423 (J. N)

DUAL 4 INPUTPOSITIVE-NOR GATESWITH STROBE

25

positive logic:Y>= GIA+B+C+D) 1A IB STROBE 1C ID IV CHO

1C

SN5425 (J, W) SN7425 U, N)

QUADRUPLE 2 INPUTHIGH-VOLTAGE INTERFACEPOSITIVE-NAND GATES

26

positive logic:Y -ÂB IB IV 2A ?B ?Y GND

SN5426 <J) SN7426 U, N)SN54LS26 (J. W) SN74LS26 (J. N)

314

54/74 FAMILIES OF COMPATIBLE TTL CIRCUITSPIN ASSIGNMENTS (TOP VIEWS)

TRIPLE 3-INPUTPOSITIVE-NOR GATES

27

positiv» logic:Y = A + B+C

Vçc 1C IV X 38 3A 3'

IA 18 2A 78 2C 7Y GNO

SN5427 (J, W) SN7427 (J. NISN54LS27 <J. W) SN74LS27 (J. Nt

QUADRUPLE 2-INPUTPOSITIVE-NOR BUFFERS

28

positiv« logic:Y - Â T B

2A 76 GNO

SN542S (J. W) SN7428 (J, N)SN54LS28 (J. W) SN74LS2S U, N)

B-INPUTPOSITIVE NANO GATES

30

positiv» logic:Y - ABCDEFGH

D f F GNO

SN5430 (Jl SN7430 (J. N)SN54H30 (J) SN74H30IJ.N)SN54L30 (J) SN74L30 (J. N)SNS4LS30 |J. W) SN74LS30 (J. N)SN54S30 (J. W) SN74S30 (J. N)

MC NC v GNO M G T"

NC A 8 VCC C O E

SN5430(W)SN54H30 (W)SNML30ITI

NC —No internal connection

DUAL 4-INPUTPOSITIVE-NAND BUFFERS

40

positive logic:

NC 1C ID IV CNO

SNS440 (J) SN7440 (J. NISN54H40 (J) SN74H40 (J, N)SN54LS40U.W) SN74LS40 (J. N)SNS4S40 (J. W) SN74S40IJ, N)

10 1C 18 GND ?V 20 2C

IA IV NC VCC NC 2A 28

SN5440 (W)SN54H40(W)

NC~No internal conneciion

315

54/74 FAMILIES OF COMPATIBLE TIL CIRCUITSPIN ASSIGNMENTS (TOP VIEWS)

4 LINE-TO-10 LINE DECODERS

42 BCD-TO-OECIMAL

43 EXCESS-3-TO-DECIMAL

44 EXCESS-3-GRAY-TO-DECIMAL

OUTPUTS

SN5442A (J, W) SN7442A <J, N)SN54L421J) SN74L42(J,NISN54LS42 (J. W) SN74LS42 (J, N)SN5443A (J, W) SN7443A (J. N)SN54L43 (Jl SN74L43 (J. N)SN5444A (J. W) SN7444A (J. N)SN54L44 (J) SN74L44 (J. N)

BCD-TO-DECIMAL DECODER/DRIVER

45 LAMP, RELAY,OR MOS DRIVER80-mA CURRENT SINKOUTPUTS OFF FOR INVALID CODES

U

2 3 __.___*__._j__ 6 , GNOOUTPUTS

S N 544 5 (J, Wl SN744S (J. NI

BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

46 ACTIVE-LOW, OPEN-COLLECTOR. 30-V OUTPUTS

47 ACTIVE-LOW. OPEN-COLLECTOR. 15-V OUTPUTS

-R—L _ rz

SN5446A (J. W) SN7446A U, N)SN54L46 U) SN74L46 IJ, N)SNS447A (J, W) SN7447A (J. N)SN54L47 (J) SN74L47 (J, N)SNS4LS47 (J. W) SN74LS47 (J. NI

BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

48 INTERNAL PULL-UP OUTPUTS

SN5448 (J, W) SN7448 (J. N)SN54LS48 (J. W) SN74LS48 (J, N)

316

54/74 FAMILIES OF COMPATIBLE TTL CIRCUITSPIN ASSIGNMENTS (TOP VIEWS)

BCD TO SEVEN SEGMENT DECODERS/DRIVERS

49 OPEN-COLLECTOR OUTPUTS

SN5449 (VYISN54LS49 (J. V» SN74LS49 (J. NI

DUAL 2-WIDE 2-INPUTAND OR INVERT GATES(ONE GATE EXPANDABLE)

50positiv« togtc:Y = AB+CD+X

'50: X = output of SN5460/SN7460•H50: X = output of SN54H6GYSN74H60

or SN54H62/SN74H62

^r j-, j-. ^ , i-, L-. v-iiT K

SN5450 U) SN7450 (J. N)SN54H50 (J) SN74H50 (J. NI

ID 1C IV GNO 2V 20 7C

SN5450 IW)SN54H50 (W)

AND-OR-INVERT GATES

51'51,'H51,-S51DUAL 2-WIDE 2-INPUTpositive logic:Y = AB+CD

MAKE NO EXTERNAL CONNECTION

SN5451 (J) SN7451 (J. N) SN5451 (W)SN54H51 U) SN74H51 U. N) SN54H51 (W)SN54S51IJ.W) SN74S51IJ.N)

•L51/LS612-WIDE 3-INPUT.2-WIDE 2-INPUT

positive logic:1Y * (1A-1B-1CKI1D-1E.1F)2Y = (2A-2B1 + I2C-2D)

1C IB IV GND 2V 2O 2C

2B 7C 2D 7V GND

SN54L51 U) SN74L51 <J. N)SNS4LS51 (J.W) SN74LS51 (J, N)

1A ID IE

SN54L51 (Tl

317

54/74 FAMILIES OF COMPATIBLE TTL CIRCUITSPIN ASSIGNMENTS (TOP VIEWS)

AND GATED J K POSITIVE EDGE TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR

70 FUNCTION TABLEINPUTS

PRESETLHLHHHHH

CLEARHLLHHHHH

CLOCKLLXÎTttL

JXXXLHLHX

KXXXLLHHX

OUTPUTSQ QH LL HL' L1

QO QoH LL HTOGGLEQO Qo

NC CLR Jl J3 I Q GND Kl CK PH vcc CLR

SN5470 (J) SN7470 (J, N) SNS470 (Wt

positive logic J - J1 • J2-J _K = K1-K2-KIf inputs J and K are not used they must be groundedPreset or clear function can occur only when the clock input is low

NC No internal connection

AND GATED J K MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR

72FUNCTION TABLEINPUTS

PRESET

LH

L

H

H

H

H

CLEARH

LLH

H

H

H

CLOCKX

XX

_TL_n_-TL_TL

JX

XXLH

LH

KX

X

XLL

H

H

OUTPUTSQ QH LL H

H- H'

QO QOH L

L H

TOGGLEpositive logic J = J1-J2-J3 K1-K2-K3

SN5472 (J) SN7472 (i. N)SN54H72 (J) SN74H72 (J, N)SN54L72 (J) SN74L72 (J. N)

Kl CK PR VCC CLR NC Jl

SN5472 (W)SNS4H72(WlSN54L72IT»

NC-No internal connection

DUAL J K FLIP FLOPS WITH CLEAR

73'73. 'H73. 'L73

FUNCTION TABLE'LS73A

FUNCTION TABLE

INPUTSCLEAR CLOCK J

L X X

H -TL LH _TL HH -TL LH J"L H

K

X

LLHH

OUTPUTSQ QL H

QO QOH LL H

TOGGLE

INPUTSCLEAR

LHHHHH

CLOCKX111

1H

J

XLH

LHX

K

X

LLHHX

OUTPUTSQ QL H

QO QOH LL H

TOGGLE

QO QO

u 10 to GND 2K 20 20

SN5473 (J. W) SN7473 (J, N)SN54H73 (J. W( SN74H73 (J, MlSN54L73U, Tt SN74L73 (J, N)SNS4LS73AIJ. W) SN74LS73AU.N)

DUAL D TYPE POSITIVE EDGE TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR

74FUNCTION TABLEINPUTS

PRESET

LH

LH

H

H

CLEAR CLOCKH

L

LHH

H

X

X

Xtt

L

D

X

X

XH

L

X

OUTPUTS

Q

H

L

H*H

L

QO

Q

L

H

H'

LH

QO1D 1CK 1PK 1O

SN6474 (J) SN7474 (J. N)SN64H74 (J) SN74H74 (J, N)9N54L74 (J) SN74L74 (J, N)SNMLS74A (J, W) SN74LS74A (J. N)SNS4S74 (J. W) SN74S74 {J, N)

SNS474 (WlSNS4H74 (WlSN64L74 (T)

'ThisconligurAtion is nonstable that it it will not persist whan preMt and claar input» raturn to lhair inactiva (high) l«v«l

318

54/74 FAMILIES OF COMPATIBLE TIL CIRCUITSPIN ASSIGNMENTS (TOP VIEWS)

4-BIT BISTABLE LATCHES

75FUNCTION TABLE

(Each Latch)INPUTS

D

L

H

X

G

H

H

L

OUTPUTSQ

L

H

QO

Q

H

L

QOSNS475 (J, W) SN7475 U. N)SN54L75 (J) SN74L75IJ, N)SN54LS75 (J. W) SN74LS75 (J. N)

H = high level, L = low level, X = irrelevantQQ = the level of Q before the high-to low transition of G

DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR

76•76. 'H76

FUNCTION TABLEINPUTS

PRESETL

H

LH

H

H

H

CLEARH

L

L

H

H

H

H

CLOCKX

XX

J\

J\

JT.S\.

JX

X

X

L

H

L

H

K

X

X

X

L

LH

H

OUTPUTSOH

L

H*

°0H

L

OLH

H-

QOL

H

TOGGLE

•LS76AFUNCTION TABLE

INPUTSPRESET

L

H

LH

H

H

H

H

CLEAR

H

L

LH

H

H

H

H

CLOCK

X

X

X

JlJtH

J

X

X

X

L

H

L

H

X

K

X

X

X

L

L

H

H

X

OUTPUTS

0 O

H L

L H

H' H'

QO QOH L

L H

TOGGLE

QO °o

IO 10 GNO jjt 2Q To

SN5476 (J, W) SN7476 (J. N)SNS4H76 (J. Wl SN74H76IJ, N)SN54LS76A (J. W) SN74LS76A (J, N)

4-BIT BISTABLE LATCHES

77FUNCTION TABLE

(Each Latch)INPUTSD

LHX

G

H

H

L

OUTPUTSQ

L

H

Oo

QH

L

QOH - high level. L - low level, X * irrelevantQQ - th« l« v« I of Q before th« hlgh-to-low transition of G

SN5477 (W)SN54L77 IT)SN54LS77(W)

This configuration it nonttabl«; that it. it will not pirtltt whan pratat and claar input» raturn to thalr inactiva (high) lava!.

319

54/74 FAMILIES OF COMPATIBLE TIL CIRCUITSPIN ASSIGNMENTS (TOP VIEWS)

DUAL J-K FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK

vrr 1 rn CIH It 1 PR CK I*.JO -H78, -L78

FUNCTION TABLE

INPUTSPRESET CLEAR CLOCK 1 K

L H X X X

H L X X X

OUTPUTS

O O

H L

1 II

H- H*

J^T-J^U^T— T"l— n*!-!"'!— [~*1—1 ————— }

' p '

0 0

_L_L

t^H- — \—+ -M1 T iK c V J

0 0

11

1 1

S«« pag« 6-50 and 6-54

•LS78AFUNCTION TABLE

INPUTS

PRESET

L

H

l

H

hl

H

H

H

CLEAR

H

L

L

H

hl

H

H

H

CLOCK

X

X

X

1I!

1

H

J

X

X

X

L

hl

1

hl

X

K

X

X

X

l1H

H

X

OUTPUTSQ Q

H L

L H

H' H-

"o °oH L

L M

TOGGLt

Ofl O0

2O GNO

SN54H78(J,W) SN74H78(J,N)

CK t PR U CLR 2 PR 2K

SN54L78U.T) SN74L78U.N)SN54LS78A(J.W) SN74LS78A(J,NI

QUADRUPLE BUS BUFFER GATES WITH THREE STATE OUTPUTS

125

positive logic:

Y = AOutput is of! IdiSdbled) when C is high.

SN54125IJ, Wl SN74125U. N)SN51LS125AIJ, W) SN74LS125AIJ. N)

QUADRUPLE 2-INPUT POSITIVE NAND SCHMITT TRIGGERS

132

positive logic:

Y = AB

SN54132 (J. W) SN74132 (J, N)SN54LS132U.WI SN74LS132 (J, N)SN54S1321J, Wl SN74S132 (J, NI

*ThI« configuration ii nonstabl«; that it. It will not partitt whan pr«««t and claar input* raturn to thair inactiva (high) (aval.

320

54/74 FAMILIES OF COMPATIBLE TTL CIRCUITSPIN ASSIGNMENTS (TOP VIEW)

3 TO 8 LINE DECODERS/MULTIPLEXERS

138

DAT AOUT?« T»

r1 1 1 1 ,

*• c C?A c.i« c

ï ï

1Y«

ï

J>-l

• C /V-C?* CM C*/ »I CUD

ItLlCT IMAtlt

SN54LS138 (J,W) SN74LS138 (J. N)SN54S138U.W) SN74S138 (J. N]

BCD TO DECIMAL DECODER/DRIVER

141 DRIVES COLD CATHODEINDICATOR TUBES

SN74141 (J. NI

DUAL 4 LINE TO 1 LINE DATA SELECTORS/MULTIPLEXERS

153

SIBOBf « O A I » I N » U I S

nr«^ir 1t~^1ci

A ï" y y "•» yI .A !.. I.. !.. !„ I

1(^ S F L f C T UATA INDUIS 1Y

SN54153U.W) SN741S3IJ.N)SN54L153U) SN74L153IJ, NISN54LS153 (J.WI SN74LS1S3U. MSN54S153 (J, Wl SN74S153 (J. NI

4 LINE TO 16 LINE DECODERS/DEMULTIPLEXERS

154

INWJTÎ OUTPUTS

SN54154 (J.W) SN74154U. N)SN54L1S4IJ) SN74L154U, N)

321

54/74 FAMILIES OF COMPATIBLE TIL CIRCUITSPIN ASSIGNMENTS (TOP VIEWS)

DECODERS/DEMULTIPLEXERS

DUAL 2- TO 4-LINE DECODER

DUAL 1-TO 4-LINE DEMULTIPLEXER

3 TO 8 LINE DECODER

1. TO 8-LINE DEMULTIPLEXER

155

156

TOTEM-POLE OUTPUTS

OPEN COLLECTOR OUTPUTS

StllCT OUTPUTS

DAT* STgTscTm^ 1Y3 iv? iTi woy GHD1C IG INTUI

SN541551J, W) SN741551J. MSN54LS155 (J,W) SN74LS155 (J. NISN54156IJ. W) SN74156U. N)SN54LS156 (J.W) SN74LS156 (J, N)

SYNCHRONOUS UP/DOWN COUNTERS

190 BCD

191 BINARY4_i_.l_l

Se« pa«* 7-296

SN54190U, W) SN74190IJ. N)SN54LS190U.W) SN74LS190 U, N)SN54191 (J,W) SN7419KJ.N)SN54LS191 (J, W) SN74LS191 (J, N)

SYNCHRONOUS UP/DOWN DUAL CLOCK COUNTERS

192 BCD WITH CLEAR

193 BINARY WITH CLEAR

TT* Cll»« •O*"O*»t*««i' 10*0

COUMT OMMT

••. "T •» ",

c

UD

SN54192IJ.W)SN54L192 (J)SN54LS192 (J,W)SN54193 (J. W)SN54L193 U)SN54LS193U.W)

SN74192 IJ. N>SN74L192IJ, N)SN74LS192IJ.N)SN74193IJ. N)SN74L193U. N)SN74LS193 (J. N)

4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS

194

°c OQ cioc« si so

-c

1 1o» OB QC oo eiJ£.K $1

CICAH SO

H A B C 0 L

T~ 1J

cilAflSHirr A • c o SHIM GNOWIGNt »———————v———————J L IFTSfftlAL MflALKL tMn«T$ $f RIAL

SN54194 U. W) SN74194 (J, N)SN54LS194A (J. W) SN74LS194A <J. N)SN54S194 (J. W) SN74S194 (J. N)

322

54/74 FAMILIES OF COMPATIBLE TTL CIRCUITSPIN ASSIGNMENTS (TOP VIEWS)

OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS

241 NONINVERTED 3-STATE OUTPUTS

SN54LS241 (J) SM74LS241 (J, N)SN54S241 (J) SN74S241 (J, N)

QUADRUPLE BUS TRANSCEIVERS

242 INVERTED ESTATE OUTPUTS

CAS NC 1A ÏA 3* «A GfcO

SN54LS242 (J, W) SN74LS242 (J, N)NC-No internal connection

QUADRUPLE BUS TRANSCEIVERS

243 NONINVERTED 3-STATE OUTPUTS

VCC G»* NC 18 » » «8

CAB NC IA JA j*

SN54LS243 (J. Wl SN74LS243 (J. NINC—No internal connection

OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS

244 NONINVERTED 3-STATE OUTPUTS

SN54LS244 (J) SN74LS244 (J, N)

OCTAL BUS TRANCEIVERS

245 NONINVERTED 3-STATE OUTPUTS

DIft AI Al

SN54LS245 (J) SN74LS245 (J. N)

323

54/74 FAMILIES OF COMPATIBLE TTL CIRCUITSPIN ASSIGNMENTS (TOP VIEWS)

BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

246 ACTIVE-LOW, OPEN-COLLECTOR. 30-V OUTPUTS

247 ACTIVE-LOW, OPEN-COLLECTOR, 15-V OUTPUTS

SN54246U.W) SN74246U. NISN54247(J,W) SN74247 (J, N)SN54LS247 IJ.W) SN74LS247 (J, NI

BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

248 INTERNAL PULL-UP OUTPUTS

249 OPEN-COLLECTOR OUTPUTS

SN54248(J,W) SN74248 (J, N)SN54LS248 (J, W) SN74LS248 (J. N)SN54249 (J, W) SN74249 (J. N)SN54LS249 (J, W) SN74LS249 (J, N)

OCTAL O-TYPE FLIP-FLOPS

374 3-STATE OUTPUTSCOMMON OUTPUT CONTROLCOMMON CLOCK

SN54LS374 U)SN54S374 (J)

SN74LS374 (J, N)SN74S374 U. N)

324

TYPES TIL13Î THRU TIL1339-ELEMENT ARRAYS AND 9-CHANNEL PAIR

TIL131 . . . 9-ELEMENT GALLIUM ARSENIDE (RED ARRAYTIL132 . . . 9-ELEMENT PHOTOTRANSISTOR ARRAYTIL133 . . . 9-CHANNEL PAIR

• Center-to-Center Spacing of 2,54 mm (0.100 Inch) for Tape Reading• Reliable Solid-State Components• IRED's Eliminate Lamp-Filament-Sag Problems• Spectrally Matched for Improved Performanceo Printed Circuit Board Construction Allows Precise Alignment

descriptionThe TIL131 is an array of nine TIL23 gallium arsenide infrared-emitting diodes mounted in a printed circuit board. TheTIL132 is an array of nine selected LS600 phototransistors. The TIL133 is a pair of selected arrays comprising aTIL131 and TIL132 and offering guaranteed channel performance.

mechanical dataThe printed circuit board material is glass-base F R-4, class II, 2-oz copper clad on both sides. The approximate weightof theTIL131 and TIL132 is 3.7 grams each.

TIL131,TIL132 Î5I ±OOS(00991:0002)

4 MOUNTING HOLES

0 7610 M[0030 ±0003»

~~ IOIES

V fa I u uo_

/(0030ÏO OK

18 WIRE HO

PHOTOTRANSISTORSOH

Id EMITTING DIODES

2 54 10 05 (0 100 ' 0002) 8 PLACESTOLERANCE NONACCUMULATIVESee Nol«A

762(03001

SIDE VIEWSOF ACTIVE ELEMENTS

ALL DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHESNOTE A Tolerance! shown on drawing apply for location dimensions of the

mounting holet and the active elements Tolérance ol 1 0 13 <± 0 005}applies lor location dimensions ol wire holes

325

TYPES TIL131 THRU TIL1339-ELEMENT ARRAYS AND 9-CHANNEL PAIR

TIL131 absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)

Reverse Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 VContinuous Forward Current at (or below) 25°C Free-Air Temperature (See Note 1) . . . . . . . . . . 100mAOperating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -65°Cto125°CStorage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°Cto150°CSoldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

NOTE 1: Derate linearly to 12S°C (ree-air temperature at the rate o( 1 nvA/°C.

TIL131 operating characteristics of each element at 25°C free-air temperaturePARAMETCR

PO Radiant Power Output\p Wavelength at Peak EmissionAX Spectral Bandwidth»HI Half-Intensity Beam AngleVF Static Forward Voltage

TEST CONDITIONS

If = 50mA

MIN TYP MAX0.4 1

0.9350035°

1.25 1.5

UNITmWfimA

V

TIL 132 absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)

Collector-Emitter Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 VEmitter-Collector Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VContinuous Device Dissipation at (or below) 25°C Free-Air Temperature (See Note 2) . . . . . . . . . 50 mWOperating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . —65°C to 125°CStorage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°CSoldering Temperature ( 10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

NOTE 2: Derate linearly to 126°C tree-air temperature at the rate öl O.5 mW/"c.

TIL 132 electrical characteristics a* 25°C free-air temperature

individual element characteristic«

PARAMETER

V(BR)CEO Collector-Emitter Breakdown VoltageV(BR)ECO Emitter-Collector Breakdown VoltageIQ Dark CurrentIL Light Current

VCE(SM) Collector-Emitter Saturation Voltage

TEST CONDITIONS

lc=100nA, E e -0IE'100)JA, Ee = 0

VCE - 30 V. Ee - 0VcE"5V, Ee - 20mW/cm2. See Note 3

1C = 0.4 mA, Ee = 20 mW/cm2. See Note 3

MIN TYP MAX

507

1002 12

0.15

UNIT

VV

nAmAV

element matching characteristics

PARAMETER

li min— = ——— Light Current Matching FactoriLmax

TEST CONDITIONS

VCE = 5V. Ee-20mW/cm2, See Note 3

MIN TYP MAX

0.5

UNIT

NOTE 3: Imdianc« <E,)it th« radiant pow«r p*r unit area incidant upon a turfac«. For this m«atur«mant tha tourc» i« an unfiltarad tungstenlinear-filamant lamp operating at a color température of 2870 K.

326

TYPES TIL131 THRU TIL1339-ELEMENT ARRAYS AND 9-CHANNEL PAIR

TIL133 absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)Maximum ratings of TIL131 and TIL132 apply

TIL133 electrical characteristics at 25°C free-air temperaturePARAMETER

1C Output Collector CurrentvCE(satl Collector Emitter Saturation Voltage

TEST CONDITIONS*

If -50mA. V C E - 5 VIf -50mA, IG "2mA

MIN TYP MAX

2.5 4 10

04 07

UNITmAV

TIL133 switching characteristics at 25°C free-air temperaturePARAMETER

tr Rise Timetf Fall Time

TEST CONDITIONS*

Vcc -SV . lC(on)-2mA,RL=-100n. SeeFigurel

MIN TYP MAX

1 5

1 5

UNIT

Ht

ft1 These parameter» are measured at a lens to lent distence of 0 100 Inch

PARAMETER MEASUREMENT INFORMATION

INPUT(See Note A)

OUTPUT° (See Note B)

RL- 10011

Adjust amplitude of input pulsef°r 'Clon) M

INPUT

90%

OUTPUT

90%

TEST CIRCUIT

• 10%

VOLTAGES WAVE FORMS

NOTES A The input waveform it supplied by * generator with the following characteristics Zout * SO fi, tr < IS ns. duty cycle * 1 %,t« * 100 ps

8 The oulpul waveform is monitored on an oscilloscope with the following characteristics tr < 12 ns. R,n > 1 M£l, Cin < 20 pF

FIGURE 1-SWITCHING TIMES

TYPICAL CHARACTERISTICS

TIL133COUPLING CHARACTERISTICS

4

2

t

0.4

02

01

002

001

- fXH

—

R CI(Or26'

"I

'••

; - • -

c --

HW-VCE

TA -

*>

WR•6is'

ss

s

001 002 CM 0.1 02 04Osuntit tttwein L*n»M-in

FIGURE 2

327

TYPES TIL131 THRU TIL1339 ELEMENT ARRAYS AND 9 CHAMNEl PAIR

TYPICAL CHARACTERISTICS

TIL131FORWARD CONDUCTION CHARACTERISTICS

0.« 1.0 M U 1.3 1.« 1.5Vr-Fonmrd Vätwei-V

FIGURE 3

itiv»

to V

»luf

*t

IF •

W m

A

'•*

—

M

*

*4

O

Out

put

Pow

tr ta

li

es

s

TIL131RELATIVE POWER OUTPUT

«iFORWARD CURRENT

:TA.— - •!:Sw*

//

to it

j,/-

4 ~~"

^

r••

/

10 30 40 TO 100 aoo «x> tot»p-Forwwd Currtm-mA

FIGURE 4

TIL131RELATIVE PHOTON INTENSITY

ANGULAR DISPLACEMENT

I 0.C

| o.esr-4

X

-7)• D" l

1

/

(

f 0

\c9

>

1<

\\\

)' 7«

V>" 3D

TIL131CHANGE IN WAVELENGTH OF PEAK INTENSITY

nFREE-AIR TEMPERATURE

II

IF «Conn««

FIGURE s

-75 -SO -25 0 26 50 75 100 125TA-Fr«».Air T«mp«l1uf»-'C

FIGURE 6

TIU32NORMALIZED LIGHT CURRENT

VfANGULAR DISPLACEMENT

J 100 _..-.-.

0.7S —— —— ...

SO* 40* 30* 10* 10* 0" 10* Hf yf tfVf0-Anfuto Ditplactmtnt

10000

1000

< H»

I to

1 'Q 0.1

0.01

TIL132DARK CURRENT

viFREE AIR TEMPERATURE

V«_*«•

———

-

'

•300

/

V

--^ ///

/

-SO -» 0 2» to 75 10O 12STA-Fr«»-Aif Tt

FIGURE 7

NOT E 4: Thew psrnm»t«r» w«r« maaiurtd using p u It» techniques ty, • 0.04 mi, duty cycle < 10%.

FIGURE 8

328

TYPE TIL138SOURCE AND SENSOR ASSEMBLY

OPTOELECTRONIC MODULE FOR TRANSMISSIVE SENSING APPLICATIONS

Compatible With Standard DTL and TTL Integrated Circuits

High-Speed Switching: tr = 1.5 MS, tf = 15 us Typical

Designed for Base or Side Mounting

For Sensing Applications such as Shaft Encoders, Sector Sensors, Level Indicators, andBeginning-of-Tape/End-of-Tape Indicators

mechanical data

The assembly consists of a T1L32 gallium arsenide infrared-emitting diode and a TIL78 n-p-n silicon phototransistormounted in a molded ABS^ plastic housing. The assembly will withstand soldering temperature with no deformationand device performance characteristics remain stable when operated in high-humidity conditions. Total assembly weightis approximately 1.5 grams

ST\\L7

»660 <0 260) »660(0260)4

VL/508(0200)503 10 198)t 5 03 10 198)

061 (00?*lnjcmnioi Wu**t

COlLECTOfl_____ T T

ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLYKM INCHES TOLERANCE OF ±0,13 l± 0 005I UNLESS OTHERWISE NOTED

absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)

Source Reverse Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 VSource Continuous Forward Current (Se« Note 1) . . . . . . . . . . . . . . . . . . . . . . 40mASensor Collector-Emitter Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 VSensor Emitter-Collector Voltage . . . . . . . . . . . . . . . . . . . . . . . 7 VSensor Continuous Dissipation at (or below) 25°C Free-Air Temperature (See Note 2) . . . . . . . . . . 50 mWStorage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°CLead Temperature 1,6 mm (1/16 Inch) from Assembly for 3 Seconds . . . . . . ... 260°C

NOTES. 1. D«r«t« llnMrlv to 80 C >r« *ir t«mp«r«tur« •( tht r«t« of 0.73 mA/ C2. D*r»t« ImMrlv to 80°C fr«« air T«mp«r«tur« •! th« r«t« of 0 91 mW/°C.

^ABS th«rmopl»ctict «r* dcrivad from acrvlonitnl«, butadivn« jnd styf«n*

329

TYPE TIL138SOURCE AND SENSOR ASSEMBLY

electrical characteristics at 25°C free-air temperaturePARAMETER

V(BR)CEO Collector-Emitter Breakdown VoltageV(BR)ECO Emitter-Collector Breakdown Voltage'C(off) Off-State Collector Current

'C(on) On-State Collector Current

Vf Input-Diode Static Forward Voltage

TEST CONOITIONSt

ic - 100 »JA, IF -oIE = loOjiA, ip -oVÇE-30V, IF = 0

VCE = 0.5V. IF -15mAVCE = 0.5V. IF=- 35mAIf = 15mA

1 p =• 35 mA

MIN TYP MAX50

7

250.4 1

1.6 4

1.15 1.51.2

UNITVVnA

mA

V

switching characteristics at 25°C free-air temperature

PARAMETER

t<j Delay Timetr Rise Timets Storage Timetf Fall Time

TEST CONDITIONS*

VC C-30V, lc(on) = 500 MA,

RL * 1 kn. See Figure 1

MIN TYP MAX

3

1.50.515

UNIT

Ht

Ht

c«ft

t Stray irradiation outside the range of device sensitivity may be present A satisfactory condition has been achieved when the parameter beingmeasured approaches a value which cannot be altered by further irradiation shielding

PARAMETER MEASUREMENT INFORMATION

200 n

INPUT

ADJUST AMPLITUDEOF INPUT PULSE FOR

O OUTPUT

RL = 1

INPUT

90%OUTPUT

10%

NOTE: The input pulse Is supplied by a generator having th«following characteristics: Zout - 50 (1, t, < 100 n»,tf < 100 ns. duty cycle » 50%.

TEST CIRCUIT VOLTAGE WAVEFORMSFIGURE 1-SWITCHING TIMES

TYPICAL CHARACTERISTICS

<E

PHOTOTRANSISTOR COLLECTOR CURRENTvs

INPUT DIODE FORWARD CURRENT

1 2 3

E -Collector Emitter Volt»ge-V

FIGUREZ

PHOTOTRANSISTOR COLLECTOR CURRENT

to

4

2

04

01

004

n ni

-TA - 25°C

//

'

/ - - -

j..-/::;

/•

1 2 4 1 0 2 0 4 0 1 0 0

Ip-lnput-Diod« Forward Currtnt-mA

FIGURE 3

330

TYPE TIL139SOURCE AND SENSOR ASSEMBLY

OPTOELECTRONIC MODULE FOR REFLECTIVE SENSING APPLICATIONS

Adaptable for Printed Circuit Board MountingDesigned for Sensing Applications such as Line Finders, Batch Counters, Level Indicators, andBeginning-of-Tape/End-of-Tape Indicators

mechanical data

The assembly consists of a TIL32 gallium arsenide infrared-emitting diode and a TIL7B n-p-n silicon phototransistormounted in a molded ABS* plastic housing. The assembly will withstand soldering temperature with no deformationand device performance characteristics remain stable when operated in high-humidity conditions. Total assembly weightis approximately 1.2 grams.

CPTMJURUCNC

& M 10 200} 5 06 <0 200)ALL DIMENSIONS ARE IN MILLIMETERS AN D PARENTHETICALLYIN INCHES WITH TOLERANCE OF ±0.131+ OOO5I UNLESS OTHERWISE NOTED

absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)

Source Reverse Voltage . . . . . . . . . . . . . . . . . . .Source Continuous Forward Current (See Note 1) . . . . . . . . . .Sensor Collector Emitter Voltage . . . . . . . . . . . . . . . .Sensor Emitter-Collector Voltage . . . . . . . . . . . . . . . .Sensor Continuous Dissipation at (or below)

25°C Free-Air Temperature (See Note 2) . . . . . . . . . . .Storage Temperature Range . . . . . . . . . . . . . . . . . .Lead Temperature 1,6 mm (1/16 Inch! from Assembly for 3 Seconds

NOTES 1 O«r«t« lm««rly to 80°C Ire« »ir t»mp»c«tur« «I th« r«t» of 0 73 mA/°C2 O«r«t» linMrly to 80"C <rM «ir t*mp*r«tur« «I th« r*t* of 0 91 mW/°C.

' ABS tharmoplHtici if« d*nv*d from acrylonitnl«. but»di«n*, «nd »tyr*n*.

5V40mA

50V7 V

. . 50 mW-40°C to 85°C. . 260°C

331

TYPE TIL139SOURCE AND SENSOR ASSEMBLY

electrical characteristics at 25°C free-air temperature

'PARAMETERV(BR)CEO Collector Emitter Breakdown VoltageV(BR)ECO Emitter Collector Breakdown Voltage'C(off) Off-State Collector Current

'Clonl On State Collector Current

VF Input Diode Static Forward Voltage

TEST CONDITIONS'ic - loojiA. IF = oIE = loonA. IF = oVCE -30V, IF = oVcg = 5V, IF = 40mA, See Note 3VCE ~ 5 v- IF = 40mA. See Note 4VCE = 5 V, 'F " 40mA. See Note 51 F = 40 mA

MIN TYP MAX

507

25

10 1255 60

100 1100

12 16

UNITV

V

nA

*A

V

'Stray irradiation outside the range of device sensitivity may be present. A satisfactory condition has been achieved when the parameter beingmeasured approaches a value which cannot be altered by further irradiation shielding

NOTES 3 Reflective surface is Eastman Kodak (or equivalent) neutral white paper with 90% diffuse reflectance placed 3,81 mm (0 150 inch) from read head

4 Reflective surface is Mylarlf {or equivalent) magnetic tape placed 3.81 mm (0 ISO inch) from readhead

5 Reflect ive surface is 0,025 mm (0 001 inch) thick aluminum foil, typical of beginning of tape/endof tape strips on magnetic tape surface, placed 3,81 mm (0 150 inch) from read head

+ Trademark of E I duPont

332

TYPES TIL306, TIL307NUMERIC DISPLAYS WITH LOGIC

SOLID-STATE VISIBLE DISPLAYS WITH INTEGRAL TTL MSI CIRCUIT CHIPFOR USE IN ALL SYSTEMS WHERE THE DATA TO BE DISPLAYED

IS THE PULSE COUNT

• 6,86mm (0.270-1 nch)-HighCharacter

• High Luminous Intensity• TIL306 Has Left Decimal• TIL307 Has Right Decimal

• Easy System Interface• Wide Viewing Angle• Internal TTL MSI Chip and Counter, Latch,

Decoder, and Driver• Constant-Current Drive for Light-Emitting Diodes

mechanical data

The display chips and TTL MSI chip are mounted on a header and this assembly is then cast within a red, elec-trically nonconductive, transparent plastic compound. Multiple displays may be mounted on 11,43 mm(0.450 inch) centers.

TIL306A

•/^ o, PIN i —|

36, (01501

2 54 ,0 IOO1-, I

...JL.. rf-j—L ——,—i—,

0 66(0 026) J f\

445(0,«,»»« ——' U 10 67 (0420)965(0380) "

I NO ANU6OMCJM

(>1 IAII »OH »O'H ITTK s

NOTES: A. The true postlion pin spacing is 2.54 mm (0.100 inch) between centerlines. Each pin center lineis located within 0.254 (0.010) of its true longitudinal position relative to pin 1 and 16.

B. Centerlines of character segments and decimal points are shown as dashed lines Associateddimensions are nominal.

C. Lead dimensions ara not controlled above the seating plane.D. All dimensions are in millimeters and parenthetically in inches unless otherwise specified

PIN ASSIGNMENTSFOR BOTH TYPES

PIN 1 LATCH OUTPUT QB

(BINARY WEIGHT 2)PIN 2 LATCH OUTPUT Qc

(BINARY WEIGHT 4)PIN 3 LATCH OUTPUT QD

(BINARY WEIGHT 8)PIN 4 LATCH OUTPUT QA

(BINARY WEIGHT 1)PIN 5 LATCH STROBE

INPUTPIN 6 RIPPLE-BLANKING

INPUTPIN 7 MAXIMUM-COUNT

OUTPUTPIN 8 GROUNDPIN 9 PARALLEL COUNT

ENABLE INPUTPIN 10 SERIAL COUNT

2 54 io loo, t P ENABLE INPUTPIN 11 RIPPLE-BLANKING

OUTPUTPIN 12 CLEAR INPUTPIN 13 DECIMAL POINT

INPUTPIN 14 BLANKING INPUTPIN 15 CLOCK INPUTPIN 16 SUPPLY VOLTAGE.

TIL306 TIL307

333

TYPES TIL306, TIL307NUMERIC DISPLAYS WITH LOGIC

functional block diagram

z5

UlO

S>

85oQUl

ZUlZa

Zuj>UJ</>Œ

>Ee(EuQ

8

m«r

Z

OuOumv>

OOocIUzS;

334

TYPES TIL306, TIL307NUMERIC DISPLAYS WITH LOGIC

descriptionThese internally-driven seven-segment light-emitting-diode (LED) displays contain a BCD counter, a four-bit iatch, anda decoder/LED driver in a single 16-pin package. A description of the functions of the inputs and outputs of thesedevices follows:

PIN NO. DESCRIPTION12 When low. resets and holds counter at 0. Must be high for normal

counting.

15 Each positive-going transition will increment the counter provided that thecircuit is in the normal counting mode (serial and parallel count enableinputs low, clear input high).

9 Must be low for normal counting mode. When high, counter will beinhibited. Logic level must not be changed when the clock is low.

10 Must be low for normal counting mode, also must be low to enablemaximum count output to go low. When high, counter will be inhibitedand maximum count output will be driven high. Logic level must not bechanged when the clock is low.

7 Will go low when the counter is at 9 and serial count enable input is low.Will return high when the counter changes to 0 and will remain high duringcounts 1 through 8. Will remain high (inhibited) as long as serial countenable input is high.

5 When low, data in latches follow the data in the counter. When high, thedata in the latches are held constant, and the counter may be operatedindependently.

4, 1, 2, 3 The BCD data that drives the decoder can be stored in the 4-bit latch andis available at these outputs for driving other logic and/or processors. Thebinary weights of the outputs are. QA = 1, QQ = 2, QC = 4, Qrj = 8.

13 Must be high to display decimal point. The decimal point is not displayedwhen this input is low or when the display is blanked.

14 When high, will blank (turn off) the entire display and force RBO low.Must be low for normal display. May be pulsed to implement intensitycontrol of the display.

6 When the data in the latches is BCD 0, a low input will blank the entiredisplay and force the RBO low. This input has no effect if the data in thelatches is other than 0.

11 Supplies ripple-blanking information for the ripple-blanking input of thenext decade. Provides a low it Bl is high, or if RBI is low and the data inthe latches is BCD 0; otherwise, this output is high. This pin has a resistivepull-up circuit suitable for performing a wire-AND function with anyopen-collector output. Whenever this pin is low the entire display will beblanked; therefore, this pin may be used as an active-low blanking input.

The TTL MSI circuits contain the equivalent of 86 gates on a single chip. Logic inputs and outputs are completelyTTL/DTL compatible. The buffered inputs are implemented with relatively large resistors in series with the bases of theinput transistors to lower drive-current requirements to one-half of that required for a standard Series 54/74 TTL input.The serial-carry input, actually two internal loads, is rated as one standard series 54/74 load.

The logic outputs, except RBO, are active pull up, and the latch outputs QA, Qß. 0-C- ar|d O-D are eacn capable ofdriving three standard Series 54/74 loads at a low logic level or six loads at a high logic level while the maximum-countoutput is capable of driving five Series 54/74 loads at a low logic level or ten loads at a high logic level. The RBO nodewith passive pull-up serves as a ripple blanking output with the capability to drive three Series 54/74 loads.

The LED driver outputs are designed specifically to maintain a relatively constant on-level current of approximatelyseven milliamperes through each LED segment and decimal point. All inputs are diode-clamped to minimizetransmission-line effects, thereby simplifying system design. Maximum clock frequency is typically 18 megahertz andpower dissipation is typically 600 milliwatts with all segments on.

FUNCTIONCLEAR INPUT

CLOCK INPUT

PARALLEL COUNTENABLE INPUT(PCEI)

SERIAL COUNTENABLE INPUT(SCEI)

MAXIMUM COUNTOUTPUT

LATCH STROBEINPUT

LATCH OUTPUTS(QA, QB- QC. QD>

DECIMAL POINTINPUT

BLANKING INPUT(Bl)

RIPPLE-BLANKINGINPUT(RBI)

RIPPLE-BLANKINGOUTPUT(RBO)

335

TYPES TIL306, TIL307NUMERIC DISPLAYS WITH LOGIC

description (continued)

The display format is as follows.

0 / Z7 Z7 /_/ cO

~7 a/_/ C7

The displays may be interconnected to produce an n-digit display with the following features:

• Ripple blanking input and output for blanking leading or trailing zeroes

• Floating-decimal point logic capability

• Overriding blanking for suppressing entire display or pulse modulation of LED brightness

• Dual count enable inputs for parallel look-ahead and serial ripple logic to build high-speed fully synchronous,multidigit counter systems with no external logic, minimizing total propagation delay from the clock to thelast latch output

• Provision for ripple count cascading between packages

• Positive-edge-triggered synchronous BCD counter

• Parallel BCD data outputs available to drive logic processors or remote slaved displays simultaneously withdata being displayed

• Latch strobe input allows counter to operate while a previous data point is displayed

• Reset-to-zero capability with clear input.

absolute maximum ratings over operating case temperature range (unless otherwise noted)Supply Voltage, VCG (S66 Note'': Continuous . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Nonrepetitive Peak, t w < 100ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VInput Voltage (See Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 VOperating Case Temperature Range (See Note 2) . . . . . . . . . . . . . . . . . . . . 0°C to 85°CStorage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to 85°C

NOTES 1 Voltage values are with respect to network ground terminal2 Cas« temperature it the surface temperature of the plestic encapsulant measured directly over the integrated circuit Forced-air

cooling may be required to maintain this temperature

recommended operating conditions

Supply Voltage, Vcc

Normalised Fan-Out from Each Output, N(to Serie» 54/74 Integrated Circuits)

Low Logic Level

High Logic Level

Clock Pulte Width, tyyfciocfc)

QA.QB, QC,QD, RBO

Maximum CountRBO

QA. OB. QC.QDMaximum CountHigh Logic Level

Low Logic LevelClear Pulte Width, tw(c|,ar)Latch Strobe Pulte Width, tw<(atcn ,trobel

Setup Time, ««tup (S<* Not« 3)Serial Carry and Parallel CarryClear Inactive State

MIN NOM MAX

4.75 5 5.25

3

536

102555254530

60

UNIT

V

nt

nint

nt

NOTE 3* Minimum Mtup t im« it the interval immediately p r »cod ing the positive-going edge of the clock puls« during which Interval the deta tobe recognized muit be maintained et the input to en tu re tit recognition.

336

TYPES TIL306, TIL307NUMERIC DISPLAYS WITH LOGIC

operating characteristics at 25°C case temperature

PARAMETERLuminous Intensity

v (See Note 4)Figure QDecimal Point

Ap Wavelength at Peak EmissionÛA Spectral Bandwidth

VIH High-Level Input Voltage

VIL Low-Level Input VoltageVIK Input Clamp Voltage

VOH High-Level Output Voltage

Low-Level Output Voltage°L (See Note 6)

RBO

QA. QB, QC. QoMaximum Count

OA.QB. QC.QD. R8°Maximum Count

l| Input Current at Maximum Input Voltage

I|H High-Level Input Current

I|L Low-Level Input Current

'OS Short-Circuit Output Current

Serial Carry

RBO NodeOther InputsSerial Carry

RBO NodeOther Inputs

QA, QB. QC. QDMaximum Count

'CC Supply Current

TEST CONDITIONS

VC C -5V

Vcc " 5 V , See Note 5Vcc - S V. See Note 5

V C C - 4 7 5 V . l | - -12mA

VCC- 4.75V, lOH--120uAVCC- 4.75V, IOH--240^A

VCC* 4.75V, lOH = -400uA

Vcc ' 4-75 V. IOL" 4.8mAVCC- 4.75V. lOL-8mAVCC" 5.25V. V | - 5 5 V

VCC- 5.25V. V | - 2 4 V

Vcc = 5.25V, V | -0 .4V

VCC - 5.25 V

VCC - 5 25 V. See Note 5

MIN TYP* MAX

700 1200

40 70

640 660 68020

20.8

-1 5

24

0.4

1

40

-0.12 -0.520

-1.6

-1.5 -2.4-0.8

-9 -27.5

-15 -55

120 200

UNITMCd

MCd

nmnmVVV

V

V

mA

MmAMA

mA

mA

mA

+ Alt typical values are at VQQ - 5 VNOTES 4 Luminous intensity is measured with a light sensor and filter combination thai approximates the ClE (International C

on Illumination) eye response curve5 These parameters are measured with all LED segments and the decimal point on6 This parameter is measured with the display blanked

ommission

switching characteristics, Vcc = 5 V, TC - 25°C

PARAMETER!

'max'PLH

'PHL'PLH

'PHL«PLH

'PHL'PHL

FROM

(INPUT)

Serial Look-Ahead

Clock

Clock

Clear

TO

(OUTPUT)

Maximum Count

Maximum Count

QA, QB. QC. QDQA. QB. QC. QD

TEST CONDITIONS

CL-15pF. RL-560n.See Figure 1

CL= 15 pF, RL- 1.2 kfi.Se« Figure 1

MIN TYP MAX

12 18

1223

26

29

283857

UNIT

MHZ

ns

ni

ni

nt

^ Propagation d«1»y tim», low to high-lev«) output'PHL s Propagation delay time, high to low-l«v»l output

vcc

FROM OUTPUTUNDER TEST

NOTES: A. CL includn prob« »nd jig c«pacit«nc*8. All d.od««r»1N3O64.

LOAD CIRCUIT-FIGURE 1

337

TYPES TIL306, TIL307NUMERIC DISPLAYS WITH LOGIC

TYPICAL CHARACTERISTICS

OC

I

RELATIVE SPECTRAL CHARACTERISTICS

600 620 640 660 680X-Wavelength—nm

FIGURE 2

CMnU

o»

3Ocl

0.7

0.4

-E 0.2

0.1

RELATIVE LUMINOUS INTENSITYvs

CASE TEMPERATURE

—Vcc = 5

10 20 30 40 50 60 70

Tc-Case Temperature-°CFIGURE 3

TYPICAL APPLICATION DATA

This application demonstrates how the displays may be cascaded for N-bit display applications. It features:

Synchronous, look-ahead countingRipple blanking for leading zerosOverriding blanking for total suppression or intensity modulation of displayDirect parallel clearLatch strobe permits counter to acquire data for the next display while viewing current display.

For other counter configurations, see Counting Circuits Using TIL306 and TIL308 LED's.

MOflEDIGIISMAVBECONNECTED HERE

(MOST SIGNIFICANTDIGIT LATCH OUTPUTS

LEAST SIGNIFICANTDIGIT

U0<« INPIII

LAIlHSIlUJf l lIM'L'T

RIFI-LIBl ANViINPUl

OVERRIDING.BLANKING INPUT L .ClFARINeur H.

OAOB ocQoSTRB l / CK

OR6I RBO

redBl CLEAR or

UlUMALI-OINT JINPI'IS j —

STHB C

OMAXCOUNT

CK

RBO

SCEI

PC£t

Bl CLEAR OP

OA O,QC ÖDSTFtS l / CK

OMAXCOUNT

RIO *-

SC€I

PCEI

Bl CLEAR OP

o» o„ QC ÖDS T R B / / C K

O

MAXCOUNT

SI CLEAR OP

*TI>* »rial carry input ol the leait-tignificant digit li normally grounded, however. It may be utad a« a count-enable control for the amir*counter (high to disable, low to count) provided the logic level on'thlf pin it not changed while the clock line It low or falte counting mayi «full

338

CD4001M/CD4001C, CD4011M/CD4011C

CD4001M/CD4001C Quadruple 2-lnput NOR GateCD4011M/CD4011C Quadruple 2-lnput NAND Gâte

General DescriptionThe CD4001M/CD4001C, CD4011M/CD4011C are monoli-thic complementary MOS (CMOS) quadruple two-inputNOR and NAND gate integrated circuits. N- and P-channel enhancement mode transistors provide a sym-metrical circuit with output swings essentially equal tothe supply voltage. This results in high noise immunityover a wide supply voltage range. No DC power other thanthat caused by leakage current is consumed during staticconditions. All inputs are protected against static dis-charge and latching conditions.

Features• Wide supply voltage range• Low power

» High noise immunity

3.0V to 15V

10nW(typ.)

0-45 VDD (typ.)

Connection Diagrams

Ja. 12

d10

VDO

14 13 12

TOP VIEW

11

TOP VIEW

339

CD4001M/CD4001C, CD4011M/CD4011C

Absolute Maximum Ratings (Note 1)Voltage an Any Pin Vss - 0.3 V to VDD + 0.3 VOperating Temperature Range

CD4001M, CD4011M -55°C to +125°CCD4001C.CD4011C -40°C to +85°C

Storage Temperature Range -65°C to +150°CPackage Dissipation 500 mWOperating VDD Range Vss + 3.0V to Vss +15 VLead Temperature (Soldering, 10 seconds) 300°C

DC Electrical Characteristics - CDAOOIM,

Parameter

IL Quiescent DeviceCurrent

PD Quiescent DeviceDissipation/Package

VOL Output Voltage LowLevel

VOH Output Voltage HighLevel

VNL Noise Immunity(All Inputs)

VNH Noise Immunity(All Inputs)

IpN Output Drive CurrentN-Channel (4001)

IDP Output Drive CurrentP-Channel (4001)

IDN Output Drive CurrentN-Channel (4011)

IDP Output Drive CurrentP-Channel (4011)

I) Input Current

Conditions

VDD = 5.0VVDO = 10VVDD = 5.0VVDD = 10VVDD = 5.0V, V, = VDO, I0 = OAVDD = 10V, V| = VDD, I0 = OAVOD = 5.0V, V,= Vss, I0 = OAVDD = 10V, V, = Vss, b = OAVDD = 5.0V, V0 = 3.6V, lo = OAVDD = 10V, V0 = 7.2V, I0 = OAVDD = 5.0V, V0 = 0.95V, lo = OAVDD = 10V, V0 = 2.9V, I0 = OAVDD = 5.0V, Vo = 0.4V, V, = VDD

VDD = 10V, V0 = 0.5V, V, = VDD

VD O=50V, V0 = 2.5V, V|=VSS

VDD = 10V, V0 = 9.5V, V, = Vss

VDD = 50V, V0 = 0.4V, V, = VDD

VDD = 10V, V0 = 0.5V, V, = VOD

VDD = 5.0V, V0 = 2.5V, V, = Vss

VDD = 10V, V0 = 9.5V, V,= Vss

Limits-55°C

Min.

4.959.951.53.01.42.90.51.1

-0.62-0.62031063-0.31-0.75

Max.

0.050.10.251.0

0.050.05

25°CMin.

4.959.951.53.01.53.0

0.400.90.50.5

0.250.5

-0.25-0.6

Typ.

0.0010.0010.0050.01

00

5010

2.254.52254.5102.520

-1.00.50.6-0.5-1.210

Max.

0.050.1

0.251.0

0.050.05

125°CMin.

4.959.951.42.91.53.0

0.28065-035-0.350.1750.35

-0.175-0.4

Max.

3.06.01560

0.05005

Units

^A^A

MWMWVVVVVVVV

mAmAmAmAmAmAmAmApA

Nole 1: 'Absolute Maximum Ratings" are those values beyond which the safety o1 the device cannot be guaranteed Except for"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits The table ol"Electrical Characteristics" provides conditions lor actual device operation

340

CD4023M/CD4023C, CD4025M/CD4025C

CD4023M/CD4023C Triple 3-lnput NAND GâteCD4025M/CD4025C Triple 3-lnput NOR Gate

Genera! DescriptionThese triple gates are monolithic complementary MOS(CMOS) integrated circuits constructed with N- andP-channel enhancement mode transistors. All inputsare protected against static discharge with diodes toVDO and VSs-

Features• Wide supply voltage range• High noise immunity• 5-10V parametric ratings• Low Power

3.0V to 15V0.45 VDD (typ.)

Connection Diagrams

VDD

t 2 3 4 5 t |7

CD4023M/CD4023CTOP VIEW

v "14 13 12U£J

f

A

n

L

10

(9

\

1

CD4025M/CD4025CTOP VIEW

v$s

341

CD4023M/CD4023C, CD4025M/CD4025C

Absolute Maximum Ratings (Note i>Voltage at Any Pin Vss- to VDD + 0 3VOperating Temperature Range -55°C to +125gC

CD4023M.CD4025M -55°C to +125°CCD4023C,CD4025C -40°Cto+85°C

Storage Temperature Range -65°C to -H50°CPackage Dissipation 500mWOperating VDD Range Vss + 3 0 V to Vss +15 VLead Temperature (Soldering, 10 seconds) 300°C

DC Electrical Characteristics - 004023«, co4025M

Parameter

IL Quiescent DeviceCurrent

PO Quiescent DeviceDissipation/Package

VOL Output Voltage LowLevel

VOH Output Voltage HighLevel

VNL Noise Immunity(All Inputs)

VNH Noise Immunity(All Inputs)

IDN Output Drive CurrentN Channel (4025)

I0P Output Drive CurrentP Channel (4025)

IrjN Output Drive CurrentN Channel (4023)

I[>P Output Drive CurrentP Channel (4023)

I| Input Current

Conditions

VOD = 50VVDD = 10VVDD = 50VVDD = 10VVDD = 50V,V| = VDD, I0 = OAVDD = 10V, V| = VDD, I0 = OAvDD = 50v>v, = vss, IO = OAVDD = 10V, V| = VSS, I0 = OAVDD = 50V, V0 = 36V, I0=OAVDO = 10V, V0 = 72V, I0 = OAVDO = 50V, V0 = 095V, I0 = OAVDO = 10V, V0 = 29V, I0 = OAVDD = 50V,V0 = 04V,V|=VDDVDD = 10V, V0 = 05V, V, = VDD

VDD = 50V, V0 = 25V, V, = VSSVDD = 10V, V0 = 95V, V,=VSS

VDD = 50V, VO = 04V, V, = VOD

VOD=10V, V0 = 05V, VI=VODVDD = 50V, V O =25V, V, = VSSVDD = 10V, V0 = 95V, V, = VSS

Limits-55°C

Min.

49599515301429051 1

-062-062031063-031-075

Max.

0050102510

005005

25°C

Min.

4959951530153004009-05-0502505

-025-06

Typ.

000100010005001

00

5010

22545225451025-20-100506-05-1210

Max.

005010251 0

005005

125'C

Min.

4959951 4291 530

028065-035-035

0175035

-0175-04

Max.

30601560

005005

Units

nAfA

MWMWVVVV

VVVV

mAmAmAmAmAmAmAmApA

342

CD4027BM/CD4027BC

CD4027BM/CD4027BC Dual J-K Master/SlaveFlip-Flop with Set and Reset

General Description FeaturesThese dual J-K flip-flops are monolithic complementary • Wide supply voltage rangeMOS (CMOS) integrated circuits constructed with N-andP-channel enhancement mode transistors. Each flip-flophas independent jJj K, set, reset, and clock inputs andbuffered Q and "Q" outputs. These flip-flops are edgesensitive to the clock input and change state on thepositive-going transition of the clock pulses. Set or resetIs independent of the clock and Is accomplished by ahigh level on the respective input.All inputs are protected against damage due to staticdischarge by diode clamps to VDD and Vss.

» High noise immunity

• Low power TTLcompatibility

• Low power

• Medium speed operation

3.0V to 15V

0.45 VDD (typ.)

fan out of 2 driving 74Lor 1 driving 74LS

50nW(typ.)

12 MHz (typ.)with 10V supply

Schematic Diagram1.9

SET O

6.10

5 .11

CL

3D-

4.12RESET O

Connection Diagram Dual-ln-Line and Flat Package

VDO t

1"

—

t

Il 01

15 II«

CLOCK 1 RES

T,F/FI

L

_J

—

ET1

12

K1 j11

2 3

| ———

4

T l

F/F2

JJ1

5 IE

,. "I!

—

' i-02 02 CLOCK 2 RESET 2 K2 J2 SET 2

TOP VIEW

343

CD4027BM/CD4027BC

Absolute Maximum Ratings (Notes 1 and 2» Recommended Operating ConditionsVQO dc Supply Voltage -0.5 to +18VIM Input Voltage -OS to VQD +05 VQCTg Storage Temperature Range -65°C to +150"CPO Package Dissipation 500 mWT|_ Lead Temperature (Soldering. 10 seconds) 300°C

(Note 2)VDD dc Supply Voltag«VIM Input Voltag«TA Operating Temperature Range

CD4027BMC04027BC

3to15VD C

Oto VDD VDC

-55°Cto+125°C+85°C

DC Electrical Characteristics CD402/BM (Note 2»

PARAMETER

IDD Quiescent Device Current

VOL Low Level Output Voltage

VOM High Level Output Voilage

VIL Low Level Input Voltage

VIH High Level Input Voltage

IOL Low Level Output Current

'OH Hiqh Level Output Current

I|N Input Current

CONDITIONS

VDD "5VVDD- lovVDO' i5vlloK I^AVOD = 5vVDO' iovVDD-- '5vllQK l^A

VDD ' 5vVOD = iovVDD = i5vVDD ' 5V. VQ - 0 5V or 4 5VVDD' iov. VQ- iv or 9vVDD= '5v. VQ = 1 5v or 13 svVDD - 5V. VQ - 0 5V or 4 5VVDD' iov. vo= iv0r9vVDD = ' 5V VQ = ' 5V or 1 3 5V

VDD = 5v. vo '04vVDD = lov. vo 'OSvVDD = 'sv. VQ- ' svVDD • 5v, VQ = * 6vVOD° IOV. Vo '9SVVOD' 15V. VO' 135V

VOD- 15V. V iN 'OVVoD' 15V. V|N= 15V

55 C

MIN

4959951495

3 57011 0

0641 64 2

-064

-1 6-42

MAX

1

24

005005005

1 5304 0

0 1

01

25°C

MIN

4959951495

357011 0

0511 334

-0.511 3

-34

TYP

000

51015

OBS22588

-088-225-88

-10-510-5

MAX

1

24

005005005

1 5304 0

-0101

125°C

MIN

4959951495

357011 0

0360924

-036-09-24

MAX

3060120

0.05005005

1 5304 0

-101 0

UNITS

HA«A

HA

V

V

V

V

V

V

V

V

V

V

V

V

mA

mA

mA

mA

mAmA

H*HA

DC Electrical Characteristics (Contu) co4027Bc (Note 2)PARAMETER

'DO Quiescent Device Current

VOL Low Level Output Voltage

VOH High Level Output Voltage

VIL Low Level Input Voltage

VIH High Level Input Voltage

IOL Low Level Output Current

CONDITIONS

VDD ' 5vVDD= 'ovV0D = '5V

llQK luA

VDD * 5VVDO - iovVOD- 'sv||Q|< 1pA

VDD • svVDD - 'ovVDD' '5vVDD * 5V. VQ - 0 5V or 4 5VVDD- 10V. vo= 'vor 9vVDD " '5V. VQ ' ' SV or 13 5V

VDD " 5V. VQ •= 0.5V or 4.5VVDD ' 'ov. VQ- 'Vor9vVDD • 'sv. VQ = i.sv or 13 svVDD • 5v. vo = 04vVDD • 'ov. VQ = o svVOD' 15V. VQ- 1 5V

-40°C

MIN

4959951495

3570".0

0.521 33.6

MAX

4

816

005005005

1 53040

2S°C

MIN

4959951495

357011.0

0.441.13.0

TYP

000

51015

0.8822588

MAX

48

16

OOR005005

1 5304 0

86"C

MIN

4959951495

3570110

0360924

MAX3060120

1

005005005

1 53040

UNITS

(lA

„A

KA

V

V

V

VVV

V

V

V

VV

V

mAmAmA

344

CD4027BM/CD4027BC

DC Electrical Characteristics co402?Bc (Note 2)

PARAMETER

'OH High Level Output Cum-nt

1 IM Input Curium

CONDITIONS

VQO - 5V. VQ 4 6V

VDD - iov. vo 9 5vV[)O 15V. VQ 135V

VDD '5v. VIN ovVDD • '5v. VIM IBV

40 C

WIN

052

1 33.6

MAX

03

03

25 C

MIN

044

1.1

30

TYP

088

725

88

to '•>to 5

MAX

0.3

0.3

85 C

MIN

036

097 4

MAX

1 0

1 0

UNITS

MlA

ii.A

INA

«A

^A

AC Electrical Characteristics TA = 25°C, CL = 50pF, trCL = tiCL = 20ns, unless otherwise specified.

PARAMETER

'PHL Of tPLH Propagation Delay Time Fioni

Clock to O 01 Q

tPHL or tpLH Propagation Delay Time FromSet to Q or Reset to Q

tpHL. Dr IPLH Propagation Delay Time FromSet to Q or Reset to Q

ts Minimum Data Set Up Time

lTHLo r 'TLH Transition Time

fCL Maximum Clock Frequency(Toggle Mode)

VCL of '(CL Maximum Clock Rise andFall Time

tyv Minimum Clock Pulse Width

(tWH =• <WL>

ÎWH Minimum Set and ResetPulse Width

C|tsl Average Input Capacitance

CPD Power Dissipation Capacity

CONDITIONS

VDD- 5vVDD1- IOVVDD- i5vVDD * 5vVDD' iovVDD^ i5vVDD * 5vVDD - 'ovVDD * 16VVDD - 5vVDD- iovVDD- i5vVDD * 5vVDD =- iovVDD- i5vVDD - 5vVDD ' 10V

VDD * i5vVDD = 5vVDD = iovVDD - 15VVDD - 5vVDD - iovVDD- 15VVOD 5VVDD = iovVDD - '5VAny Input

Per Flip Flop(Note 3)

MIN

2 56.27.6

15105

1

TYP

2008065

1707055

1105040

1355545

1005040

512.5155

1004032

803025

5

35

MAX

400160130

340140110

22010080

27011090

20010080

-v.

2008065

1606050

7.5

UNITS

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

n s

ns

ns

nsns

MH/

MH/

MH/

us

us

us

ns

ns

ns

ns

ns

ns

pF

PF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant toimply that the devices should be operated at these limits. The table of "Recommended Operating Conditions" and "Electrical Characteristics"provides conditions for actual devrce operation.Note 2: Vgs = OV unless otherwise specified.Note 3: CPQ determines the no load ac power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristicsapplication note AN-90.

345

CD4027BM/CD4027BC

Typical Applications

Ripple Binary Counters

Shift Registers

DATAINPUT J 0

K CIK Ö

j a J 0

K CIK 0

Truth Table

•tn_1 INPUTS

CL*

J~

J~

J~

J~

~\_

X ^

X

X

JI

X

0

X

X

X

X

X

K

X

oX

I

X

X

X

X

s0

0

oooI

oI

R

0

0

0

0

ooI

I

Q

0

I

0

IX

X

X

X

*tn OUTPUTS

Q

I

I

O

0

I

oI

Q

0

oII

0

I

I

(No change)

Where I = High LevelO = Low Level» = Level ChangeX = Don't Care• = tn_i refers to <he time interval prior to the

positive clock pulse transition* = tn refers to the time intervals after the

positive clock pulse transition

346

CD4066BM/CD4066BC

CD4066BM/CD4066BC Quad Bilateral SwitchGeneral DescriptionThe CD4066BM/CD4066BC is a quad bilateral switchintended for the transmission or multiplexing of ana-log or digital signals. It is pin-for-pin compatible withCD4016BM/CD4016BC, but has a much lower "ON"resistance, and "ON" resistance is relatively constantover the input-signal range.

Features• Wide supply voltage range 3Vto15V• High noise immunity 0.45Voo(tyP-)• Wide range of digital and ±7.5VpEAK

analog switching• "ON" resistance for 15V operation 80Q• Matched "ON" resistance ARON = 5Q(typ.)

over 15V signal input• "ON" resistance flat over peak-to-peak signal range• High"ON"/"OFF" 65dB(typ.)

output voltage ratio @ fjS = 10kHz, R|_ = 10kQ• High degree linearity 0.1% distortion (typ.)

@ fis = 1kHz, Vis = 5Vp.p,

• Extremely low "OFF" 0.1nA(typ.)switch leakage @ VDD - VSs = 10 V, TA = 25°C

• Extremely high control input impedance 1012Q(typ.)

• Low crosstalk -50dB(typ.)between switches @ fis = 0.9MHz, RL=1kQ

» Frequency response, switch "ON" 40 MHz (typ.)

Applications• Analog signal switching/multiplexing

• Signal gating• Squelch control• Chopper• Modulator/Demodulator• Commutating switch

• Digital signal switching/multiplexing• CMOS logic implementation• Analog-to-digital/digital-to-analog conversion• Digital control of frequency, impedance, phase, and

analog-signal-gain

Schematic and Connection Diagrams

H MHÇ ö-OUT/IN

Dual-ln-Line Package

OUT/IN

347

CD4066BM/CD4066BC

Absolute Maximum Ratings(Notes 1 and 2)

Supply VoltageVIM Input VoltageTS Storage Temperature RangePO Package Dissipation

-O5V to+18VO.5V to VOD + 0 5V

-65"C to+150"C500 mW

T L Lead Temperature (Soldering, 10 seconds) 300° C

Recommended Operating Conditions(Note 2)

VDD Supply VoltageVIM Input VoltageTA Operating Temperature Range

CD4066BMC04066BC

3V to 15VOVtoV D D

-55°Cto+125"C40" C to +85" C

DC Electrical Characteristics (Note 2)

IDD Quiescent Device Current VDD = 5VvDD= lovVDD* i5v

-55°C

Mm Max

0.250.51.0

25°C

Mm Typ

0.010.010.01

Max

0.250.51.0

125°C

Mm Max

7.51530

Units

^AHApA

Signal Inputs and Outputs

RON "ON" Resistance

ARoN A "ON" ResistanceBetween any 2 of4 Switches

I|S Input or Output LeakageSwitch "OFF"

Control Inputs

VILC Low Level Input Voltage

V|HC High Level Input Voltage

IIN Input Current

RL=10kUtoVDP2-VSSvc - VDD. Vis = vss to VDDVDD = 5VVDD "iovVDD = 15V

RL= 10k» to V°DgVSSvc = VDD. Vis = vss to VDDVDD= iovVDD = 15Vvc = oV|S= 15V and 0V.VQS= OVand 15V

2000400220

±50

27012080

105

±0 1

2500500280

±50

3500550320

±500

nan

nn

nA

V|S= Vss and VDDVQS * VDD and vssVOD = 5vVDD = iovVDD= i5vVDD = 5vVDD= IOV (see note 6)VDD= i5vVDD- vss = i5vVDD ^ Vis> Vss

3.57.011.0

1 53.04.0

iO.1

3.57.011.0

2.254.56.75

2.755.58.25

no-5

1.53.04.0

10.1

3.57.011.0

1.5304.0

11.0

vvvvvv

*<A

DC Electrical Characteristics CDAMÔBC (Note 2)

IDD Quiescent Device Current VDD = 5VVDD= iovVDD=15V

-40°C

Min Max

1.02.04.0

25°C

Min Typ0.010.010.01

Max

1.02.04.0

B5°C

Min Max

7.51530

Units

^A^AHA

348

CD4066BM/CD4066BC

DC Electrical Characteristics (Contu) co-toeeec (Note 2}

Parameter Conditions-40°C

Mm Max

25°C

Min Typ Max85°C

Mm MaxUmt>

Signal Inputs and Outputs

RON "ON" Resistance

ARQN A"ON" ResistanceBetween Any 2 of4 Switches

I|S Input or Output LeakageSwitch "OFF"

RL= iokntoVpD aVss

vc - VOD. vss to VDDVDD = 5vVDD = iovVDD= 15V

Vnn - VecD. — i r* t. f~i * _ "L/L/ * Don L — l u Kit to ——— n — ^

VGC = VDD. vis = vss to VDDVDD = lovV D D=15V

VG = O

2000450250

±50

270 2500120 50080 280

105

±01 ±50

3200520300

±200

nnn

nnnA

Control Inputs

VILC Low Level Input Voltage

VIHC High Level Input Voltage

IIN Input Current

V|S= Vss and VDDVOS = VDD and Vss

VDO = 5V

VDD = 15VVDD * 5vVDD= 10V (See note 6)VDD = 15VVDD- vss = 15V

VDD > vc > Vss

1.53040

3.57.011.0

±0.3

225 154.5 306.75 4.0

3.5 2.757.0 5.511.0 8.25

±10-5 ±0.3

1.53.04.0

3.57.011.0

±1.0

VVV

VVV

pA

AC Electrical Characteristics TA = 25°C, tr = t, = 20ns and VSS = OV unless otherwise specified

Parameter

tPHL, tpi_H Propagation Delay Time SignalInput to Signal Output

'PZH. 'PZL Propagation Delay TimeControl Input to SignalOutput High Impedance toLogical Level

tPHZ. tPLZ Propagation Delay TimeControl Input to SignalOutput Logical Level toHigh Impedance

Sine Wave Distortion

Frequency Response-Switch"ON" (Frequency at -3 dB)

Conditions

Vc ~ VDD. CL = 50 pF, (Figure 1)R L = 200kVDD = 5vVDD = iovVDD = 15VR L » 1.0 kfi, CL = 50 pF, (Figures 2and 3)VDD = 5VVDD=10VVDD = i5vR L * 1-0 kfi, CL = 50 pF, (Figures 2and 3)VDD = 5VVDD*= iovVDD= i5vvc = VDD = 5 v, vss " -5 vRL = 10 ku. Vis = 5 Vp.p, f = 1 kHz.(Figure 41

vc = VDD = 5v, vss = -5v.RL= 1 kJ2, V|S= 5Vp_p,20 Lo91o Vos/VosdkHz)-dB,(Figure 4)

Mm Typ

251510

0 1

40

Max

553525

1256050

1256050

Uniti

nsnsns

nsnsns

nsnsns

%

MHz

349

CD4066BM/CD4066BC

AC Electrical Characteristics (continued)TA = 25°C, tr = tt = 20ns and VSS = OV unless otherwise noted

ParameterFeedthrough — Switch "OFF"(Frequency at -50dB)

Crosstalk Between Any TwoSwitches (Frequency at -50dB)

Crosstalk; Control Input toSignal Output

Maximum Control Input

C,s Signal Input CapactanceCos Signal Output CapacitanceCIOS Feedthrough CapacitanceC|N Control Input Capacitance

ConditionsVOD = 5.0V, VCc = Vss = -5.0V,RL = 1 kS, V,s = 5.0 Vp p, 20 Log10,Vos/Vis = -50 dB, (Figure 4)VDD = VC(A) = 5.0V; Vss = VC(B) = -5.0V,RL=1kQ, V,S(A) = 5.0Vp.p, 20 Log ,o,Vos(B)/V|S(A) = -50dB, (Figure 5)VDD = 10V, RL = 10kQ, R|N = 1.0kQ,Vcc = 10 V Square Wave, CL = 50 pF(Figure 6)RL = 1.0kQ, CL = 50pF, (Figure 7)Vos(f)=1/Wos(1.0kHz)VDD = 5.0VVDD = 10VVDD = 15V

VDD = 10VVC = OV

Min. Typ.

1.25

0.9

150

6.0808.58.08.00.55.0

Max.

7 5

Units

MHz

mVpp

MHzMHzMHz

PF

PF

pF

PF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed They are notmeant to imply that the devices should be operated at these limits The tables of "Recommended Operating Conditions" and"Electrical Characteristics" provide conditions for actual device operation.Note 2: Vss - 0 v unless otherwise specified.Note 3: These devices should not be connected to circuits with the power "ON"Note 4: In all cases, there is approximately 5 pF of probe and |ig capacitance in the output; however, this capacitance is included in CLwherever it is specifiedNote 5: Vis is the voltage at the in/out pin and VQS is the voltage at the out/in pin Vc is the voltage at the control inputNote 6: Conditions for V|Hc'

a) V|S = VDD. IQS = standard B series IQH b) vis = 0 V, IQL = standard B series IQL-

AC Test Circuits and Switching Time Waveforms1

CONTROL VOD

INJOUT ""' OUTMI

vss l. ir *«OS

l T'»oo r ——

vos

FIGURE 1.1 PH L. 'PLH Propagation Oalay Tim* Signal Input to Signal Output

'PZH «PHZ

»IJ «00

»It •

cONiROL VDD

»SS

1

COHTBOL VQQ

V»

1

!.. LT"" !"

FIGURE 2- iRZH't

«00

1,_ - -£i— —»«i

«PZL 'PLZ

FIGURE 3. tpzi. 'PLZ Propagation O*Uy Tim« Control to Signal Output

350

CD4066BM/CD4066BC

AC Test Circuits and Switching Time Waveforms

•vBS«is

-2SV

__ Vf; » VOD for distortion and frequency response tests~ Vç = Vss '°' feedthrough test

FIGURE 4. Sine Wave Oittortion, Frequency Rctponw and Faedthrouph

«I.u

' "OS(2)

FIGURE 5. Crcmtalk BttwMn Any Two Switch«

ve

Vis

>IN>n

,

\CONTROL VOD

""01JTW,ÏCfH4tSOUT/1"

vssi !»VDO ——————

ov —————— «

Cl

-T58"

^\f to-. >

FJ. Y '. !v —— CROSS1

FIGURE 6. Crowtilk: Control Input to Sign«! Output

VOD

»is •

COKTROL VOD

vss 1., rvos

I T'FIGURE 7. Maximum Control Input Frequency

351

CD4066BM/CD4066BC

Typical Performance Characteristics

"ON" Resistance vs SignalVoltage for TA - 25°C

- 400

~z 350occ- 300u

< 2SO<Ä

Z 200cc

g '50

-i 100

- If

D J -

^

\ ss

//

5V

//

\

^

00i-

- V

4-1

II-

ss

H=VOD - vss •

ov

i15V

- 8 - 5 - 4 - 2 0 2 4 6 I

SIGNAL VOLTAGE (V,sl (V)

"ON" Resistance as a Functionof Temperature for

300

250

200

ISO

100

50

0

TA

TU

TAi

-1

_j

»iH»2:

5

25

5

:5

CM

-C

1 ,

f*

•*•

/

s^

s

•*

shs\

- 8 - 6 - 4 - 2 0 2 4 6 8

SIGNAL VOLTAGE (V1S1 (V)

"ON" Resistance as a Functionof Temperature forVDD-VSS=ISV

- 8 - 6 - 4 - 2 0 2 4 6 «

SIGNAL VOLTAGE IV|sl (VI

"ON" Resistance as a Functionof Temperature forVDD - Vss - 5V

^ 350occi 300u5 250

2 200se.^ 150

1

/

///

Y

//

s

S•>

f

f\q

I

tl

A

^A

T|

12

•2

& C

IC

- 8 - 6 - 4 - 2 0 2 4 6 t

SUPPIG VOLTAGt IV|S> W)

Special ConsiderationsIn applications where separate power sources are usedto drive VDD and the signal input, the VQQ currentcapability should exceed Vprj/Rt. (Rl_ = effectiveexternal load of the 4 CD4066BM/CD4066BC bilateralswitches). This provision avoids any permanent currentflow or clamp action on the VDD supply when power isapplied or removed from CD4066BM/CD4066BC.

In certain applications, the external load-resistor currentmay include both VQD anQl signal-line components. To

avoid drawing VßD current when switch current flowsinto terminals 1, 4, 8 or 11, the voltage drop across thebidirectional switch must not exceed 0 6V at TA < 25°C,or 0.4V at TA > 25°C (calculated from RON valuesshown).

No VOD current will flow through RL if the switchcurrent flows into terminals 2, 3, 9 or 10.

352

MM74C925, MM74C926, MM74C927, MM74C928

MM74C925, MM74C926, MM74C927, MM74C928 4-DigitCounters with Multiplexed 7-Segment Output DriversGeneral DescriptionThese CMOS counters consist of a 4-digit counter, aninternal output latch, NPN output sourcing drivers fora 7-segment display, and an internal multiplexingcircuitry with four multiplexing outputs. The multi-plexing circuit has its own free-running .oscillator,and requires no external clock. The counters advanceon negative edge of clock. A high signal on the Resetinput will reset the counter to zero, and reset the carry-out low. A low signal on the Latch Enable input willlatch the number in the counters into the internal out-put latches. A high signal on Display Select input willselect the number in the counter to be displayed; a lowlevel signal on the Display Select will select the numberin the output latch to be displayed.

The MM74C925 is a 4-decade counter and has LatchEnable, Clock and Reset inputs.

The MM74C926 is like the MM74C925 except that ithas a display select and a carry-out used for cascadingcounters. The carry-out signal goes high at 6000,goes back low at 0000.

The MM74C927 is like the MM74C926 except thesecond most significant digit divides by 6 rather than 10.Thus, if the clock input frequency is 10 Hz, the displaywould read tenths of seconds and minutes (i.e., 9:59.9).

The MM74C928 is like the MM74C926 except the mostsignificant digit divides by 2 rather than 10 and the

carry-out is an overflow indicator which is high at2000, and it goes back low only when the counter isreset. Thus, this is a 3 1/2-digit counter.

Features• Wide supply voltage range 3V to 6V• Guaranteed noise margin IV• High noise immunity 0.45 VQC (typ-)• High segment sourcing current 40mA

@VC C - 1.6V, Vcc = 5V« Internal multiplexing circuitry

Design ConsiderationsSegment resistors are desirable to minimize powerdissipation and chip heating. The DS75492 serves as agood digit driver when it is desired to drive brightdisplays. When using this driver with a 5V supply atroom temperature, the display can be driven withoutsegment resistors to full illumination. The user must usecaution in this mode however, to prevent overheating ofthe device by using too high a supply voltage or byoperating at high ambient temperatures.

The input protection circuitry consists of a series resistor,and a diode to ground. Thus input signals exceedingVcc will not be clamped. This input signal should not beallowed to exceed 15V.

Connection DiagramDual-ln-Line Package

MM74C92SDual-ln-Line Package

MM74C926, MM74C927 and MM74C928

r-

' -

n

t 1 *

-

1 4 '

-

1

Functional DescriptionReset — Asynchronous, active high

Display Select — High, displays output of counterLow, displays output of latch

Latch Enable - High, flow through conditionLow. latch condition

Clock - Negative edge sensitive

Segment Output — Current sourcing with 40 mA @VOUT « Vcc - 1.6V (typ.)Also, sink capability - 2 LTTLloads

Digit Output - Current sourcing with 1 mA @VOUT = 1-75V. Also, sink capa-bility = 2 LTTL loads

Carry-out — 2 LTTL loads. See carry-outwaveforms.

353

MM74C925, MM74C926, MM74C927, MM74C928

Absolute Maximum Ratings (Note 1)Voltage at Any Output PinVoltage at Any Input PinOperating Temperature Range (TA)Storage Temperature RangePackage DissipationOperating Vcc RangeVcc

Gnd - 0.3V to VCC+0.3VGnd-0.3Vto+15V

-40°C to +85°C-€5°Cto+150°C

Refer to PDIMAXI vs TA Graph3V to 6V

6.5VLead Temperature (Soldering, 10 seconds) 300°C

DC CharaCteriStiCS Win/max limits apply at -40°C < T, < +85°C, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

CMOS TO CMOS

V)N(D Logical "1" Input Voltage

VINIOI Logical "0" Input VoltagevouT(i) Logical "1" Output Voltage

(Carry out and Digit Output

Only)

VOUT(OI Logical "0" Output Voltage

'iNm Logical "1" Input Current

IINIOI Logical "0" Input Current

lcc Supply Current

Vcc = 5.0V

Vcc = 5 0V

VCC = 5.0V, I0=-10KA

Vcc = 5.0V, I0 = 10^A

VCC = 5.0V, VIN = 15V

Vcc = 5.0V, V1N = 0V

Vcc = 5.0V. Outputs Open Circuit,VIN = 0V or 5V

3.5

4 5

-1.0

0005

-0005

20

1.5

0.5

1 0

1000

V

V

V

V

AiA

MA

HA

CMOS/LPTTL INTERFACEviN(ii* Logical "1" Input Voltage

VINIOI Logical "0" Input VoltageVOUTID Logical "1" Output Voltage

ICarry-Out and DigitOutput Only)

VOUT(0] Logical "0" Output Voltage

Vcc = 4.75V

Vcc = 4 75V

Vcc = 4.75V,I0 = -360 AtA

Vcc = 4.75V,

I0 = 360^A

Vcc-1.5

24

0.8

0.4

V

V

V

V

OUTPUT DRIVE

VOUT Output Voltage (SegmentSourcing Output)

RON Output Resistance (SegmentSourcing Output)

Output Resistance (Segment

Output) Temperature Coefficient

'SOURCE Output Source Current(Digit Output)

'SOURCE Output Source Current(Carry-out!

'SINK Output Sink Current(All Outputs)

0jA Thermal Resistance

IOUT = -65 mA, Vcc = 5V, T, = 25°C

IOUT = -40 mA, Vcc = 5V 1 ^ }^j°£

'OUT = -65 mA. Vcc - 5V, T, = 25°C1 T, = 100°C

OUT - . cc - | T( = 150oc

Vcc = 4.75V, VOUT = 1.75V, T, = 150°C

Vcc = 5V, VOUT = 0V, T, = 25°C

Vcc = 5V. VOUT = Vcc, T, = 25°C

MM74C925 (Note 4)MM74C926, MM74C927, MM74C928

Vcc-1.6

-1

-1.75

1.75

Vcc-1.3

Vcc-1-2Vcc-1.4

203035

0.6

—9

-3.3

3.6

7570

4050

0.8

10090

V

V

V

nnn

%/°c

mA

mA

rrrA

°C/W°C/W

Not« 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "OperatingRange" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" providesconditions for actual device operation.Note 2: Capacitance is guaranteed by periodic testing.Note 3: Cprj determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristicsapplication note, AN-90.Not* 4: 6|A measured in free-air with device soldered into printed circuit board.

354

MM74C925, MM74C926, MM74C927, MM74C928

AC Electrical Characteristics TA = 25°C,CL = SOpF, unless otherwise notedPARAMETER

•MAX Maximum Clock Frequency

1,, t( Maximum Clock Rise or Fall Time

tWB Reset Pulse Width

tWLt Latch Enable Pulse Width

'sETicK.i_e> Clock to Latch Enable Set-Up Time

1LR Latch Enable to ResetWait Time

ISETIR.LEI Reset to Latch Enable Set-Up Time

IMUX Multiplexing Output Frequency

CUM Input Capacitance

CONDITIONS

Vcc = 5.0V. T, = 25°CSquare Wave Clock T, = 100"C

Vcc = 5.0V

T. = 25" CVcc = 5.0V 'cc T, = 100 C

T, = 25"CVcc = 5,0V 'cc T, = 100 C

-••» :;:2cVcc = 5.0V T, = 25"C

T, = 100°C

T. = 25"CV-=5'°V T, = 100°C

Vcc = 5.0V

Any Input (Note 2)

MIN

21.5

250320

250320

25003200

00

320400

TYP

43

100125

100125

12501600

-100-100

160200

1000

5

MAX

15

UNITS

MHz

MHz

^

ns

ns

ns

ns

nsns

nsns

nsns

Hz

pF

Typical Performance CharacteristicsTypical Segment Current vsOutput Voltage

Logic and Block DiagramsMM74C925

•I 2200o 2000S tiogn .BOOl 1400£ 1200° 1000zl 800

i eooI 400» 200

! «

Maximum Power Dissipationvs Ambient Temperature

MM!4C926fl]

~M» It CÏ i

MM 74k:s;S

S

7/1

s

IHM

\'S

M

^

92

^'s,

1

fc

-40 -20 0 20 40 60 10 100

T» - AMBIENT TEMPERATURE 1 C)

OCIOCK

DISPLAY ,SELECT l

LATCHEKAtLE l

AOUT <"oCo Sir

CNOO-i .NDO-1

Typical Average SegmentCurrent vs Segment ResistorValue

0 10 20 30 «0 SO GO 70

SEGMENT «ESISTOH il}

Note. VQ - Voltage across digitdriver.

MM74C926

tLATCH

t

f«LATCH

t-

f'

LAICH

t.

^

LATCH

t-MULTIPLEXER

'

4-josc

1

i!O

=O CLOCK

MM74C927 MM74C928

CARRYOUT

DISPLAY ^ SSELECT "^LATCH ^ S

ENAILE "

f'

4 BITLATCH

i

f'

4611LATCH

t-

y4 BIT

LATCH

to

1«4 HT

LATCH

t"

MULTIPLEXER 4-|osc|

ICO

TO 7

SECM

EKT

DECO

DER

AND

DRIV

ERS

O CLOCK

355

MM74C925, MM74C926, MM74C927, MM74C928

Segment Output Driver Input Protection

Common Cathode LED Display Segment Identification

D IE 3 '-I5 Ë 7 S 5

Switching Time WaveformsInput Waveforms

IJUCHEHABK

1 1

n'..,!--

U« —

1 -M?'-

n '~' — '- -i .„„.,„n ——i,_ ...

r—— 1/JÏT

n

Multiplexing Output Waveforms Carry Out Waveform!

r "»«_n_ru-u~LTLMM71C9»

CARRY OUT

MMMCIirCARRY OUT

M«7<C!HCARRY OUT

COUNTSIM 1000

COUNT

COUNTHM tm

COUNT«M 0009

I STAYS HIGHJ IMTIIRESEI

356

UCN-4202A STEPPER MOTOR TRANSLATOR/DRIVER

UCN-4202ASTEPPER MOTOR TRANSLATOR/DRIVER

FEATURES•600 mA Power Drivers•15 V Sustaining Voltage•20 V Output Breakdown•Full-Step or Double-Step Operation•Single-Input Direction Control•Power-On Reset•Transient Suppression Diodes•Schnitt Trigger Inputs

THE UCN-4202A Translator/Driver isspecifically designed for driving small-to-

medium permanent magnet (PM) steppermotors rated to 500 mA and 15 V. Thismonolithic integrated circuit employs a full-step,double pulse drive scheme that produces up to90% utilization of the available PM steppermotor torque.

The UCN-4202A is a unique bipolar I2Ldesign containing approximately 100 logic gates,suitable input/output circuitry for TTL com-patibility, and 600 mA outputs with internal in-ductive load suppression. The circuit operateswith a minimum of external components, andprovides an additional uncommitted driver.

The PM stepper motor is controlled by the in-tegral step logic. To step the load from one posi-tion to the next, the STEP INPUT is pulleddown to a logic low for at least 1 MS, then allow-ed to return to a logic high. The step logic isactivated on the positive-going edge, which inturn activates one of four output sink drivers.The DIRECTION CONTROL determines thesequence of states (A-B-C-D, or A-D-C-B).

OUTPUTÊNAÔlËl 1

13)TIME/OUTMONOSTABLE

11 MONOSTABLER C

9] STEPENABLE

owe. m. A - i u l e «

In the full-step mode the MONOSTABLE RCtiming pin is tied to Vcc» making states B and Dstationary states. A separate input pulse is re-quired to move through each of the four outputstates.

The UCN-4202A will also perform a double-step function. In the double-step mode, states Band D are transition states with duration deter-mined by the MONOSTABLE RC timing. Im-proved motor torque is obtained at double thenominal motor step angle, and motor stability isimproved for high step rates.

Higher current ratings, or bipolar operationcan be obtained by using the UCN-4202A as alogic translator to drive discrete high-powertransistors or the Sprague UDN-2949Z Half-Bridge Motor Driver.

357

UCN-4202A STEPPER MOTOR TRANSLATOR/DRIVER

ABSOLUTE MAXIMUM RATINGSat TA = +25°C

Supply Voltage, Vcc

V«(P in7)Output Voltage, VCEInput Voltage, VINOutput Sink Current, IQUT

70V20V20V

7 0 V600mA

Power Dissipation, Pß(0ne Driver)(Total Package)

Operating Temperature Range, TAStorage Temperature Range, TS•Derate 16 6 mW/°C above + 25°C

0 8 W2 0 W *

-20°Cto + 85°C-55°Cto+150°C

ELECTRICAL CHARACTERISTICS at TA = +25°C/ VCc = +5.0 V unless otherwise noted

CharacteristicSupply Current

Symbol

iceTest Conditions2 Drivers ON

LimitsMm Max

85

UnitsmA

TTL Input» (pint 1, 9, and 15). TTL Outputs (pint 13 and 14)

High Level Input VoltageLow Level Input VoltageHigh-Level Input CurrentLow-Level Input CurrentInput Clamp VoltageHigh Level Output VoltageLow-Level Output VoltageShort-Circuit Output Current

V|N(1)

V|N(0)

'lN(l)

I|N(0)

'lN(CLMP)VOUI(1)VOUT(0)

'OUT(SC)

VCC = * 5VVCC = 5 5 VVcc = 5 5 V, V,,, = 2 4 VVcc = 5 5 V, V,« = 0 4 VI|N = -12 mAVcc = * 5 V, IOUI = 80 ^Vcc = 4 5 V, lour = 3 2 mAVCC = 5 5 V

2 00 840

-16-15

2 40 438

VV

MAmAVVV

mA

Second Stop Monostable RC Input (pin 11)

Time ConstantReset VoltageReset Current

IRCVMR•MR

R = 200 ko, I,N = 25 nAVIN = 20V

095 1350

40

s/RCmV

MA

Schmitt Trigger Inputs (pins 10 and 12)

Threshold Voltage

HysteresisHigh Level Input Current

Low Level Input CurrentInput Clamp Voltage

VT+VT-AVT

'lN(l)

hN(0)V|N(CLMP)

Vcc = * 5 V, V,,, = 2 4 V, TA == 25°CVcc = 4 5 V, V,« = 2 4 V, TA = 70°CVcc = 5 5 V, VIN = 0 4 VI,N = -12 mA

13 2106 1 10 2

5 040

-16-15

VVV

MA^AmA

V

Op*n Collector Outputs (pins 2, 3, 4, 5, and 6)

Output Leakage Current

Output Saturation Voltage

Output Sustaining VoltageTurn-On DelayTurn-Off DelayClamp Diode Leakage CurrentClamp Diode Forward Voltage

'CEX

VcE(SAT)

VCE(SUS)

tpdfl

4pdlIRVF

Vcc = 5 5 V, K = Open, VOUT = 20 V, TA = 25°CYcc = 5 5 V, K = Open, VOUT = 20 V, TA = 70°CVcc = 4 5 V, IOUT = 300 mAVcc = 4 5 V, IOUT - 400 mAVcc = 4 5 V, IOUT - 500 mAIOUT = 30 mA, t£= 300 ^s, Duty Cycle<2%0 5 Em (pm 10) to 0 5 Eout

0 5 E,n (pin 10) to 0 5 Eout

VR = 20 VIF = 500 mA

50010500750900

151010503 0

MAmAmVmVmV

VMS

MSMAV

358

UCN-4202A STEPPER MOTOR TRANSLATOR/DRIVER

RECOMMENDED OPERATING CONDITIONS

CharacteristicSupply Voltage, Vcc

VKOutput Voltage, VCE

Output Sink Current, IQUTOperating Temperature, TA

Mm.

4 5

-

-

10

Typ.

5012

-

-25

Max

5.513.5

13.550055

Units

VV

VmA

°C

No ConnectionTo UncommittedDriver (PIN 2)

= 5 ov

= 12V

05 10 15 20 25 30 35MOTOR TIME CONSTANT L/R

IN ms

45 50

nur, NO A n. 1

MAXIMUM COLLECTOR CURRENT AS A FUNCTION OFMOTOR TIME CONSTANT AND STEP RATE

Notes. 1. Values shown take into account static d-c losses (VSAT'OUT and Vcc'cc)as we" as

switching losses induced by inductive flyback through the clamp diodes withVK = 12 volts. Maximum package power dissipation is assumed to be 1.33watts at +70°C. Higher package power dissipation may be obtained at loweroperating temperatures.

2 Use of external discrete flyback diodes will eliminate power dissipationresulting from switching losses and will allow the full 500 mA outputcapability (Output A, B, C, or D and the Driver Output) under all conditions.

359

UCN-4202A STEPPER MOTOR TRANSLATOR/DRIVER

FUNCTIONAL DESCRIPTION

Pow«r-On R«s«tAn internal RS flip-flop sets the Output A

"ON" with the initial application of power.This state occurs approximately 30 /^s after thelogic supply voltage reaches 4 volts with supplyrise times of up to 10 ms/V. Once reset, the cir-cuit functions according to the logic input condi-tions.Step Enabl»

Pin 9 (Step Enable) must be held high toenable the step pulses for advancing the motorto reach the translator logic clock circuits. Pull-ing this pin low inhibits the translator logic.Stop Input

Pin 10 (Step Input) is normally high. The logicwill advance one position on the positive transi-tion after the input has been pulled low for atleast 1 ps. The Step Input current specification iscompatible with NMOS and CMOS.Direction Control

The direction of output rotation is determinedby the logic level at pin 12. If the input is heldhigh the rotation is A-D-C-B; if pulled low therotation is A-B-C-D. This input is also NMOSand CMOS compatible.

Output Enabl*

Outputs A through D are inhibited (all out-puts "OFF") when pin l(Output Enable) is athigh level. This condition creates a potential forwire-ORing of device outputs, or other potentialcontrol functions such as chopping or bi-leveldrive.

Transient Suppression

All five power outputs are diode protectedagainst inductive transients. However, Zenerdiode or resistor "flyback" voltage techniquesare not allowed.

Full-Step /Double-StepFull-Step operation is the most commonly

used drive technique. The UCN-4202A iscapable of unipolar drive without external activedevices, either in a full-step mode (pin 11Monostable RC tied high), or in a double-stepmode (pin 11 connected to RC timing). Thedouble-step mode provides improved torquecharacteristics, while the specified angular incre-ment is doubled.

STEP ENABLE -»[ I«- 1/iS Mil

STEP INPUT

DIRECTION CONTROL

OUTPUT A

OUTPUT B

OUTPUT C

OUTPUT D | 11 5ms->| \^ I_J~Nom

TIME/OUTMONOSTABLE

MONOSTABLER/C

I)-". Nil A-11,1)16

TIMING CONDITIONS(Double-Step Mod«)

Note: State B and State D output pulse duration is typically 11.5ms when R - 510 kQ and C - 0.02 F.

360

UCN-4202A STEPPER MOTOR TRANSLATOR/DRIVER

TYPICAL STEPPER MOTORS

ManufacturerEastern AirDevices

SigmaInstruments

North AmericanPhillipsSuperiorElectric

Mode!LA23ACK-2LA23ACY-1LA34ADK-618-2013D24-F3218-2013D48-F3220-2220D200-F23K82701-P2K83701-P2M061-FO-301

L/R1.4 ms1.2 ms2.6 ms1.5 ms1.5 ms1.5 ms1.5 ms1.5 ms0.8 ms

TypicalRatings

440 mA/12V440 mA/12V530 mA/14V340 mA/12V340 mA/12V500 mA/12V330 mA/12V330 mA/12V440 mA/12V

StepAngle

1.8°7.5°1.8°15°

7.5°1.8°7.5°15°1.8°

TYPICAL APPLICATIONS

OUTPUT-ENABLE

•H2V

o+5V

DIRECTIONCONTROL

«STEP INPUT«STEP ENABLE

DUG. NO. A-11 .187

L/R DRIVE CIRCUITUsed to Drive A 12-Volt 500 mA

Unipolar Stepper Motor (Double-Step Mode)

361

UCN-4202A STEPPER MOTOR TRANSLATOR/DRIVER

TYPICAL APPLICATIONS

UDN-2949Z UDN-2949Z UDN-2949Z UDN-2949Z

STEPPER MOTORBIPOLAR BRIDGEDRIVE CIRCUIT(Full-Step Mod«)

DIRECTIONCONTROL

STEP INPUT

STEP ENABLE

DWG. NO. A-11,188

362

UCN-4202A STEPPER MOTOR TRANSLATOR/DRIVER

TYPICAL APPLICATIONS

o +15VL/R DRIVE CIRCUITUsing Four PNP Power TransistorsTo Drive Unipolar Stepper Motors(Double-Step Mode)

STEP INPUT

STEP ENABLE

DUG. NO. A-11,189

-15 V

UON-2949Z UON-2949Z

A-C MOTOR DRIVE CIRCUIT

363

UCN-4401A and UCN-4801A BiMOS LATCH/DRIVERS

UCN-4401A and UCN-4801ABiMOS LATCH/DRIVERS

FEATURESHigh-Voltage, High-Current OutputsOutput Transient ProtectionCMOS, PMOS, NMOS, TTL Compatible InputsInternal Pull-Down ResistorsLow-Power CMOS Latches

'T'HESE high-voltage, high-current latch/drivers-*- are comprised of four or eight CMOS datalatches, a bipolar Darlington transistor driver foreach latch, and CMOS control circuitry for thecommon CLEAR, STROBE, and OUTPUT ENA-BLE functions. The bipolar/MOS combination pro-vides an extremely low-power latch with maximuminterface flexibility. The UCN-4401A contains fourlatch/drivers while the UCN4801A contains eightlatch/drivers.

The CMOS inputs are compatible with standardCMOS, PMOS, and NMOS circuits. TTL or DTLcircuits may require the use of appropriate pull-upresistors. The bipolar outputs are suitable for usewith relays, solenoids, stepping motors, LED orincandescent displays, and other high-power loads.

Both units feature open-collector outputs and in-tegral diodes for inductive load transient suppres-sion. The output transistors are capable of sinking500 mA and will sustain at least 50 V in the OFFstate. Because of limitations on package power dis-sipation, the simultaneous operation of all drivers atmaximum rated current can only be accomplished bya reduction in duty cycle. Outputs may be paralleledfor higher load current capability.

The UCN-4401A 4-latch device is furnished in astandard 14-pin dual in-line plastic package. TheUCN-4801A 8-latch device is furnished in a 22-pindual in-line plastic package with lead centers on0.400" (10.16 mm) spacing. All outputs are pinnedopposite their respective inputs to simplify circuitboard layout.

TYPE UCN-4401 A

GROUND

DUG NO A-10.498A

TYPE UCN-4M1A

COMMON MOS TYP)CAL MOS LATCH TYPICAL IlKXAH DRIVER

FUNCTIONAL BLOCK DIAGRAM

364

UCN-4401A and UCN-4801A BiMOS LATCH/DRIVERS

ABSOLUTE MAXIMUM RATINGS

Output Voltage, Va............................................................................................50 VSupply Voltage, VDD............................................................................................ 18 VInput Voltage Range, V I N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to V^ +0.3 VContinuous Collector Current, lc..............................................................................500 mAPackage Power Dissipation, PD (UCN-4401A)... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6/ W*

(UCN-4SOIA).... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 W**Operating Ambient Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°CStorage Temperature Range, Ts..................................................................... -55°C to +125°C

•Derate at the rate ol 16.7 mW/°C above TA - 25°C."Derate at the rate of 20 mW/°C above TA = 25°C.

ELECTRICAL CHARACTERISTICS at T» = +25°C, VDD = 5 V, V« = 0 V (unless otherwise specified)

CharacteristicOutput Leakage Current

Collector-EmitterSaturation Voltage

Input Voltage

Input Resistance

Supply Current

Clamp DiodeLeakage CurrentClamp DiodeForward Voltage

Symbol'ctx

VCEISM]

VINIOIVINID

RIN

IDDION)(Each stage)

loCKOFf)

I.VF

Test ConditionsV C E = 50V,T A = +25°CVCE = 50V,TA = +70°Clc = 100 mAlc = 200 mAlc = 350 mA, VDD = 7.0V

VDD = 15 VVDD = 10 VVDD = 5.0V (See note)VD D= 15VVDD = 10 VVDD = 5.0VVD D= 15VV«,= 10 VVDD = 5.0VAll Drivers OFF, All Inputs = 0 VV» = 50 V, TA = +25°CV, = 50 V, TA = +70°CIF = 350 mA

LMin._.._————13.58.53.5505050———-———

Typ.——0.91.11.3————2003006001.00.90.750——1.7

mitsMax.

501001.11.31.61.0--——--2.01.71.010050

1002.0

Units^AMAVVVVVVVknknk umAmAmAMAMAxAV

'Note: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to insure the minimum logic "I"

TRUTH TABLE

INN

01XXXX

STROBE11XX00

CLEAR001X00

OUTPUTENABLE

00X100

OUTNt-1

XXXXONOFF

tOFFONOFFOFFONOFF

Information present at an input is transferred to itslatch when the STROBE is high. A high CLEARinput will set all latches to the output OFF conditionregardless of the data or STROBE input levels. Ahigh OUTPUT ENABLE will set all outputs to theOFF condition regardless of any other input condi-tions. When the OUTPUT ENABLE is low, theoutputs depend on the state of their respectivelatches.

X = irrelevantt-1 = previous output statet = present output state

365

UCN-440IÂ and UCN-4801A BiMOS LATCH/DRIVERS

CUA«

TIMING CONDITIONS(Logic Levels are VDO and Vss>

IM; NO, ».-it),»95*

A. Minimum data active time before strobe enabled (data set-up t ime). . . . . . . . . . . . . . . . . . 100 nsB. Minimum data active time after strobe disabled (data hold time) .................... 100 nsC. Minimum strobe pulse width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 nsD. Typical time between strobe activation and output on to off transition . . . . . . . . . . . . . . . .500 nsE. Typical time between strobe activation and output off to on transition ................ 500 nsF. Minimum clear pulse width.................................................300 nsG. Minimum data pulse width ................................................. 500 ns

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UMBER Of OUTFUONOUCTINOMULTANEOUSLY

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PERCENT DUTY CYCLE

ÇA UTION: Sprogue CMOS devices feature input static protection but are still susceptible to damage when ex-posed to extremely high static electrical charges.

366

UGN-30T9T, UGS-3019T

TYPE UGN-3019T and UGS-3019T SOLID-STATELOW-COST 'HALL EFFECT' DIGITAL SWITCHES

FEATURES:• Operate from 4 5 V to 16V d-c power source• Operable with a small permanent magnet• High Reliability — eliminates contact wear contact bounce;

no moving parts• Small size• Constant amplitude output• Output compatible with all digital logic families

TYPE UGN-3019T and UGS-3019T are low-cost magnetically-activated electronic switches

utilizing the Hall effect for sensing a magnetic field.Each circuit consists of a voltage regulator, Hall cell,signal amplifier, Schmitt trigger, and current sinkingoutput stage integrated into a monolithic silicon chip.

The circuit output can be interfaced directly withbipolar or MOS logic circuits. The on-boardregulator insures stable operation over a wide rangeof supply voltages. Operation over an extendedtemperature range is made possible by the carefulmatching of components which can be doneeconomically only on a monolithic chip.

These devices are packaged in the 3-pin single out-put plastic "T" package.

The UGN-3019T was originally introduced as theULN-3006T.

GROUND

0«9 NO A.11,002

FUNCTIONAL BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGSPower Supply, VccMagnetic Flux Density, BOutput "OFF' Voltage, VOUT(0mOutput "ON" Current, ISNKStorage Temperature Range, TsOperating Temperature Range, TA

UGS-3019TUGN-3019T

20VUnlimited

20V50mA

-65°Cto +150°C

-40°C to +150°C0°C to +70°C

ELECTRICAL CHARACTERISTICS: Vcc = 4.5 V to 16 VOC, TA = 25°C

CharacteristicMagnetic Flux Density

"Operate Point""Release Point"

HysteresisOutput Saturation VoltageOutput Leakage CurrentSupply Current

Output Rise Time

Output Fall Time

Symbol

BwBRP

BH

VSAT

'OFT

1«

t,

t.

Test Conditions

B ^ 500 Gauss, lsw( = 15 mAB s 100 Gauss, Vout = 16VVa = 5 V, output open.Vcc = 12 V, output openV,, = 12 V, RL = 820 n,C;"=20pFVc, = 12 V, RL = 820 n,Ct"= 20 pF

LimitsMm Typ. Max

— 420 500100 300 —

50 120 —— 150 400— 1 20— 7 9— 12 16— 15 —

— 100 —

Units

GaussGaussGauss

mVAiAmAmAns

ns

Not«- Magnetic ilux,density is measured at most sensitive area of device Thu area is located 0032" =0002 (081 ±005 mm) below the branded face of the pack«(<

367

UGN-3019T, UGS-3019T

Catalog Numbering System

UG M - 3019 T

T •PACKAGE STYLE. T . PLASTIC 3-LEAD SIP

•DEVICE NUMBER. 3000 - 3199 - DIGITAL, SINGLE OUTPUT————OPERATING TEMPERATURE RANGE,

N . 0°C TO +706CS = _40°C TO +150°C

•SEMICONDUCTOR FAMILY. UG - HALL EFFECT DEVICES

PACKAGE INFORMATION

0.02S

«O.OM «.0.178 -0.000 _

MAGNETSOUTH

0.0*0 ±0.001

J

4O.M

'

t ,j «0.10 _— *•" -o.oo •*

... *-;*;-" )_i

it

2.03*0.03i

MAGNETSOOTH r

»0.0020.176 -0.000 . . . . .

0.07»

O.SOO MIN.

l:-Jo.osoU-100 -w »- O.OIS iO

NOTES: 1. All difMXion or« .n inch«. ..,«„2. Moll cell ijcwmilly loeot«. °*3- »«• •-»'««»

.O.Oi-0.00

2.0

12.70 MIN.

l

II2.5« _»j

! Î 3NOTES: l. All dtmanBiom or« in millimalri

2. Holt cell ii c.fmoüy locsnxl.

0.38 SC

D»«, he. »-976U tf

GUIDE TO INSTALLATION

1. All Hall effect integrated circuits aresusceptible to mechanical stress effects. Cautionshould be exercised to minimize the applicationof stress to the leads or the epoxy package.

2. To prevent permanent damage to the Hallcell I.C., heat sink the leads during handsoldering. For wave soldering, the pan shouldnot experience more than 230°C for more than 5seconds and no closer than 0.125" to the epoxypackage.

368

OPERATIONThe output transistors are normally "off" when

the magnetic field perpendicular to the surface of thechip is below the threshold or "operate point."When the field exceeds the "operate point," eachoutput transistor switches "on" and is capable ofsinking 15 mA of current. Selections to 30 mA areavailable.

" The output transistors switch "off" when themagnetic field is reduced beiow the "release point"(which is less than the "operate point"). This isillustrated graphically in the transfer characteristicscurve. The hysteresis characteristic provides for un-ambiguous or non-oscillatory switching.

The simplest form of magnet which will operatethe Mali effect digital switch is a bar magnet asshown. Other methods are possible.

In the illustration, the magnet's axis is on thecenter line of the packaged device and the magnet ismoved toward and away from the device. Also, notethe orientation of the magnet's south pole in relationto the branded surface of the package.

The magnetic flux density is indicated for themost sensitive area of the device. This area is cen-trally located and 0.032" ±0.002" (0.81 ±0.05mm) below the branded surface of the package.

For reference purposes, both an Alnico VTII mag-net, 0.212" (5.38 mm) in diameter and 0.187"(4.75 mm) long and a samarium cobalt magnet,0.100" (2.54 mm) square and 0.040" (1.02 mm)thick, are approximately 1200 gauss at its surface.

The flux density decays at a high rate as thedistance from a pole increases.

As an example, using the Alnico VIII magnetreferenced above in good alignment and the polesurface in contact with the branded surface of thepackage, the flux density at the active Hall sensingarea of the device would be approximately 850gauss (0.032" below the package surface).

The flux density would drop to approximately 600gauss with an air-gap between the package and themagnet of 0.031" (0.79 mm).

Switching point variations with temperatureshould be considered in applications covering awide temperature range.

For additional information on Hall Effect deviceapplications, see Sprague Engineering Bulletin No.27701, "Hall Effect Applications Guide."

UGN-30T9T, ÜGS-30T9T

o>

4

Ï3 J

'OUTOFF

«.P.

ON

0 100 200 300 «00 500 »30MAGNETIC flUX DENSITY IN GAUSS

On«. 10. A- Ï015C

TRANSFER CHARACTERISTICS SHOWING HYSTERESIS

BASIC 'HEAD-ON' MODE OF OPERATION

untu

SE »SOD1 — .—— r-

).........INRMAlEftCIACUK CHIP

IMNOCO f*C£ Of MC««

lil

U u •SENSOR CENTER LOCATION

-50 -25 0 +25 »50 »75 »100 »125 *150TEMPERATURE IN °C _

D««î so 1-lI .DC«

SWITCHINS POINT VARIATION WITH TEMPERATURE

369