A

SEMINAR REPORT

ON

SURFACE CONDUCTION ELECTRON EMISSION DISPLAY ( SED)

SUBMITTED BY: SUBMITTED TO:

Avinash Rawal Dr. Rajesh Bhadada

B.E. Final Year

E.No. 07/05706

Roll No. 2388

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

M.B.M. ENGINEERING COLLEGE

DECLARATON BY THE STUDENT:

I hereby declare that the contents present in this report are genuine and are not copied from anywhere.

Avinash Rawal Date:

B.E. Final Year (2010-2011)

Electronics and Communication Engineering

E. no. E/07/5706

Fac. No. 07/15427

Roll No. 2388

M.B.M. Engineering College

Jodhpur

CERTIFICATE

This is to certify that Avinash Rawal , E no. E/07/05706 (Roll No 2388) of B.E. final Year (Electronics and Communication Engineering) has prepared this seminar report titled surface conduction electron emission display (SED) under my guidance and supervision.

DATE Dr. Rajesh Bhadada

Professor

Dept. of Electronics & Comm.

M.B.M. Engg. College

Jodhpur

ACKNOWLEDGEMENT

I would like to express my heartfelt thanks to Dr. Rajesh Bhadada , Associate Professor, Department of Electronics and Communication Engineering for their invaluable guidance during the course of this seminar. His scholarly guidance, encouragement and affectionate pressure helped me in completing this seminar report.I also extend my sincere thanks to all other members of the faculty of Electronics and Communication Engineering Department and my friends for their co-operation and encouragement.Last, but not at all the least, I thank God, the almighty for his blessings in the course of this work.

AVINASH RAWAL

CONTENTS:-

1. INTRODUCTION ……………………………………...1

2. WORKING OF SED….………………………………....3

2.1 PRINCIPLE OF WORKING……………………..3

2.2 COMPARISON…………………………………..7

3. FABRICATION PROCESS…………………………….8

4.1 METHOD OF CALCULATION………………..10

4.2 EFFECT OF PROCESS VARIATION ON SEC.12

4. CONCLUSION………………………………………...23

5. REFERENCES………………………………………...24

1. INTRODUCTION :-

1.1 Surface conduction Electron emitter Display(SED)

The SED technology has been developing since 1987. The flat panel display technology that employs surface conduction electron emitters for every individual display pixel can be referred to as the Surface-conduction Electron-emitter Display (SED)[1]. Though the technology differs, the basic theory that the emitted electrons can excite a phosphor coating on the display panel seems to be the bottom line for both the SED display technology and the traditional cathode ray tube (CRT) televisions. When bombarded by moderate voltages (tens of volts), the electrons tunnel across a thin slit in the surface conduction electron emitter apparatus. Some of these electrons are then scattered at the receiving pole and are accelerated towards the display surface, between the display panel and the surface conduction electron emitter apparatus, by a large voltage gradient (tens of kV) as these electrons pass the electric poles across the thin slit. These emitted electrons can then excite the phosphor coating on the display panel and the image follows.The main advantage of SED’s compared with LCD’s and CRT’s is that it can provide with a best mix of both the technologies. The SED can combine the slim form factor of LCD’s with the superior contrast ratios, exceptional response time and can give the better picture quality of the CRT’s. The SED’s also provides with more brightness, color performance, viewing angles and also consumes very less power. More over ,the SED’s do not require a deflection system for the electron beam, which has in

turn helped the manufacturer to create a display design, that is only few inches thick but still light enough to be hung from the wall. All the above properties has consequently helped the manufacturer to enlarge the size of the display panel just by increasing the number of electron emitters relative to the necessary number of pixels required. The technology is still developing and we can expect further breakthrough on the research.

2. WORKING OF SED :-

2.1 PRINCIPLE OF SED WORKING :-

SED is a display device includes an electron-emitting device which is a laminate of an insulating layer and a pair of opposing electrodes formed on a planar substrate. A portion of the insulating layer is between the electrodes and contains fine Particles of an electron emitting substance, that portion acting as an electron emitting region. Electrons are emitted from the electron emission region by applying a voltage to the electrodes, thereby stimulating a phosphorous to emit light (Fig. 2.1)[3]. An SED-TV creates a picture in much the same way. It's essentially a flat panel television that uses millions of CRTs instead of one electron gun. These miniature CRTs are called Surface Conducting Electron emitters (SCEs). A set has three SCEs for every pixel -- one each for Red, Green and Blue. A widescreen, high definition set can have more than 6 million SCEs. An SED-TV has millions of these SCEs arranged in a matrix, and each one controls the Red, Green or Blue aspect of one pixel of the picture. Rather than directing electrons to create the image one row at a time, the matrix activates all the SCEs needed to create the picture virtually simultaneously (Fig.2.2)[4]. As with a CRT set, the inside of an SED-TV is a vacuum. All of the SCEs are on one side of the vacuum, and the phosphor-coated screen is on the other. The screen has a positive electrical charge, so it attracts the electrons from the SCEs. When bombarded by moderate voltages (tens of volts), the electrons tunnel across a thin slit in the surface conduction electron emitter apparatus. Some of these electrons are then scattered at

Fig. 2.1 SED WORKING. [3]

the receiving pole and are accelerated towards the display surface ,between the display panel and the surface conduction electron emitter apparatus, by a large voltage gradient (tens of kV) as these electrons pass the electric poles across the thin slit. These emitted electrons can then excite the phosphor coating on the display panel and the image follows.

Fig. 2.2 INTERNAL CONNECTION.[4]

When they reach the screen, the electrons pass through a very thin layer of aluminum. They hit the phosphors, which then emit red, green or blue light. Our eyes and brain combine these glowing dots to create a picture (Fig. 2.3)[3]. Any part of the

screen that's not used to create pixels is black, which gives the picture better contrast. When the SED-TV receives a signal, itA. Decodes the signalB. Decides what to do with the red, green and blue aspect of each pixelC. Activates the necessary SCEs, which generate electrons that fly through the vacuum to the screen When the electrons hit the phosphors, those pixels glow, and your brain combines them to form a cohesive picture. The pictures change at a rate that allows you to perceive them as moving. This process happens almost instantaneously, and the set can create a picture sixty times per second. Unlike a CRT, it doesn't have to interlace the picture by painting only every other line. It creates the entire picture every time.

Fig. 2.3 INTERNAL STRUCTURE. [4]

2.2 COMPARISON :-

The only constant that we can count on is change. Nowhere is this more accurate than with display technologies. All manufactures are trying to reduce their manufacturing cost profiles by introducing new techniques. SED technology, or surface conduction electron-emitter displays. CRTs are typically as wide as they are deep. CRTs can have image challenges around the far edges of the picture tube. But their thickness is much more. Plasma TV shows close to black colour, gray levels actually showing up. This means they are actually dark gray – not black. Plasma has been getting better in this regard but still has a way to go to match as CRT. The pixels in a Plasma panel are Inherently digital devices that have only two states, on and off. A Plasma produces gradations of light intensity by changing the rate at which each pixel produces its own series of very-short, equal-intensity flashes. LCD latency has been a problem with television pictures with an actual 16ms speed needed in order to keep up with a 60Hz screen update. Also, due to LCD's highly directional light, it has a limited angle of view and tends to become too dim to view off axis, which can limit seating arrangements. LCD generally suffers from the same black level issues and solarization, otherwise known as false contouring, that Plasma does.

3. FABRICATION PROCEDURE:-

Fig. 3.1 schematically shows the structure of the SCE device. P-type (1 0 0) Si wafer is used as the substrate. A 150-nm-thick Sio2 layer is first thermally grown on the Si substrate. The Ti layer with 5 nm thick is electron-beam-evaporation (e-beam) deposited on the oxide as an adhesion layer for the subsequently

Fig. 3.1 Schematic plot of SCE structure and cross section of SCE in x–z plane.The thicknesses of this device are shown in the bottom-right corner.[1]

Fig. 3.2 Cross-sectional plots along the x–z plane. Four types of the SCEs caused by process variation are considered in this study. The first plot shows the normal one of the SCE.[1]

e-beam deposited Pt thin film with a thickness of 10 nm. Pattering of the Pt/Ti line electrodes with a width of 80 μm is photolithographically performed using liftoff method. The Pdthin film 30 nm thick is then e-beam deposited on the Pt/Ti bottom electrode and the liftoff method is also used to pattern the Pd electrode line 50 μm long and 3 μm wide. A nano gap with a separation of 90 nm on the Pd strip is then produced by the FIB. Electron emission characteristics in the nano gap are studied using a dc voltage power supply. The measurement is carried out under a vacuum condition of 1.0 × 10-6

torr. This fabrication method is easily reproducible and compatible with contemporary IC technology. The width of nano gap of original type can be readily controlled by tuning the ion beam energy. However, the four types of nano gaps, shown in (Fig. 3.2), could be induced by the process variations in FIB operations or

predefined by other fabrication methods. The edges of emitter are smooth and straight according to the SEM observation. The type 1 may be formed by adjusting the direction of FIB with a proper angle. Type 2 is the inverse of type 1 by changing the opposite direction of the FIB in type 1. Type 3 can be fabricated by using advanced microfabrication technology based on FIB, dry etching, and thermal oxidation. Type 4 by using the same technique FIB.[1]

3.1 METHOD OF CALCULATION

We first formulate a calibration model with the experimental data by using the simulation program that has been developed to calculate the emission efficiency of different SCEs. The electromagnetic PIC codes are performed in the numerical simulation, Starting from a specified initial state, we simulate electrostatic fields as its evolution in time. We then perform a time integration of Faraday’s law, Ampere’s law, and the relativistic Lorentz equation

subject to constraints provided by Gauss’s law and the rule ofdivergence of B

∇ · E = ρ/εand ∇ · B = 0

We notice that E and B are the electric and magnetic fields, x isthe position of charge particle, and J and ρ are the current density and charge density resulting from charge particles. The full set of Maxwell’s time-dependent equations is simultaneously solved to obtain electromagnetic fields. Similarly, the Lorentz force equation is solved to obtain relativistic particle trajectories. In addition, the electromagnetic fields are advanced in time at each time step. The charged particles are moved according to the Lorentz equation using the fields advanced in each time step. The weighted charge density and current density at the grids are subsequently calculated. The obtained charge density and current density are successively used as sources in the 3-D Maxwell equations for advancing the electromagnetic fields. These steps are repeated for each time step until the specified number of time steps is reached. We notice that the space–charge effects are automatically included in the simulation algorithms. The effect of space–charge on field emission was discussed by Stern. This 3-D FDTD-PIC method thus approaches to self-consistent simulation of the electromagnetic fields and charged particles. In the field emission process, the electron emission is modeled by the F-N equation

SI unit. The emission current density is determined by the equation according to the local electric field, the work function of emitter material, and the geometric factors. We notice that, in the entire simulation, all dimensions of physical quantities are the same with the experimental settings.

3.2 EFFECT OF PROCESS VARIATION ON FIELD EMISSION IN SCE :-

For exploring the effects of the gate voltages and the inclined angle of nano gaps upon the emission current, we analyze the electron trajectories and the electric fields simultaneously for the constant angle of inclination, the computed I–V characteristics with various nano gap emitters compared with the experimental data of the nano gap of original type are shown in Fig. When the gate voltage varies from 10 to 100 V, the four kinds of symbols indicate the simulated data of four types and the line represents the experimental data of original type. It is found, shown in Fig. 3.3 , that the turn-on voltage of 60 V is obtained at an emission current of 70 μA for nano gap of 90 nm wide. However, there is a significant effect upon the electron emission of the inclination of surface and gate voltage. When the gate voltage is 60 V, we find that the emission current of type 1 and type 2 are larger than the

emission current of the original type, but as the gate voltage is raised to 100 V, only the emission current of type 1 is larger than the emission current of the original type.

Fig 3.3 I-V characteristics of the SCE device with different types caused by process variation.[1]

A very high emission current of 0.3 mA is estimated at the gate voltage of 80 V for the emitter of 90 nm wide. When the gate voltage is fixed at 60Vand the inclined angle is 60◦, the electric field contours with different types of nano gaps are shown in Fig. 3.4. The local electric field near the nano gap, shown in Fig. 3.4(b), is higher than Fig. 3.4(a) and (c)–(e). Therefore, the emission current in Fig. 3.4(b) should be higher than that of Fig. 3.4(a) and (c)–(e). This structure of type 1 that has a tip around the corner on the left electrode implies that it can produce high

electric fields around the emitter apex, and generate high emission current. Fig. 3.4 compares the electron emission current with angle of inclination under two different gate voltages. We find that the emission current attains the maximum in the type 1 and it is always larger than the value when the surface is vertical .When the angle is smaller than 90◦,

the emission efficiency has no improvement in the type 3 and type 4. This phenomenon is caused by the electric fields are not concentrated on the emitted surface and the distributed electric field broadens the potential barrier at the metal–vacuum interface for the electrons to have a less chance of tunneling from the solid into vacuum. It is obvious that the type 3 and type 4 are not seriously influenced by the inclination of surface, but the type 1 can improve the emission efficiency when the angle is smaller. In addition, decreasing the inclined angle or the gate voltage can enhance the emission current in type 2.High brightness and long lifetime are the main targets of emission material investigations for scientific instrument applications, but high current density and low power consumption are the guiding rules for display applications. Hence, we here explored the emission characteristics caused by different material work functions with respect to the nano gap of original type because changes of the local work functions lead to field emission current fluctuation. Therefore, we propose that the morphology of nano gap edge can be greatly modified by the plasma treatment. After a hydrogen plasma treatment on the SCE device, the edges become very rough due to severe ion bombardment. The surface-conducting properties of the SCE can be great of progress after the hydrogen plasma treatment. Fig. 3.5 shows the field emission I–V curves for the Pd emitter with a 90 nm nano gap after the plasma treatment under various

Fig. 3.4 Contour plots of electric fields (a) Original type (b) type 1 (c)type 2 (d) type3 (e) type 4 width of nano gap app. 90 nm,gate voltage 60 and angle of inclination 600.[1]

treatment times. We can find the emission current increase after this treatment. Here, the turn-on voltage is defined as the gate voltage at which the F-N plot began to show the linear behaviour. We can find that the turn-on voltages near 80 and 70 V are observed in the 90 nm nano gap with no hydrogen plasma treatment and hydrogen plasma treatment for 1 min, respectively. After the hydrogen plasma treatment for 3 min, the turn-on voltage dropped from 80 to 30 V. From the observations of Fig. 3.5, the emission current indeed convinces the mechanism of F-N model. The significant reduction in the turn-on voltage after the hydrogen plasma treatment might be ascribed to the formation of a rugged nano gap edge and the decrease of the work function in the electron-emitting area. During the hydrogen plasma treatment, the Pd electrodes are subject to hydrogen ion bombardment leading to the formation of a rough surface on the Pd electrodes. The nano gap edges thus

Fig 3.5 I-V characteristics after hydrogen plasma treatment under various times. [1]

become rugged. Therefore, electric fields can concentrate around areas with sharp features resulting in the enhancement of field emission efficiency . In addition, the surfaces of Pd electrodes are hydrogenated during the plasma treatment forming Pd hydrides that have a smaller work function than the metallic Pd. The reduction in the work function of the emitter surface can effectively increase the field emission current and thereby decrease the turn-on voltage. Except the process variations on nano gap, controlling the roughness and the local work function at emission point are also important issues.

Fig 3.6 plot of the inclined angles of nano gap is 90nm. The gate voltage is (a) 60V.[1]

The anode voltage (Va ) and cathode voltage (Vd ) are fixed at 1960 and 40 V for all of the following calculations. We notice that the SCEs fabricated by HE method [1]-[2] under such bias

condition maintain enough voltage to turn on the emitter electrode based on our experimental characterization. The gap width and the tilted angle of SED, are two process variables to be examined for designing a high-performance SED device. We first find that the SED collects no current on the anode electrode if the separation width and the tilted angle of SCE nano gap are 147 nm and 100. The structure with an extremely tilted angle weakens the strength of electric field around the emitter, as shown in Fig. 3.7(a); from the electronic trajectory perspective, which is shown in Fig. 3.7(b), the emitted electrons under this configuration are strongly blocked by the geometry. For the case with a smaller separation width and a larger tilted angle, 0 nm and 80◦, for example, a large number of electrons are emitted from the emitters due to a strong electric field. The narrower gap width implies the stronger electric field. The electric field between the left and right emitter electrodes is strong enough to attract more electrons due to smaller gap width. However, more emitted electrons are attracted, and hence, move downward along the direction of the strong electric field

Fig 3.7 plot of (a) electric field and (b) electron trajectory.with 147 nm separation width and 100 tilted angle. [2]

around the tip of electric field. It results in more electrons beingabsorbed by the cathodes because the distribution of electric field is limited in a smaller region. Only very few emitted electrons could be collected by the anode. According to the earlier observations, we know that too narrow separation width or large tilted angle will decrease the collected current due to a strong electric field around the apex of cathodes. The most part of emitted electrons moves downward rapidly; consequently, the anode electrode could merely collect few electrons.

Fig 3.8 plot of (a) electric field and (b) electron trajectory.With 27nm separation width and 200 tilted angle [2]

For example, if we further decrease the tilted angle from 800 to 200 and increase the separation width of gap from 0 to 27 nm, the strength of electric field is reduced and the distribution of electric field becomes wider, as shown in Fig. 3.8(a). Comparedwith the SCE with 0 nm separation width and 800 tilted angle, the electric field reduction is about 60% due to a wider gap. However, the gap width is still narrow that could not prevent the emitted electrons from moving downward to be absorbed, as

shown in Fig. 3.8(b). Only fewer emitted electrons are attracted by the tip of electrode due to the weak electric field. Most of electrons are moving upward as they are attracted by the anode, and thus, result in large collected current, and a high efficiency of field emission could be expected. We know that an increased tilted angle can avoid significant reduction of the strength of electric field. For a wide gap width, only few electrons could be emitted from the electrode due to the weaker electric field. As the gap width is increased from 27 to 87 nm and the tilted angle is slightly increased from 20 to 40, the gap with the larger titled angle demonstrates that the distribution of electric field is wider and extends upward from the electrode, as shown in Fig. 3.9(a). Thus, more emitted electrons move upward.

Fig. 3.9 plot of (a) electric field and (b) electron trajectory.With 87nm separation width and 400 tilted angle.[2]

Compared with the case of 0 nm and 80, the electric field reduction is about 45%. The reduction of electric field is less than that for the case of 27 nm and 20. We could conclude that

the variation of titled angel is more sensitive than the variation of gap width in field emission. It is found that more emitted electrons move upward to the anode as the driving voltage is increased, as shown in Fig. 3.9(b). Consequently, there is a trade off between the separation width of gap and the tilted angle. According to the analyses given before, the collected and emitted currents are shown with respect to different separation width and tilted angle of SCE nano gap. By defining the efficiency as the collected current divided by the emitted current and considering the emitted current, which is greater than 1×10-

6A, where the electric field, emitted and collected currents, and efficiency for the interesting cases of 57 and 117 nm are listed in Table I. Most of emitted electrons enter into the oxide conduction band, which results in degradation of efficiency. It is then noted that the gap width and the tilted angle have an influence on the amount of electrons that enter the oxide. The results show that the explored structure with the range of the separation width from 57 to 117 nm and the larger tilted angle from 30 to 60 possess promising emission efficiency. To investigate the focus capability, we further examine the SCE structure with 80◦ tilted angle and 147 nm gap, which is out of the suggested range. We compare it with the SCE with30◦ tilted angle and 87 nm gap, where they have similar strength of electric fields, as shown in Fig. 3.10(a) and (b). The distribution of electric field for the case with 30◦ tilted angle and 87 nm gap is relatively small, and the emitted electrons can move upward and are localized centrally. However, the emitted electrons with a wider gap width spread out.

Fig. 3.10 plot of electric field for the case of structure with (a) 87nm gap and 300 tilted angle (b)147nm gap and 800 tilted angle. [2]

4. CONCLUSION:-

In this study, a single nano gap in the Pd strip electrode of a novel SCE structure by hydrogen absorption under high pressure treatment has been explored, where the field emission efficiency has been optimized by varying the separation width of gap and the tilted angle. The emitter with a small tilted angle limits those emitted electrons to move upward to the anode and reduces the collected current. Therefore, a fixed separation width of gap with a higher tilted angle has been examined. The high electric field gathered around the emitter tip induces a higher emission current. However, the high electric field around the emitter tip attracts more emitted electrons and reduces the collected current on the anode. On the other hand, a wide gap between two electrodes of cathode decreases the electric field and reduces the number of emitted electrons. Thus, a narrow space between two electrodes has been used to increase the electric field and emit a large number of electrons. The stronger electric field between two electrodes attracts electrons and reduces the collected current. For better field emission efficiency, the separation width of gap could be varied from 57 to 117 nm, and the range of tilted angle is within 30◦–60◦ for the SED under the specified bias condition. We are currently studying the field emission property of the novel nano gap fabricated by HE method with different material and morphology. Such investigation may produce higher emission current under lower supply voltage, and thus, it will benefit high-performance SED application.

5. REFERENCES :-

[1] IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 7, NO. 4, JULY 2008.

[2] IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 6 NOV. 2009

[3] www.electronics.howstuffworks.com

[4] www.howstuffworks.com