Studies of Radiation SEE Effects in NAND-Flash and DDR

Studies of Radiation SEE Effectsin NAND-Flash

and DDR Types of memories

ESTEC Technical Officers:Mr. Reno Harboe Sørensen (TEC-QCA)Mrs. Véronique Ferlet-Cavrois (TEC-QEC)

R&D Final Presentation DaysMarch, 28-29, 2011, ESTEC, Nordwijk

Institut für Datentechnik und Kommunikationsnetze, TU Braunschweig

K. Grürmann, D. Walter, M. Herrmann, F. Gliem

March, 29, 2011

Topics

1. 8-Gbit NAND-Flash (4k Blocks x 64 Pages x 4k byte x 8 bit)Samsung K9WBG08U1M, datecode: 3708, Micron MT29F8G08AAA-WP, datecode: 4208

• Angular Dependence of the Static SEU Cross Section

2. 2-Gbit DDR2 SDRAM (8 Banks x 32k rows x 256 columns x 4x8 bit)Micron MT47H256M8HG-37E, datecode: 0742, Elpida EDE2108ABSE-8G-E, datecode: 0811

• Thinning of DDR2 dies (300 ... 200 μm → 80 ... 60 μm)• SEU- and SEFI-Cross Section @ 125 MHz with DLL on

Studies of Radiation SEE Effectsin NAND-Flash and DDR Types of memories

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March, 29, 2011

Topics






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March, 29, 2011

Angular Dependence of the NAND-Flash SEU Cross Section


4

Motivation:Previous Heavy Ion tests exhibited substantially different SEU Cross Sections for 60° tilting around the long (x) and the short (y) die axis.

To sample the whole hemisphere a set up was implemented for DUT tilting around two orthogonal axes (azimuth angle θ: 0° – 360°, elevation angle ψ: 0° – 90°).

zy

e

xΘ

(short axis)

(long axis)

ψ

March, 29, 2011

Angular Dependence of the NAND-Flash Static SEU Cross Section, Micron


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Normalized SEU cross section, ψ ≤ 60°, Micron DUT

Normalized SEU cross section, ψ ≥ 60°, Micron DUT

• With increasing elevation angle (ψ), the polar diagram develops a dipole shape with a deep notch at Θ = 90° and Θ = 270°, i.e. for ion incidence along the short axis of the die. It remains within the normal incidence circle.

• For ψ ≥ 60°, the dipole shape remains, but the cross section increases along the long axis of the die (Θ = 0° and Θ = 180°), and exceeds the normal incidence circle by up to a factor of three.

-1.5

-1

-0.5

0

0.5

1

1.5

-1.5 -1 -0.5 0 0.5 1 1.5

Psi = 60°

Psi = 30°

Psi = 15°

Θ = 0°: long axis

Θ = 90°

Ar, LET = 10.1, ψ = 0°, σ_norm = 8.64 E-12 sqcm / bit

-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

3

-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3

Psi = 60°

Psi = 67.5°

Psi = 75°

Psi = 82.5°

Psi = 85°


Θ = 0°: long axis

Θ = 90°

March, 29, 2011

Angular Dependence of the NAND-Flash Static SEU Cross Section, Samsung


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Normalized SEU cross section, ψ = 60°..75°, Samsung DUT

Normalized SEU cross section, ψ ≥ 75°, Samsung DUT

• The polar diagrams of the Samsung device are qualitatively similar,but σ_norm = 9.15E-13 < 8.64E-12 (Micron)

• The tilt effect is much more significant. At grazing incidence, along the long axis of the die, the SEU cross section increases by more than a factor of ten.

-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

3

-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3

Psi = 60°Psi = 67.5°Psi = 75°


Θ = 0°: long axis

Θ = 90°

-15

-10

-5

0

5

10

15

-15 -10 -5 0 5 10 15

Psi = 75°Psi = 82.5°Psi = 85°


Θ = 0°: long axis

Θ = 90°

ψ < 60°not measured

March, 29, 2011

Angular Dependence of the NAND-Flash Static MBU Cross Section


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MBU to SEU ratio, Micron DUT MBU to SEU ratio, Samsung DUT

-1

-0,8

-0,6

-0,4

-0,2

0

0,2

0,4

0,6

0,8

1

-1 -0,8 -0,6 -0,4 -0,2 0 0,2 0,4 0,6 0,8 1

Psi = 60°Psi = 75°Psi = 82.5°Psi = 85°

Θ = 0°

Θ = 90°

Ar, LET = 10.1 MC1 -1

-0,8

-0,6

-0,4

-0,2

0

0,2

0,4

0,6

0,8

1

-1 -0,8 -0,6 -0,4 -0,2 0 0,2 0,4 0,6 0,8 1

Psi = 60°Psi = 75°Psi = 82.5°Psi = 85°

Θ = 0°

Θ = 90°

Ar, LET = 10.1 SI4

• MBU (= Multi Bit Upset) clusters are defined by error address distances ≤ 6 in row and/or column direction.

• At normal incidence, the MBU/SEU ratio is less than 2%. It remains < 20% until ψ = 60° (Micron) and ψ = 75° (Samsung). At larger elevation angles (ψ = 85°), the MBU/SEU ratio explodes up to about 80%.

March, 29, 2011

MBU Features common to the Samsung and Micron Device


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(i) All MBUs are 0 → 1 falsifications (= charge loss).

(ii) Always only one bit per byte was corrupted.

(iii) At ψ ≤ 45° nearly no MBUs occurred.At ψ ≥ 60° the MBU percentage off all SEUs rises steeply.

(iv) Only very few MBUs show corrupted bits over more than4 columns / more than 4 pages.MBU classification according to the column distance: D-1 … D-5.

March, 29, 2011

MBU Features differing to the Samsung and Micron Device(i) Samsung: Page Distance 1, 2, 3, (≥ 4 very rare)

Column Distance: 1, 3 or 5Mostly D-3 and D-5 MBUs.D-1 MBUs only for incidence along the short die axes.Potential explanation: Even and odd columns are physically separated.

Micron: In contrast both, even and odd page, and even and odd column distances.Mostly D-1 MBUs.

(ii) The average omnidirectional SEU cross section σ4π has been calculated and has been compared to the cross section σ0,0 at normal incidence:Samsung: σ4π/ σ0,0 = 2.1 @ LET = 10.1Micron: σ4π/ σ0,0 = 0.8 @ LET = 10.1


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March, 29, 2011

Angular Dependence of MBU Address Distances


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Column Address Distances, Samsung, Elevation ψ = 85°

0

100

200

300

400

500

600

700

800

0 15 30 45 30 60 75 90 105 120 135 150 165 180 195 210 225 240 255 270 285 300 315 330 345 360

Azimut angle θ [°]

Num

ber o

f Add

ress

Dis

tanc

es

Distance 1Distance 2Distance 3Distance 4Distance 5Distance 6Distance 7

March, 29, 2011

Topics






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March, 29, 2011

DUT Preparation


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• DDR2-SDRAM and DDR3-SDRAM in FBGA-Package• die thickness between 180 µm and 350 µm

penetration of ion beams is about 90 µm at LET = 30=> backside thinning down to 60 – 70 µm

• etching of the plastic surface at 70°C with HNO3• sampling of the die curvature• grinding of the die with steps of about 20 µm along the die curvature• monitoring of the applied forces

Die Glas Fiber Substrate

Solder Balls

Back Surface of the Die

March, 29, 2011

DDR2 SDRAM Test Set Up Architecture


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Error FIFO B

Virtex-4 FPGA

Test logic

Test Controller

Address Generator

Pattern Generator

MUX

IF 1

IF 8

IF 2

Error FIFO A

FPGA ERROR FIFOUSB FIFO IF

USB UC IF

DDR2 APP IF

...

...

SYS CLOCK

SEE ADC IF

Pattern Selector

Constant Pattern

Random Pattern

Counting Pattern

ERROR FIFO IFWRITEREAD

Comparator

USB

Power

DUT 8

DUT 2

DUT 1

• DDR3 Test Bed ready for use in June 2011

March, 29, 2011

Error Distribution in Read Mode M1a, 4-Byte Burst


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No initialisation

15N4+

20Ne6+

40Ar12+

56Fe15+

82Kr22+

131Xe35+

15N4+

20Ne6+

40Ar12+

82Kr22+

131Xe35+

Short initialisation

56Fe15+

• Frequent initialisation reduces significantly the count of SEFI related errors.

March, 29, 2011

Cross section of single bit errors in Storage Mode M3


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• Elpida shows a substantial lower Cross Section• Cross Sections of Storage Mode (M3 a/b), Read Mode (M1 a/b)

and Marching Mode (M2 a/b) are nearly identical• also in M1 and M2 nearly all SEUs are static

1.00E-17

1.00E-16

1.00E-15

1.00E-14

1.00E-13

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

0 10 20 30 40 50 60

LET [MeV mg-1 cm2]

σSEU

[cm

2 bi

t-1]

Micron M3aMicron M3bElpida M3aElpida M3bMicronElpida

• a/b: without/with short initialisation

March, 29, 2011

Example of DDR2 SEFI types


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March, 29, 2011

Transient SEFI Cross Section in Marching Mode M2


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1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

0 10 20 30 40 50 60

LET [MeV mg-1 cm2]

σSEF

I [cm

2 de

v-1]

Micron M2aMicron M2bElpida M2aElpida M2bMicron

n = 8kn = 2kn < 128

• Transient SEFIs are for example Page Errors or Column Errors• short initialisation improves the cross section substantially

• a/b: without/with short initialisation, in M2 every n rows

March, 29, 2011

Publications and Acknowledgements

Publications[1] H. Schmidt et al., "TID and SEE Tests of an Advanced 8 Gbit NAND-Flash

Memory", NSREC 2008 Data Workshop[2] H. Schmidt et al.,"TID Test of an 8-Gbit NAND Flash Memory",

IEEE Trans. Nuclear Science, Vol. 56, Nr. 4, August 2009[3] L.Li et al., "Heavy Ion SEE Test of an Advanced DDR2 SDRAM",

TUZ Conference Proceedings, 2009, Bremen[4] K. Grürmann et al., "SEU und MBU Angular Dependence of Samsung and

Micron 8-Gbit SLC NAND-Flash Memories under Heavy-Ion Irradiation", accepted for NSREC 2011 Data Workshop

AcknowledgementsWe would like to thank Reno Harboe-Sørensen and Véronique Ferlet-Cavrois for their support and for their understanding of the imperfections associated with real work.Further we thank the technical staff of RADEF, PIF-PSI and CASE for their excellent support and Daniel Peyre, formerly with Astrium France, for refreshing discussions.


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Documents

Studies of Radiation SEE Effects in NAND-Flash and DDR