THE BOUNDARY-SCAN HANDBOOKSECOND EDITION

Analog and Digital

THE BOUNDARY-SCAN HANDBOOKSECOND EDITION

Analog and Digital

by

Kenneth P. ParkerHewlett-Packard Company

KLUWER ACADEMIC PUBLISHERSNEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: 0-306-47656-8Print ISBN: 0-7923-8277-3

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Dordrecht

Dedication

This book is dedicated to the memory of an Uncle for whom I was namesake.

Kenneth Fredric Parker, 1912-1998

TABLE OF CONTENTSList of Figures xiiiList of Tables xviiiList of Design-for-Test Rules xixPreface to the First Edition xxiPreface to the Second Edition xxiiiAcknowledgement xxv1 Boundary-Scan Basics and Vocabulary 1

22478

10162021272930313233333435353636373839393940414242434546

1.1 Digital Test Before Boundary-Scan1.1.11.1.2

Edge-Connector Functional TestingIn-Circuit Testing

1.21.3

The Philosophy of 1149.1-1990Basic Architecture

1.3.11.3.21.3.31.3.41.3.51.3.61.3.71.3.8

The TAP ControllerThe Instruction RegisterData RegistersThe Boundary RegisterOptimizing a Boundary Register Cell DesignArchitecture SummaryField-Programmable IC DevicesBoundary-Scan Chains

1.4 Non-Invasive Operational Modes1.4.11.4.21.4.31.4.41.4.5

BYPASSIDCODEUSERCODESAMPLEPRELOAD

1.5 Pin-Permission Operational Modes1.5.11.5.21.5.31.5.41.5.51.5.6

EXTESTINTESTRUNBISTHIGHZCLAMPExceptions Due to Clocking

1.61.71.8

ExtensibilitySubordination of IEEE 1149.1Costs and Benefits

1.8.11.8.21.8.3

CostsBenefitsTrends

1.9 Other Testability Standards

2 Boundary-Scan Description Language (BSDL) 492.1 The Scope of BSDL 52

2.1.12.1.22.1.3

Testing 52Compliance Assurance 53Synthesis 55

2.22.3

Structure of BSDL 57Entity Descriptions 61

2.3.12.3.22.3.32.3.42.3.52.3.62.3.72.3.82.3.92.3.102.3.112.3.122.3.132.3.142.3.152.3.162.3.17

Generic Parameter 62Logical Port Description 62Standard USE Statement 63Use Statements 64Component Conformance Statement 64

656667686970717275767777

Device Package Pin MappingsGrouped Port IdentificationTAP Port IdentificationCompliance Enable DescriptionInstruction Register DescriptionOptional Register DescriptionRegister Access DescriptionBoundary-Scan Register DescriptionRUNBIST Execution DescriptionINTEST Execution DescriptionUser Extensions to BSDLDesign Warnings

2.4 Some advanced BSDL Topics 782.4.12.4.2

Merged Cells 7880Asymmetrical Drivers

2.52.6

BSDL Description of 74BCT8374 8084Packages and Package Bodies

2.6.12.6.22.6.32.6.42.6.5

STD_1149_1_1999 85899199

Cell Description ConstantsBasic Cell Definitions BC_0 to BC_7User-Defined Boundary CellsDefinition of BSDL Extensions 100

101103

2.72.8

Writing BSDLSummary

3 Boundary-Scan Testing 1053.1 Basic Boundary-Scan Testing 106

3.1.13.1.23.1.33.1.43.1.53.1.6

The 1149.1 Scanning Sequence 106112113114116118

Basic Test AlgorithmThe “Personal Tester” Versus ATEIn-Circuit Boundary-ScanIC TestIC BIST

viii

3.2 Testing with Boundary-Scan Chains 1193.2.13.2.23.2.33.2.43.2.5

1149.1 Chain Integrity 119122136138141142144

Interconnect TestConnection TestsInteraction TestsBIST and Custom Tests

3.33.4

Porting Boundary-Scan TestsSummary

4 Advanced Boundary-Scan Topics 1454.14.24.34.44.54.64.74.84.94.10

DC Parametric IC Tests 146147150151154155157159160163

Sample Mode TestsConcurrent MonitoringNon-Scan IC TestingNon-Digital Device TestingMixed Digital/Analog TestingMulti-Chip Module TestingFirmware Development SupportIn-System ConfigurationHardware Fault Insertion

5 Design for Boundary-Scan Test 1675.1 Integrated Circuit Level DFT 169

5.1.15.1.25.1.35.1.45.1.55.1.65.1.75.1.85.1.95.1.10

TAP Pin Placement 169170174175176177178178179180

Power and Ground DistributionInstruction Capture PatternDamage Resistant DriversOutput PinsBidirectional PinsPost-Lobotomy BehaviorIDCODEsUser-Defined InstructionsCreation and Verification of BSDL

5.2 Board-Level DFT 1825.2.15.2.25.2.35.2.45.2.55.2.65.2.75.2.8

Chain Configurations 182185186187188190190192

TCK/TMS DistributionMixed Logic FamiliesBoard Level ConflictsControl of Critical NodesPower DistributionBoundary-Scan MastersPost-Lobotomy Board Behavior

5.3 System-Level DFT 1935.3.15.3.2

The MultiDrop Problem 194195Coordination with Other Standards

5.4 Summary 195

ix

6 Analog Measurement Basics 1976.1 Analog In-Circuit Testing 197

6.1.16.1.26.1.36.1.4

Analog Failures 198200204206

Measuring an ImpedanceErrors and CorrectionsMeasurement Hardware

6.2 Limited Access Testing 2116.2.16.2.26.2.3

Node Voltage Analysis 212Testing With Node Voltages 213Limited Access Node Voltage Testing 215

6.3 The Mixed-Signal Test Environment 2176.4 Summary 220

7 IEEE 1149.4 Analog Boundary-Scan 2217.1 1149.4 Vocabulary and Basics 222

7.1.17.1.27.1.37.1.4

The Target Fault Spectrum 223Extended Interconnect 223Digital Pins 225Analog Pins 226

7.2 General Architecture of an 1149.4 IC 2277.2.17.2.27.2.37.2.47.2.5

Silicon “Switches” 229The Analog Test Access Port (ATAP) 230The Test Bus Interface Circuit (TBIC) 231The Analog Boundary Module (ABM) 236The Digital Boundary Module (DBM) 242

7.3 The 1149.4 Instruction Set 2437.3.17.3.27.3.37.3.47.3.57.3.6

The EXTEST Instruction 244The CLAMP Instruction 247The HIGHZ Instruction 247The PROBE Instruction 247The RUNBIST Instruction 248The INTEST Instruction 248

7.4 Other Provisions of 1149.4 2507.4.17.4.27.4.37.4.4

Differential ATAP Port 250Differential I/O 251Partitioned Internal Test Buses 253Specifications and Limits 256

7.5 Design for 1149.4 Testability 2577.5.17.5.27.5.3

Integrated Circuit Level 257Board Level 259System Level 260

7.67.7

Summary 261262Epilog: What Next for 1149.1/1149.4?

x

APPENDIX A: BSDL Syntax Specifications 263A.1A.2A.3A.4A.5

Conventions 263264267269273

Lexical elements of BSDLNotes on syntax definitionBSDL SyntaxUser Package Syntax

Bibliography 275

281Index

xi

List of FiguresFigure 1-1: In-Circuit test setup with full nodal access. The component under test

may be embedded within a board and connected to other components. 5Figure 1-2: Cutaway drawing of a board resting on top of an In-Circuit, vacuum-

actuated test fixture: the “bed of nails.” The module interface pins are themechanical interface to the ATE pin electronics, which are placed very close toreduce path lengths. 6

Figure 1-3: General, simplified architecture of an 1149.1 compliant IntegratedCircuit. 9

Figure 1-4: State transition diagram of the sixteen-state TAP controller. 11Figure 1-5: Architecture detail of a typical Boundary-Scan register with shift and

parallel hold ranks. 17Figure 1-6: Example of an instruction register cell design. The expanded cell shows

several control signals generated by the TAP state machine. 19Figure 1-7: A Typical Boundary Register Cell. 22Figure 1-8: A Bidirectional pin with separate input and output Boundary Register

cells. 23Figure 1-9: A Bidirectional pin served by a reversible Boundary Register cell. 25Figure 1-10: Compensating inversions in an input Boundary Register cell that

monitors an inverting input buffer. 26Figure 1-11: Compensating inversion in an output Boundary Register cell connected

to an inverting output buffer. 26Figure 1-12: Two logical symbols for typical boundary cells, one with an Update

(UPD) flip-flop (A) and one without (B). 27Figure 1-13: An example (adapted from [Whet95]) of an output cell design that

eliminates both a discrete register stage and a multiplexer delay. 28Figure 1-14: Block Diagram of a Boundary-Scan IC. 29Figure 1-15: A field-programmable component with Boundary-Scan hard-wired into

its I/O Blocks (IOBs). Each IOB starts out with bidirectional support for acomponent pin, but subsequent programming may reduce each to supportinginput or output only. 31

Figure 1-16: A simple chain of Boundary-Scan ICs. 32Figure 1-17: Code bit allocation in a Device Identification Register accessed by

IDCODE. 34Figure 1-18: Observe-Only Boundary Register cell for inputs. 40Figure 1-19: Product introductions by Companies X and Y, and their relative

performance. 44Figure 2-1: BSDL use model within or outside of a VHDL environment. 51Figure 2-2: BSDL used as a test driver. 53Figure 2-3: A process for checking the compliance of an IC with the Standard. 54Figure 2-4: An 1149.1 synthesis system that both creates and uses BSDL. 56Figure 2-5: The relationship of a BSDL entity to the standard package and package

body. 59Figure 2-6: Candidate for merged cell design. 78Figure 2-7: Design with input and control cells merged. 79Figure 2-8: A design illustrating several merged cell situations. 81Figure 2-9: Texas Instruments 74BCT8374 Octal D Flip-Flop with Boundary-Scan. 82

Figure 2-10: An abstraction of a Boundary Register cell showing capture data sources.90

Figure 2-11: Cell architecture BC_1, a basic but very flexible design. 92Figure 2-12: Cell architecture BC_2. This cell can capture its own Update latch

content. 93Figure 2-13: Cell architecture BC_3, an input cell with no Update latch. 94Figure 2-14: Cell architecture BC_4, a cell with no Update latch and no series

multiplexer. 95Figure 2-15: Cell architecture BC_5, a control cell that can support HIGHZ-type

behavior. 95Figure 2-16: Cell architecture BC_7 (see the circuitry in the dotted line box) which

supports bidirectional data flow. 97Figure 2-17: A cell that captures a constant 1 during EXTEST. 99Figure 3-1: Side view of a Surface-Mount IC soldered to a board. An open and a short

are pictured. The poor quality joint will be invisible to electrical test methods,including Boundary-Scan. 106

Figure 3-2: TAP Controller state diagram showing path taken to shift an N-bitinstruction into the Instruction Register. 108

Figure 3-3: The newly loaded instruction is activated when UPDATE-IR is passed,selecting a new data register targeted between TDI and TDO when we enter theData Column of the state diagram. 109

Figure 3-4: Sequence of states traversed to capture data and shift it out while at thesame time entering new data. 110

Figure 3-5: Completing a data shifting operation and updating the parallel hold portionof a data register. 111

Figure 3-6: An IC undergoing an INTEST function while loaded on a board. 117Figure 3-7: A chain that has just passed CAPTURE-IR, loading all Instruction

Registers with “01”. 120Figure 3-8: A Boundary-Scan chain of ICs with four interconnect nodes. 123Figure 3-9: Interconnect test drives unique patterns assigned to each node from drivers

to receivers. A short is shown that creates a Wired-OR result. 124Figure 3-10: An interconnect open that prevents driven data from reaching one of two

receivers on a node. This fact can help a diagnostic isolate the location of theopen. 125

Figure 3-11: Simple interconnect test showing STVs (horizontal patterns) for 4 nodes.The columns are PTVs and represent the data as transmitted at each UPDATE-DRstate. Note two nodes are bussed. 126

Figure 3-12: Three examples of bus wire driver opens not detected by interconnectshorts test. 132

Figure 3-13: Control cell fanout combined with board topology that results inundetected opens. 133

Figure 3-14: Parallel testing of two bussed nodes. 134Figure 3-15: A case where four buses containing different numbers of drivers are

tested in parallel. 135Figure 3-16: A circuit where not all Boundary-Scan pins can be tested via interconnect

test. 137Figure 3-17: Example of potential interactions between a Boundary-Scan node and

two non-scanned nodes. 138

xiv

Figure 3-18: Boundary-Scan nodes B and C that can interact (by shorting) withnodes A, D or F. 139

Figure 3-19: Two cooperating components provide stimulus vectors and capture asignature response for data path logic. 141

Figure 3-20: Developing and porting a manually generated test for similarapplications. 142

Figure 3-21: Developing a Boundary-Scan test for similar applications. 143Figure 4-1: The analog testing subsystem of an IC tester is used to switch load and

test resources to measure analog parametric properties of an IC. 147Figure 4-2: A simple circuit and its timing diagram showing setup and hold times, and

the effects of system clock skew. 148Figure 4-3: Simple circuit showing the relationships between the system clock and

TCK during SAMPLE operation. 149Figure 4-4: Concurrent sampling of component I/Os during system diagnostics, with

sampled data compressed in a multiple-input signature analysis register (MISR).151

Figure 4-5: Testing a non-scan IC U7 with a combination of physical nails andBoundary-Scan pins. 152

Figure 4-6: A timing diagram that shows how Boundary-Scan resources must becoordinated with the resources of a host ATE system. 153

Figure 4-7: Shorted inputs on a NAND gate that may not be detectable when tested byordinary Boundary-Scan drivers. 154

Figure 4-8: A Boundary-Scan testable node that has a termination resistor to eliminatenoise. 154

Figure 4-9: A mixed digital/analog IC with the Boundary Register partitioning thedigital from the analog. 155

Figure 4-10: Two digital ICs that communicate by differential signaling, an analogtechnique. 156

Figure 4-11: Three examples of “unusual” differential signaling applications. 157Figure 4-12: Multi-Chip Module shown in cross section. This example shows a multi-

layer ceramic PGA made of multiple dielectric and metalization layers. Bare ICdie and other discrete components are mounted on the top surface. 158

Figure 4-13: Four macro states an FPGA/CPLD can be in and the transitionsbetween them. 162

Figure 4-14: A BC_1 Boundary Register cell modified to support fault insertion. 164Figure 5-1: Three pin layouts for TDI and TDO. 169Figure 5-2: An oscillograph of a Ground-Bounce induced clock cycle on TCK during

UPDATE-DR, measured at the package TCK pin referenced to componentground. 170

Figure 5-3: A high pincount IC with two 32-bit buses. 172Figure 5-4: The transition timing for activities on the two buses in Figure 5-3. 172Figure 5-5: Deliberately inserted delays in the Boundary Register control signal

paths can be used to distribute driver edge placements in time. 173Figure 5-6: A Boundary Register output cell design with the capability of monitoring

its driver output pad during EXTEST. 176Figure 5-7: A Siamese chain pair with common TCK and TMS signals, but

independent data paths. Any number of chains could be linked in parallel thisway. 183

xv

Figure 5-8: A Siamese chain pair with separate TMS lines, common TCK, and sharedboard-level TDI and TDO signals. 184

Figure 5-9: A simple chain with buffered TCK and TMS signals needed to avoidoverloading. 185

Figure 5-10: A low-skew clock buffer with 50% duty cycle preserved by utilizinginversion. 186

Figure 5-11: A simple Boundary-Scan chain containing ICs from different logicfamilies. Logic level conversion must be made between them. 186

Figure 5-12: A simple Boundary-Scan chain with a scanned level conversion interfacefor the parallel signals. Note the TCK and TMS lines must not have a scannedconversion. 187

Figure 5-13: A Boundary-Scan IC during test can set two normally complementaryoutputs to the same state, exciting conflicts in conventional ICs downstream. 188

Figure 5-14: Two Boundary-Scan nodes A and B need additional support from testerresources to enable proper testing. 189

Figure 5-15: A Boundary-Scan master interfaces between a microprocessor on oneside and 1149.1 on the other. (The directions of TDI and TDO are reversed,reflecting mastership.) 190

Figure 5-16: The 74ACT8997 Scan-Path linker IC linking simple chains A, B and C.Extra shift stages (marked with “*”) are inserted in the linked chain. These stagesare actually resident in the ‘8997, which itself appears in a normal 1149.1 form atthe end of the chain. 192

Figure 5-17: A system of several boards where each slot may accept several boardtypes, or not contain a board at all. A simple 1149.1 chain through these boardswould be broken at an empty slot. 194

Figure 6-1: A simple filter circuit and the actual circuit when parasitic capacitance isincluded. 198

Figure 6-2: Distribution of resistance values for a 4.7 Kohm resistors with atolerance of ±5%. 199

Figure 6-3: Measuring impedance with current source stimulus (A) and with voltagesource stimulus (B). 201

Figure 6-4: Measuring the impedance of a device on a board, connected to a silicondevice (A), and as seen by an ATE system (B). 202

Figure 6-5: Devices may be connected into networks providing parallel pathways forcurrents. 203

Figure 6-6: Some sources of error in an ATE setup for measuring a simpleimpedance. 205

Figure 6-7: Error impedances for a delta measurement (A) and a 6-wiremeasurement configuration (B). 206

Figure 6-8: An operational amplifier with feedback resistor used as a current meter.207

Figure 6-9: An operational amplifier setup to integrate a DC voltage V over time.207Figure 6-10: An operational amplifier setup for DC Dual Slope Integration. 208Figure 6-11: A dual slope integrator modified for AC measurements. 209Figure 6-12: A dual slope integrator used to measure a reactive component. 210Figure 6-13: Imaginary voltage waveform seen when measuring a capacitor. 211Figure 6-14: A simple network containing four resistors with full nodal access. 212Figure 6-15: Three-dimensional coordinates for graphing voltage differences. 213

xvi

Figure 6-16: Three-dimensional plots where only some components are potentiallyfaulty at any one time. 214

Figure 6-17: Example circuit with access to node B removed. 215Figure 6-18: Projecting the shadow of a three-dimensional object onto a plane. 215Figure 6-19: Projections of failure spaces for R2 and R3 onto two of the voltage

planes. 216Figure 6-20: A mixed-signal printed circuit board. 217Figure 6-21: Key to the color photograph appearing on the cover of this book. 219Figure 6-22: Comparison of relative sizes of various features. 220Figure 7-1: A mixed-signal circuit with some possible defects. 223Figure 7-2: Examples of interconnections seen in mixed-signal circuits. 224Figure 7-3: General (minimal) architecture of an 1149.4 compliant IC. 227Figure 7-4: Detail of 1149.4 data register structure. 228Figure 7-5: Symbols used for opened and closed switches. 230Figure 7-6: Two or more 1149.4 ICs chained together. Note AT1 and AT2 are not

required to be connected in parallel as shown here. 231Figure 7-7: A TBIC switching structure inserted between AT1/AT2 and AB1/AB2.

Note one-bit digitized values of the AT1/AT2 signals are generated. 232Figure 7-8: Control structure for the switches shown in Figure 7-7. 234Figure 7-9: ABM design detail for a generalized analog function pin. 237Figure 7-10: Control structure for the switches shown in Figure 7-9. 239Figure 7-11: ESD protection circuit for a typical pin (A) and an 1149.4 pin (B). 242Figure 7-12: Alternative forms for the Boundary Register depending on whether

INTEST and/or RUNBIST are supported. 243Figure 7-13: An ATE system set up to utilize 1149.4 resources in an IC to measure

an externally connected impedance. 244Figure 7-14: Two measurements (A) and (B) used to find the voltage across Z for a

known current. 245Figure 7-15: Testing the digital core using INTEST. The analog core is not directly

tested. 249Figure 7-16: The analog core can be tested by patterns supplied at the D/A interface

and by signals supplied or controlled by the ABMs. 250Figure 7-17: An example implementation for differential inputs and outputs. 252Figure 7-18: Example of a TBIC structure with one extension (k=2). 253Figure 7-19: Control structure for the extended TBIC switches in Figure 7-18. 254Figure 7-20: A conventional transmission gate switch and a shunting “T” switch

structure that reduces coupling when the switch is off. 258Figure 7-21: Degrees of guarding between two ATn signals. 260

xvii

List of TablesTable 1-1:Table 2-1:Table 2-2:Table 2-3:Table 2-4:Table 2-5:Table 2-6:Table 2-7:

Instruction Register operation during each TAP Controller state. 18637475899092

Pin types in a BSDL logical port description.Function symbols and their meanings.Definition of Disable Result field symbols.Definitions of allowable CELL_TYPE symbols.Definitions of CAP_DATA symbols.Mode signal assignment for cell BC_1 used in any context.Mode signal assignments for cell BC_2 in the context of use. See text for

an exception regarding INTEST. 93949698

Table 2-8:Table 2-9:Table 2-10:Table 3-1:

Mode signal assignment for cell BC_3.Mode signal assignments for cell BC_5.Mode signal assignments for BC_7 and its related BC_5 control cell.

Example data bits for chains shown in Figure 3-7. The bits for IC7 are thefirst to appear at TDO. 120

Table 3-2: Data streams from chains shown in Figure 3-7 with IC4 TDI and TDOshorted together, producing a Wired-AND. 122

Table 3-3: Sequential Test Vectors for a set of nodes. The rows are STVs and thecolumns are PTVs. 129

Table 3-4: A set of test PTVs (the columns) for interconnect test. (The Notes areexplained in the text.) 131

Table 3-5:Table 3-6:

Parallel test data for two bussed nodes. 134136Test data required for bus wires with different numbers of drivers.

Table 6-1: Node voltages for the circuit in Figure 6-14 when the component valuesvary from nominal. 212

Table 7-1: Comparison of parameters of various switches. 229Table 7-2: TBIC switching patterns (P0 through P9) for the switches shown in

Figure 7-7. 233234Table 7-3:

Table 7-4:Assignment of TAP instructions to mode signal values for the TBIC.Selection of TBIC switch patterns versus Boundary Register cell content.

235236Table 7-5: Logic equations for TBIC switch control.

Table 7-6: ABM switching patterns (P0 through P19) for the switches shown inFigure 7-9. 238

Table 7-7: Selection of ABM switch patterns versus Boundary Register cell content.240241Table 7-8: Logic equations for ABM switch control.

Table 7-9: TBIC extension switching patterns for the switches in Figure 7-18 forextension k. 254

Table 7-10: Selection of TBIC extension switch patterns versus Boundary Registercell content. 255

256Table 7-11: Logic equations for TBIC extension switch control.

xviii

List of Design-for-Test RulesDFT-l: Place TDI and TDO pins on the end or the corner of a package to reduce

their likelihood of being bridged by solder. 170DFT-2: When possible, place power pins between TDI and TDO pins and other

signal pins. 170DFT-3: Ensure that worst-case switching of all IC drivers will not cause

power/ground transients that disrupt the operation of the TAP controller. 174DFT-4: Use higher-order bits of the Instruction Register capture pattern to

implement an informal ID code. The bits captured must be predictable “0”s and“l”s. 174

DFT-5: If design-dependent bits are captured in the Instruction Register, then anycombination of these bits should decode to the same operation. 175

DFT-6: Specify a tolerance period that drivers can withstand shorts to each other orto Power/Ground voltages. 176

DFT-7: Use self-monitoring output cells in the Boundary Register to improveBoundary-Scan diagnosis of shorts and opens. 177

DFT-8: For bidirectional pins, utilize a single-cell bidirectional design with a self-monitoring capability (such as cell BC_7). 178

DFT-9: When the 1149.1 logic executes a pin-permission instruction, the systemlogic should be forced into a state that prevents internal conflicts. 178

DFT-10: When the 1149.1 logic returns to non-invasive mode, the system logicshould stay in a state that will not conflict with board level signals. 178

DFT-l1: Use formal or informal ID codes to differentiate similar components orrevisions of components. 179

DFT-l2: Consider board-level testing problems that will require user-definedinstructions for their solutions, before final implementation of the 1149.1 logic.

180DFT-13: Verify that a BSDL description matches the silicon implementation of

1149.1 on every component. 181DFT-14: Before designing a board-level chain configuration, be sure that the

software that will be used during testing will support it. 184DFT-15: If there are field-programmable components in a chain of 1149.1 devices,

group them together in the chain order and place the group at either end of thechain. 184

DFT-l6: Utilize simple buffering (where possible) of the broadcast TCK/TMSsignals. Document the enabling and initialization requirements needed topreserve the 1149.1 protocol through TCK/TMS distribution. 185

DFT-17: Do not allow logical inversion in the TCK or TMS pathways. 186DFT-l8: When mixed logic families are used on a board, use scanned level

converters for the parallel signals and a non-scanned level conversion forTCK/TMS distribution. 187

DFT-l9: Check conventional portions of board circuitry that may be affected byBoundary-Scan test data for damaging conflicts that may be induced. Designdisable methods into these portions that will make them insensitive to thistesting activity. 188

DFT-20: Provide for the ability of a tester to disable conventional ICs whose outputswould otherwise conflict with nodes involved in Boundary-Scan tests. 189

xix

DFT-21: Provide for the ability of a tester to create strong drive values on weaknodes. 189

DFT-22: Make sure you locate and condition all Test Reset (TRST*) pins and allcompliance enable pins before executing any Boundary-Scan tests. 189

DFT-23: Design analog and digital subsystems such that the analog power can beshut off while Boundary-Scan testing is being done. 190

DFT-24: If a Boundary-Scan master is used in a board design, provide for testequipment access and control of the 1149.1 side of the master’s interface. 191

DFT-25: Ensure that a board, after any 1149.1 operation completes, will have safestates on all components and nodes. 193

DFT-26: Restrict 1149.1 implementations for system tests to simple systemarchitectures not containing a multidrop scheme. 195

DFT-27: Eliminate all common conductive paths between a system pin pad and theATn switches (SB1 and SB2). 258

DFT-28: Partition internal analog test buses (per section 7.4.3) to control on-chipcross talk, leakage, and capacitance. 258

DFT-29: Examine the location of switches for places where the circuit may besensitive to parasitic coupling and leakage. Use enhanced switch designs inthese areas to reduce these effects. 258

DFT-30: Analyse the layout of the ATn pins with respect to leakage and parasiticeffects between them and other signals. 259

DFT-31: Group compatible ATAPs together on common ATn buses. Be prepared toaccommodate more ATAP buses than there are TAP chains. 259

DFT-32: For ATn ports expected to be used in measurements of very highimpedances, place a board-level guard wire between the ATn signals. 260

DFT-33: Consider which of all ATn ports in a system will be needed for system testand provide access to them. 260

DFT-34: Consider if noise-immunity testing of differential signaling is required inthe system. 261

xx

Preface to the First EditionIn February of 1990, the balloting process for the IEEE proposed standard P1149.1was completed creating IEEE Std 1149.1-1990. Later that summer, in record time,the standard won ratification as an ANSI standard as well. This completed over sixyears of intensive cooperative effort by a diverse group of people who share a visionon solving some of the severe testing problems that exist now and are steadilygetting worse.

Early in this process, someone asked me if I thought that the P1149.1 effortwould ever bear fruit. I responded somewhat glibly that “it was anyone’s guess”.Well, it wasn’t anyone’s guess, but rather the faith of a few individuals in theproposition that many testing problems could be solved if a multifaceted industrycould agree on a standard for all to follow. Four of these individuals stand out; theyare Harry Bleeker, Colin Maunder, Rodham Tulloss, and Lee Whetsel. In that I amconvinced that the 1149.1 standard is the most significant testing development in thelast 20 years, I personally feel a debt of gratitude to them and all the people wholabored on the various Working Groups in its creation.

Why do I feel that 1149.1 is more significant than, say, In-Circuit testing (mid1970’s) or the various scan design approaches (mid 70’s again) such as LSSD?Surely these were very significant. However, the In-Circuit test technique, while thebasis of several trillion dollars worth of electronics production, is basically anAd-Hoc technique where the creation of a board test is only partially automatable andsubject to potentially severe debugging problems. In short, every new board is anadventure. The various scan approaches were very significant in their ability to lead tothe automation of test development. However, they were most successful when carriedout within large, vertically integrated electronics companies. As such, they did notcontribute to testing problem solutions of the electronics industry at large.

A major contribution of 1149.1 is that it provides a standard mechanism fordissimilar segments of the electronics industry to provide support for testingproblems without requiring them to understand all those various problems. As anexample, members of the IC Merchant community have virtually no concept of theproblems of board level testing; nor should they have to if they will provide the1149.1 capability in their devices.

Another major contribution of 1149.1 is revealed in the first half of its formalname, “Standard Test Access Port”. This “Port” is an I/O and control protocol assurely as RS-232 and Ethernet are. Combined with the open-ended extensibility ofthe standard, the 1149.1 standard is a gateway to new testing approaches.Built-In-Self-Test (BIST) immediately comes to mind. It is this particular focus thatsuddenly makes the standard attractive to IC designers. They say, “well, I am beingforced to add these four pins and some overhead, but, look at the neat things I couldthen do with it.” These “things” are not limited to the field of testing.

This book is aimed at professionals in the electronics industry who are concernedwith the practical problems of competing successfully in the face of rapid-firetechnological change. Since many of these changes affect our ability to do testing andhence cost-effective production, the advent of the 1149.1 standard is rightly lookedupon as a major breakthrough. However, there is a great deal of misunderstanding about

what to expect of 1149.1 and how to use it. Because of this, this book is not a re-hash ofthe 1149.1 standard nor does it intend to be a tutorial on the basics of its workings. Thestandard itself should always be consulted for this, being careful to follow supplementsissued by the IEEE that clarify and correct it. Rather, this book attempts to motivateproper expectations and explain how to use the standard successfully.

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Preface to the Second EditionI was delighted when Carl Harris of Kluwer asked me to consider producing thissecond edition. This indicated that he believed 1149.1 and the newly emerging1149.4 standards are of continuing interest to the engineering profession.

IEEE standards, when embraced by practicing engineers, are living entities thatgrow and change quickly. That justifies this edition, but also should serve as awarning that the material in this book may be superceded by upcoming changes inthe standards. Always consult the most recent editions of the standards themselvesfor information needed for implementation. This book is intended to describe thesestandards in simple English rather than the strict and pedantic legalese encounteredin the standards. After reading this book, it is my hope the reader will find it easier tofollow the course of the standards themselves.

Since the first edition of this book became available, the IEEE has formalized theBoundary-Scan Description Language (BSDL) and made it a part of the standard.Indeed, to be compliant, devices must now be documented in BSDL so thatcomputer applications can use their features.

The 1149.1 standard is now over eight years old and has a large infrastructure ofsupport in the electronics industry. Today, the majority of custom ICs andprogrammable devices contain 1149.1. New applications for the 1149.1 protocolhave been introduced, most notably the “In-System Configuration” (ISC) capabilityfor Field Programmable Gate Arrays (FPGAs).

This book also introduces the very recently balloted standard, IEEE 1149.4“Mixed-Signal Test Bus”. This standard builds upon the base created by 1149.1. In1990, it was not at all clear how analog pins in mixed-signal devices should betreated by a testability standard. Now that 1149.4 exists, the two Working Groupshave begun the process of reconciling the two, with the possibility that the twodocuments will be merged together. Be alert for this event since it will mean morechange in the future.

Finally, the cover of this book shows a picture of what is driving our industrytoday. (See Figure 6-21 on page 219 for a key and discussion of this photograph.)Miniaturization is rampant in many sectors of our industry. Two examples arecellular telephones and handheld video cameras. A trend in our industry is thatminiaturized components are becoming the low-cost alternative because of thevolumes that consumer applications demand. Thus, those portions of industry thatdon’t need these components for reasons of density will still find it attractive toadopt them. This portends an increase in testing problems that 1149.1 and 1149.4 aremeant to solve. It is my sincere hope that this book will be of some use in solvingthese problems.

AcknowledgmentI’d like to acknowledge those who contributed to this effort. Significant technicalcontributions have been made over several years by Stig Oresjo, Ken Posse, JohnMcDermid and Rod Browen. Beth Eikenbary made management support happen.Others who influenced this work were Colin Maunder, Rod Tulloss, Chi Yau, NajmiJarwala, Lee Whetsel, Gordon Robinson, Peter Hansen, Tom Williams, Luke Girard,Dick Chiles, Larry Saunders, David Simpson, Grady Giles, Tom Langford, MarkusRobinson, C. J. Clark, Carl Thatcher, Adam Cron, Steve Sunter, Mani Soma, KeithLofstrom, Steve Dolens, Brian Wilkins and Ramaswami Dandapani.

Special mention goes to my friends at Matsushita Electric Industries in Osaka,Japan who worked incredibly quickly to produce working silicon containing 1149.4structures. They are Kozo Nuriya, Katsuhiro Hirayama, Akira Matsuzawa, AtsushiKukutsu and Ren Franse.

Reviews of various manuscripts were conducted by Anne Dudfield and JohnMcDermid of Hewlett-Packard, Ben Bennetts of Bennetts Associates, ColinMaunder of British Telecom and Keith Lofstrom of KLIC Incorporated, directed byCarl Harris of Kluwer Academic Publishers. All errors and omissions that survivedtheir careful efforts are my own.

I am indebted to my wife Jana, and my eight and six-year-old daughtersKatherine and Lisa who missed paternal contact while their father spent all thosehours in the basement. Without their support, I could not have completed this work. Ithank them. Now that this is finished, I look forward to making it up to them.

Fort Collins, Colorado