The CMOS Inverter: A First Glance€¦ · © Digital Integrated Circuits2nd Inverter The CMOS Inverter: A First Glance V in V out C L V DD

© Digital Integrated Circuits2nd Inverter

The CMOS Inverter: A First GlanceThe CMOS Inverter: A First Glance

Vin Vout

CL

VDD


CMOS PropertiesCMOS Properties

Full rail-to-rail swingSymmetrical VTCPropagation delay function of load capacitance and resistance of transistorsNo static power dissipationDirect path current during switching


CMOS InverterCMOS Inverter

Polysilicon

In Out

VDD

GND

PMOS 2λ

Metal 1

NMOS

OutIn

VDD

PMOS

NMOS

Contacts

N Well


Two Cascade InvertersTwo Cascade Inverters

Connect in Metal

Share power and ground

VDD


VOL = 0VOH = VDDVM = f(Rn, Rp)

VDD VDD

Vin = VDD Vin = 0

VoutVout

Rn

Rp

CMOS Inverter: FirstCMOS Inverter: First--Order DC AnalysisOrder DC Analysis


Voltage TransferVoltage TransferCharacteristicCharacteristic


PMOS Load LinesPMOS Load Lines

VDSp

IDp

VGSp=-2.5

VGSp=-1VDSp

IDnVin=0

Vin=1.5

Vout

IDnVin=0

Vin=1.5

Vin = VDD+VGSpIDn = - IDp

Vout = VDD+VDSp

Vout

IDnVin = VDD+VGSpIDn = - IDp

Vout = VDD+VDSp

IDn

IDp+

-VGSp

VGSn+

-


CMOS Inverter Load CharacteristicsCMOS Inverter Load Characteristics

IDn

Vout

Vin = 2.5

Vin = 2

Vin = 1.5

Vin = 0

Vin = 0.5

Vin = 1

NMOS

Vin = 0

Vin = 0.5

Vin = 1Vin = 1.5

Vin = 2

Vin = 2.5

Vin = 1Vin = 1.5

PMOS


CMOS Inverter Voltage Transfer CharacteristicsCMOS Inverter Voltage Transfer Characteristics

Vout

Vin0.5 1 1.5 2 2.5

0.5

11.

52

2.5

NMOS resPMOS off

NMOS satPMOS sat

NMOS offPMOS res

NMOS satPMOS res

NMOS resPMOS sat

Vdd = 2.5(V)

VM Switching Threshold

Vout = Vin


CMOS Inverter Voltage Transfer CharacteristicsCMOS Inverter Voltage Transfer Characteristics

Copyright © 2005 Pearson Addison-Wesley. All rights reserved.


Switching Threshold as a function of Switching Threshold as a function of Transistor RatioTransistor Ratio

100 1010.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

MV(V

)

Wp/Wn


Noise in Digital Integrated CircuitsNoise in Digital Integrated Circuits

VDDv(t)

i(t)

(a) Inductive coupling (b) Capacitive coupling (c) Power and ground

noise


Mapping between analog and digital signalsMapping between analog and digital signals

"1"

"0"

VOHVIH

VIL VOL

UndefinedRegion

V(x)

V(y)

VOH

VOL

VIHV

IL

Slope = -1

Slope = -1


Definition of Noise MarginsDefinition of Noise Margins

VIH

VIL

UndefinedRegion

"1"

"0"

VOH

VOL

NMH

NML

Gate Output Gate Input

Noise Margin High

Noise Margin Low


Noise Margins: DefinitionNoise Margins: Definition



Noise Margins: CMOS InverterNoise Margins: CMOS Inverter


Mp onMn off

Mp offMn on

“0” “1”


VVOHOH andand VVOLOL for the inverter circuitfor the inverter circuit

Noise MarginsNoise Margins

Introduction to Circuits, Fourth Edition by Peter Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved.


A simple Approach to Determine A simple Approach to Determine VVIHIH and Vand VILIL

VOH

VOL

Vin

Vout

VM

VIL VIH

A simplified approach


Inverter GainInverter Gain

0 0.5 1 1.5 2 2.5-18

-16

-14

-12

-10

-8

-6

-4

-2

0

Vin (V)

gain


The Regenerative PropertyThe Regenerative Property

(a) A chain of inverters.

v0, v2, ...

v1, v3, ... v1, v3, ...

v0, v2, ...

(b) Regenerative gate

f(v)

finv(v)

finv(v)

f(v)

(c) Non-regenerative gate

v0 v1 v2 v3 v4 v5 v6...


Impact of Process Variations Impact of Process Variations (1)(1)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin (V)

V out

(V)

Good PMOSBad NMOS

Good NMOSBad PMOS

Nominal


0 0.05 0.1 0.15 0.20

0.05

0.1

0.15

0.2

Vin (V)

Vou

t (V

)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin (V)

Vou

t(V)

Gain=-1

VTC vs. Supply Voltage variation (0.25 um)

Impact of Process Variations Impact of Process Variations (2)(2)


Propagation DelayPropagation Delay


Propagation time definitionsPropagation time definitions


tpf = tpHL

tpr = tpLH


Delay DefinitionsDelay Definitions

tpHL tpLH

t

t

Vin

Vout

50%

50%

tr

10%

90%

tf


RC switch model equivalent for the CMOS RC switch model equivalent for the CMOS InverterInverter



CMOS Inverter Propagation DelayCMOS Inverter Propagation DelayApproach 1Approach 1

VDD

Vout

Vin = VDD

CLIav

tpHL = CL Vswing/2

Iav

CLkn VDD

~


Evolution of the inverter switching modelEvolution of the inverter switching model



CMOS Inverter Propagation DelayCMOS Inverter Propagation DelayApproachApproach

tpHL = f(Rn .CL)= 0.69 Rn CL

V out

R n

V DD

V in = V DD

CL

Vout

R p

V DD

CL

V in = 0

(a) Low-to-high (b) High-to-low


0 0.5 1 1.5 2 2.5

x 10-10

-0.5

0

0.5

1

1.5

2

2.5

3

t (sec)

Vou

t(V)

Transient ResponseTransient Response

tp = 0.69 CL (Reqn+Reqp)/2

?

tpLH tpHL


Computing the CapacitancesComputing the Capacitances

VDD VDD

Vin Vout

M1

M2

M3

M4Cdb2

Cdb1

Cgd12

Cw

Cg4

Cg3

Vout2

Fanout

Interconnect

VoutVin

CLSimplified

Model


The Miller EffectThe Miller Effect

Vin

M1

Cgd1Vout

ΔV

ΔV

Vin

M1

Vout ΔV

ΔV

2Cgd1

“A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value.”


Computing the CapacitancesComputing the Capacitances


Design for PerformanceDesign for Performance

Keep capacitances smallIncrease transistor sizes

watch out for self-loading!Increase VDD (????)


1 1.5 2 2.5 3 3.5 4 4.5 53

3.5

4

4.5

5x 10

-11

β

t p(s

ec)

tpLH

NMOS/PMOS ratioNMOS/PMOS ratio

tpHL

tp β = Wp/Wn


Delay as a function of VDelay as a function of VDDDD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD

(V)

t p(n

orm

aliz

ed)


2 4 6 8 10 12 142

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8x 10

-11

S

t p(s

ec)

Device SizingDevice Sizing

(for fixed load)

Self-loading effect:Intrinsic capacitancesdominate

tp = 0.69RrefCiref(1+Cext/S.Ciref)tp = tpo(1+Cext/S.Ciref)


Impact of Rise Time on DelayImpact of Rise Time on Delayt p

HL(

nsec

)0.35

0.3

0.25

0.2

0.15

trise (nsec)10.80.60.40.20


Inverter SizingInverter Sizing


Inverter ChainInverter Chain

CL

In Out

If CL is given:- How many stages are needed to minimize the delay?- How to size the inverters?

May need some additional constraints.


Inverter DelayInverter Delay

• Minimum length devices, L=0.25μm• Assume that for WP = 2WN =2W

• same pull-up and pull-down currents• approx. equal resistances RN = RP• approx. equal rise tpLH and fall tpHL delays

• Analyze as an RC network

WNunit

Nunit

unit

PunitP RRW

WRWWRR ==⎟⎟

⎠

⎞⎜⎜⎝

⎛≈⎟⎟

⎠

⎞⎜⎜⎝

⎛=

−− 11

2W

W

tpHL = (ln 2) RNCL tpLH = (ln 2) RPCLDelay (D):

unitunit

gin CWWC 3=Load for the next stage:


Inverter with LoadInverter with Load

Load (CL)

Delay

Assumptions: no load -> zero delay

CL

tp = k RWCL

RW

RW

Wunit = 1

k is a constant, equal to 0.69


Inverter with LoadInverter with Load

Load

Delay

Cint

CN = Cunit

CP = 2Cunit

CL

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)= Delay (Internal) + Delay (Load)

2W

W


Delay FormulaDelay Formula

( )

( ) ( )γ/1/1

~

0int ftCCCkRt

CCRDelay

pintLWp

LintW

+=+=

+

Cint = γCgin with γ ≈ 1f = CL/Cgin - effective fanoutR = Runit/W ; Cint =WCunittp0 = 0.69RunitCunit


Apply to Inverter ChainApply to Inverter Chain

CL

In Out

1 2 N

tp = tp1 + tp2 + …+ tpN

⎟⎟⎠

⎞⎜⎜⎝

⎛+ +

jgin

jginunitunitpj C

CCRt

,

1,1~γ

LNgin

N

i jgin

jginp

N

jjpp CC C

Cttt =⎟

⎟⎠

⎞⎜⎜⎝

⎛+== +

=

+

=∑∑ 1,

1 ,

1,0

1, ,1 γ


Optimal Tapering for Given Optimal Tapering for Given NN

Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N

Minimize the delay, find N - 1 partial derivatives

Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

Size of each stage is the geometric mean of two neighbors

- each stage has the same effective fanout (Cout/Cin)- each stage has the same delay

1,1,, +−= jginjginjgin CCC


Optimum Delay and Number of Optimum Delay and Number of StagesStages

1,/ ginLN CCFf ==

When each stage is sized by f and has same eff. fanout f:

N Ff =

( )γ/10 Npp FNtt +=Minimum path delay

Effective fanout of each stage:


ExampleExample

CL= 8 C1

In Out

C1 1 f f2

283 ==f

CL/C1 has to be evenly distributed across N = 3 stages:


Optimum Number of StagesOptimum Number of Stages

For a given load, CL and given input capacitance CinFind optimal sizing f

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛+=+=

fffFtFNtt pNpp lnln

ln1/ 0/10

γγ

γ

0ln

1lnln2

0 =−−

⋅=∂

∂

fffFt

ft pp γ

γ

For γ = 0, f = e, N = lnF

fFNCfCFC in

NinL ln

ln with ==⋅=

( )ff γ+= 1exp


Optimum Effective Optimum Effective FanoutFanout ffOptimum f for given process defined by γ

( )ff γ+= 1expfopt = 3.6for γ=1


Impact of SelfImpact of Self--Loading on Loading on tptp

1.0 3.0 5.0 7.0u

0.0

20.0

40.0

60.0

u/ln

(u)

x=10

x=100

x=1000

x=10,000

No Self-Loading, γ=0 With Self-Loading γ=1


Normalized delay function of Normalized delay function of FF

( )γ/10 Npp FNtt +=


Buffer DesignBuffer Design

1

1 8

1 4

1 642.8 8 22.6

64

64

6416

N f tp

1 64 65

2 8 18

3 4 15

4 2.8 15.3

The CMOS Inverter: A First GlanceCMOS PropertiesCMOS InverterTwo Cascade InvertersCMOS Inverter: First-Order DC AnalysisVoltage Transfer�CharacteristicPMOS Load LinesCMOS Inverter Load Characteristics CMOS Inverter Voltage Transfer CharacteristicsSwitching Threshold as a function of Transistor RatioNoise in Digital Integrated CircuitsMapping between analog and digital signalsDefinition of Noise MarginsVOH and VOL for the inverter circuitA simple Approach to Determine VIH and VILInverter GainThe Regenerative PropertyImpact of Process Variations (1)Propagation DelayPropagation time definitionsDelay DefinitionsRC switch model equivalent for the CMOS InverterCMOS Inverter Propagation Delay�Approach 1Evolution of the inverter switching modelCMOS Inverter Propagation Delay�ApproachTransient ResponseComputing the CapacitancesThe Miller EffectComputing the CapacitancesDesign for PerformanceNMOS/PMOS ratioDelay as a function of VDDDevice SizingImpact of Rise Time on DelayInverter SizingInverter ChainInverter DelayInverter with LoadInverter with LoadDelay FormulaApply to Inverter ChainOptimal Tapering for Given NOptimum Delay and Number of StagesExampleOptimum Number of StagesOptimum Effective Fanout fImpact of Self-Loading on tpNormalized delay function of FBuffer Design

Documents

The CMOS Inverter: A First Glance€¦ · © Digital Integrated Circuits2nd Inverter The CMOS Inverter: A First Glance V in V out C L V DD