The design of the TimePix The design of the TimePix chipchip

Xavier Llopart, CERN

MPI-Munich, October 2006

2

From Medipix to TimepixFrom Medipix to Timepix A novel approach for the readout of a TPC at the future linear

collider is to use a CMOS pixel detector combined with some kind of gas gain grid

Using a naked photon counting chip Medipix2 coupled to GEMs or Micromegas demonstrated the feasibility of such approach

6 mm

2 mm

2mm

1 mm

e-

σpos

σcluster-size

14 mm

6 mm

2 mm

2mm

1 mm

e-

σpos

σcluster-size

14 mm

14.08mm14

.08m

m

GEMMicromegas

50um

3

MotivationMotivation These experiments (by NIKHEF/Saclay, Freiburg 2004/2005 )

demonstrated that single electrons could be detected using a naked Medipix2 chip 2D

Did not provide information on the arrival time of the electron in the sensitive gas volume 3D (position + time) !!!

To further exploit this approach the Medipix2 is being redesigned to incorporate a time stamp with a tunable resolution of 100 to 10ns.

Requirements: Keep Timepix as similar as possible to Medipix2 in order to benefit from

large prior effort in R/O hardware and software Avoid major changes in pixel and/or readout logic – risk of chip failure due to

poor mixed mode modelling Eliminate 2nd threshold Add possibility of programming pixel by pixel arrival time or TOT information

This modification is supported by the JRA2/EUDET Collaboration (www.eudet.org)

4

Preamp

DiscL

BWD

Vth Low

Vth High

14-bit

Shift Register

Input

Ctest

Testbit

Test Input

Maskbit3 bits Threshold

Adjust

3 bits Threshold Adjust

Shutter

Mux

Mux

ClockOut

Previous Pixel

Next Pixel

Conf

8-bit configuration

Polarity

Analog Digital

DiscH

Overflow Control

DelayN

Where we come from Where we come from (Mpix2MXR20 (Mpix2MXR20 Schematic)Schematic)

Pixel Configuration Bits

Maskbit

Masks pixel

TestBit Enables TestPulse

BL0 Low Threshold – B0

BL1 Low Threshold – B1

BL2 Low Threshold – B2

BH0 High Threshold – B0

BH1 High Threshold – B1

BH2 High Threshold – B2

5

Where we go… Where we go… (Timepix Schematic)(Timepix Schematic)

Pixel Configuration Bits

Maskbit

Masks pixel

TestBit Enables TestPulse

BL0 Low Threshold – B0

BL1 Low Threshold – B1

BL2 Low Threshold – B2

BL3 Low Threshold – B3

P0 Mode Selection – P0

P1 Mode Selection – P1

Preamp

Disc

THR14 bitsShif t

Register

I nput

Ctest

Testbit

Test I nput

Mask

4 bits thr Adj

Mux

Mux

Clk_Read

Previous Pixel

Next Pixel

Conf

8 bits configuration

Polarity

Analog Digital

Ref _Clk

TimepixSynchronization

Logic

Ref _Clkb

P0

P1

Shutter

Ovf Control

Clk_Read

Shutter_ int

6

Medipix Medipix ￫ ￫ Timepix: Analog side Timepix: Analog side changeschanges

Changes in Preamp: Added cascode to preamp

Changes in the discriminator:

Only 1 discriminator 4-bit threshold equalization Polarity control Added hysteresis

Preamp

Disc

THR14 bitsShif t

Register

I nput

Ctest

Testbit

Test I nput

Mask

4 bits thr Adj

Mux

Mux

Clk_Read

Previous Pixel

Next Pixel

Conf

8 bits configuration

Polarity

Analog Digital

Clk_Count

TimepixSynchronization

Logic

Clk_Countb

P0

P1

Shutter

Ovf Control

Clk_Read

Shutter_ int

Preamp

Disc

THR14 bitsShif t

Register

I nput

Ctest

Testbit

Test I nput

Mask

4 bits thr Adj

Mux

Mux

Clk_Read

Previous Pixel

Next Pixel

Conf

8 bits configuration

Polarity

Analog Digital

Clk_Count

TimepixSynchronization

Logic

Clk_Countb

P0

P1

Shutter

Ovf Control

Clk_Read

Shutter_ int

7

Medipix Medipix ￫ ￫ Timepix: Preamplifier Timepix: Preamplifier changechange

Added cascode (8-bit DAC controlled):

Gain ↑ (~18mV/Ke-) keeping Voutrms noise cte ￫ SNR ↑

Expected ENC 75e-

Expected Linearity: 0.6 to 1.5 Volts ￫ 50Ke- linear range

Expected Missmatch: vt 2.11mV ￫ vt 117e-

y = 0.0178x

R2 = 0.9999

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 50 100 150 200

Ke-

Vp

ream

po

ut[

V]

8

Medipix Medipix ￫ ￫ Timepix: Preamp Out vs Ikrum Timepix: Preamp Out vs Ikrum DACDAC

18.75 Ke input charge Ikrum DAC set: 5, 10, 20 and 40 Direct measurement on the Timepix

test output pads

18.75 Ke input charge Ikrum current set: 1.7, 3.4, 6.8, 13.6 nA

50mV

1 μs

9

Medipix Medipix ￫ ￫ Timepix: Gain Timepix: Gain LinearityLinearity

Expected gain linearity up to ~50Ke-

>50Ke- the Preamp output saturates50m

V

1 μs

50mV

1 μs

y = 0.0178x

R2 = 0.9999

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 50 100 150 200

Ke-

Vp

ream

po

ut[

V]

Simulation Measurement: ∆Qin and ∆Ikrum

10

Medipix Medipix ￫ ￫ Timepix: Timepix: Preamp Out vs Preamp Out vs Preamp DACPreamp DAC

Gain (ENC noise) depends on the preamp current Tunable peaking time: ~90ns to 400ns ￫ check Time-walk!

Lower Preamp current

50mV

200 ns

11

0

200

400

600

800

1000

1200

1400

1600

1800

2000

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

Input charge (Ke-)

Pix

el

Co

un

ts

1.17Ke Input Pulse

2.34Ke Input Pulse

3.51Ke Input Pulse

4.68Ke Input Pulse

TestPulse on 1 pixel (Medipix Mode) TestPulse on 1 pixel (Medipix Mode) Ikrum=5Ikrum=5

Gain is ~16.06mV/Ke- (Ikrum=5)σ ~ 3.9 DACs ~98e- rmsPixel Min Threshold < 500e-

12

Medipix Medipix ￫ ￫ Timepix: Discriminator Timepix: Discriminator changeschanges

Added hysteresis (8-bit DAC controlled) in discriminator: ~200e- lower threshold and no glitches at the disc output It can be turned off

Polarity selection on the discriminator: Hysteresis possible Optimization of the zero crossing design

4-bit threshold adjustment: Expected Threshold dispersion after adjustment ~25e-

IDisc

4·Ith2·IthIth

B2B1B0

OTAVth

VinDisc Out

FDL

IDisc

8·Ith

B3

IHist

Polarity

1

0

Mux

Sel

13

Medipix Medipix ￫ ￫ Timepix: Discriminator Timepix: Discriminator OutputOutput

1 μs

14

Medipix Medipix ￫ ￫ Timepix: Time walk Simulation-Timepix: Time walk Simulation-MeasurementMeasurement

Measured timewalk with the default DAC values Possible offline correction combined with TOT measurement can bring

timewalk < Ref_Clk period

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 250

30

60

90

120

150

180

210

240

270

300

Input charge [Ke-]

[ns]

0

10

20

30

40

50

60

70

80

90

100

1 10 100 1000Ke-

Tim

e W

alk

[ns]

Column top pixel

Column bottom pixel

~28ns ~23ns

0

10

20

30

40

50

60

70

80

90

100

1 10 100 1000Ke-

Tim

e W

alk

[ns]

Column top pixel

Column bottom pixel

~28ns ~23ns

Simulation Measurement: ∆Thr

15

Medipix Medipix ￫ ￫ Timepix: TOT vs Ikrum Timepix: TOT vs Ikrum (simulation)(simulation)

0

1

2

3

4

5

6

7

8

9

10

11

12

0 20 40 60 80 100 120 140 160 180 200

Ke-

TO

T w

idth

[u

s]

0

10

20

30

40

50

60

70

80

90

100

TO

T g

ain

[n

s/K

e-]

Ikrum=5nA (~55nA/Ke-)

Ikrum=10nA (~28nA/Ke-)

Ikrum=20nA (~14nA/Ke-)

TOT Linearity > 200 Ke-

16

TOT gain is a function of Ikrum DAC setting Ref_Clk=71.1MHz

0

0.5

1

1.5

2

2.5

3

3.5

4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Thr [Ke-]

[us]

Ikrum=40 (23.8ns/Ke-)

Ikrum=20 (52.7 ns/Ke-)

Ikrum=10 (114.2ns/Ke-)

Medipix Medipix ￫ ￫ Timepix: TOT vs Ikrum Timepix: TOT vs Ikrum (measurement)(measurement)

17

7520 7530 7540 7550 7560 7570 7580 7590 7600 7610 7620 7630 7640 7650 7660 76700

2000

4000

6000

8000

1 104

1.2 104

1.4 104

1.6 104

THL DAC

Cou

nts

Timepix equalization (I)Timepix equalization (I)

µ15=7561.5σ15=9.01 (225 e-)

µ=7591.8σ=1.48 (~36.8 e-)

µ0=7624σ0=9.13 (228 e-)

Equalization using the noise as trigger and Medipix Mode (P0=P1=0)

The measured DNL of the 4-bit DAC is < 1THL DAC -> Interpolation in the equalization can be used

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 157560

7570

7580

7590

7600

7610

7620

7630

7640

7650

7660

1

0.8

0.6

0.4

0.2

0

0.2

0.4

0.6

0.8Mean

±1sigmaLinear InterpolationDNL

Mean±1sigma

Linear InterpolationDNL

Threshold adjustment bit

TH

L

18

Analog pixel summaryAnalog pixel summary

Simulated Measured

Amplifier Gain ~18mV/Ke- ~16.06mV/Ke-

Peaking Time (∆ Preamp) 90ns…400ns 90ns…400ns

Pixel noise ~75e-rms ~98e-

rms

Threshold dispersion ~170e- ~225e-

Adjusted Threshold dispersion

~25e- ~38e- (not optimized)

Voltage linear range 0 to 50 Ke- (< 2%) Measured up to 20Ke-

TOT linear range >200Ke- Measured up to 50Ke-

Time Walk ~25ns (2Qth to ∞ ) ~60ns (with default DACs)

TOTgain ~55ns/Ke- (Ikrum=5nA) 52.7ns/Ke- (IkrumDAC=20)

Analog Pixel consumption (Max)

2.9μA x 2.2V = 6.38 μW (30% less than Mpix2MXR20)

Maximum possible Qin injected via Testpulse is ~50Ke-

19

Medipix Medipix ￫ ￫ Timepix: Digital side Timepix: Digital side changeschanges

Added time reference (Ref_Clk)

Selectable operation modes (P0 and P1)

TSL (Timepix synchronization Logic)

Pixel-by-pixel synchronized Shutter

Preamp

Disc

THR14 bitsShif t

Register

I nput

Ctest

Testbit

Test I nput

Mask

4 bits thr Adj

Mux

Mux

Clk_Read

Previous Pixel

Next Pixel

Conf

8 bits configuration

Polarity

Analog Digital

Ref _Clk

TimepixSynchronization

Logic

Ref _Clkb

P0

P1

Shutter

Ovf Control

Clk_Read

Shutter_ int

20

Medipix Medipix ￫ ￫ Timepix: Added Time Timepix: Added Time reference (I)reference (I)

Column length= 55x256= 14080μm

W=0.4μm,T=0.54μm, H=0.8μm R2.8KΩ Ctot<=2pF Parasitic cap negligible at D>3

μm

W

Cline-Cline

D

Cline-GND

Cline-VDD

T

H

Cline-Cline

Cline-GND + Cline-VDD

Ctot

21

Medipix Medipix ￫ ￫ Timepix: Added Time Timepix: Added Time reference (II)reference (II)

N buffer per column: Min size buffer inverter per pixel No differential signals needed Power uniformly distributed over

clock period

N=256, f=100MHz Propagation delay = ~50ns

(~195ps/inv) Simulation takes care of parasitic

capacitances and top-down resistive power lines.

~50ns

~0.820mA/col ~210mA/chip

Clock_in Rtot/ N

Ctot/ N

Rtot/ N

Ctot/ N

Clock !Clock

22

Medipix Medipix ￫ ￫ Timepix: Expected digital power Timepix: Expected digital power dissipationdissipation

Pvdd=V2·f·Ctot Simulation @ Vdd=2.2V

but digital part could work to 1.8V (33% less power)

0

50

100

150

200

250

300

350

400

0 25 50 75 100 125 150 175 200 225

Clock [MHz]

Ivd

d [

mA

]

N=128

N=64

N=32Ivdd[mA] 2·f[MHz]

23

Medipix Medipix ￫ ￫ Timepix: TSLTimepix: TSL

Mask

P1

P0 Mode

0 0 0 Masked

0 0 1 Masked

0 1 0 Masked

0 1 1 Masked

1 0 0 Medipix

1 0 1 TOT

1 1 0 Timepix-1hit

1 1 1 Timepix

Use of 3-bit High threshold adjustment bits for : 4th equalization bit and P0, P1.

Each pixel can be configured independently in 5 different modes.

This logic needs 128 Trts (Mpix2MXR20 had 92 Trts)

24

Timepix Synchronization Logic Timepix Synchronization Logic (TSL)(TSL)

Hit is synchronized with Ref_Clk and Shutter generating the signal to the counter and internal Shutter depending on P0, P1 and Mask bits.

Power consumption only when Hit is present TSL Core is divided in 2 blocks: Core1 used for the Timepix and TOT

modes and Core2 used for Medipix mode. Core blocks have being designed using an asynchronous network with S-R

Flip-flops with race-free state assignment

Core

25

TSL Core1 Asynchronous TSL Core1 Asynchronous designdesign

1 2

3

4 5 4 5 1

6

8 1

4

5 4 5

4

7 1

4

78

8

1 2

3

2

1

Z1=0Z2=0

Z1=1

Z2=0

Z1=1

Z2=1

Z1=1Z2=1

1,2,3 7,4

5,6

4

8

5,4

1

5

1

8

Hit (X1)

Clock (X2)

Gate Clock (Z1)

To Counter (Z2)

TSL desired time diagrams

State diagram

26

TSL Core Asynchronous TSL Core Asynchronous design (II)design (II)

Z1=0Z2=0

Z1=1

Z2=0

Z1=1

Z2=1

Z1=1Z2=1

1,2,3 7,4

5,6

4

8

5,4

1

5

1

8

Z1=0Z2=0

Z1=1

Z2=0

Z1=1

Z2=1

Z1=1Z2=1

00 01

10

4

8,5*

5,1*

11

1,4*

State diagram Reduced State diagram

27

TSL Core Asynchronous design TSL Core Asynchronous design (III)(III)

Z1=0Z2=0

Z1=1

Z2=0

Z1=1

Z2=1

Z1=1Z2=1

00 01

10

4

8,5*

5,1*

11

1,4*

Conf

Reduced State diagram with initialization

Implementation with SR flip-flops (62 trts)

28

TSL Core2 Asynchronous TSL Core2 Asynchronous designdesign

Gate Clock (Z1)

To Counter (Z2)

1

Medipix2 (Z3)

2 3 4 1 2 35 4 5 4 5 12

3 1

TSL desired time diagrams

Implementation using gates (20 trts) since inputs are race-free “by design”

29

Timepix Mode Timepix Mode (P0=1,P1=1)(P0=1,P1=1)

17

10MHz 100MHz

164

30

TOT Mode (P0=1,P1=0)TOT Mode (P0=1,P1=0)

33 50 12

10MHz 100MHz

2Ke- 4Ke- 2Ke-

31

Medipix Mode Medipix Mode (P0=0,P1=0)(P0=0,P1=0)

10MHz 100MHz

32

Internal Shutter controlInternal Shutter control

Internal Shutter is always synchronous to the clock to avoid glitches

Counter starts counting if a hit is present when shutter starts

Shutter closing happens with a maximum delay of 1Tclk if a hit is present when shutter closes

33

Digital power Digital power consumptionconsumption

Reduce digital power of the TSL cores ￫ No power consumption in stand-by (no hit)

In stand-by the only digital consumption is the buffering of the Ref_Clk

Controlled by design of the core1 asynchronous network.

34

Pixel measurementsPixel measurements

From the 2 test pixels [120:121,0] one can measure the preampOut, discOut, internal Ref_Clk and the counter clock

State Machine of the counter Modes (P0, P1) work as expected

No visible coupling of the Ref_Clk signal into the analog signals (preampOut and discOut)

Thr

Shutter

PreampOut

discOut

CounterClk

35

Timepix Layout statusTimepix Layout status

11 22 44

55

66

33

55μm

55μm

Mpix2MXR20 layout Timepix layout

11 22 44

55

66

55μm

55μm

36

Timepix chip Timepix chip architecturearchitecture

IO

Logic

LVDS

In

LVDS

Out32-bit CMOS Output

256-bit Fast Shift Register

3584

-bit

Pix

el C

olu

mn

-035

84-b

it P

ixel

Col

um

n-0

Bandgap + 13 DACs

1612

0 m

14111 m35

84-b

it P

ixel

Col

um

n-1

3584

-bit

Pix

el C

olu

mn

-1

3584

-bit

Pix

el C

olu

mn

-255

3584

-bit

Pix

el C

olu

mn

-255

1408

0 m

(pi

xel a

rray

)

Chip architecture almost identical to Mpix2MXR20

M0=M1=1 and Shutter ON -> FClock used as Ref_Clk

256x256 55µm square pixels Analog Power -> 440mW Digital Power (Ref_Clk=50MHz) ->

220mW Serial readout (@100MHz) -> 9.17 ms Parallel readout (@100MHz) -> 287 µs > 36M Transistors

37

Periphery Verilog Periphery Verilog SimulationsSimulations

This simulation tests 1 row of pixels and the full chip control logic Tested with normal and corner (3) parameters successfully Pixel control logic is initialized after a set mask command M0=1 and M1=1 when counting will enable the clock distribution to

the pixel matrix

M0

M1

En

ab

le_IN

Sh

utte

r

Rese

t

P_S

I/O

FClo

ck n

um

(p

er ch

ip)

Operation

X X X X 0 X I X General reset of the chip 1 1 X 0 1 X X X Counting 0 0 0 1 1 0 I/O 917768 Serial Readout Matrix (Slow Reset Matrix)

0 0 0 1 1 1 I/O 28688Parallel Readout Matrix (Fast Reset

Matrix)0 1 0 1 1 X I 917768 Set Matrix 1 0 0 1 1 X I/O 264 Write/Read FSR (DACs and CTPR)

38

Single chip Verilog Single chip Verilog simulationsimulation

1:SetDACs2:SetMatrix3:ResetMatrix

(PS=1)4:Counting5:Readout (PS=1)

1 2 3 4 5

39

Counting Modes (Mask,P0 and Counting Modes (Mask,P0 and P1)P1)

Pixel Masked P0=X, P1=X and Mask=1

Tpix-1h mode P0=0, P1=1 and Mask=0

Mpix2 mode P0=0, P1=0 and Mask=0

Tpix mode P0=1, P1=1 and Mask=0

CCD mode P0=1, P1=0 and Mask=0

40

Medipix2 vs TimepixMedipix2 vs TimepixMedipix2 Timepix

Physical dimensions = =IO PADs = =Charge collection e-, h+ e-, h+

Pixel functionality PhotonCounting PhotonCounting, TOT, Timepix Amplifier Gain ~10mV/Ke- ~18mV/Ke-

Noise ~110e- ~75e-

Linearity Up to 100Ke- Up to 50Ke-

Thresholds 2 (3+3 bits adj) 1 (4bits adj)σ equalized ~100e- ~25e-

Minimum Threshold ~900e- (measured) ~500e- (expected)*

Counter Depth/Overflow

14-bits/Yes 14-bits/Yes

Max Analog power 10μW/pix

300mA/chip6.5μW/pix 190mA/chip

Static Digital Power none 200mA@100MHzReadout Serial/Parallel Serial/Parallel

Readout compatibility 100%95% (Clock active when shutter

ON)

41

Summary & ConclusionsSummary & Conclusions

Timepix is a modification of the Medipix chip

Improvements in Gain and threshold equalization -> expected lower threshold (~900e- ￫ ~600e-)

Pixel operation mode is selectable for each pixel

TimeStamp reference (Ref_Clk) generated by a common clock distributed all over the chip

Timepix time line: Desgin: 6 months (January06-June06)

Fabrication: 2 months (July06-August06)

Testing: 1 months so far ( mid September06-?)