The SILC ProjectThe SILC Project(SiLC:(SiLC: SSiliconilicon tracking for thetracking for the IInternationalnternational LLinearinear CCollider)ollider)

Aurore Savoy-Navarro, LPNHE-UPMC/IN2P3-CNRS

on behalf of the SILC R&D Collaboration

(with material from last SiLC meeting in Vienna)

JORNADAS SOBRE EL FUTURO  COLISIONADOR LINEALJORNADAS SOBRE EL FUTURO  COLISIONADOR LINEAL Palacio Ducal, GANDÍA, Palacio Ducal, GANDÍA, 1 al 3 de Diciembre 2005 1 al 3 de Diciembre 2005

R&D on Si Trackers R&D on Si Trackers WHHHHYYYYYY ?WHHHHYYYYYY ?

??

Volume 45-9: Nov 2005Volume 45-9: Nov 2005

A lot to be already learned A lot to be already learned from LHC!from LHC!

But material budget is not the ONLY reasonBut material budget is not the ONLY reason

The SILC R&D CollaborationThe SILC R&D Collaboration

U.S.AU.S.A

Michigan U. Michigan U. SCIPP-UCSCSCIPP-UCSC

EuropeEurope

IMB-CNM/CSIC, Barcelone (SP) IMB-CNM/CSIC, Barcelone (SP) (eudet ass.)(eudet ass.)

Geneva U, Geneve (CH)Geneva U, Geneve (CH)Helsinki U. (Fi) Helsinki U. (Fi) (eudet)(eudet)

IEKP, Karlsuhe U. (D)IEKP, Karlsuhe U. (D)Moscow St. U. , Moscou(Ru)Moscow St. U. , Moscou(Ru)Obninsk St. U., Obninsk (Ru)Obninsk St. U., Obninsk (Ru)

LPNHE, Paris (Fr) LPNHE, Paris (Fr) (eudet)(eudet)

Charles U. , Prague (CZ) Charles U. , Prague (CZ) (eudet)(eudet)

IFCA, Santander(Sp) IFCA, Santander(Sp) (eudet)(eudet)

Torino U., Torino (It)Torino U., Torino (It)IFIC-CSIC Valencia (Sp) IFIC-CSIC Valencia (Sp) (eudet ass.)(eudet ass.)

IHEP, Academy Sci., Vienna (Au)IHEP, Academy Sci., Vienna (Au)

AsiaAsia

Kyungpook U. Taegu, KoKyungpook U. Taegu, KoYonsei U., Seoul, KoYonsei U., Seoul, KoKorea U. Seoul, KoKorea U. Seoul, Ko

Seoul Nat. U., Seoul, KoSeoul Nat. U., Seoul, KoSungKyunKwan U. SeoulSungKyunKwan U. Seoul

Tokyo U. (Japan)Tokyo U. (Japan)HAMAMATSU (Japan)HAMAMATSU (Japan)

Close connections: FNAL (DOE prop 05funded)UCSC, FNAL,

LPNHE SLAC (DOE prop 03:funded): UCSC, SLACMichigan U, LPNHEand meetings SiD

CERN (developed interest)

Launched January 2002, Proposal to the PRC May 2003, Report Status May 2005,Several contracts of collaborations between Institutes, ex:

HPRN-CT-2002-00292, CICYT-IN2P3, IN2P3-Hamamatsu, DOE proposals, EUDETCollaboration still growing.

(underlined are the contracts/ proposals including spanish teams in SiLC)

R&D GoalsR&D Goals

• Very high precision on momentum (x10 better) & spatial measurements (down to 4µm, in certain regions, average 7-8 µm), large angle coverage.

• Low material budget• Robustness• Easy to build and to work with• Low cost

SiLC is a generic R&D collaboration to develop the next generation of large area Silicon Detectors for the ILC; It applies to all the detector concepts

and indeed gathers teams from all 3 detector concepts:

SILC R&D offers a unique framework to compare tracking performances between the various detector concepts.

Main difference between the detector concepts = tracking system

SiDGLD

LDC

LDC

To achieve these goals:To achieve these goals:

R&D on sensorsR&D on sensors R&D on ElectronicsR&D on Electronics R&D on MechanicsR&D on Mechanics

together with developing the appropiate tools:together with developing the appropiate tools:

Test benchesTest benchesCalibrations and MonitoringCalibrations and MonitoringSimulationsSimulationsTest BeamTest Beam

R&D on SensorsR&D on Sensors Silicon strips are the baseline with:Silicon strips are the baseline with:• Larger size wafers, single and double sided• Thinner/Thinning• Smaller pitch• High yield• Eventually different shapes Possibility to use new technos in some regions:Possibility to use new technos in some regions: • Pixelization: Pixels, DEPFET, MAPS/FAPS, SOI

In order to achieve this R&D:In order to achieve this R&D: Lab test bench for full characterization of the sensors (most Labs

in SiLC) with a continuous upgrade. Fabrication line for new ideas on sensors at various Institutes (Korean Institutes, Helsinki U., IMB-CNM/CSIC) Process Quality Control and sensor characterization (Vienna,

Karlsruhe, Korea, Helsinki) Medium size fab line for small size production (looking at

different such places, in Europe and Asia for the time being) Transfer to Industry for full production (presently Hamamatsu

but could evolve).

1)Tests & results on Si strips1)Tests & results on Si stripsSIGNAL / POSITION LASER

Laser LD1060 avec collimateur F18 - Precision en ZC 554 - 1L

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Position Laser (pas=5um)

Sig

nal

(m

V)

Z=7970g

Z=7971g

Z=7972g

Z=7972d

Deplacement Laser g : Y croissant

lc-sig-y-f8-613-01-05

piste aluminium ( 20 um )

Same amplitude for L=28 up to 112 cm with Tsh=3.7µs

VA64_hdrTsh=3.7µs

Variable lengths:28cm x N=1,4

Built by Geneva U.

Paris test bench

Sr90Source testsParis-Prague

• Pedestal and common mode subtraction

• Signal spectrum summed over a cluster

MPV: 51 mV

Mean: 79 mV

Noise: 2.6 mV

28 cm 56 cm

MPV: 55 mV

Mean: 83 mV

Noise: 4.6 mV

• Pedestal and common mode subtraction

• Signal spectrum summed over a cluster

112 cm224 cm

Sr 90 Source tests(Paris-Prague)

• Noise scales with strip length: ENC~20 e/cm

• S/N drops below 10 for 224 cm

• Noise optimisation of the setup needed

• Improved FE electronics

(here VA_64hdr)(Z. Dolezal & F. Kapusta,Vienna’05)

NEW & Preliminary

Several Institutions in SILC are developing new sensor research lines

(IMB-CNM/CSIC, Helsinki, SiLab, Korea)Strategy:

The research Labs develop & test new ideas transfer to small fabs for reduced prod.

Large production, high quality and reliability: HAMAMATSU Monopoly

2) R&D on new sensors2) R&D on new sensors

N-side P-side

waferTOPSIL(5inch, high resistivity, (100), FZ, DSP)

strip width 9m

strip pitch 50(100) m

thickness 380 m readout pitch 50m

size 51 x 26 mm2 readout channel 512(512)

Prototype

DSSD Designed, Fabricated and Tested: - IV/CV shows good quality sensor

- S/N shows that the sensors are in good shape - more tests are in progress

- will fabricate AC-SSD on 6-inch(400 mm) and 8-inch(500 mm) wafers

S/N=25

KOREAN KOREAN TEAMTEAM

3) Quality Control: Sensor Test Setup3) Quality Control: Sensor Test Setupcourtesy of Thomas Bergauer (HEPHY Vienna)

• Light-tight Box, Instruments, Computer

• vacuum support carrying the sensor– Mounted on freely movable table in

X, Y and Z

• Needles to contact sensor bias line – fixed relative to sensor

• Needles to contact:– DC pad (p+ implant)

– AC pad (Metal layer)

– Can contact ever single strip while table with sensor is moving

Example Measurements: StripscanExample Measurements: Stripscan

• After IV-CV ramp, bias voltage is adjusted to stable value (e.g. 400 V) and stripscan is started

• 4 parameters tested for each strip:

– dielectric current Idiel

– coupling capacitance Cac

– poly-silicon resistor Rpoly

– strip leakage current Istrip

• For each test, the switching matrix has to be reconfigured

– Full characterization of detector with 512 strips: 3h

TS-CAP

sheet

GCD

CAP-TS-AC CAP-TS-AC

baby diode

MOS in

MOS out

Standardized Set of Test StructuresStandardized Set of Test Structures

Com

pany t

est

-str

uct

ure

s

“Standard Half moon” with 9 different structures adressing all

important sensor characteristics

SummarySummary

• Future experiments with large tracker require huge number of sensors. – CMS Si Tracker: 206 m2 , 24.244 sensors, 9.316.352 channels

• Fabrication will last many months (years) and a stable production during the whole production time is mandatory.

• Strip-by-strip test of detectors is necessary but not sufficient– Slow, reduced set of parameters to test

• Measurements on dedicated test-structures is a powerful possibility to monitor the fabrication process– During a long production time– Also on parameters which are not accessible on the main sensor (e.g. MOS)– Destructive tests possible– Fast measurement allows high throughput

• Test structures must be optimized by improving with• Smaller structures• Better design of some structures (e.g. diode, sheet)• To put it on unused space of their wafer design

Si detector simulation:Si detector simulation:important for the sensor & electronics studies important for the sensor & electronics studies and to include in G4 simu for detector studiesand to include in G4 simu for detector studies(ex: IMB-CNM, Helsinki, Karlsruhe, Prague, Paris)(ex: IMB-CNM, Helsinki, Karlsruhe, Prague, Paris)

• ISE-TCAD, TMA, Silvaco

• Technology simulation

• Electrical simulation

– Charge collection

– charge sharing in 3D

or: G4 simu

R&D on ElectronicsR&D on ElectronicsThe Si tracking system includes: a few 100m2, a few 106 stripsEvents tagged every bunch (300ns) during the overall train (1 ms)Data taking/pre-processing ~ 200 msOccupancy: < a few %

Requested features for FE chip:Requested features for FE chip:Low noise preamplifiers

Shaping time (from 0.5 to 5 µs,depending the strip length)

Analogue samplingHighly shared ADC

Digitization @ sparsification Very low power dissipation

Power cyclingCompact and transparent

Choice of DSμE & go to VDSM

First LPNHE prototype fulfills First LPNHE prototype fulfills most of these requirementsmost of these requirements

Other electronics issues:Other electronics issues:Time measurement

Calibration/Monitoring of the electronic chain

ConnecticsCabling

Integration into DAQData taking/pre-processing

On detectorOutside detectorBunch tagging

Discussed at the SiLC Meeting, Discussed at the SiLC Meeting, Vienna Nov. 18thVienna Nov. 18th

Front-End chips under design(Courtesy of Jean François Genat, LPNHE)

SLACCalorimetry and tracking (submitted to MOSIS 0.25µ, Oct 24)

Charge: linear 1 or 2-gains, 2500 MIPSShaping: reset-sample (2-correlated sampling like) Time: BC id

UC Santa CruzTracking Charge: Time Over Threshold, Lo+Hi thresholds,

128 MIPSShaping: sTime: BC id

LPNHE ParisTracking

Charge: linear, multiple sampling including pedestal, 50MIPS

Time: 2-scales BC id 1-10 ns timing (long. coordinate over strips)

Present Si tracker FE designsPresent Si tracker FE designs

SCIPP-UCSC: Double-comparator discrimination system

Charge by TOTImprove spatial resolution (25%)

2nd Foundry: May 05, arrived August 05

LPNHE-Paris:Analogue sampling+A/D,

including sparsification on sums of 3 adjacent strips.

Deep sub micron CMOS techno.First chip successfully submitted

Fully testedNext version: in progress

Expected Performance for time measurements Two different designs must be considered wrt the time scale to be

achieved: Time stamping (order of 30 to 50 ns) Fine time measurement (~ 2 to 5 ns)

Preamp + shaper + sampling have to be designed accordingly.

This will impact the performance on power dissipation and technology choice. Currently investigated both on Lab test-bench and simulations

Simulated time resolution using multiple samplingand least square fit algorithm (J.F. Genat)

Paris Front-end Prototype Chip

Low noise amplification + pulse shaping

Pulse sampling Threshold detection Power dissipation less than 500

W/ch.

Technology: CMOS 180 nmSent Nov 2004, received February 2005

Preamp CR RC Shaper FollowerComparator

16 identical channels

3mm

Preamp results

Gain: 8mV/MIP OK

Dynamic range: 50 MIP OK

Linearity: +/-1.5% expected: +/-0.5% -

Noise @ 70 W power, 3s-20s rise-fall times:

498 + 16.5 e-/pF 490 + 16.5 e-/pF expected OK

Shaper results

Peaking time: 2-6 s tunable peaking time vs 1-10 expected -

Linearity: 6%, 3.5% expected -

Noise @ 3 s shaping time and 70 W power:

325 + 10.1 e-/pF vs 274 + 8.9 e-/pF expected OK

Measured Shaper output

Small oscillations at the shaper output mainly due to packaging parasitics325 e- input noise for 280 simulated with chip-on-board wiring

Measured waveform as expected

Packaged chip

Bare chip on board

Process spreads (CMOS 180 nm)

Process spreads: 3.3 % quite good Preamp gain distribution (Preamp + shaper) power distribution

First foundry in 180 nm: quite successful and very well testedFirst foundry in 180 nm: quite successful and very well tested

128 channel chip128 channel chipUMC 130 nm CMOS technoUMC 130 nm CMOS techno

with sampling included;2nd chip prototype under design,

submission Sept 06 (preproto 4-8 channel-chip, submitted March 06).

Will equip the test beam prototypes

Second LPNHE FE chip prototype: underway Second LPNHE FE chip prototype: underway

analogue

R&D on MechanicsR&D on Mechanicsconcentrates on:concentrates on:

CAD design of Si tracking components: essential for baseline design studies of detector concepts

Elementary module design in close collaboration with FE electronics designers

Large structure: robust, light, easy to build Materials Positioning & alignment Cooling Robotisation & Industry transfer Integration issues

For all these items new solutions must be found

Silicon Envelopesurrounding TPC

SiD:all Si-tracker

TPC volume

44 Si tracking components in detector concept with TPC internal and external Si tracking components in barrel and large angle (forward/end caps) regions, acting as intermediate trackersand forming a complete coverage Si tracking system

How it compares with

SiD tracker?

Si tracking components in a detector with central TPC

Barrel

Internal barrel + forward

TPC

µvertex zone

SIT zone FTD zone

Thermal insulation

30 cm

Microvertex zone includes: µvertex + 2 disks with samepixel technology

SIT zone includes: 2 or 3 Si layers + 2 disks strips and/or pixel techno

FTD zone includes: at least 3 more disks extending from 60cm to 150cm or up to the end of

TPC length with eventually more disksThe ensemble {µvertex + SIT +FTD} is inside a thermal

insulation (under study)Nb of layers and disks & preferred techno are being

studied (preliminary simulations studies: M. Berggren)

Tiles vs Ladders ?SET if TPC ? How?

CAD & main issues for Si components: detector CAD & main issues for Si components: detector design & performancesdesign & performances

Ø203mm

~405mm

~405mm

270mm

230mm59mm

104mm

~117mm

~157mm

sensor

Projective

XUV

……..

……

..

FE electronics

foam

Si + support

EndCapTkEndCapTk

Ladders with 3 or 2 sensors

Outer ECT layers: Projective vs XUV ? Nb of layers? How to arrange them? (simu studies)

How many layers? If TPC: layers set up?TPC+ Si &/or Calo + Si

Level arm?(simu studies)

~1 – 1.3 m

Mechanical team

LPN

HE

-P

aris

Elementary modules: to be totally revisited!Elementary modules: to be totally revisited!

Ladder with 1 to 3 sensorsLadder with 1 to 3 sensors

0.7%X0

Next step = chip inserted onto the detector: connectics/VDSM/cabling issues (study starting: see SiLC meeting)

Modules: light, precise, Modules: light, precise, robust, easy to build & assemblerobust, easy to build & assembleNew sensors (next generation)Support: materials & designFE electronics connectics, packaging and cablingModule positioning on large size support structureEasy to build (robotisation ?)Industry Transfer (large #)Universal sensor vs diff. types Be innovative!

N.B. This is just a very first ladder prototype: just a very preliminary exercise…

By no means what will be the final one!!

Old fashioned FE electronics!!

Enlightening talk by Manolo Lozano IMB-CNM/CSIC @SiLC meeting

AMS handmade ladder production lineAMS handmade ladder production line

Automatized Automatized production production line at CMSline at CMS

Starting point: both expertise exist within SiLC; Need to be further developped

Robotic assembly

Probe station

LADDER PRODUCTION LINE: examplesLADDER PRODUCTION LINE: examplesG

enev

a U

niv

ersi

ty &

ET

H

Zu

rich

LIGHT COOLING (?): Thermo mechanical studiesLIGHT COOLING (?): Thermo mechanical studies

External Temp: 45°C

Si detector temp: 30°C

Cooling water Temp: 20°C

Cu screen: ~25°C

1h 2h 8h

Temp. probes

Foam insulator & cooling screen (high module C fiber) with water cooling is OK

(LPNHE-Paris)

Alignment(s)Alignment(s)

Two techniques are so far developed in the collaboration:

Frequency Scanned Interferometry (FSI) (quite advanced) Precision below 1µm by the University of Michigan Embedded Straightness Monitor (just starting) by the IFCA-Cantabria University (EUDET)

To ensure the challenging high precision performances of To ensure the challenging high precision performances of the Silicon tracking system in an ILCthe Silicon tracking system in an ILC

experiment, one crucial key issue is the alignmentexperiment, one crucial key issue is the alignment

Embedded straightness monitor - Conceptual Design

(courtesy, C. Rivero & I. Vila)

• Collimated laser beam (IR spectrum) going through silicon detector modules. The laser beam would be detected directly in the Si-modules.

• Based on previous AMS-1 experience we can project that few microns resolutions would be achieved.

• Main advantages:– Particle tracks and laser beam share the same sensors

removing the need of any mechanical transfer.– No precise positioning of the aiming of the collimators.

The number of measurements has to be redundant enough

Embedded straightness monitor - Initial R&D

IR Laser assembly

Optically treated silicon modules

Imaging/Power detector

– Silicon module surface requires special treatement to improve its optical quality

– From an optical point of view the silicon wafer will behave as a plane parallel plate.

– Dedicated ultra-stable test stand for “optical” characterization of the modified silicon modules: reflectivity, transmitance, absorption, polarization sensitivity, wedge effect, response uniformity...

Ultra-stable Survey network

Embedded straightness monitor - Initial R&D

Start up plan:– Study/selection of precise laser wavelength(s)*

adequated to the Si module sensibility.– Small laser test stand for Si-mod readout:

determine spatial resolution achievable.– Study of feasibility of optical treatment of the Si

wafer.

(*) Using more than one wavelengths may allow us to correct for “atmosferic” effects that will deflect the laser beams.

SIMULATIONSSIMULATIONS G4 geometry of the Si Envelope G4 geometry of the Si Envelope

(V. Saveliev, Obninsk St U.)(V. Saveliev, Obninsk St U.)

Ext. FWD

Ext. FWD Ext Barrel

Int. Barrel+FWD

DB description in G4 thanks to the detailed CAD

Occupancies calculated with BRAHMS full simulation (Si-Envelope+TPC), Higgstrahlung HZ with bbbar and q qbar at Ecm=500 GeVValues at most of order a few% for the hotest places in the detector!Thus medium size ladder looks to be appropriate.

Higgs event in the SiD detector design, using MOKKA G4 framework

SiD detector included in geometry DB (V. Saveliev)

A lot of work performed with fast but enough detailed simulation (SGV): See talk by M. Berggren @Vienna

But dramatically lacking a full reconstruction program in the G4 framework for complete detector concept studies.

Agreement @ SiLC meeting-Vienna to make a WW effort for Si tracking G4 reconstruction (meeting Dec 15th)

Test beams: GoalsTest beams: Goals

To qualify in conditions closest to the real life: prototypes of detectors (including New Si technologies) and of the associated FE and readout electronics.

Detection efficiency vs operational parameters Spatial resolution, cluster size Signal/Bruit Effect of magnetic field (Lorenz angle determination) Angular scans, bias scans Integration with other sub-detectors Alignment Cooling (including power cycling) In the specific & new ILC conditions.

Detector Prototypes:Detector Prototypes:Support mobile

• Design (just started)• Fabrication• Assembling & Mounting Module with 3 sensors Module with 2 sensors

Second layer partly covering the first one.

Total of 60 trapezoidal sensors,

About 10 K readout channelsReady by end 2006/beg. 2007Other prototypes: Ladders of

different sizes and sensors

Forward Prototype:under CAD study

Test beam schedule (SiLC-EUDET)Test beam schedule (SiLC-EUDET)

2007

2006

Preparation:Construction barrel prototypeNew foundry (>=512 ch + techno)

Preparation: Endcap Prototype with 128 channels(130 nm CMOS-UMC)

2008 20092005

DESY CERN?

CERN or FNAL?

PreparationLadders+ FE

tests 2 ladders,1st proto chips

Tests End Cap proto(s),with 2nd foundry chips

Tests barrel proto also combined withother sub detectorsand new foundry

These coming 4 years: 2006 to 2009 will be essential to the development of this R&D: the test beams will be instrumental to test new ideas and new prototypes on all the different aspects of this R&D (sensors, electronics, & mechanics). Look for combined test with other subdetectors. Synergy with LHC now and for future upgrade.

GOAL of SiLC R&D to develop the next generation of large area Si trackers with high

performance in spatial and momentum measurements at ILC. All R&D aspects on: SENSORS, ELECTRONICS & MECHANICS

All needed tools: SIMULATIONS, ALIGNMENT & CALIBRATIONS.

Highlights/important progress these last 2 years:Sensors: characterization of variable length strips, New Fab Lines

FE electronics in Deep SubMicron CMOS technoCAD of all tracking components both for LDC (Si Envelope) & SiD

Thermo mechanical studies

THESE NEXT FOLLOWING YEARS, PRIORITIZED R&D OBJECTIVES: Sensors: larger, thinning, pixelization, Fab Lines.

Electronics: VDSM FE readout + Connectivity + DAQ processing Mechanics: New materials,realistic CAD components, integration, protos

Alignment/position monitoring and CoolingG4-based simulations

Test beams: getting closer to real life conditions & combined tests with other major subdetectors (microvertex, calorimetry & TPC SI/NO)

Collaboration & close contacts with all 3 detector concepts

KEEPING SYNERGY with LHC (SuperLHC).