Convergent Automated Chip Level Lithography

Checking and Fixing at 45nm

Valerio Pereza, Shyue Fong Quek

a, Sky Yeo

a, Colin Hui

a, Kuang Kuo Lin

a, Walter Ng

a

Michel Coteb, Bala Kasthuri

b, Philippe Hurat

b

Matt A. Thompsonc, Chi-Min Yuan

c, Puneet Sharma

c

aChartered Semiconductor Mfg Ltd, 60 Woodlands Industrial Park D, Street2 Singapore 738406;

bCadence Design Systems, 555 River Oaks Parkway, San Jose, CA, USA 95134;

cFreescale Semiconductor, 7700 West Parmer Lane, Austin, TX, USA 78729

ABSTRACT

To provide fabless designers the same advantage as Integrated Device Manufacturer (IDMs), a design-oriented litho

model has been calibrated and an automated lithography (litho) hotspot detection and fixing flow has been implemented

during final routing optimization.

This paper shows how a design-oriented litho model was built and used to automate a litho hotspot fixing design flow.

The model, calibrated and validated against post-OPC contour data at 99%, was embedded into a Litho Physical

Analyzer (LPA) tech file. It allowed the litho contour of drawn layouts to be simulated at full chip level to detect litho

hotspots and to provide fixing guidelines. Automated hotspots fixing was hence made possible by feeding the guidelines

to the fixing tools in an industry based integrated flow. Post-fixing incremental checks were also performed to converge

to a clean design.

1. INTRODUCTION

As technology advances, designs are being scaled down to meet the ever-increasing demand for functionality contained

in a single chip. Scaling down to smaller geometry poses great challenges on silicon. One of the demanding challenges is

lithography. This is the process of printing and transferring of a design into silicon. Resolution enhancement technique

(RET) such as optical proximity correction (OPC), which introduces distortion on drawn layers to counteract the effects

of optics is widely deployed for technology nodes at 0.18um and below to improve printability and yield. Optical rule

check (ORC) is also applied to verify the correctness and fitness of the OPC operation on the layout [1-2]. These post-

processing operations are usually done by the foundry for the fabless companies. Traditionally, designers do not have the

visibility of how their layouts will look like in printing onto silicon and if there are any points in the layout that might

become litho weak points. A litho physical analyzer with the ability of accurately predicting at full chip level the post-

OPC contour and based on a calibrated OPC model can provide a reliable mean for designers to detect and repair the

litho hotspots up front in the design flow before submitting for tape-out.

2. LPA MODEL CREATION AND QUALIFICATION

To provide hotspot detection at chip level, designers must be able to simulate the silicon image of their entire design with

sufficient accuracy and minimum CPU requirements. It also requires a silicon image simulation that can easily be

supported by foundries and that integrates easily in the design flow to provide fast analysis, and convergent fixing. A

Litho Physical Analyzer (LPA) was selected for hotspot detection and fixing was done using Chip Optimizer because it

matches these requirements [3-5].

2.1 LPA model overview

The first step to set-up a convergent hotspot detection and fixing flow is to setup the silicon contour simulation

methodology. Unlike lithography simulation models that only capture the behavior of the lithography system, the LPA

model captures the entire RET/OPC manufacturing flow, including litho conditions, retargeting, assist-feature insertion,

Phase Shift Masking (PSM), and OPC information specific to the 45nm manufacturing facility. This enables an accurate

and secure LPA model to be built to provide an accurate prediction of silicon contours from the full drawn full chip

design. As explained in Section 2, such a model was jointly developed for metal layers to capture the process

performance and predict the effects of RET, OPC, litho, and mask effects on design shapes without having to run the

manufacturing flow. Designers can apply this model to their design databases to accurately predict the silicon contours

across the (focus, exposure, mask error) process window. The model is fast enough to enable simulation across the

process window of a full-chip database in hours.

Then, printability hotspots are detected using hotspot scoring functions which checks contours for dimension thresholds

(e.g. width, spacing) and lithography sensitivity metrics (e.g. sensitivity to defocus, dose, and mask error). Finally fixing

guidelines to enable automated design tools to fix hotspots with minimum perturbation and maximum convergence.

Figure 1: Litho Physical Analyzer simulates the drawn layout to predict silicon contours, detect hotspot and generate fixing guidelines

using LPA Model, which encapsulates the entire mask-making flow

When building the LPA models, additional challenges arise that are not usually faced by the engineers who develop the

post-GDSII OPC/RET flows for their respective fabs. OPC/RET engineers creating the normal silicon manufacturing

flow will create a litho model (shown on the left of Figure 1) for each of their significant layers (active, poly and metals)

using the appropriate reticles and silicon steps to replicate the structures expected when a die is processed. These

engineers would have taken measurements from wafers, usually about five hundred to a thousand measurements per

process point, and would have used their software tools to create models of the nominal process and of process points

representing the edge of the process window. These models may also represent different stages of the flow, such as a

model for resist at different process points. In a traditional manufacturing flow, the engineers use these models to

implement OPC recipes.

With LPA, the goal is to start from the drawn layout and simulate the systematic lithography effects through the process

window to capture the shape as it manifests on the wafer. To do this accurately, LPA combines the many steps involved

in the fab’s production flow into a fast, efficient platform that accurately simulates the systematic effects of what occurs

on the wafer. To do this, LPA matches the shape operations that are performed in the OPC flow using a matching model

to simulate the OPC process.

2.2 LPA Model Development Procedure

To calibrate an LPA model for the 45nm OPC/RET flow, it was necessary to match the target adjustments (retargeting)

as well as the nominal OPC model. For proper modeling across process window of the non-linear effects of RET

techniques, a through process-window Litho model was developed and scattering bar insertion was reproduced. With

these modules, LPA predicts accurately the contours across process window, and then setup for hotspot and guideline

creation has been defined.

The development flow of the LPA model is shown in Figure 2.

1. Data collection: Process information was provided, such as the lithography conditions and the RET/OPC

conditions. A retargeting and scattering bar information was provided to enable the development of LPA

retargeting and scattering bars.

2. Test pattern generation: Based on fab data, a set of calibration test patterns was created. These patterns have

been designed to not only capture the lithography effects but also to extract the retargeting and scattering bars

implementation rules. They also include some design test patterns used to calibrate and also validate the LPA

model.

3. Contour generation: These patterns were then run through the production OPC and contour-generation flow.

Based on the post-OPC layout and contour data , LPA retargeting, scattering bar insertion and litho models

were developed.

4. LPA lithography calibration: The LPA lithography modeling tools were used to create an optical model that

matched the production OPC model. To match an existing optical model requires more information than what is

needed to create a model used only for OPC implementation. While each OPC implementation tool in the

market has its own unique characteristics when creating an optical model, the LPA modeling software is

capable of calibrating to results produced by other simulation tools. To adequately match an existing model

requires more data than is usually obtained from SEM measurements alone. To build an accurate LPA model, it

is necessary to digest contours of sample layouts simulated using the production flow, and to extract four to five

thousand measurement points to thoroughly sample the models we are trying to match. For this optical model,

the LPA modeling software found the best set of illumination conditions for a given halo, a fixed number of

resist loading terms and fixed number of kernels, all in approximately 14 CPU hours on 14 2-GHz Athlon

machines. The resulting nominal model had a maximum error edge placement accuracy of 1.92 % for 5625

measurements. Two defocus models were also developed. The maximum error edge placement accuracy was

1.5 % for the negative defocus model and 1.6 % for the positive defocus model for 5625 measurements on 1D,

2D test patterns and complex topologies from sample designs.

5. Techfile development: Using LPA’s shape-based programming environment, we then implemented the

targeting adjustments and scattering bars to match the retargeting and scattering bars from the production flow.

6. LPA Contour accuracy check: Combining the litho models, the retargeting and scattering bars module, LPA can

then create contours across process windows. The validation is described in the following section.

Figure 2: LPA TechFile Development flow

7. Hotspot calibration: The hotspots are detected by applying Critical Dimension (CD) checks or sensitivity checks

on the contours. The hotspot detection was setup to consider the CD change due to dose variation of 4%,

defocus variation of 60nm and mask error of 2nm:

Based on these sensitivities, the hotspot function space can be segmented into different regions (spheres) using

different thresholds for the hotspot function. For instance, Figure 3 shows one quadrant of the hotspot sphere

based on a threshold of 0.1 (10 %). Any location that results in a point outside this sphere will be flagged as a

hotspot. For each hotspot level, different threshold are defined and each sphere representing where the

manufacturability is critical (level 1), difficult (level 2), where marginal (level 3), and good (no hotspot).

Figure 3: Process window where manufacturability is acceptable

2.3 LPA Model Validation

The LPA model for silicon-contour simulation of 45nm Metal layers was checked against contours created with the

production flow by using verification test patterns that were not used for the techfile calibration. As reported in Table 1,

the contours predicted across process window from drawn layout by LPA matched the production contours at more than

99% with a 2nm tolerance, 97.3% with 1nm tolerance and 94.6& with a 0.5nm tolerance.

0

0.02

0.04

0.06

0.08

0.1

0

0.02

0.04

0.06

0.08

0.1

0

0.02

0.04

0.06

0.08

0.1

CD

CDEXP %)4(∆

CD

nmCDDOF )60(∆

CD

nmCDMEEF )4(∆

CD

CDEXP %)4(∆

CD

nmCDDOF )60(∆

CD

nmCDMEEF )2(∆

ThresholdCD

nmCD

CD

nmCD

CD

CD MEEFDOFEXP

<��

���

� ∆+�

�

���

� ∆+�

�

���

� ∆222

)2()60(%)4(

Table 1: Contour accuracy with tolerance of 2nm, 1.5nm, 1nm and 0.5nm

The model was then further validated with industry provided sample layouts. As shown in Figure 4, the LPA contours (in

red/dark grey) was compared with the production contours (in yellow/light grey) and found a good match even in

location where manufacturability is difficult.

Figure 4: Contour comparison at U-Shape

2.0nm 1.5nm

condition layer cut_cs cs_in_CT Ratio condition layer cut_cs cs_in_CT Ratio

EnFn 300 92.22902197 91.831789 99.57% EnFn 300 92.22902197 91.54909544 99.26%

E0Fn 301 92.40148303 92.02110459 99.59% E0Fn 301 92.40154116 91.73884056 99.28%

EpFn 302 92.61511853 92.23824203 99.59% EpFn 302 92.61516516 91.97546641 99.31%

EnF0 303 92.41944169 91.98462306 99.53% EnF0 303 92.41955309 91.70825191 99.23%

E0F0 304 92.52451681 92.02391206 99.46% E0F0 304 92.52456672 91.66318159 99.07%

EpF0 305 92.65903813 91.87532503 99.15% EpF0 305 92.65900944 91.24254566 98.47%

EnFp 306 92.28602003 91.80205259 99.48% EnFp 306 92.28602294 91.50426269 99.15%

E0Fp 307 92.42639722 91.98576628 99.52% E0Fp 307 92.42645191 91.66536331 99.18%

EpFp 308 92.56319238 92.10063191 99.50% EpFp 308 92.56324628 CRASH NA

1nm 0.5nm

condition layer cut_cs cs_in_CT Ratio condition layer cut_cs cs_in_CT Ratio

EnFn 300 92.22902197 90.96662247 98.63% EnFn 300 92.22902197 89.06725041 96.57%

E0Fn 301 92.40154116 91.13841544 98.63% E0Fn 301 92.40154116 89.19074981 96.53%

EpFn 302 92.61516516 91.44302019 98.73% EpFn 302 92.61516516 89.9344085 97.11%

EnF0 303 92.41955309 91.20903222 98.69% EnF0 303 92.41955309 90.03338397 97.42%

E0F0 304 92.52456672 91.01387563 98.37% E0F0 304 92.52456672 89.81191534 97.07%

EpF0 305 92.65900944 90.19578253 97.34% EpF0 305 92.65900944 88.36035572 95.36%

EnFp 306 92.28602294 90.96382081 98.57% EnFp 306 92.28602294 89.59740169 97.09%

E0Fp 307 92.42645191 90.96716903 98.42% E0Fp 307 92.42645191 89.09386613 96.39%

EpFp 308 92.56324628 90.60715684 97.89% EpFp 308 92.56324628 87.43603922 94.46%

Figure 5 : Contour comparison at Z-shape

The comparison on the sample layout was also done across the process window as shown in Figure 6, where contours are

shown at nominal, 60nm negative defocus and 60nm positive defocus.

Nominal Defocus1 Defocus2

Ca

se T

op

Ca

se M

idd

le

Ca

se B

ott

om

Figure 6 : Contour across process windows

Finally the LPA techfile was run on several designs to calibrate the hotspot thresholds and monitor runtime. Three

categories of hotspots were defined:

• Width: detecting pinching

• Spacing: detecting bridging

• Lineend: detecting lineend pullback

For each hotspot type, three level of hotspots were defined:

• Level 1: Must-Fix hotspots. Designers are required to fix them prior to tapeout.

• Level 2: Hotspots recommended to be fixed. Designers should fix them to maximize yield.

• Level 3: These are nice to fix hotspots

The runtime reported was compiled and shown in Table 2 where distributed processing was used to reduce runtime:

Design Area Layers Number

CPUs

Runtime per

CPU

Design 1 66mm2 M2 50 2h28m

Design D 15.6mm2 M2-M5 83 13h14m

Design M 5.1mm2 M2-M5 61 3h26m

Table 2: LPA runtime

3. MODEL APPLICATION

3.1 Design flow

There are three steps involved in the detection and repair of litho hotspots. Figure 7 shows the litho hotspot detection and

repair flow. The design is developed using conventional Place and Route (P&R) tools. A GDSII format is required for

the lithography simulation. With the calibrated model, litho simulations are then performed on the GDS. Litho hotspot

markers are produced to show the exact location of each hotspot. Fixing hints are also produced to guide the chip

optimizer tool to fix the hotspot during the design optimization phase. Another round of litho simulations is again

performed to check the fixing effectiveness of the optimizer tool.

Place and Route Tool

LPA

Chip Optimizer

gds

Design phase

Lithography simulation phase

Optimization phase

Figure 7: Litho hotspot detection and repair being integration within

the conventional design flow

Litho hotspots markers

Fixing hints

3.2 LPA results and interpretation

The LPA results are categorized based on the different checks and the level of severity. Three checks are performed

according to how the model was calibrated: line end, width and spacing. Each check is divided into three levels. L1

hotspots are likely to have significant yield impact and therefore it is a must to fix. L2 hotspots have moderate impact on

yield; they should be fixed if it does not cause any other violations, L3 does not contribute a significant yield impact,

fixing them is optional.

A design was done to go through the litho detection and repair flow. As shown in Figure 8, LPA detected 15 L3 width

hotspots, 10 L2 width hotspots, 1 L3 line-end hotspot and 1 L2 line-end hotspot. No L1 hotspots were detected for this

design. Figure 9 captures some of the hotspot samples in the layout.

0

2

4

6

8

10

12

14

16

Lin

e E

nd

L1

Lin

e E

nd

L2

Lin

e E

nd

L3

Wid

th L

1

Wid

th L

2

Wid

th L

3

Sp

aci

ng L

1

Sp

aci

ng L

2

Sp

aci

ng L

3

No. of Hotspots

Hotspot

Figure 8: Number of hotspots detected by LPA on each check and level

Figure 9: Sample markers showing width hotspots overlay into the layout

3.3 Fixing results

With the use of the fixing guidelines the optimizer tool repaired all of the reported hotspots as illustrated in Figure 10.

Figure 11a shows the width hotspots before the repair and Figure 11b shows the same layout after the repair. It was

noticed that the router performed incremental re-routing across the affected area leading to a hotspot–clean layout.

0

2

4

6

8

10

12

14

16Li

ne E

nd L

1

Line

End

L2

Line

End

L3

Wid

th L

1

Wid

th L

2

Wid

th L

3

Spac

ing

L1

Spac

ing

L2

Spac

ing

L3

Before Repair

After Repair

Figure 10: Reduction of hotspots in all levels with the help of a chip optimizer

Figure 11a: Hotspot marker before

fix shows width hotspot

Figure 11b: Hotspot marker after fix

shows width hotspots are

now clean

4. CONCLUSION

This paper shows that an accurately calibrated LPA model was developed which can reflect the actual Fab lithography

environment. These calibrated models were then applied to an actual design to close any litho hotspot violations.

Hotspots that were reported were fixed, eventually leading to a higher yeild. Here, we can see that an accurately

calibrated litho model has helped the designer improve the layout by minimizing litho hotspots.

Tradionally, these checks were performed in the Fab, but with the use of these litho simulation tools and models,

designers can now predict the contours, therefore correcting any hotspot violation that may be reported. As technology

moves to smaller nodes, these checks would become a requirement within the design flow and future imrpovements

would even predict the electrical behavior using the extracted litho contours.

REFERENCES

[1] L. Scheffer, “Physical CAD changes to incorporate design for lithography and manufacturability.” in ASP-DAC, pp. 768–773,

2004. [2]

D. Pan, “Lithography-Aware Physical Design”, 2005 [3]

Chi-Min Yuan, Matt Thompson, Shyue Fong Quek, Walter Ng, Michel Cote, Bala Kasthuri, Philippe Hurat, “Lithography-

Checking Development and Deployment at 45nm” in CDNLive!2008 [4]

J. Brandenburg et al., “A Genuine Design For Manufacturing Checker for Integrated Circuit Designers”, SPIE2006 [5]

Ed Roseboom et al., “Automated Full-Chip Hotspot Detection and removal Flow for Interconnect Layers of Cell-Based

Designs”, SPIE2007