Calorimeter upgrade meeting – CERN – December 10 th 2010

Calorimeter upgrade meeting – CERN – December 10th 2010

Analog FE ASIC: first test results

Upgrade of the front end electronics of the LHCb calorimeter

E. Picatoste, A. Sanuy, D. Gascón

Universitat de Barcelona

Institut de Ciències del Cosmos ICC-UB

10/December/2010 LHCb Upgrade 2

Outline

(1) Introduction(2) Key tests on the first prototype(3) Test set-up(4) Offset(5) Noise(6) Input impedance(7) Linearity(8) Flatness: jitter of clock vs input signal


Introduction

• ECAL analogue FE IC: channel architecture

MP2MP1

Q1

Re

Ib1 MN2

MP4MP3

MN1

Rf

Vee

Vcc

1 : K : mK : mK

Ib2

Ii

Io ∫

∫

I I

Current amplifier (mirrors)

TH

TH

AnalogueMultiplexer

Drv

ADC driver

Switched integrator

Track and Hold

First Prototype


Introduction

• IC sent: ICECAL

Current preamp

Integrators


Introduction: Current mode preamplifier

• Pros:– “Natural” current processing

– Lower supply voltage

– All low impedance nodes:

• Pickup rejection

– No external components

– No extra pad

• Cons:– Trade-off in current mirrors: linearity

vs bandwidth

• Low voltage– Only 1 Vbe for the super common

base input stage

• Better in terms of ESD:– No input pad connected to any

transistor gate or base

MP2MP1

Q1

Re

Ib1 MN2

MP4MP3

MN1

Rf

Vee

Vcc

1 : K : mK : mK

Ib2

Ii

Io ∫

∫

I I

Current amplifier (mirrors)

TH

TH

AnalogueMultiplexer

Drv

ADC driver

Inner loop: lower input impedance

Outer loop: control input impedance

fem

i mRK

K

K

RgZ

11

1 1


Introduction: Integrator

• Switched integrator architecture

+

-

-

+

In+

In-Out+

Out-

FDOA

FDOA specifications

Parameter Value

Gain bandwidth

500 MHz

Phase margin > 65º

Slew rate > 2 V/μs

VCM 1.65 V

CMOS switches


M

M

Vin+

M

Vcas

VrefCE

Vout+

M

M

M

M

Vin-

M

Vcas

VrefCE

Vout-

M

MM

M

Vcmref

M

M

Vb1

Vb2 Vb2Vb2

Vb1

Vb2

Introduction: FDOA design

• Fully differential Operational Amplifier

Folded cascode

NPN CE amp

Pole compensation

RDegenertion

Common Mode

Feedback


Key tests on the first prototype

• The purpose of this prototype is to test key points of a novel circuit idea:– Input impedance control by current feedback

– Low noise performance

– Dynamic range:

• Linearity

• Also to test critical aspects of a switched solution:– Offset between subchannels

– Noise

– “Flatness” of the integrator output• Effect of jitter on clock versus signal

• Finally, the two key building blocks are prototyped separately in order to be characterized: – Current preamplifier

– Fully differential OpAmp


SCOPE

AWG2021 50 Ohms

50

cm

10m

IN OUT

ICECALDiff

ere

ntia

l P

robe

Differential Probe

50 Ohms

Test set-up

Tektronix AWG2021 Waveform Generator:

•250 MS/s•12 bit

50Ω || 50Ω = 25Ω ⇨ emulate clipping impedance

Tektronix TDS7154B Oscilloscope:

•BW = 1.7 GHz•20 GS/s•8 bit

Differential probe:•BW = 400 MHz•Cin = 1 pF


Test set-up

AWG signal

50 470

1uF

1uF

ICECALIN

sbch1

sbch2

INT

INT_BAR

CLOCKPCB

Input circuit with AC coupling and Rpar

Integrator clock signals generated with comparator

Outputs are measured at ASIC outputs and after x10 amplification


Test set-up


Offset

Offset measurement:

V at cycle end

2 ns

V offset

Preamp current offset is integrated

=> Offset at output


Offset

• About 5 % of the full scale range (2 V)• Slight asymmetry between subchanels (clock)

Distribution of the offset (12 chips)

0

1

2

3

4

5

6

7

-200 -160 -120 -80 -40 0 40 80 120 160 200

Offset [mV]

Entr

ies

Subch1Subch2Total

Subch Mean

[mV]

Std Dev

[mV]

1 27 20

2 34 35

5 % of dynamics


Distribution of offset difference between subchannels

0

0,5

1

1,5

2

2,5

3

3,5

-100 -80 -60 -40 -20 0 20 40 60 80 100

Offset difference [mV]

Entr

ies

Diff Subch1-Subch2

ABS (Diff Subch1-Subch2)

Offset

• With AC coupling between ICECAL and ADC what really matters is the difference between the offset of the 2 subchannels

• Well below the 5 % of the full scale range (2 V)

5 % of dynamics


-1,27 -1 -0,73 -0,46 -0,19 0,09 0,36 0,63 0,9 1,170

5

10

15

20

25

30

V(T0)-V(T2) (mV)

Noise after dynamic pedestal subtraction

rms = 2.29·10-4 mV

σ = 0.479 mV

-0,95 -0,74 -0,52 -0,31 -0,1 0,12 0,33 0,54 0,75 0,970

5

10

15

20

25

30

V(T0) (mV)

σ = 0.377 μVNoise

Noise: simulation

• Transient noise analysis

Integrator 1 output

Clock

Sampling time t1 Sampling time t2

• Correlated noise: distribution of V(t2)

• Uncorrelated noise: distributon of V(t1)- V(t2)

0.78 ADC counts

0.98 ADC counts


Noise

• The noise:– Generate a

histogram of the voltage value by the end of the cycle.

– Gaussian fit => standard deviation

• Noise is dominated by the differential probe at the ASIC output => use an amplifier of gain 10.


Noise• Average noise is about 1.8 ADC counts, higher than expected• Histogram is not fully Gaussian:• Noise pick-up:

– Depends on chip connection (socket)

Noise distribution for 12 chips

0

2

4

6

8

10

12

14

16

18

0,0 0,3 0,5 0,7 0,9 1,1 1,3 1,5 1,7 1,9

Noise [mV rms]

Entr

ies

Subch1Subch2Total


Noise

• Alternative method: acquire 100 waveforms and make histogram

Integrator output

-6,00E-02

-4,00E-02

-2,00E-02

0,00E+00

2,00E-02

4,00E-02

6,00E-02

8,00E-02

1,00E-01

0,00E+00 2,00E-08 4,00E-08 6,00E-08 8,00E-08 1,00E-07 1,20E-07

Time [s]

[V]

Output fluctuation at different sampling times

0

5

10

15

20

25

30

35

-10 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10

ADC counts

Entr

ies

Value @ T0

Value @ T0-50 ns

Value @ T0 - 100ns


Noise• Alternative method: acquire 100 waveforms and make histogram• Study effect of correlated sampling CDS (dynamic pedestal subtraction)

– Typically noise improves after CDS• CDS increases uncorrelated noise (HF)• CDS attenuates LF noise

– That confirms the presence of pick-up noise– After CDS noise is about 1.2 ADC counts (close to simulation:1 ADC count)


0

5

10

15

20

25

30

35

-10 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10

ADC counts

Entr

ies

Value @ T0

Value @ T0-50 ns

Value @ T0 - 100ns

Output fluctuation sampled with dynamic pedestal subtraction

0

5

10

15

20

25

30

35

40

-10 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10

ADC counts

Entr

ies

CDS 50n

CDS 100n


Noise• On very few cases noise after CDS is higher

– 1.1 ADC counts before CDS

– 1.2 ADC counts after CDS

• That means that pick up noise and the increase of uncorrelated noise by CDS are comparable


0

10

20

30

40

50

60

-10 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10

ADC counts

Entr

ies

Value @ T0

Value @ T0-50 ns

Value @ T0 - 100ns

Output fluctuation sampled with dynamic pedestal subtraction

05

101520253035404550

-10 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10

ADC counts

Entr

ies

CDS 50n

CDS 100n


SCOPE

AWG2021

50 Ohms50

cm

10m

IN OUT

ICECALDiff

eren

tial

Pro

be

Differential Probe

50 Ohms

Input impedanceWaveform Generator

-1,2

-1,0

-0,8

-0,6

-0,4

-0,2

0,0

0,2

0 25 50 75 100 125 150 175 200

t (ns)

V n

orm

aliz

ed

Clipped Pulse (Anatoli)

Test Pulse

Test Pulse Vs. Clipped Pulse

Fast pulse (no tail) to measure reflections


Input impedance

AWG signal

50 470

1uF

1uF

ICECALIN

sbch1

sbch2

INT

INT_BAR

CLOCKPCB

Rp

• PCB input circuit:– AC coupling– Rpar:

• Zin a little higher than 50Ω • Rp used to fine tune Zin


SCOPE

AWG2021

50 Ohms50

cm

10m

IN OUT

ICECALDiff

eren

tial

Pro

be

Differential Probe

50 Ohms

Input impedance

IC in

put s

igna

l

(PC

B)INT

Waveform Generator

Source signal

sbch

1sb

ch2


SCOPE

AWG2021

50 Ohms50

cm

10m

IN OUT

ICECALDiff

eren

tial

Pro

be

Differential Probe

50 Ohms

Input impedance

IC in

put s

igna

l

(PC

B)INT

Waveform Generator

Source signal

sbch

1sb

ch2

ICECAL OFF

Large reflections


Input impedance

Source (AWG)

IC input (PCB)

Out sbch1Out sbch2

INT

Reflection coefficients

Reflection Coefficients for source, IC input, and output signals.

Refl. Coeff. = 1st pulse integral / 2nd pulse integral


Input impedance

• Optimal Rp is between 360 and 390 ohm• Dynamic variation of input impedance is << 1 % for full dynamic (50 pC)• Measurement error for second reflection is quite high for low amplitudes

– Noise of the differential probe

Impedance adaptation

-5

-4

-3

-2

-1

0

1

2

3

4

5

0,0E+00 1,0E-11 2,0E-11 3,0E-11 4,0E-11 5,0E-11 6,0E-11 7,0E-11PM delivered charge [C]

Area

Coe

ffici

et [%

]

First Reflection

Second reflection

Integrator output

Rp = 360 Ohm

Impedance adaptation

-5

-4

-3

-2

-1

0

1

2

3

4

5

0,0E+00 1,0E-11 2,0E-11 3,0E-11 4,0E-11 5,0E-11 6,0E-11 7,0E-11

PM delivered charge [C]

Area

Coe

ffici

et [%

]

First Reflection

Second reflection

Integrator output

Rp = 390 Ohm


Input impedance

• Dispersion is low: < 0.5 %– Only 5 chips have been measured

Rp = 360 Ohm

Histogram of input impedance matching for 5 chips

0

1

2

3

4

5

6

7

8

-2,5 -2 -1,5 -1 -0,5 0 0,5 1 1,5 2 2,5

Area coeffcient [%]

Entr

ies

First

Second

Int Output

Mean

[%]

Std Dev

[%]

First 1,99 0,21

Second -1,75 0,43

Int output

-0,82 0,11


ICECAL linearity

0,00

0,50

1,00

1,50

2,00

2,50

3,00

3,50

0,0E+00 2,0E-11 4,0E-11 6,0E-11 8,0E-11 1,0E-10 1,2E-10PM delivered charge [C]

Inte

grat

or o

utpu

t [V] Chip1 Subch1

Chip1 Subch2Chip2 Subch1Chip2 Subch2Chip6 Subch1Chip8 Subch1Chip8 Subch2Chip9 Subch1Chip9 subch2Chip6 Subch2

Linearity• Dynamic range is ok (50 pC required)• Rp (input impedance) affects the amount of charge sensed by the ASIC

– Rp 360 Ohm: negative reflection coefficient: lower amplitude @ ICECAL input– Rp 390 Ohm: positive reflection coefficient: higher amplitude @ ICECAL input

Rp = 360 Ohm

Rp = 390 Ohm


0

0,5

1

1,5

2

2,5

3

3,5

32 32,4 32,8 33,2 33,6 34 34,4 34,8 35,2 35,6 36

Gain [mV/pC]

Entr

ies

Subch1

Subch2

Linearity

• Slight sistematic difference between subchannels (clock)

Rp = 360 Ohm

Rp = 390 Ohm

Subch Mean

[mV/pC]

Std Dev

[mV/pC]

1 34,43 0,27

2 34,18 0,18


Linearity• Relative linearity error is below 1% for the full range (50 pC)• Very difficult calibration of the measurement system:

– Scope vertical scale and attenuation of the probe– Cross-check using calibrated attenuators

• Problems with very low amplitudes: see next slides– Still well below 1 % of the Full Scale

ICECAL linearity relative error

-5,0-4,0-3,0-2,0-1,00,01,02,03,04,05,0


Rela

tive

erro

r [%

]

Chip1 Subch1Chip1 Subch2Chip2 Subch1Chip2 Subch2Chip6 Subch1Chip8 Subch1Chip9 Subch1Chip9 Subch2+1% of Full Scale-1% of Full ScaleChip6 Subch2


Linearity• What happens at low amplitudes?• Problem with AWG generator:

– Different signal delay as fucntion of the amplitude (advanced for low amp)– Again, it can be bypassed using calibrated attenuators

Normalized input pulse for diferent amplitudes

-0,2

0

0,2

0,4

0,6

0,8

1

1,2

5,0E-8 5,5E-8 6,0E-8 6,5E-8 7,0E-8 7,5E-8 8,0E-8 8,5E-8 9,0E-8 9,5E-8 1,0E-7

Time [s]

No

rma

lize

d a

mp

litu

de

Low AWG amplitude (<500 mV)

Medium AWG amplitude


Linearity

• Adding some delay for low AWG amplitudes corrects the problem

• In that case, relative linearity error is well below 1 % even for low amplitudes

ICECAL linearity relative error

-5,0-4,0-3,0-2,0-1,00,01,02,03,04,05,0


Rela

tive

erro

r [%

]

Chip6 Subch1

Chip6 Subch1 delay -1n for low amp

Chip6 Subch1 delay -2n for low amp


Flatness at the integrator output

• Problem: – Due to clock jitter, the

signal at the output must be stable (<1%) for 4 ns.

• Input signal: – AWG generated similar to

clipped (see next slide)

• Method:– Delay clock signal in 1ns

increments

– Use LEMO cable (minimum number of cables, 0 to 3)

– Measure output signal and analyze

SCOPE

AWG 2021

50 Ohms

50cm

10m

IN OUT

ICECALDiff

eren

tial

Pro

be

Differential Probe

50 Ohms

Marker

LEMO delay

Setup:

CLOCK



Waveform Generator signal vs. Measured clipped signal (Anatoli)

-1,2

-1,0

-0,8

-0,6

-0,4

-0,2

0,0

0,2

0 25 50 75 100 125 150 175 200

t (ns)

V n

orm

aliz

ed

Clipped Pulse (Anatoli)

Test Pulse



• The output variation is smaller than 1% for about 3 ns delay variation– Consistent for different signal amplitudes

• Can be improved using a resistor in parallel to the integrator capacitor– See next talk

Effect of time alingment (signal versus clock)

-5

-4

-3

-2

-1

0

1

2

3

4

5

-10 -5 0 5 10

Delay variation [ns]

Re

lati

ve

va

ria

tio

n [

%]

150 mV output600 mV output1.2 V output

Documents

Calorimeter upgrade meeting – CERN – December 10 th 2010