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Bram Teetaert
wireless communicationDesign of a time-interleaved sampling platform for 60GHz
Academic year 2015-2016Faculty of Engineering and ArchitectureChair: Prof. dr. ir. Daniël De ZutterDepartment of Information Technology
Master of Science in Electrical EngineeringMaster's dissertation submitted in order to obtain the academic degree of
Counsellors: Haolin Li, Prof. dr. ir. Johan Bauwelinck, Hannes RamonSupervisors: Prof. dr. ir. Guy Torfs, Prof. dr. ir. Dries Vande Ginste
Bram Teetaert
wireless communicationDesign of a time-interleaved sampling platform for 60GHz
Academic year 2015-2016Faculty of Engineering and ArchitectureChair: Prof. dr. ir. Daniël De ZutterDepartment of Information Technology
Master of Science in Electrical EngineeringMaster's dissertation submitted in order to obtain the academic degree of
Counsellors: Haolin Li, Prof. dr. ir. Johan Bauwelinck, Hannes RamonSupervisors: Prof. dr. ir. Guy Torfs, Prof. dr. ir. Dries Vande Ginste
Preface
Working on this master’s dissertation showed me a lot of steps in the design cycle of a wirelessreceiver back end. It has been very interesting and I’m grateful for the knowledge and insightsI acquired. I want to thank prof. dr. ir. Guy Torfs, Hannes Ramon and Haolin Li for their closeinvolvement, the regular follow-up and the sharing of their knowledge. Their contributionhas been of major importance during the making of this master’s dissertation. Furthermore, Ithank prof. dr. ir. Johan Bauwelinck for making it possible to do my thesis at his departmentand I thank Jan Gillis for helping with the review of the PCB layout.
A special thanks goes to my family, friends and Saskia for their listening ears and their spokenand unspoken support. Finally, I’m glad I could spend a lot of time in the lab with Bert, Laurensand Michiel. They were very entertaining and also their help is appreciated a lot.
i
Permission to Consult
The author gives permission to make this master dissertation available for consultation and tocopy parts of this master dissertation for personal use. In the case of any other use, the copy-right terms have to be respected, in particular with regard to the obligation to state expresslythe source when quoting results from this master dissertation.
Bram Teetaert, May 31
ii
Design of a time-interleaved sampling platformfor 60GHz wireless communication
by
Bram TEETAERT
Master’s dissertation submitted in order to obtain the academic degree of Master of Science inElectrical Engineering
Academic year 2015-2016
Supervisors: Prof. dr. ir. Guy TORFS, Prof. dr. ir. Dries Vande GINSTE
Counsellors: Prof. dr. ir. Johan BAUWELINCK, ir. Haolin LI, ir. Hannes RAMON
Faculty of Engineering and ArchitectureGhent University
Department of Information TechnologyChairman: Prof. dr. ir. Daniel DE ZUTTER
Abstract - With the exploding number of wireless devices, the need for more spectrum is grow-ing. The 60 GHz band, positioned between 57 GHz and 66 GHz, provides a globally unlicensedband with a bandwidth that is an order of magnitude higher than what is available up to 7 GHz.To use this band at full power, appropriate receivers are necessary. In this master’s dissertation,a broadband sampling platform is developed for this purpose. A high bandwidth is achievedin an economical way by the use of 2 time interleaved ADCs. For fast data acquisition, thesampling platform is co-designed with a digital design on FPGA.
Keywords - 60 GHz, time interleaved, FPGA, Analog-to-Digital Converter.
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Design of a time-interleaved sampling platform for60GHz wireless communication
Bram TeetaertProf. dr. ir. Guy Torfs, Prof. dr. ir. Dries Vande Ginste, Prof. dr. ir. Johan Bauwelinck
ir. Hannes Ramon, ir. Haolin Li
Abstract—With the exploding number of wireless devices, theneed for more spectrum is growing. The 60 GHz band, positionedbetween 57 GHz and 66 GHz, provides a globally unlicensed bandwith a bandwidth that is an order of magnitude higher thanwhat is available up to 7 GHz. To use this band at full power,appropriate receivers are necessary. In this master’s dissertation,a broadband sampling platform is developed for this purpose. Ahigh bandwidth is achieved in an economical way by the use of2 time interleaved ADCs. For fast data acquisition, the samplingplatform is co-designed with a digital design on FPGA.
Index Terms—60 GHz, time interleaved, FPGA, Analog-to-Digital Converter
I. INTRODUCTION
The number of wireless devices is exploding and at thesame time, the devices become more demanding in termsof bandwidth. To cope with future bandwidth shortage, the60 GHz band, positioned between 57 GHz and 66 GHz, isbecoming an important topic in research and development. Inthis master’s dissertation, a broadband sampling platform isdeveloped to serve as back-end for a commercially available 60GHz wireless receiver from Hittite (HMC6001LP711E). Thisreceiver can demodulate signals with a bandwidth up to 1.8GHz and its phase noise and quadrature balance allow digitalmodulation formats up to 16-QAM. With this information,specifications can be derived to build a system architectureand the feasibility of this architecture is checked with extensivesimulations.
II. DESIGN OF THE SAMPLING PLATFORM
A. System architecture
The purpose is to analyse the analog baseband I and Qoutputs of the 60 GHz receiver. A conversion to the digitaldomain is necessary and for this a sampling platform isdesigned of which the functional block diagram is shown inFig. 1. The output signals of the 60 GHz receiver have avarying amplitude depending on received power and receiverconfiguration. To cope with this uncertainty, variable gainamplifiers (AD8370) are used to dynamically change the inputsignal amplitude to the Full-Scale Range (FSR) of the ADCs.As the receiver supports a bandwidth up to 1.8 GHz, an idealsample rate of 3.6 GSPS is necessary which is very highto be obtained by a single, commercially available ADC. Asolution is found in the use of time-interleaved ADCs. Thistechnique allows a multiplication of the sample rate of oneADC with the number of ADCs in the system. In this design,
ADC1 ADC2 clk
VGAQ VGAI
FPGA
60 GHz receiver
I Q
Fig. 1. System architecture of the sampling platform.
the sample rate of the selected ADC (ADC08DL502) is 500MSPS and by using 2 of these ADCs, a sample rate of 1GSPS is obtained. Both ADCs are clocked with clocks equalin frequency and 180 out of phase. Consequently, they havedifferent sampling instants that are equally distributed in time.This is illustrated in Fig. 2. The two high-rate clock signals
Fig. 2. A waveform sampled with 2 interleaved ADCs. The samples of ADC1 are represented with • and the samples of ADC 2 are represented with N.
are provided by a clock generator (AD9523-1) that has twointernal phase-locked loops and an external voltage controlledcrystal oscillator for extra low-jitter performance. Finally, theoutputs of the ADCs are connected to the KC705 evaluationboard carrying a Kintex-7 FPGA. This FPGA will capture the2 GBps data stream generated by the ADCs and will also serveto configure the components on the sampling platform usinga serial interface.
B. Performance analysis of 2 interleaved ADCs
Simulations show that the interleaving of 2 ADCs usuallyresults in signal distortion due to component imperfections.The effect of three possible imperfections is analysed: clockphase mismatch (the clock signals of the 2 ADCs are notexactly 180 out of phase), unequal gain error and offset error.A clock phase mismatch generates an amplitude modulation
2
of the sampled signal resulting in a spurious component withinthe Nyquist bandwidth. The effect is worse for higher inputfrequencies. In Fig. 3, the results of a clock phase mismatchsimulation are visualised. The Signal-to-Noise Ratio (SNR)
0 5 10 15
SN
R [d
B]
15
20
25
30
35
40
45
50
55
degrees
EN
OB
2.2
3
3.9
4.7
5.5
6.4
7.2
8
8.8
10 MHz50 MHz150 MHz250 MHz400 MHz500 MHz
0 2 4 6 8 10 mm
Fig. 3. SNR and ENOB of the interleaved ADC system in function of clockphase mismatch and equivalently trace length difference in mm based on asignal speed of 1.42 · 108 m/s.
and Effective Number Of Bits (ENOB) in function of degreesclock phase mismatch can be seen. A cause of clock phasemismatch is a different length of the clock traces on the PCBand this length is also seen on the second x-axis in the figure. Anext thing to look into is gain error, a result of Full-Scale Error(FSE). An unequal gain error of both ADCs also results in anamplitude modulation. The severity of the effect can be seen inthe simulation results in Fig. 4. The FSEs used in the figure are
FSE ADC 1 [mV]-25 -20 -15 -10 -5 0 5 10 15 20 25
SN
R [d
B]
20
25
30
35
40
45
50
55
EN
OB
3
3.9
4.7
5.5
6.4
7.2
8
8.8
FSE ADC 2: -25mVFSE ADC 2: 0mVFSE ADC 2: 25mV
Fig. 4. SNR and ENOB of an interleaved ADC system for a varying FSEfor both ADCs and fin=149.66MHz.
the possible FSEs of the selected ADC component. It can beseen that the effect of gain errors can be quite severe resultingin a resolution loss up to 4 bits. However, the effect can becorrected by post-processing the samples. Also the effect ofoffset error is simulated but with a typical offset error of acalibrated ADC, the effect is limited to a loss of 0.5 bits in aworst case situation.
III. DATA ACQUISITION ON FPGA
The ADCs produce a data stream of 2 GBps. In order to testthe performance of the sampling platform, the output of bothADCs in a certain time-interval is saved in the Block Random
Access Memory (BRAM) on the Kintex-7 FPGA. After that,the captured data is sent to a computer using a slower serialinterface after which interleaving of the data streams can bedone and the performance can be measured.
IV. PERFORMANCE MEASUREMENTS
The phase noise of the sampling clocks generated by theclock generator have an important influence on the ENOBof the ADCs. The phase noise of the 500 MHz clock signalis plotted in Fig. 5. The integrated phase jitter from 10 Hz
frequency [Hz]101 102 103 104 105 106
pow
er [d
Bc/
Hz]
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
Fig. 5. Phase noise of the clock generator 500 MHz output.
to 1 MHz is equal to 4 ps. This phase jitter sets an upperlimit on the ENOB of 7 bits at 250 MHz and 6 bits at500 MHz. Actual ENOB measurements are performed forseveral frequencies using the sinewave curve fitting method.The results can be seen in Fig. 6. The datasheet of the ADC
frequency [MHz]0 50 100 150 200 250 300 350 400 450 500
EN
OB
3
3.5
4
4.5
5
5.5
6
6.5
1 ADC 500 MSPS2 ADCs 1GSPS: uncorrected2 ADCs 1GSPS: offset and gain correction2 ADCs 1GSPS: offset, gain and timing correction
Fig. 6. ENOB measurements for a single ADC at 500 MSPS and for 2interleaved ADCs at 1 GSPS. Also the ENOB after digital error compensationis plotted.
specifies an ENOB of 7.5 bits at 125 MHz. For a single ADC,the ENOB is on average 6.2 bits meaning that 1.3 bits are lost.This is caused by non-linearities of the VGAs and ADCs, noisefrom clock jitter and other types of noise (thermal...). For theinterleaved output using 2 ADCs, at frequencies below theNyquist frequency of a single ADC, the ENOB is lower thanthe ENOB of a single ADC. This is mainly due to clock phasemismatch and gain errors. Beyond the Nyquist frequency ofa single ADC, the ENOB drops quickly. Gain errors can beestimated and corrected leading to a substantial increase in
3
ENOB as can be seen in Fig. 6. Also clock phase mismatch canbe compensated by interpolating with a Lagrange interpolationfilter [1]. This leads to an additional increase in ENOB asshown in Fig. 6.
V. CONCLUSION
A sampling platform for 60 GHz wireless communication isdeveloped with a bandwidth of 500 MHz. The ENOB is higherthan 5.7 bits up to 450 MHz after a digital error compensation.
REFERENCES
[1] C. A. Schmidt, “Efficient estimation and correction ofmismatch errors in time-interleaved adcs,” IEEE Trans-actions on Instrumentation and Measurement, 2016.
Contents
Preface i
Permission to Consult ii
Abstract iii
1 Introduction 1
2 System Design 22.1 60 GHz transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 System requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.3 Design block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.4 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4.1 DC performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.4.2 AC performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Time-interleaving of ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Analysis of the Interleaved ADC System 123.1 Coherent sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.2 Simulink model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3 Interleaving 2 ADCs: analysis with a single sinusoid . . . . . . . . . . . . . . . . . 13
3.3.1 The ideal system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.3.2 Clock phase mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.3.3 Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.3.4 Gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Interleaving 2 ADCs: analysis with digitally modulated signals . . . . . . . . . . 203.4.1 Clock phase mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.4.2 Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.4.3 Gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.4.4 IQ gain mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.4.5 IQ phase mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
vii
4 Printed Circuit Board Design 274.1 Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.1 Analog-to-Digital Converter (ADC) selection . . . . . . . . . . . . . . . . . 274.1.2 Clock generator selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284.1.3 Variable Gain Amplifier (VGA) selection . . . . . . . . . . . . . . . . . . . 304.1.4 Component interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324.3 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344.4 Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354.5 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5 Digital Design 385.1 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1.1 The SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385.1.2 Flexible high level SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . 405.1.3 Linking the SPI block with the high level interface . . . . . . . . . . . . . . 41
5.2 Data acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425.2.1 The ADC data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425.2.2 The memory options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425.2.3 The data acquisition system . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3 Constraining the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455.3.1 Physical constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455.3.2 Timing constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6 Measuring System Characteristics and Performance 476.1 Linearity of the transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.2 The clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486.3 Performance of the ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506.4 Performance of the interleaved ADC system . . . . . . . . . . . . . . . . . . . . . 52
6.4.1 Performance without error compensation . . . . . . . . . . . . . . . . . . . 526.4.2 Performance with error compensation . . . . . . . . . . . . . . . . . . . . . 53
Conclusion and Future Work 56
Appendix A 60.1 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
List of Figures
2.1 Illustration of the Hittite transceiver system. The spectra at the input and outputand the spectrum of the RF signal are shown to illustrate the bandwidth andcarrier frequency of the system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Block diagram of the HMC6000LP711E transmitter chip, illustrating its super-heterodyne architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 Block diagram of the HMC6001LP711E receiver chip, illustrating its superhetero-dyne architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.4 Block diagram of the proposed architecture for the sampling platform. . . . . . . 52.5 Illustration of how a waveform is sampled in an interleaved sampling system
with 2 ADCs . The samples of ADC 1 are represented with • and the samples ofADC 2 are represented with N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6 The ideal ADC transfer characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . 62.7 An illustration of offset error, gain error and full-scale error. The red line is the
ideal transfer characteristic. The solid blue line is the actual transfer characteristic. 72.8 An illustration of differential non-linearity. . . . . . . . . . . . . . . . . . . . . . . 82.9 An output spectrum of an ADC when a single frequency tone is sampled. The
Spurious-Free Dynamic Range is indicated. . . . . . . . . . . . . . . . . . . . . . . 92.10 Schematic representation of a system with N time-interleaved ADCs. . . . . . . . 10
3.1 Simulink model for the total interleaved ADC system. . . . . . . . . . . . . . . . . 133.2 Simulink model of the ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3 Simulink model of the error block. . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.4 DFT spectrum of the output of the interleaved ADC system without errors and
fin = 149.66 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.5 DFT spectrum of the output of the interleaved ADC system with a clock phase
mismatch of 5 and fin=149.66MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . 163.6 SNR and ENOB of the interleaved ADC system in function of clock phase mis-
match and equivalently trace length difference in mm based on a signal speed of1.42 · 108 m/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ix
3.7 DFT spectrum of the output of the interleaved ADC system with an offset er-ror of -0.45 LSB for one ADC and zero offset error for the other ADC withfin=149.66MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8 The signal that is superimposed on the output signal the interleaved system withADC 1 having an offset error of a en ADC 2 having an offset error of b. . . . . . . 18
3.9 SNR and ENOB of the interleaved ADC system with a varying offset error andfin = 149.66MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10 DFT spectrum of the output of the interleaved ADC system with a FSE of 25 mVfor ADC 1 and a FSE of 0 for ADC 2 and fin=149.66MHz. . . . . . . . . . . . . . . 19
3.11 Signal-to-Noise Ratio (SNR) and Effective Number Of Bits (ENOB) of an in-terleaved ADC system for a varying Full-Scale Error (FSE) for both ADCs andfin=149.66MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Constellation diagrams at the output of the interleaved ADC system with a 13
clock phase mismatch at 500 Mbaud. . . . . . . . . . . . . . . . . . . . . . . . . . . 213.13 Error Vector Magnitude (EVM) of the interleaved ADC system with a varying
clock phase mismatch and a 4-QAM modulation scheme. . . . . . . . . . . . . . . 223.14 EVM of the interleaved ADC system with a varying offset error, fs=500 Mbaud
and a 4-QAM modulation scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.15 Constellation diagrams of the output of the interleaved ADC system with a FSE
of -25mV for both ADCs at 500 Mbaud. . . . . . . . . . . . . . . . . . . . . . . . . 233.16 Constellation diagrams of the output of the interleaved ADC system with a FSE
of −25mV for both ADCs at 500 Mbaud for 64-QAM, with and without errorcompensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17 Constellation diagrams of the output of the interleaved ADC system with a FSEof −25mV for ADC 1 and 25mV for ADC 2 at 500 Mbaud for 64-QAM with andwithout error compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.18 EVM for the output of an interleaved ADC system with a varying FSE for bothADCs at 500Mbaud with a 4-QAM constellation. . . . . . . . . . . . . . . . . . . . 25
3.19 EVM for the output of an interleaved ADC system with varying IQ gain mis-match at 500 Mbaud for a 4-QAM constellation. . . . . . . . . . . . . . . . . . . . 26
3.20 EVM for the output of an interleaved ADC system with varying IQ phase mis-match for a 4-QAM constellation. The phase delay of the I channel is in functionof the trace length difference on a stackup with a signal speed of 1.42e8 m/s andwith this speed, 1 mm corresponds to a delay of 7 ps. . . . . . . . . . . . . . . . . 26
4.1 Basic block diagram of the AD9523-1 clock generator. PFD = Phase FrequencyDetector, CP = Charge Pump, LF = Loop Filter, V(X)CO = Voltage Controlled(Crystal) Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2 S-parameters of the resistive power splitter from a VGA to 2 ADCs. . . . . . . . . 314.3 Thermal resistance from Printed Circuit Board (PCB) copper foil to ambient in
function of the copper foil area [12]. . . . . . . . . . . . . . . . . . . . . . . . . . . 334.4 Schematic diagram of the power distribution system (LDO = Low-Dropout Reg-
ulator, SW = SWitching regulator). . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5 Dimensions of the matched microstrips. . . . . . . . . . . . . . . . . . . . . . . . . 374.6 Dimensions of the matched striplines. . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.1 Waveform describing the IO behaviour of the used Serial Peripheral Interface(SPI) block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2 The block structure of the MicroBlaze processor with its most important periph-erals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3 Block diagram of the SPI interface system. . . . . . . . . . . . . . . . . . . . . . . . 415.4 Illustration of Double Data Rate (DDR) data transfer. DATA 1 is how the data
should be captured. DATA 2 represents the way the data arrives at the FPGA,meaning a 90 phase shift should be applied to DCLK before capturing the data. 42
5.5 Waveforms describing operations with a Block Random Access Memory (BRAM)module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.6 The generation of 4 data streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445.7 Illustration of the data-transfer towards the BRAM and the reading back of the
data using MicroBlaze peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1 An IIP3 measurement of the complete wireless link at 100 MHz for the followingVGA configuration: Intermediate Frequency (IF) at Tx: 0 dB attenuation, IF atRx: 0 dB attenuation, baseband at Rx: 24 dB attenuation. . . . . . . . . . . . . . . 48
6.2 Spectrum of the clock generator 500 MHz output with the first PLL disabled. TheVoltage Controlled Crystal Oscillator (VCXO) serves as reference for the secondPLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3 Phase noise of the clock generator 500 MHz output with an external 3.125 MHzreference, with the first PLL disabled and the 100 MHz VCXO output as referenceand with a 25 MHz reference clock from the FPGA. . . . . . . . . . . . . . . . . . 50
6.4 Theoretical ENOB in function of frequency for the 3 phase jitter values from the3 clock configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.5 Measured frequency spectrum of the output of a single ADC with an input toneof 149.9 MHz and an external clock as clock reference. . . . . . . . . . . . . . . . . 51
6.6 Measured frequency spectrum of the interleaved output of both ADCs with aninput tone of 323.9 MHz and an external clock as clock reference. . . . . . . . . . 52
6.7 Measured ENOB in function of frequency for a single ADC and for the inter-leaved system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.8 Output spectra of a sampled 323.9 MHz tone. Error compensation is applied toenhance the ENOB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.9 ENOB in function of frequency for the interleaved system with and without errorcompensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10 Schematic of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6011 Schematic of the clock generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6112 Schematic of the VGA ’s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6213 Schematic of the power supply, part 1. . . . . . . . . . . . . . . . . . . . . . . . . . 6314 Schematic of the power supply, part 2. . . . . . . . . . . . . . . . . . . . . . . . . . 6415 Layout of the top layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
16 Layout of layer 2: the ground plane. . . . . . . . . . . . . . . . . . . . . . . . . . . 6617 Layout of layer 3: signal layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6718 Layout of layer 4: signal layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6819 Layout of layer 5: power plane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6920 Layout of the bottom layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7021 Picture of the soldered PCB mounted on the KC705 evaluation board. . . . . . . . 71
Acronyms
ADC Analog-to-Digital Converter
AXI Advanced eXtensible Interface
BRAM Block Random Access Memory
DDR Double Data Rate
DFT Discrete Fourier Transform
EMI Electro-Magnetic Emission
ENOB Effective Number Of Bits
EVM Error Vector Magnitude
FFT Fast Fourier Transform
FMC FPGA Mezzanine Card
FSE Full-Scale Error
FSR Full-Scale Range
GPIO General Purpose Input/Output
HPC High Pin Count
IF Intermediate Frequency
LDO Low Dropout Regulator
LO Local Oscillator
LSB Least Significant Bit
LVDS Low-Voltage Differential Signalling
xiii
Chapter 0 xiv
LVPECL Low-Voltage Positive Emitter-Coupled Logic
PCB Printed Circuit Board
PLL Phase-Locked Loop
RISC Reduced Instruction Set Computer
SINAD Signal-to-Noise and Distortion Ratio
SMPS Switched-Mode Power Supply
SNR Signal-to-Noise Ratio
SPI Serial Peripheral Interface
UART Universal Asynchronous Receiver/Transmitter
VCO Voltage Controlled Oscillator
VCXO Voltage Controlled Crystal Oscillator
VGA Variable Gain Amplifier
1Introduction
With the exploding number of wireless devices, the need for more spectrum is growing. Nowa-days the unlicensed 2.5G and 5G bands serve wireless applications worldwide but the band-width in these frequency bands is limited. Higher in the spectrum, the 60G band, positionedbetween 57 GHz and 66 GHz [1], provides a globally unlicensed band with a bandwidth, anorder of magnitude higher than what is available up to 7G. This provides a great opportunityfor high data rate applications. Nevertheless, 60G wireless communication comes with advan-tages and disadvantages. Inherent for this high frequency is the high propagation attenuation,according to Friis formula, enhancing a denser reuse of the spectrum. On the other hand thisrestricts its use to short distance links only. This can be partly overcome because antennas for60G can be very directional, providing a high antenna gain. These antennas can be made verysmall (the smallest dimension can be about half a wavelength which is 2.5 mm at 60 GHz),just as the RF components, which is desirable in mobile applications. Additionally, millimetre-wave design comes with great challenges concerning limited amplifier gain, excessive phasenoise and expensive RF front ends.
With some pros and cons, 60G wireless communication is a promising technology. In the lightof this, a broadband sampling platform serving as back end for a commercially available 60Gwireless link is designed in this master’s dissertation. Accompanying this platform, configura-tion and test hardware is designed, enabling extensive testing of the device.
In Chapter 2 the specifications for building the sampling platform are derived and a systemarchitecture is elaborated.In Chapter 3 a feasibility study done by performing extensive simulations.In Chapter 4 the design of the printed circuit board is explained and in Chapter 5 the digitaldesign on FPGA is elaborated.Finally, Chapter 6 describes the results and measurements after which a conclusion is drawnand possibilities for future work are listed.
1
2System Design
As a start, the necessary specifications of the sampling platform to be designed, are derived andanalysed. The needed input/output characteristics are defined after which a system architec-ture is proposed. Finally, imperfections in the input/output behaviour have to be consideredand the necessary information is given to understand every step in the design process.
2.1 60 GHz transceivers
The half-duplex wireless link that is considered, is set up with the HMC6000LP711E transmitterchip [2] and the HMC6001LP711E receiver chip [3] from Hittite. The wireless link they provideis accessible through an analog baseband IQ interface as illustrated in Figure 2.1. The systemallows a 1.8 GHz modulation bandwidth and wireless operation on a carrier of 57 to 64 GHz.The phase noise and quadrature balance of the chips allow digital modulation formats up to16-QAM. Both the receiver and the transmitter have a superheterodyne architecture meaning
HMC6000LP711E
TX Q
I HMC6001LP711E
RX Q
I
1.8 GHz 60 GHz 1.8 GHz
Figure 2.1: Illustration of the Hittite transceiver system. The spectra at the input and outputand the spectrum of the RF signal are shown to illustrate the bandwidth and carrier frequencyof the system.
that their functionality is based on mixing signals with a Local Oscillator (LO) signal to make
2
Chapter 2 3
the conversion from and to an Intermediate Frequency (IF) [4]. The basic block diagram of thetransmitter can be seen in Figure 2.2. The conversion from baseband to IF and from IF to RF is
0°
90° F1 F2 F3
PA
./2 X3
16.3 GHz – 18.3 GHz
I
Q
Figure 2.2: Block diagram of the HMC6000LP711E transmitter chip, illustrating its superhetero-dyne architecture.
done with clock signals derived from a common clock. This common clock is created by an in-tegrated low-phase noise frequency synthesiser that uses an external clock signal as reference.The common clock has a frequency that is tunable between 16.3 GHz and 18.3 GHz in 500 MHzsteps. In this way, frequency selectivity is created. The common clock is divided by 2 resultingin a frequency between 8.1 GHz and 9.1 GHz. After this it is mixed directly, or after a 90 phaseshift, with the incoming in phase (I) and quadrature (Q) baseband signals respectively, to createan IF signal with a frequency between 8.1 GHz and 9.1 GHz. The filter F1 is used to discardthe unwanted mixing products. Then, a Variable Gain Amplifier (VGA) amplifies the signal.The amplification factor can be configured by the user using a serial interface. The signal againpasses through a filter F2 before it is mixed with a 48.9 GHz to 54.9 GHz clock signal that iscreated by multiplying the common clock by 3. Unwanted mixing products are again filteredby F3 after which a power amplifier sends the signal to an antenna.
The basic block diagram of the receiver can be seen in Figure 2.3. The same method is used
0°
90° F1 F2 F3 LNA
X3 ./2
16.3 GHz – 18.3 GHz
FBB I
Q FBB
Figure 2.3: Block diagram of the HMC6001LP711E receiver chip, illustrating its superhetero-dyne architecture.
Chapter 2 4
here to obtain frequency selectivity: a common clock tunable from 16.3 GHz to 18.3 GHz thatis multiplied by 3 and divided by 2 to obtain the right mixing frequencies. When entering thereceiver at the antenna, the signal is amplified with a Low Noise Amplifier (LNA) for a goodreception sensitivity. Next, a filter F1 removes unwanted frequency components before mixingthe signal to IF . Undesired mixing products are discarded with F2 and therefore the dynamicrange of the subsequent VGA can be relaxed making it possible to have a high and stable gain.After filtering again with F3, I and Q signals are distracted by mixing with an in phase LOand a quadrature LO respectively. Undesired mixing products are again discarded with FBB
and the user can apply a variable amplification factor before retrieving the data at the I and Qoutput pins.
The several VGAs in the transceivers can be configured by the user using a serial interface. Thesettings of these VGAs have an influence on the linear character of the wireless link. Nextto the distance between the transmitter and the receiver and the environment of the wire-less link, the VGA settings also have an influence on the overall gain of the link. This isdiscussed quantitatively in Chapter 6, where results of IIP3 measurements with several VGAconfigurations are given. The testing is done with the 60 GHz Antenna-in-Package TransceiverEvaluation Kit from Hittite. This kit contains two transceiver boards that are equipped withboth the HMC6000LP711E transmitter and the HMC6001LP711E receiver. Configuration of thetransceivers on both boards is possible using a USB computer connection.
2.2 System requirements
The goal is to analyse the output of the Hittite HMC6001LP711E receiver chip. This outputconsists of 2 differential analog baseband signals, one differential pair for the in-phase compo-nent of the received signal and the other differential pair for the quadrature component of thereceived signal. The outputs are AC coupled to the connectors on the evaluation boards andare terminated differentially in 100Ω. The outputs have to be sampled to allow digital process-ing of the received signal meaning that a sampling platform has to be build. These receivedsignals can have a bandwidth up to 1.8 GHz. Consequently, according to the Nyquist criterion,a sample rate of at least 3.6 GSPS is required in order to explore the full bandwidth. In prac-tice, a sample rate of 3.6 GSPS is technically and economically difficult so a solution has to befound to achieve an acceptable bandwidth while keeping complexity and price low. Next tothe sample rate, also the resolution of the sampling process has minimum requirements. Asthe transceivers allow digital modulation up to 16-QAM, a minimal resolution of 2 bits is nec-essary for both the I and the Q signal. More bits are needed to cope with accuracy losses due tonoise and non-linearities. Additionally, for improved signal analysis, more bits are favourableas well.
2.3 Design block diagram
The block diagram of the proposed architecture for the sampling platform is shown in Figure2.4. The input signals for the sampling platform originate from the 60 GHz receiver block.
Chapter 2 5
ADC1 ADC2 clk
VGAQ VGAI
FPGA
60 GHz receiver I Q
Figure 2.4: Block diagram of the proposed architecture for the sampling platform.
According to the datasheet of the receiver, these in-phase and quadrature signals have a peak-peak amplitude of 10mVpp-200mVpp with a typical value of 50mVpp. These signals should beamplified in order to obtain a peak-peak amplitude equal to the Full-Scale Range (FSR) of theAnalog-to-Digital Converter (ADC) because the full resolution of an ADC is only used whenthe input peak-to-peak voltage is equal to the FSR of the ADC . This will require an amplifyingcomponent of which the gain can be controlled in a dynamic way, in other words a VGA . Now,the peak-peak voltage of the I and Q signals can be controlled to have a fixed value at the outputand the signals are ready for the next stage, sampling. As explained in the previous section,the ideal sample rate is very high to be obtained by a single, commercially available ADC in away that is technically and economically not too difficult. A solution for this is found in the useof time-interleaved ADCs. Time-interleaving of ADCs allows a multiplication of the sample
t t+1 t+2 t+3 t+4 t+5 t+6 t+7 t+8
Figure 2.5: Illustration of how a waveform is sampled in an interleaved sampling system with 2ADCs . The samples of ADC 1 are represented with • and the samples of ADC 2 are representedwith N.
rate of one ADC with the number of ADCs in the system. In this design, 2 ADCs are used forinterleaving. In that case both ADCs are clocked with signals of equal frequency that are 180
Chapter 2 6
out of phase. Consequently, they have different sampling instants that are equally distributedin time. This is illustrated in Figure 2.5. Using 2 interleaved ADCs results in doubling thesample rate of the used ADC component while keeping complexity below certain limits. Theuse of 2 ADCs implicates that the I and Q signals will each drive 2 ADCs . This means thatthe VGAs should be able to provide enough buffering for these signals. The ADCs have to bepaced by two high rate clocks 180 out of phase. To generate these clock signals, the systemuses a low-jitter clock generator.Finally, the digital ADC outputs need to be processed. Because the sample rate is high, this hasto be done by a hardware component. For this purpose an FPGA will be used. The FPGA willalso serve to configure the clock generator, the VGAs and the ADCs.
2.4 ADC characteristics
The ADC is a key element in this design so in order to make the right design choices one has tounderstand the most important specifications that determine its performance. The ideal trans-fer characteristic of an ADC should be as in Figure 2.6. There are a discrete number of output
𝑉𝐼𝑁
𝑉𝑂𝑈𝑇
FSR
1 LSB
Figure 2.6: The ideal ADC transfer characteristic.
values/quantization levels. If N bits are used to represent the output, 2N output values areavailable. The input voltage range that is mapped onto one single output value is referred toas 1 Least Significant Bit (LSB) . The FSR is the input range in which every input step of 1 LSBresults in a different output value. A real ADC will not have the ideal transfer characteristicfrom Figure 2.6. Several deviations can be defined and are quantified in the component speci-fications. They are categorised in two ways: DC performance and AC (dynamic) performance.
2.4.1 DC performance
The DC performance relates to static errors. The most important ones are quantization error,offset error, Full-Scale Error (FSE) and differential non-linearity. These errors are visible whena constant or slowly varying signal is sampled by the ADC .
Chapter 2 7
• Quantization errors are inherent to quantization, they are unavoidable and can not becorrected. The error has a value between -1/2 LSB and +1/2 LSB . Quantization causesnoise and, for an N-bit ADC , results in a signal-to-noise ratio as given by [5]:
SNR = 6.02N + 1.76 dB (2.1)
• Offset error is the value of the input voltage that results in a zero output voltage. Ifnot dealt with, an offset error results in a smaller FSR and DC errors in the sampledsignal. Usually, offset error can be trimmed, either by the ADC component or by digitalprocessing. It should be noted that this is only possible if correct estimations of the offseterror can be made, at any time.
• Positive Full-Scale Error is defined as the difference between the input voltage that resultsin the highest possible code in the actual ADC and the input voltage that would result inthe highest possible code in the ideal ADC . A negative FSE is defined in the same way forthe lowest possible code. In the following it is considered that positive FSE and negativeFSE are equal and both are referred to as FSE .
• Gain error is an effect caused by FSE and has as a result that the slope of the transfercharacteristic differs from ideal value of 1. It is equal to the FSE minus the offset error.A negative gain error results in unused codes and a positive gain error results in unusedanalog input range. Usually, a gain error can be corrected in software by dividing theindividual samples with the gain error. However, for this to be possible, a good estimatefor the gain error is needed at any time. The relationships between gain error, offset errorand FSE are clarified in Figure 2.7.
𝑉𝐼𝑁
𝑉𝑂𝑈𝑇 FSE
Offset error
Gain error
Figure 2.7: An illustration of offset error, gain error and full-scale error. The red line is the idealtransfer characteristic. The solid blue line is the actual transfer characteristic.
• Differential non-linearity (DNL) is the deviation from the ideal step size of 1 LSB. Inother words, it describes the distance between neighbouring codes. DNL is illustratedin Figure 2.8. If the DNL is larger than or equal to +1 or smaller than or equal to -1, acode is skipped which is called a missing code. In a component datasheet, the maximumDNL can be specified. Also specified in datasheets is the integral of all differential non-linearities: the integral non-linearity (INL). DNLs cannot be corrected and usually theycan be minimised by a correct calibration of the ADC .
Chapter 2 8
𝑉𝐼𝑁
𝑉𝑂𝑈𝑇
1 LSB
1.5 LSB
0.5 LSB
1 LSB
DNL = 0
DNL = 0.5
DNL = -0.5
DNL = 0
Figure 2.8: An illustration of differential non-linearity.
2.4.2 AC performance
AC performance describes the performance of the ADC up to the Nyquist frequency. One wayof testing the AC performance is by sampling a single frequency tone that has a peak-peakamplitude equal to the FSR of the ADC . At the output, the Discrete Fourier Transform (DFT)spectrum can be calculated and the Signal-to-Noise Ratio (SNR) can be extracted. In the SNRcalculation, the signal component is the output signal at the input frequency. The noise com-ponent in the SNR includes thermal noise, noise from clock jitter, quantization noise, harmonicspurs and so on. Usually, spurious components are not included in the SNR calculation andalso in this discussion this is not done. Quantization noise is already discussed in the previoussection and is inherent to the sampling process. The other kinds of noise: thermal noise andnoise originating from clock jitter are influenced by the circuit implementation and are calledcircuit noise. They are discussed below.
Jitter on the sampling clock leads to an imperfection in the time at which a sample is taken andintroduces noise. The RMS error of the time at which the sample is taken is denoted by ta. If asine wave with frequency fin is used as an input, the highest error caused by jitter on the clockis at the zero-crossing of the waveform. At this point the slope of the waveform is given by
d
dtsin(2πfint)
∣∣∣∣t=0
= 2πfin
The rms value of the voltage error made at this point is 2πfinta. SNRjitter can now be derivedas:
SNRjitter = 20 log
(1
2πfinta
)(2.2)
Thermal noise imposes a fundamental limitation on ADC performance. In this discussion itis supposed that the thermal noise completely originates from the input source resistance Rin.The input FSR of the ADC is VFSR [V], the absolute temperature is T [K] and the sample rate isfs. If a single frequency tone with a peak-peak amplitude equal to VFSR is sampled, the SNR
Chapter 2 9
due to thermal noise is equal to [6]:
SNRthermal = 10 log
(V 2FS
16kTRinfs
)In this equation, k is Boltzmann’s constant. The total SNR including SNRjitter and SNRthermal
can be calculated starting from the signal power Ps, the clock jitter noise power Pjitter and thethermal noise power Pthermal. The total SNR is equal to:
SNR =Ps
Pjitter + Pthermal
=
(Pjitter
Ps+
Pthermal
Ps
)−1=
(SNRjitter + SNRthermal
)−1=
(V 2FS
16kTRinfs+ (2πfinta)
2
)−1Finally, this can be expressed in dB:
SNR = −10 log
(V 2FS
16kTRinfs+ (2πfinta)
2
)(2.3)
In the discussion above, spurious components are not considered for calculating the SNR .These components are present in the output spectrum of an ADC because of non-linearitiesand they should be considered while evaluating the ADC performance because they have alarge influence on the signal quality. An example of a measure for evaluating spurious effectsis Spurious-Free Dynamic Range (SFDR). The SFDR is indicated in Figure 2.9. It is defined as
𝑓𝑠2
SFDR
f [Hz]
A [dB]
Figure 2.9: An output spectrum of an ADC when a single frequency tone is sampled. TheSpurious-Free Dynamic Range is indicated.
the ratio (in dB) of the power at the output of the input signal to the worst spurious componentin the output signal. Other measures for non-linearities include total harmonic distortion and3rd order intercept point.
Chapter 2 10
A key specification of ADCs is Effective Number Of Bits (ENOB) . The formula for ENOB isderived from equation 2.1 using Signal-to-Noise and Distortion Ratio (SINAD) instead of SNRand is given by:
ENOB =SINAD− 1.76
6.02(2.4)
Next to quantization noise, thermal noise and noise due to clock jitter, the SINAD also includesharmonic distortion. The formula for ENOB is dependent on frequency because the SINAD isfrequency dependent because harmonic distortion and noise due to clock jitter are frequencydependent.
A last AC characteristic of ADCs that is worth mentioning is full-power bandwidth. This isa measure for the frequency at which a signal at the ADC output drops 3 dB in comparisonwith the signal at the ADC input that has a full-scale amplitude. This full-power bandwidthcan be much higher than the Nyquist bandwidth and this is important in an interleaved ADCsystem because frequencies higher than the Nyquist frequencies of the individual ADCs can besampled and reconstructed.
2.5 Time-interleaving of ADCs
In order to increase the sampling rate of a system, one can time-interleave the outputs of mul-tiple ADCs . In this design interleaving is done with 2 ADCs . Interleaving can also be donewith more than 2 ADCs and this is illustrated in Figure 2.10 for N ADCs . Every ADC is driven
𝑥(𝑡)
𝑓𝑠
φ1 = 0
ADC1 ADC2 ADCN … φ2 =2π
𝑁 φ𝑁 =
2π
𝑁(𝑁 − 1)
MUX
𝑓𝑠 𝑓𝑠
𝑁𝑓𝑠
…
𝑦[𝑛]
Figure 2.10: Schematic representation of a system with N time-interleaved ADCs.
by a sampling clock with frequency fs. In order to have a uniform distribution of the sampleinstants, the sampling clock input of ADCn is delayed in time with respect to the clock inputof ADC1, providing an exact phase shift of ϕn = 2π
N (n − 1). The combined sampled outputy[n] contains Nfs samples per second so the sampling rate of the system is multiplied by the
Chapter 2 11
number of ADCs in the system.In an ideal system the output y[n] of the configuration of Figure 2.10 would be
y[n] = x
(n
Nfs
)= x[n]
In a real system however y[n] 6= x[n]. This is due to:
• Imperfections of the single ADC elements.
• The differences in imperfections of the single ADC elements.
• Clock phase mismatch: the clock phase shift ϕ of ADCn is not exactly equal to ϕn =2πN (n− 1).
• Sampling clock jitter.
The origin of a clock phase mismatch can originate from imperfections in the output phasesof the clock generator component or it can arise due to a difference in trace length on thePCB carrying the components. In chapter 3, the effect and severity of several imperfectionsis discussed.
3Analysis of the Interleaved ADC
System
In the following, a system of 2 interleaved Analog-to-Digital Converters (ADCs) is simulated.The performance of the system will be evaluated by calculating the Signal-to-Noise Ratio (SNR)or, equivalently, the Effective Number Of Bits (ENOB). Also the Error Vector Magnitude (EVM)is evaluated to assess the effect of the non-idealities on digitally modulated signals.
3.1 Coherent sampling
To calculate the SNR, a single frequency signal is sampled and the Discrete Fourier Transform(DFT) of the output signal is calculated, to find the power at the input frequency. Generally,the power of the input signal will be distributed over several DFT bins and one should applywindowing to evaluate the output power in a correct manner. Usually, this technique willintroduce errors in signal magnitudes. For this reason, a windowing technique is not used hereand the smearing out of frequency components is avoided by getting the signal energy of asingle sinusoid into 1 DFT bin. To obtain this, one can choose the input frequency fin in orderto have an integer number of cycles M, included in the N samples that are used to calculate theDFT. With a sample frequency fs, the number of cycles M is equal to
M = N · finfs
(3.1)
Sampling using the relationship from equation (3.1) with M integer is called coherent sampling.To be able to use the Fast Fourier Transform (FFT), N is chosen a power of 2. To make sure thatthe same samples are not repeated, M is chosen to be a prime number. The value of M is derivedstarting from the sampling frequency fs, the used value of N and the desired input frequency
12
Chapter 3 13
fin. With these values and equation (3.1), M is chosen to be the closest prime number and theaccompanying new value of fin is calculated and used for the simulation.
3.2 Simulink model
The simulations are done using Matlab and Simulink. A simulink model with the block dia-gram from Figure 3.1 was build. The model includes 2 ADCs that have an internal structure
ADC1
ADC2
²
CLK
transport delay
ERROR
ERROR
Figure 3.1: Simulink model for the total interleaved ADC system.
as shown in Figure 3.2. The sampling is done by a sample-and-hold block after which thissampled signal is quantized using a certain amount of bits. The ADCs are clocked by the CLK
S/H
CLK
IN OUT
Figure 3.2: Simulink model of the ADC.
block. ADC1 is clocked directly and ADC2 receives the clock through a transport delay block.Ideally this block applies a 180 phase shift. However, to introduce a clock phase mismatch,this phase shift will be adjusted to deviate from the ideal sampling moment. The signal to besampled is generated by a sine wave source block. Before going to the ADC blocks, the errorblock can add an offset to the signal to simulate an offset error or multiply the signal with again to simulate a Full-Scale Error (FSE). The structure of the error block is shown in Figure 3.3in which K is the gain factor and C is the offset.
3.3 Interleaving 2 ADCs: analysis with a single sinusoid
In this section, simulations are performed using the system from section 3.2. The goal is to anal-yse SNR and ENOB. The parameters and specifications used for every simulation are shown inthe table below. Also the typical specifications for the ADCs that are considered for this designare shown in the table below.
Chapter 3 14
K
C
IN OUT
Figure 3.3: Simulink model of the error block.
Clock frequency 500 MHzTotal sample rate 1 GSPSTotal bandwidth 500 MHzADC resolution 8 bits
Input full scale range 840 mVpp
To use the complete input Full-Scale Range (FSR) , the input sine wave always has an ampli-tude of 840 mVpp unless specified differently. To calculate the DFT, the number of samples Nis chosen equal to N = 212. The value of M determines the frequency of the input signal. Forexample, for the input frequency fin = 149.66 MHz, M is equal to the prime number 613.With this model and these parameters, the system is tested for SNR and ENOB under 4 situa-tions. The first one is the ideal system that has no clock phase mismatch, no FSE and no offseterror. The subsequent systems introduce a clock phase mismatch, an offset error and a FSErespectively.
3.3.1 The ideal system
As a start, the accuracy of the system is evaluated by sampling a 150 MHz pure sine wave,with no clock phase mismatch, no offset error and no FSE. The closest coherent frequency(fin = 149.66 MHz) is used for better accuracy. The output spectrum of the time-interleavedsampled signal is shown in Figure 3.4. The peak at f = 149.66 MHz has a magnitude of−7.5 dBwhich is equal to 20 · log(0.42) as expected. The noise power is calculated as the total power ofthe spectrum with the bin at f = 149.66 MHz set to zero. Calculating this noise power, the SNRis equal to SNR = 50 dB. According to equation (2.4) this corresponds to 8.01 ENOB proving thecorrectness of the model. This is also verified for the input frequency range from fin = 1 MHzto fin = 500 MHz.As observed from Figure 3.4 the DFT noise floor is at ≈ −90 dB which does not correspond tothe expected value of:
−50dB− 7.5dB = −57.5dB
This is an effect of the DFT and can be explained as follows. If N bins are used, and the totalnoise power is Pnoise,tot, then the noise power per bin is equal to Pnoise,tot/(N/2) (only powersin the half sided spectrum are considered). Taking the logarithm one can find
DTF noise in a bin = 10 log(Pnoise,tot)− 10 logN/2
Chapter 3 15
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 108
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f [Hz]
20lo
g(A
)
Figure 3.4: DFT spectrum of the output of the interleaved ADC system without errors and fin= 149.66 MHz.
This means that the DFT noise floor is 10 log(N/2)dB lower than the actual noise floor. For N =212 as in Figure 3.4, one calculates 10 log(N/2) = 33 dB so the DFT noise floor is at:
−7.5dB− 50dB− 33dB = −90.5dB
This noise floor value can be visually verified.
3.3.2 Clock phase mismatch
A clock phase mismatch is introduced by using the transport delay block from Figure 3.1. Theideal setting for the transport delay is 180. In a first test, this is changed to 185 which cor-responds to 5 degrees clock phase mismatch. An input frequency of fin=149.66 MHz is usedand the output spectrum is shown in Figure 3.5. A peak at f=149.66 MHz is observed as wellas some power in the 350.34 MHz bin. This second peak will degrade SNR and ENOB . To ex-plain this, one can see that the sampled signal is a repetitive sequence of a correct sample anda sample that is taken a the wrong moment. The error on the second sample scales with themagnitude of the phase mismatch and the amplitude of the input signal at that instant. It alsoscales with the input signal frequency since sampling at the wrong time instance is more severeif the value to be sampled changes rapidly. This erroneous sample pattern can be seen as anamplitude modulation of the signal with a modulation frequency of 500 MHz. This introducespower at 149.66 MHz + 500 MHz = 649.66 MHz. After sampling this component is mirrored to350.34 MHz and this is observed in Figure 3.5.In Figure 3.6 the simulation is performed for several input frequencies and clock phase mis-matches. As one of the sources of clock phase mismatch is a difference in trace length of theclock signal traces on the Printed Circuit Board (PCB), this trace length difference is also shownin the Figure on the x-axis. The signal speed used for this illustration is 1.42 · 108 m/s which
Chapter 3 16
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 108
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f [Hz]
20lo
g(A
)
Figure 3.5: DFT spectrum of the output of the interleaved ADC system with a clock phasemismatch of 5 and fin=149.66MHz.
is equal to the signal speed with the stackup used in this design. It is observed that the SNRdegrades more rapidly for high input signal frequencies, as explained above. Within the range0 to 15 phase mismatch, the effect of this error is negligible for input frequencies lower than10 MHz. For the highest possible input frequency of 500 MHz, the effect of clock phase mis-match is very severe with only 2.6 bits left for a 15 error. It is clear that this kind of error has tobe avoided. On PCB however, one can easily keep the trace length difference of the clock linesbelow 500 µm, in this way minimizing this concern.
3.3.3 Offset Error
An offset error is introduced in each ADC by adding a constant to the signal entering the ADCusing the error block from Figure 3.1. An offset error of 0.45 Least Significant Bit (LSB) is atypical maximum value for a calibrated ADC. In Figure 3.7 the output spectrum is shown ofa sampled 149.66 MHz sine wave with ADC 1 having an offset error of -0.45 LSB and ADC 2having no offset error. In the output spectrum, a DC component and a component at 500 MHzare present, both degrading the SNR. The origin of these components is different from the caseof a clock phase mismatch where the error at a certain sampling instant is dependent of theamplitude of the signal, thereby introducing an amplitude modulation. For offset error, theerror in the sampled signal is independent of the amplitude of the signal at any time. Supposethat ADC 1 has an offset error a and ADC 2 has an offset error b. On the output signal, the signalfrom Figure 3.8 is superimposed. Time t corresponds to the sample instant of ADC 2, time t+ 1
corresponds to the sample instant of ADC 1, and so on. The amplitude of this superimposedsignal is |a − b|/2, the offset of this signal is (a + b)/2 and the frequency of this signal is equalto the sample frequency of a single ADC. Suppose a sine wave with angular frequency ω0 is
Chapter 3 17
0 5 10 15
SN
R [d
B]
15
20
25
30
35
40
45
50
55
degrees
EN
OB
2.2
3
3.9
4.7
5.5
6.4
7.2
8
8.8
10 MHz50 MHz150 MHz250 MHz400 MHz500 MHz
0 2 4 6 8 10 mm
Figure 3.6: SNR and ENOB of the interleaved ADC system in function of clock phase mismatchand equivalently trace length difference in mm based on a signal speed of 1.42 · 108 m/s.
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 108
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f [Hz]
20lo
g(A
)
Figure 3.7: DFT spectrum of the output of the interleaved ADC system with an offset error of-0.45 LSB for one ADC and zero offset error for the other ADC with fin=149.66MHz.
sampled with a total sample frequency 2ωs. At the output of the interleaved sampling systemone observes:
cos(ω0t) +a+ b
2+|a− b|
2cos(ωst)
Chapter 3 18
𝑎
𝑏
0 𝑎 + 𝑏
2
|𝑎 − 𝑏|
2
t t+1 t+2 t+3 t+4 t+5 t+6 t+7
Figure 3.8: The signal that is superimposed on the output signal the interleaved system withADC 1 having an offset error of a en ADC 2 having an offset error of b.
The DFT of this signal indeed contains a component at DC and a component at ωs next to thedesired component at ω0. To check the correctness of this theory, it is verified that for a = b, theonly undesired component is at DC and for a = −b, the only undesired component is at ωs.In Figure 3.9, ADC 2 gets an offset as specified in the legend and ADC 1 gets an offset accordingto the x-axis. First of all it is observed that, for the offset errors used in the plot, the effect of anoffset error on the ENOB of the interleaved system is rather small. Second, it is observed thatthe SNR is exactly the same if ADC 2 has an offset of b = −0.45 LSB or b = +0.45 LSB. Thisis according to the theory: in the table below, the amplitude and offset of the superimposedsignal is given if the offset of ADC 1 is a (the unit of the figures in the table is LSB):
b = 0.45 b = -0.45component at DC (a+0.45)/2 (a-0.45)/2component at ωs (0.45-a)/2 (0.45 + a)/2
One observes that for both b = 0.45 and b = −0.45 the sum of the magnitudes of the com-ponents at DC and at ωs is the same which explaines what is observed in Figure 3.9. In anycase, offset error has a small effect and in modern ADCs it can be tuned up to 0.05 LSB, therebyalmost nullifying the problem.
3.3.4 Gain error
Datasheets of ADCs specify a maximum absolute value of a positive FSE and a negative FSE.From this a gain factor m can be calculated graphically (for example from Figure 2.7) as:
m =FSR/2
FSR/2 + FSE
For FSE = +25 mV and FSE = -25 mV this results in m = 0.9438 and m = 1.0633 respectively fora FSR of 840 mVpp. These values can be used as gain factor in the error block from Figure 3.1.In Figure 3.10 the output spectrum of a sampled signal with frequency fin = 149.66 MHz isshown. The model was configured for ADC 1 to have a FSE of 25 mV and ADC 2 having noFSE. A component at 149.66 MHz is observed together with a peak at 350.34 MHz, degradingthe SNR. This results from the sequence of one correct sample and one sample affected bya gain factor. Just as with clock phase mismatch this introduces an amplitude modulationwith 500 MHz resulting in a component at 649.66 MHz which is mirrored to 350.34 MHz after
Chapter 3 19
0ffset ADC 1 [LSB]0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
SN
R [d
B]
46
47
48
49
50
51
EN
OB
7.3
7.5
7.7
7.8
8
8.2
only ADC 1, half sample rateinterleaved, ADC 2: offset -0.45LSBinterleaved, ADC 2: offset 0interleaved, ADC 2: offset 0.45LSB
Figure 3.9: SNR and ENOB of the interleaved ADC system with a varying offset error and fin
= 149.66MHz.
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 108
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f [Hz]
20lo
g(A
)
Figure 3.10: DFT spectrum of the output of the interleaved ADC system with a FSE of 25 mVfor ADC 1 and a FSE of 0 for ADC 2 and fin=149.66MHz.
sampling. A difference with clock phase mismatch however is that the error is independent ofthe signal frequency. In Figure 3.11, ADC 2 has a FSE as shown in the legend and ADC 1 hasa FSE according to the x-axis. It is observed that only a difference in gain error causes a lowSNR. If both errors are the same and negative, no bits are lost but only the FSR gets smaller. Ifboth errors are the same and positive, a small amount of bits is lost, not due to the amplitude
Chapter 3 20
FSE ADC 1 [mV]-25 -20 -15 -10 -5 0 5 10 15 20 25
SN
R [d
B]
20
25
30
35
40
45
50
55
EN
OB
3
3.9
4.7
5.5
6.4
7.2
8
8.8
FSE ADC 2: -25mVFSE ADC 2: 0mVFSE ADC 2: 25mV
Figure 3.11: SNR and ENOB of an interleaved ADC system for a varying FSE for both ADCsand fin=149.66MHz.
modulation but because it is inherent to positive FSE. If the gain error is known, it can becorrected by dividing the samples of the erroneous ADC by the gain error corresponding withthat ADC. In the situation of one ADC having a +25 mV FSE ant the other one having a -25 mVFSE, the SNR of the corrected signal can be improved to 49.7 dB. This shows that gain error canbe almost nullified if the error can be measured.
3.4 Interleaving 2 ADCs: analysis with digitally modulated signals
In this section, the same situations as in section 3.3 are analysed with digitally modulated sig-nals instead of with a single sinusoid. Errors are evaluated using the Error Vector Magnitude(EVM) which is expressed in dB and defined here as:
EVM = 10 log
(PerrorPsent
)[dB] (3.2)
In this equation, Psent is the total power of all symbols that are sent over the link and Perror isthe total power of the error vectors, defined as the vectors from the sent symbols to the receivedsymbols.Several QAM modulation schemes are considered and the modulation and demodulation aredone using a root-raised-cosine filter with a roll-off factor of 0.2. In the model of Figure 3.1 ev-ery ADC is replaced by 2 ADCs for the I and the Q channel. Furthermore, the same parametersapply as in section 3.3. They are repeated here for convenience:
Clock frequency 500 MHzTotal sample rate 1 GSPSTotal bandwidth 500 MHzADC resolution 8 bits
Chapter 3 21
The FSR of the ADCs will be adapted to the maximal signal amplitude present in the signal.Next to clock phase mismatch, offset error and gain error it is necessary to also include a gainand phase mismatch between the I and the Q channel in the discussion.
3.4.1 Clock phase mismatch
In Figure 3.12 scatter diagrams are shown for 4-QAM, 16-QAM and 64-QAM constellations.The data rate is 500 Mbaud and a clock phase mismatch of 13 is introduced, correspondingto a trace length difference of about 1 cm of the clock traces. Due to erroneous sample in-stants, clouds of received symbols are formed and EVM degrades, reducing the noise margin.In Figure 3.13, clock phase mismatch is varied and EVM is calculated for different symbol rates.
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
real(x)
imag
(x)
(a) 4QAM
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
real(x)
imag
(x)
(b) 16QAM
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
real(x)
imag
(x)
(c) 64QAM
Figure 3.12: Constellation diagrams at the output of the interleaved ADC system with a 13
clock phase mismatch at 500 Mbaud.
For the ideal situation of 0 clock phase mismatch, EVM varies for different symbol rates be-cause there are less samples per symbol for higher symbol rates (2 samples per symbol for 500Mbaud, 4 samples per symbol for 250 Mbaud...). Next to this, EVM degrades quickly with ris-ing clock phase mismatch. The EVM boundary for 64-QAM detection is estimated at −22 dBand is visualised by a line in the figure.
Chapter 3 22
0 5 10 15
EV
M [d
B]
-60
-55
-50
-45
-40
-35
-30
-25
-20
degrees
500 Mbaud333 Mbaud250 Mbaud166 Mbaud100 Mbaud
0 2 4 6 8 10 mm
Figure 3.13: EVM of the interleaved ADC system with a varying clock phase mismatch and a4-QAM modulation scheme.
3.4.2 Offset Error
An offset error of maximally 0.45 LSB is considered. In Figure 3.14 the offset error of ADC 2is varied in the legend and the offset error of ADC 1 is varied along the x-axis. It can be seen
offset ADC 1 [LSB]0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
EV
M [d
B]
-51
-50
-49
-48
-47
-46
-45
-44
-43
-42
offset ADC 2: -0.45LSBoffset ADC 2: 0offset ADC 2: 0.45LSB
Figure 3.14: EVM of the interleaved ADC system with a varying offset error, fs=500 Mbaudand a 4-QAM modulation scheme.
that the EVM is lowest when the offset (a + b)/2 of the superimposed signal from Figure 3.8
Chapter 3 23
has the smallest absolute value. This can be seen at a = 0, b = 0 and a = 0.45 LSB , b = −0.45
LSB . The reason for this is that the received signal is subjected to the receive filter which has alow-pass characteristic resulting in a filtering of the AC component of the superimposed signalfrom Figure 3.8.
3.4.3 Gain error
The gain errors applied in this section are again based on a maximal FSE value of± 25 mV witha FSR of 840 mVpp. In Figure 3.15 the effect of a FSE of both ADCs of -25 mV is shown on a4-QAM and 16-QAM constellation with a data rate of 500 Mbaud. In Figure 3.16 the same error
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
real(x)
imag
(x)
(a) 4-QAM
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
real(x)
imag
(x)
(b) 16-QAM
Figure 3.15: Constellation diagrams of the output of the interleaved ADC system with a FSE of-25mV for both ADCs at 500 Mbaud.
configuration is applied on a 64-QAM constellation. To compensate the error, one can dividethe erroneous samples by the gain error. The scatter diagram belonging to the compensatedsignal is also shown in Figure 3.16. In Figure 3.17 the effect of different gain errors on a 64-
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
real(x)
imag
(x)
(a) No compensation for gain error
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
real(x)
imag
(x)
(b) Compensation for gain error
Figure 3.16: Constellation diagrams of the output of the interleaved ADC system with a FSE of−25mV for both ADCs at 500 Mbaud for 64-QAM, with and without error compensation.
Chapter 3 24
QAM constellation is shown. The scatter diagrams of the original and the compensated signalare visualised. With this compensation, the EVM is brought from −34 dB to −47 dB. In Figure
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
real(x)
imag
(x)
(a) No compensation for gain error
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
real(x)
imag
(x)
(b) Compensation for gain error
Figure 3.17: Constellation diagrams of the output of the interleaved ADC system with a FSEof −25mV for ADC 1 and 25mV for ADC 2 at 500 Mbaud for 64-QAM with and without errorcompensation.
3.18 the FSE of ADC 2 is varied according to the legend and the FSE of ADC 2 is varied along thex-axis. Also, the detection boundary for 64-QAM, estimated at -22 dB, is plotted as a horizontalline on the figure. A symbol rate of 500 Mbaud is used and the EVM is independent of this rate.The highest EVM is obtained if both errors are the same. In comparison with the discussion ofsection 3.3 this is very different because there the best case situation for the SNR occurred if botherrors were the same. The reason for this is that an equal gain error preserves the frequencycomponents in the signal, thereby not effecting SNR because the gain is also very small. ForQAM formats however, amplitude is critical and EVM will be affected at any kind of gainerror configuration as can be seen in Figure 3.18. It is noted that in reality, digital receivers areequipped with an automatic gain control loop. This will correct the gain error if both FSEs areequal. If both FSEs are unequal, a modulation of the signal occurs, as explained in section 3.3.4.This cannot be corrected by an automatic gain correction loop. The effect of unequal FSEs canbe observed on figure 3.18 as well. Lets consider the case in which the error of ADC 2 remainsat -25 mV. If the error of ADC 1 is varied from -25 mV to +25 mV is is observed that the EVMdrops. This can be explained by looking at the samples: one sample will get a gain higher than1 while the next sample will get a gain lower than 1. When low-pass filtering with the receivefilter, this high frequency error is smoothed, resulting in a lower EVM. Also, for a positive FSE,bits are lost resulting in a slightly higher EVM for positive FSE in comparison with negativeFSE.
Chapter 3 25
FSE ADC 1 [mV]-25 -20 -15 -10 -5 0 5 10 15 20 25
EV
M [d
B]
-55
-50
-45
-40
-35
-30
-25
-20
FSE ADC 2: -25mVFSE ADC 2: 0mVFSE ADC 2: 25mV
Figure 3.18: EVM for the output of an interleaved ADC system with a varying FSE for bothADCs at 500Mbaud with a 4-QAM constellation.
3.4.4 IQ gain mismatch
As can be seen on the block diagram of Figure 2.4, the I and the Q signal are amplified bydifferent Variable Gain Amplifiers (VGAs). In this way, a difference in amplification factor givesrise to a gain mismatch between the I channel and the Q channel. A typical gain resolution ofa VGA is less than or equal to 1 dB. In Figure 3.19 the gain of the Q channel is varied in thelegend and the gain of the I channel is varied along the x-axis. Also, the detection boundaryfor 64-QAM, estimated at -22 dB, is plotted as a horizontal line on the figure. It is clear that agood gain resolution of the VGAs is critical to enable the use of dense constellation schemes.
3.4.5 IQ phase mismatch
As the I and Q signals travel along different paths and through different VGAs, a phase dif-ference between both signals can be present upon entering the ADCs. If it is supposed thatthe ADCs sample the I and Q component at the exact same instant, an error will be introduced.This IQ phase mismatch is simulated and can be seen in Figure 3.20. Also, the detection bound-ary for 64-QAM, estimated at -22 dB, is plotted as a horizontal line on the figure. On the x-axisof this figure, delay is represented as trace length difference in mm. The signal speed used tocalculate this is 1.42e8 m/s, a typical speed for the PCB stackup that will be used in this design.From this, a phase difference of 1 mm corresponds to a phase difference of 7 ps. As timing ismore critical at high frequencies, the EVM is higher for the same phase error when the symbolrate is higher.
Chapter 3 26
gain error I [dB]-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
EV
M [d
B]
-55
-50
-45
-40
-35
-30
-25
-20
-15
gain eror Q: 0 dBgain eror Q: 0.1 dBgain eror Q: 0.3 dBgain eror Q: 0.5 dBgain eror Q: 1 dB
Figure 3.19: EVM for the output of an interleaved ADC system with varying IQ gain mismatchat 500 Mbaud for a 4-QAM constellation.
delay I channel [mm]0 1 2 3 4 5 6 7 8 9 10
EV
M [d
B]
-55
-50
-45
-40
-35
-30
-25
-20
500 Mbaud333 Mbaud250 Mbaud166 Mbaud100 Mbaud
Figure 3.20: EVM for the output of an interleaved ADC system with varying IQ phase mis-match for a 4-QAM constellation. The phase delay of the I channel is in function of the tracelength difference on a stackup with a signal speed of 1.42e8 m/s and with this speed, 1 mmcorresponds to a delay of 7 ps.
4Printed Circuit Board Design
In this chapter the design of the Printed Circuit Board (PCB) is elaborated. The design startswith selecting the right components with a focus on performance and compatibility. Power hasto be delivered to these components and the important problem of heat generation has to betackled. Next, a schematic can be made and the design of the actual PCB can start, taking intoaccount impedances, crosstalk and so on.
4.1 Component selection
From Chapter 3, specifications can be derived for the selection of the components that arenecessary for building the sampling platform. According to Figure 2.4, the key components tobe selected are an Analog-to-Digital Converter (ADC), a clock generator and a Variable GainAmplifier (VGA). Next to this, components for regulating the necessary voltages and deliveringpower have to be selected. However, they are dependent on the selection of the ADC, clockgenerator and VGA and this is discussed in a separate section.
4.1.1 ADC selection
In Chapter 3 it was shown that offset error and gain error can be corrected. It is preferred tohave a low value for these errors but they are not the most binding constraints for the com-ponent selection. On the other hand, sample rate and resolution are the important factors. Insection 2.2 a sample rate requirement of at least 3.6 GSPS is stated. Although difficult in a tech-nical and economical way, even with time-interleaved sampling, it is clear that the sample ratehas to be chosen as large as possible. In section 2.2 it is also stated that 16-QAM demodulationshould be possible, requiring 2 bits for the I channel and 2 bits for the Q channel. As shown inChapter 3, bits can be lost in different ways and to take this into account, a resolution of morethan 2 bits is required.
27
Chapter 4 28
The selected component is the ADC08DL502 from Texas Instruments [7]. This is a 500 MSPS,8 bit (7.6 Effective Number Of Bits (ENOB) at 248 MHz), dual channel (I and Q) ADC. The se-lection is done considering the trade-off between cost and performance (resolution and samplerate). The component requires a differential input for both the I and the Q channel as well as forthe sampling clock. The output is provided through 16 parallel differential lines. The output isclocked by a differential data clock that is a factor two slower than the sampling clock. Data isoutputted on both the rising and the falling edge of this data clock, a principle called DoubleData Rate (DDR).A lot of user control is possible by tying output pins to certain values. In this design how-ever, the extended control mode of the device is used. In this mode, configuration is doneby writing to registers using a Serial Peripheral Interface (SPI) protocol. The main reason forthis choice is the possibility to output a test pattern, which is very interesting in the testingphase of the design. Next to this, the SPI interface allows setting an offset correction for eachchannel and changing the Full-Scale Range (FSR) of each channel. The key specifications of theADC08DL502 are summarized in Table 4.1.
sample rate 500 MSPSresolution 8 bits
ENOB 7.6 bits at 248 MHzfull power bandwidth 2 GHz
FSR 560 mVpp - 840 mVpp
channels 2
Table 4.1: Key specifications of the selected ADC component (ADC08DL502).
4.1.2 Clock generator selection
The selected ADC demands a sampling clock of 500 MHz. A clock generator is necessary togenerate this signal and the only specifications are IO compatibility with the selected ADC andlow phase jitter because Signal-to-Noise Ratio (SNR) and thus ENOB degrades with increasingphase jitter according to formula (2.2). In any case, a reference clock is needed from which thenecessary 500 MHz clock can be derived. This reference can be generated by a crystal, it can bederived from a clock inside the FPGA to which the board will be connected, or it can be gen-erated externally by a signal generator. The latter option is not preferred because it makes thesystem more dependent on other devices (i.e. an external signal generator). If a reference clockfrom the FPGA is chosen, it has to be taken into account that this clock can have a substantialamount of phase jitter because of the digital circuitry it passes through inside the FPGA. In thatcase it is necessary to have a system that is able to remove this phase jitter resulting in a lowjitter output.The chosen component is the AD9523-1 low jitter clock generator from Analog Devices [8]. Thebasic block diagram of this component is shown in Figure 4.1. The component contains 2 Phase-Locked Loops (PLLs) and needs an external Voltage Controlled Crystal Oscillator (VCXO). Thefirst PLL can be used for a first jitter clean-up of the reference and relates the output frequencyof the VCXO to the input reference frequency. The jitter performance of the VCXO is retained
Chapter 4 29
PFD CP LF PFD CP LF
External VCXO
VCO
AD9523-1
OUT REF
Figure 4.1: Basic block diagram of the AD9523-1 clock generator. PFD = Phase Frequency De-tector, CP = Charge Pump, LF = Loop Filter, V(X)CO = Voltage Controlled (Crystal) Oscillator.
by choosing a low loop filter bandwidth. The very accurate external VCXO, that is allowedto be in the frequency range 15 MHz to 250 MHz, is used as reference for the second PLLthat functions as frequency multiplier, providing a frequency at the internal Voltage ControlledOscillator (VCO) output of 2.94 GHz to 3.1 GHz. The output of the internal VCO is divided,delivering a clock of 1 GHz or less to the output distribution section of the component. Theoutput distribution provides the user with up to 14 clock signals and each of these signals canbe divided to a desired value. The component can be connected to 2 external references andthe user can select which reference to use.As with the selected ADC, the configuration of the AD9523-1 is done by writing to internalregisters using the SPI protocol. This allows setting: the divider values, the charge pump cur-rents, the loop filter components (together with external capacitors), the reference selection andwhether it is single ended or differential, the output dividers, the output standard (LVPECL,LVDS, HSTL, 3.3V CMOS) for each channel, the output phase of each channel and so on. Itis clear that this component is highly configurable and very flexible which makes it easier toincorporate it into the design. The key specifications of the AD9523-1 are summarized in Table4.2.
output frequency < 1 MHz to 1 GHznumber of PLLs 2
VCXO externalnumber of selectable references 2
number of output channels 14output standard configurable: LVPECL, LVDS, HSTL and LVCMOS
Table 4.2: Key specifications of the selected clock generator component (AD9523-1).
The CVHD-950 of Crystek Crystals [9] is selected as ultra-low phase noise VCXO. The 100 MHzversion is selected because it allows, with correct divider settings, the generation of exactly 500MHz at the clock generator outputs. The CVHD-950 has a phase jitter of 40 fs from 12 kHz to20 MHz and a phase noise floor at -168 dBc/Hz. To estimate the phase noise performance ofthe combination of the selected clock generator and VCXO, the ADIsimCLK tool from Analog
Chapter 4 30
Devices is used. The phase noise performance of an external reference source (for examplea waveform generator) has to be defined by a phase noise floor which is estimated at -130dBc/Hz and a phase noise of -115 dBc/Hz at 10 kHz is entered. The simulation result is anintegrated phase jitter (10 Hz to 1 MHz) of 1.5 ps for a loop bandwidth of 100 Hz for the firstPLL and a loop bandwidth of 375 kHz for the second PLL. With this phase jitter, according toequation (2.4), the ENOB drops below 8 bits starting from a 320 MHz input frequency. With aninput frequency of 500 MHz, a 7.4 bit resolution is expected which is acceptable as the ENOBspecified by the ADC is 7.6 bits.
4.1.3 VGA selection
The 60 GHz receiver, the HMC6001LP711E, specifies an output peak-peak voltage of 10 mVpp
to 200 mVpp with a typical value of 50 mVpp. This implies that an amplifier is needed with avariable amplification factor. It should be possible to map this entire output voltage rang ontothe FSR of the ADC , that is 560 mVpp to 840 mVpp. For this a gain range of 12.5 dB to 34 dB isnecessary. An additional requirement for the selected VGA is a bandwidth of at least 500 MHzstarting from DC. Next to this also the gain resolution is important because a gain mismatchbetween the I channel and the Q channel causes an increase of the Error Vector Magnitude(EVM) as shown in Figure 3.19.The selected component is the AD8370, a digitally controlled VGA from Analog Devices [10].It has a differential input and output and the gain is digitally controlled using an 8-bit serialinterface. The device has a low gain range (-11 dB to +17 dB) and a high gain range (+6 dBto +34 dB) with a gain resolution of 1 dB and 0.5 dB respectively. The necessary gain for thetypical output value of the HMC6001LP711E receiver is about +22 dB which is in the high gainrange with a gain resolution of 0.5 dB. The bandwidth of the AD8370 is 750 MHz starting fromLF. The key specifications of the AD8370 are summarized in Table 4.3.
gain range -11 dB to 34 dBgain resolution 0.5 dB (high gain range), 1 dB (low gain range)
bandwidth LF to 750 MHznoise figure 7 dB at maximum gain
1dB compression point at 380 MHz 14 dBm at max gainOIP3 at 380 MHz 27 dBm at max gain
Table 4.3: Key specifications of the selected Variable Gain Amplifier component (AD8370).
4.1.4 Component interconnections
Clock generator - ADC [11]
The ADC requires a differential sampling clock of 500 MHz. The input standard is requiredto be Low-Voltage Differential Signalling (LVDS) and the signal lines should be AC-coupled inorder to enable the ADC to set its own common-mode level. Furthermore it is specified that adifferential voltage swing of minimally 0.4 V and maximally 2.0 V is expected. This is not in
Chapter 4 31
line with the LVDS standard that specifies a current of ±3.5 mA on the differential lines result-ing in a differential voltage swing of 350 mV because of the 100Ω termination of the differentiallines inside the ADC component and the 100Ω termination of the driver. Consequently, theLVDS outputs of the clock generator cannot be used to interface with the LVDS inputs of theADC component. The clock generator output standard can be changed to Low-Voltage Pos-itive Emitter-Coupled Logic (LVPECL) which is a current based standard just as LVDS . Thedatasheet specifies a differential output swing of 643 mV to 924 mV with a common-modevoltage of 1.9 V. The inequality of common-mode voltages of clock generator and ADC are notimportant because of the AC-coupling. The differential output swing of the LVPECL standardis now sufficient and lies in the range 0.4 V to 2.0 V as the ADC desires.
VGA interconnections
The differential input impedance of the VGA component is 200Ω. The differential outputs ofthe HMC6001LP711E receiver arrive single ended on 50Ω lines meaning that a parallel 200Ω
resistor is needed at the VGA input to terminate the lines properly.The differential output impedance of the VGAs is 100Ω and every VGA is connected to 2 dif-ferential 100Ω lines in parallel (Figure 2.4) meaning that the VGA sees a 50Ω termination. Tomatch the lines, two 25Ω resistors are placed in series with the VGA outputs. At the other sideof the lines, the ADCs have a 140Ω input impedance so a parallel resistor is placed at the ADCinputs to match with the 100Ω lines. The author is aware that this resistive power splitter isbad practice and much better solutions exist, for example using a reactive matching network.The simulated S-parameters of the resistive power splitter are shown in Figure 4.2. As can beexpected with this kind of power splitter, a high loss of 7.5 dB is observed.
frequency [MHz]0 100 200 300 400 500 600 700 800 900 1000
S11
[dB
]
-54
-52
-50
-48
-46
-44
-42
-40
-38
(a) S11
frequency [MHz]0 100 200 300 400 500 600 700 800 900 1000
S21
[dB
]
-8
-7.9
-7.8
-7.7
-7.6
-7.5
-7.4
-7.3
-7.2
-7.1
-7
(b) S21
Figure 4.2: S-parameters of the resistive power splitter from a VGA to 2 ADCs.
ADC - FPGA
The output standard of the ADC differential outputs is LVDS but not an IEEE or ANSI standardbecause of the low 1.9V supply voltage of the component. The output common mode voltageis 1.2V and the differential output swing is in the range 432 mV to 850 mV. These outputs are
Chapter 4 32
connected to the FPGA using the high speed High Pin Count (HPC) FPGA Mezzanine Card(FMC) connector on the KC705 evaluation board for the Kintex-7 FPGA. On this evaluationboard the HPC connector is connected to the High Range (HR) bank of the FPGA. The HR banksupports the Xilinx LVDS 25 standard which demands at the input a common-mode voltage of1.2V and a differential voltage swing of 100 mV to 600 mV meaning that the ADC outputs arecompatible with the FPGA pins connected to the HPC connector.
4.2 Power supply
The VGAs, ADCs and clock generator demand different supply voltages and currents as can beseen in Table 4.4. It is desired to have only one power supply line entering the board so powerconverters are needed on the PCB to generate the different voltages and supply the necessarycurrents. It can already be seen in Table 4.4 that the ADCs will require special attention sincethey can each consume op to 925 mA. Regulating a voltage can be done with a linear regulator
component supply voltage [V] typical (maximal) supply current [mA]VGA 5 82 (105)
clock generator 1.8 6.4 (12)3.3 271 (343)
ADC 1.9 digital 168 (275)1.9 analog 494 (650)
Table 4.4: Supply voltages and currents of the different components.
or a Switched-Mode Power Supply (SMPS). Both have their benefits and drawbacks which haveto be considered when designing the power supply. The first big benefit of linear regulators istheir simplicity of use. Most components maximally require two external resistors as outputdivider and proper decoupling capacitors. Next to this a power inductor at the output is notneeded because of the second benefit of linear regulators: a low ripple on the output voltage.This makes linear regulators ideal to use in designs with noise-sensitive analog components.In these designs, low Electro-Magnetic Emission (EMI) is desired and direct coupling of thenoise via the component power supply should be avoided. Since this design contains analogparts (VGA and ADC), a low ripple on the power supply and low electromagnetic emissionis desired. The main drawback of linear regulators is their low efficiency and this will be thereason that the power supply in this design partly has to rely on SMPSs. SMPSs have the ben-efit of a high efficiency, keeping internal power consumption low. The drawback of SMPSs isthe noise they introduce in the system because their operation relies on fast switching elements.
Any kind of voltage regulator heats when turned on, some more than others. It is importantthat the junction temperature (the temperature of the die) remains below a specified limit tonot cause damage to the device. In the following it is discussed how to determine the junctiontemperature and how to keep it below the limits. The important factors determining the junc-tion temperature are power consumption, heat dissipation and ambient temperature. The heatdissipation is determined by the thermal resistance RJA between the junction and the ambient.
Chapter 4 33
The thermal resistance RJA is determined by the thermal resistance RJP from the junction to thepackage, the thermal resistance RPH from the package to the heat sink and the thermal resis-tance RHA from the heat sink to the ambient. The relationship between the thermal resistancesmentioned above is:
RJA = RJP + RPH + RHA
If the case is soldered to the heat sink, RPH can be estimated as 0 K/W. The thermal resistancefrom the junction to the package RJP can be estimated as 0.2 K/W if a thermal compound isused. If the PCB copper foil is used as a heat sink, Figure 4.3 can be used to link the necessaryPCB heat sink area and the thermal resistance RHA from this heat sink to the ambient [12]. This
Figure 4.3: Thermal resistance from PCB copper foil to ambient in function of the copper foilarea [12].
means that if the maximum allowable RJA is known, it can be used to determine the heat sinkarea that is needed using RJP, RPH and Figure 4.3. The maximum allowable RJA can be derivedfrom the junction temperature TJ when the ambient temperature TA and power consumptionP are known:
TJ = TA + P · RJA (4.1)
The ambient temperature TA for this design can be determined to be maximally 25C. Thepower consumption P of a regulator is equal to [13]:
P = Vout · Iout ·1− ηη
(4.2)
In this equation Vout and Iout are the regulator’s output voltage and current respectively and ηis the efficiency of the regulator. For a linear regular η is equal to the ratio of the output voltageand the input voltage of the regulator [14]. Based on this equation (4.2) becomes for a linearregulator:
PL = (Vin − Vout) · Iout (4.3)
Chapter 4 34
As mentioned above it is preferred to only use linear regulators because of the noise a SMPSgenerates. It was also mentioned that this is not possible in this design because of the lowefficiency of linear regulators. As an example the power supply of an ADC is considered. If the1.9 analog supply is derived from a 5V supply entering the board, the power consumption ofthe linear regulator would be (equation (4.3)):
PL = (5V − 1.9V ) · 0.650 = 2W
The linear regulator that is used is the LM1084 from texas instrument [15]. This device specifiesa maximum junction temperature TJ of 125C. From equation (4.1) the maximum allowable RJA
can be calculated as:
RJA = (125C − 25C)/2W = 50K/W
From Figure 4.3 it can be found that the heat sink area corresponding with a thermal resistanceof 50 K/W has a surface of about 750mm2 which means that a copper area of about 2.7 cmsquared is at least necessary to keep the die temperature below 125C. This area is neededtwice because of the 2 ADCs. Now the same case is considered with a SMPS. The SMPS that isused in this design is the LMZ20502 [13] from Texas Instruments. This device has an efficiencyof 90% if a current of 650 mA is supplied. From equation (4.2) the consumed power is foundto be 13 mW and with equation (4.1) the maximum allowable RJA is equal to 729 K/W. FromFigure 4.3 it is clear that a very minimal heat sink area is needed to obtain this thermal resistancefrom the heat sink to the air. This solution however is not ideal because using a SMPS to supplythe analog supply rail of the ADC could lead to bad performance because of noise coupling.The hybrid solution used in this design is visualised in Figure 4.4. The analog supply voltage ofthe ADCs is delivered by cascading a SMPS and two linear regulators. In this way the voltagedrop over the linear regulators is smaller leading to less power consumption and thus a lowernecessary heat sink area. The noise generated by the SMPS is filtered by the linear regulators.Furthermore the digital supply of both ADCs is provided by a SMPS because a small amount ofnoise on the digital circuitry of the ADC is not an issue. The VGAs will be directly supplied bythe board main supply and the two voltages for the clock are provided by two cascaded linearregulators. The heat sink areas are chosen sufficiently high. For the Low Dropout Regulator(LDO) from 5V to 3.3V a minimal heat sink of 1 cm square is used. The same applies forthe LDO from 3.3V to 1.8V. The LM1086 from Texas instruments [12] is used here because themaximal specified current of 1.5A is sufficient. The SMPS for the digital supply rail of the ADCshas a heat sink of 0.5 cm square. The SMPS from 5V to 3.4V has a heat sink of 2.2 cm square.the LDOs from 3.4V to 1.9V each have a heat sink of 2.2 cm square as well. The componentused is the LM1084 from Texas Instruments [15] because of the higher current limit of 5A.
4.3 Schematic
The schematic of the sampling platform is made in the DxDesigner tool of Mentor Graphicsand can be found in the appendix. The guidelines as specified in the datasheets of the com-ponents are followed strictly. Next to this, the digital control lines (status signals, SPI signals)are equipped with a small series resistor to avoid EMI because of too steep edges of the digital
Chapter 4 35
LDO
SW
5V
LDO
SW LDO
LDO
3.3V 1.8V
3.4V 1.9V an
1.9V an
1.9V dig
Figure 4.4: Schematic diagram of the power distribution system (LDO = Low-Dropout Regu-lator, SW = SWitching regulator).
signals.
In this design phase, the connection between the designed board and the FPGA is imple-mented. This connection is made with the high speed HPC FMC connector. This connectorhas 400 pins, mapped according to the FMC specification. As mentioned above, the KC705evaluation board is used and on this board, the connections between the HPC connector andthe FPGA implement a subset of the FMC connectivity. In total, 58 differential pairs can be con-nected and every differential pair can also be used as two single ended lines. Next to this, 159ground connections are made between the FPGA evaluation board and the designed samplingplatform. Also, 2 differential clocks can be connected to clock capable FPGA pins. Mapping thesignals on the sampling platform to the FMC connector is be done with care, in particular forthe 32 differential data outputs from the ADCs, because this makes it easier to actually routethe lines to the connector, in the layout phase of the design.
4.4 Stackup
Before starting with the layout of the sampling platform, it has to be decided which stackupwill be used. While designing the stackup, it has to be assured that each signal layer is adjacentto a plane (which can be a ground or a power plane) to have a short path for the return current.Next to this, the signal layer should be close enough to the plane to allow a tight coupling.Additionally, the layer build up should be symmetrical to avoid bowing and deformation, forthe same reason the thickness of the copper on both sides of a core should be equal. Finally, thenumber of prepregs per layer is advised to be 2.
A 4-layer stackup would have 2 signal layers. Considering the amount of signals that have tobe routed in this design, this is not enough. A 6-layer stackup could have 4 signal layers, if
Chapter 4 36
structured as in Table 4.5. These 4 signal layers should be enough to allow proper routing in
layer function1 signal2 ground3 signal4 signal5 power6 signal
Table 4.5: Layer definitions of the 6-layer stackup.
this design. With these layer definitions, layer 2 serves as reference plane for signal layers 1 and3. Layer 5 serves as reference plane for layers 4 and 6. For this build up, the actual stackup hasto be designed with the available prepregs and cores. The tight coupling of signal layers to theirreference planes has to be taken into account. The designed stackup can be seen in Table 4.6.The copper thickness for the inner and outer layers are chosen in order to have the same basic
35 µm copper foil2 x 180 µm prepreg
200 µm core with 18 µm copper2 x 180 µm prepreg
200 µm core with 18 µm copper2 x 180 µm prepreg35 µm copper foil
Table 4.6: Layer buildup of the 6-layer stackup.
design rules, for trace width and spacing and minimal annular ring, for both the inner and theouter layers (specified by the manufacturer). Furthermore, the prepreg thickness at the outerlayers is chosen to be 180 µm because the 50Ω matched microstrip conductor width is aboutthe same as the signal conductor width of an SMA connector. The prepreg and core thicknessfor the inner layer allow the 100Ω differential matched striplines to be routed between the pinsof the HPC connector.
The dimensions of the 50Ω and 100Ω microstrips and striplines, are calculated using the Con-trolled Impedance Line Designer from ADS. The calculated dimensions are visualised in Fig-ures 4.5 and 4.6.
4.5 Layout
The layout of the PCB is made in the Expedition PCB tool of Mentor Graphics and the layoutof each layer can be found in the appendix. The first step is the component placing. Thesystem is symmetrical by design, and the time interleaved ADC system performs optimal ifit is fully symmetric. That is why also the signal carrying components (the VGAs, ADCs and
Chapter 4 37
700 μm
360 μm
(a) 50Ω single ended.
110 μm
240 μm 360 μm
(b) 100Ω differential.
Figure 4.5: Dimensions of the matched microstrips.
250μm
200 μm
360 μm
(a) 50Ω single ended.
100 μm
110 μm
200 μm
360 μm
(b) 100Ω differential.
Figure 4.6: Dimensions of the matched striplines.
clock generator) are placed in a symmetrical way on the top layer. The bottom layer carries thecomponents for the power supply of the board.The component placement, next to symmetry, is also influenced by heat production of the com-ponents. As mentioned in section 4.2, the voltage regulators on the board need heat sinks. Theheat sinks can consist of a single copper layer on which the regulator is placed. In this designthe heat distribution is more optimized by placing copper planes on each layer underneath theregulators and stitching these copper planes with via’s for a good heat distribution betweenthe layers and towards the copper plane on the other side of the board that is exposed to theambient. Not only for the regulators, heat production and distribution has to be considered.The package of the VGA and clock generator have an exposed pad that is also connected to theopposite layer as described above to efficiently transfer heat from the die to the ambient. TheADCs do not have an exposed pad but, as described in the component datasheet, underneaththe component, planes are placed and stitched to each other in order to have a heat transfer tothe opposite side of the component where the heat can be transferred to the ambient.Another important point is the routing of the 32 differential parallel ADC outputs togetherwith the accompanying data clock signal. These traces should all have the same length toassure that the signals arrive at the HPC connector at the same time after propagating. To dothis, meandering is applied and the matching obtained assures that the signal delays are within5 of the clock period.
5Digital Design
The developed sampling platform generates data at a rate of 2 gigabyte per second. Becauseof this high speed, dedicated hardware is necessary to be able to capture this data accurately.For this, an FPGA is the ideal platform because of its speed and flexibility. Next to this, thechips on the developed platform have to be configured through a Serial Peripheral Interface(SPI) protocol. Some configuration hardware is needed to perform this task and since an FPGAis already used for data acquisition it is convenient to use it for configuration as well.The FPGA used in this design is the Kintex-7 XC7K325T-2FFG900C FPGA from Xilinx mountedon the KC705 evaluation board [16]. The designed board is connected to this evaluation boardwith the High Pin Count (HPC) FPGA Mezzanine Card (FMC) connector. All code for theFPGA is written in Verilog and the Vivado 2015.3 Design Suite is used for editing, compila-tion, simulation and FPGA interfacing. In the following sections, the SPI system and the dataacquisition system are elaborated.
5.1 SPI interface
The chips on the sampling platform have a lot of settings, for example the gain settings ofthe Variable Gain Amplifiers (VGAs), the offset correction of the Analog-to-Digital Converters(ADCs) and the divider settings of the Phase-Locked Loops (PLLs) in the clock generator. Thesesettings are changed by writing to registers in the components using the SPI protocol.
5.1.1 The SPI protocol
The SPI protocol is a synchronous serial communication protocol used primarily in embeddedsystems. Using the SPI protocol, devices communicate in a master-slave architecture with onemaster and multiple slaves. The protocol usually works with four signals:
• SCLK: the serial clock which is an output of the master. This clock is the timing reference
38
Chapter 5 39
for communication over the SDO and SDI signal lines.
• SDO (Serial Data Out): the information output of the slave and the information inputof the master. Communication over this channel happens synchronously with the SCLKsignal.
• SDI (Serial Data In): the information input of the slave and the information output of themaster. As with SDO, communication over this channel happens synchronously with theSCLK signal. The SDO signal usually contains a header, the address of the register thathas to be accessed and, in case of a write operation, the bits to be written into the register.The combination of header, address and data is called the SPI word.
• CS (Chip Select): Every slave has a unique CS signal. A logic high on this line selects theslave, a logic low on this line disables the communication with the slave.
As every slave has its own CS signal, the master is enabled to only have one SCLK output,one SDO input and one SDI output. In this design, only the clock generator enables readingdata, which is useful for debugging. However, this debug information can also be provided at2 status pins which are connected to the FPGA and therefore the SDO signal line is not used.In the core of the SPI interface implementation, a Verilog based SPI block (designed in [17]) isused with an input output behaviour as described in Figure 5.1. The CLK and START signals
CLK
START
ACK
DRDY
SCLK
SDI
Figure 5.1: Waveform describing the IO behaviour of the used SPI block.
are inputs to the SPI block, the other signals are outputs of the SPI block. The block is timedby the CLK signal, the frequency of this CLK signal is equal to the frequency of the outputSCLK signal and it has to be chosen to be compliant with the maximum and minimum allowedSPI frequency of the chips on the developed platform. A single write operation is initiatedby a logic high on the START signal and its reception is acknowledged by a logic high on theACK line. Before starting the write operation the DRDY signal is pulled low. After the datais clocked on the SDI line synchronous with the SCLK signal, the DRDY signal is pulled highagain to finish the write operation. It can be concluded that the controller of the block has toobserve the ACK and DRDY signals and it has to apply the CLK and START signals togetherwith the SPI word, the data to be sent over the SDI line. The CS signal is not supplied by theSPI block because in this way it can be used for any number of slaves. This means the controllerhas to take responsibility of this as well.
Chapter 5 40
5.1.2 Flexible high level SPI interface
The components on the developed sampling platform contain a big amount of registers thathave to be set at startup. Therefore, a lot of SPI words have to be applied to the SPI block fromsection 5.1.1. The most straightforward way to do this is by using a state machine that appliesthe hard coded SPI words to the SPI block in a sequential way together with the steering logic ofthe block. Although this is straightforward to implement, it is not a flexible way of working aschanging the hard coded words in the Verilog code requires a new synthesis, implementationand bitstream generation which are very time-consuming tasks. This is not desired becausedebugging may require a lot of changes in the component configuration, thus a lot of changesin the SPI words to be sent.This is the reason that in this design, the controller is implemented with a focus on flexibil-ity using the Xilinx MicroBlaze soft processor core. This is a 32-bit Reduced Instruction SetComputer (RISC) processor that can be used on the Kintex-7 FPGA. The MicroBlaze processorcan be configured by the user, determining i.a. the cache sizes, clocking speed, bus-interfacesand embedded peripherals. These embedded peripherals include cache memories, a Univer-sal Asynchronous Receiver/Transmitter (UART) controller, an Advanced eXtensible Interface(AXI) interconnect block and so on. The block structure, used in this desing, of the MicroBlazeprocessor with its most important peripherals is shown in Figure 5.2. Compiled C-code can
MicroBlaze Processor
D/I Cache
AX
I in
terc
on
nec
t
AXI4
UART ctrl
GPIO
SPI AXI slave
AXI4-lite
AXI4-lite
AXI4-lite
Figure 5.2: The block structure of the MicroBlaze processor with its most important peripherals.
be sent to the data- and instruction-cache at runtime using the UART port. This is where theflexibility of this way of working lies: the SPI write operations can be initiated in the C-codeand the SPI words can be soft coded in the C-code. This system provides the basis of a highlevel SPI interface.IO operations between the MicroBlaze processor, the computer (on which the C-code is com-piled en sent to the MicroBlaze processor) and the other hardware blocks on the FPGA aredone using the AXI 4 protocol. AXI 4 is a part of ARM AMBA, an interconnect specificationfor functional blocks on a chip. On the MicroBlaze processor core, AXI 4 provides memorymapped communication with the AXI interconnect block which in turn provides an AXI 4-liteinterface to multiple AXI 4-lite slaves. AXI 4-lite is a type of AXI 4 interface for simple, lowthroughput, memory-mapped communication. Multiple AXI 4-lite slaves are available as IPblocks, for example the UART ctrl block and the General Purpose Input/Output (GPIO) block.
Chapter 5 41
The UART ctrl block serves as port for receiving data and instructions from the computer andsending debug data towards the computer. The GPIO block can drive or read signals or busesthat can be directly connected to other hardware blocks on the FPGA.
5.1.3 Linking the SPI block with the high level interface
The framework for a high level interface through the UART port is presented in section 5.1.2and the implementation of the SPI protocol is available through the SPI block as explained insection 5.1.1. In this section, it is explained how the interface and the SPI protocol are linked.The block diagram of this system is shown in Figure 5.3. The SPI AXI slave block writes the
GPIO
SPI AXI slave
AXI4-lite
AXI4-lite
SPI block control
SPI block
CS
SCLK
SDI
register 0 register 1
Figure 5.3: Block diagram of the SPI interface system.
new SPI word to register 0 on command of the MicroBlaze processor. If the data is ready, theSPI AXI slave block sets a bit in register 1. Which bit is set, depends on which chip on thesampling platform one wants to write to. The SPI block control, starts a write operation if abit in register 1 is set. Depending on the position of the bit that is set in register 1, a certainCS signal is pulled down to select the correct chip on the sampling platform. After that, theSPI word from register 0 is passed to the SPI block and the correct steering logic for the SPIblock is applied. If the SPI block finished the write operation, the SPI block control informs theMicroBlaze processor about it through the GPIO block and a new write cycle can be started forthe next SPI word.The total SPI system can now be controlled by the C-program. Functions are written in orderto be able to write a single SPI word by using one of the following instructions:
SPI_CLK_write (u32 address , u32 data ) ;SPI_ADC1_write (u32 address , u32 data ) ;SPI_ADC2_write (u32 address , u32 data ) ;
Also the VGA can be controlled in the C-program by using:
SPI_VGA_I_write (u32 gain_mode , u32 gain_code ) ;SPI_VGA_Q_write (u32 gain_mode , u32 gain_code ) ;
Chapter 5 42
For setting the gain mode (high or low) and gain code of the VGA of the I channel or the VGAof the Q channel. By using these functions, a very flexible way is provided for configuring thechips on the sampling platform.
5.2 Data acquisition
The ADC08DL502 ADC component samples 2 channels (I and Q) at 500 MSPS and each sampleconsists of 8 bits. This means that one ADC generates 1 gigabyte per second. Because of thishigh data rate, good design choices are important. First the system of data transfer of the ADCis explained after which the memory options are considered and finally the data acquisitionsystem will be elaborated.
5.2.1 The ADC data output
At every rising edge of the 500 MHz ADC input clock, 8 bits from the I channel and 8 bits fromthe Q channel are transferred via the 16 differential output lines in a parallel manner. This dataat the output of the converter is synchronised with a data clock , DCLK (which is an outputof the ADC), that has a frequency of 250 MHz, equal to half the frequency of the ADC inputclock. The 16 bit parallel output data changes on every rising and falling edge of DCLK andis stable between every rising and falling edge of DCLK, a principle called Double Data Rate(DDR). In Figure 5.4 the waveforms illustrating the DDR principle are shown. The DATA 1
DCLK
DATA 1
DATA 2
Figure 5.4: Illustration of Double Data Rate (DDR) data transfer. DATA 1 is how the datashould be captured. DATA 2 represents the way the data arrives at the FPGA, meaning a 90
phase shift should be applied to DCLK before capturing the data.
trace together with the DCLK trace represents how the data should be captured, on the risingand falling edge of DCLK. The DATA 2 trace together with the DCLK trace represents how thedata and the clock are delivered at the pins of the ADC and, consequently, how the data andthe clock arrive at the FPGA: the data is edge-aligned to the clock. To be able to capture thedata, a 90 phase shift has to be applied to DCLK.
5.2.2 The memory options
In this first design, the data will be processed completely off the FPGA meaning that all datahas to be passed to the computer. The rate at which the data arrives is too high to be streamedto the computer so it has to be saved in some memory in the FPGA or around the FPGA after
Chapter 5 43
which it will be sent to the computer with a lower speed. The Kintex-7 FPGA and the KC705evaluation board provide a number of memory options for saving data temporarily:
1. The DDR 3 SDRAM memory module on the KC705 evaluation board provides 1GB ofstorage and a data rate up to 1600 MT/s with a data-path width of 64 bits. This enables500 milliseconds of data storage [16]. The Xilinx Memory Interface Generator (MIG) canbe used to generate a memory controller. This memory is large enough and fast enough.However, the control is rather complex.
2. The SD card interface on the KC705 evaluation board could provide a lot of storage [16].However, the clock rate of 50 MHz cannot provide enough speed.
3. The Block Random Access Memory (BRAM) on the 7-series FPGAs can be used for effi-cient data storage and buffering [18]. The XC7K325T Kintex-7 FPGA contains 445 BRAMblocks, each having a capacity of 36Kb. This accumulates to a total BRAM of about 2megabytes enabling 1 millisecond of data storage. A clocking speed of up to 543 MHz ispossible with a data-path width of 32 bits or more meaning that the BRAM is fast enough.
Both option 1 and 2 are good options. Although option 1 would be the best option becausemore storage is available, option 2 is chosen in this design because of the lower complexity and1 ms of data will be enough for testing the sampling platform.BRAM blocks of 36Kb can be combined into bigger BRAMs. The combined BRAM (also re-ferred to as BRAM ) can be configured as single-port BRAM or dual-port BRAM which supportssimultaneous read and write operations. The BRAM can be controlled with six signals/buses:the address bus (ADDR), the data in bus (DIN), the data out bus (DOUT), the clock (CLK),the enable signal (EN) and the write enable signal (WEN). How these signals control the readand write operations is shown in Figure 5.5. Knowing these waveforms, an implementation
CLK
EN
WEN
DIN
DOUT
ADDR
Figure 5.5: Waveforms describing operations with a BRAM module.
of the right protocol is possible. This is discussed in the next section, together with the othernecessary hardware.
5.2.3 The data acquisition system
In the following discussion, one ADC is considered. The extension to two ADCs is trivial. The1 GBps (Gigabyte per second) output of the ADC is split into 4 data-streams which results in
Chapter 5 44
a data rate of 250 MBps for each stream, making the design less stringent concerning timingdifficulties. The 4 different streams are created by considering the data on the rising edge andthe data on the falling edge of the data clock (DCLK) as separate streams. Since the ADCoutput is already split for the I channel and the Q channel, this results in 4 streams. Because adata-width of 32 bit is used for the BRAM, each stream of 8 bits has to be packaged into 32-bitstreams each with a clock rate of 250 MHz/4 = 62.5 MHz. Everything as described above isimplemented in the FPGA as shown in Figure 5.6. The packagers (PACK) are made in 2 types:
PACK
PACK
PACK
PACK
ADC I C
Q
8-bit
8-bit
250 MHz
32-bit
62.5 MHz
32-bit
62.5 MHz
32-bit
62.5 MHz
32-bit
62.5 MHz
Δ
Figure 5.6: The generation of 4 data streams.
acting on the rising edge of the DCLK signal (output C of the ADC) or acting on the falling edgeof the DCLK signal, in this way separating the I and Q streams into 4 separate data streams.Inside the packagers, the entering data is sequentially stored on four 8-bit locations in an arrayof 32 flip-flops. These flip-flops are triggered on the rising edge or falling edge of the DCLKsignal, depending on the type of packager. Each packager also provides a single data rate clockof 62.5 MHz synchronised with the data. As mentioned in section 5.2.1, the data and the DCLKsignal arrive edge-aligned so the DCLK is delayed 90 using a PLL inside the FPGA. This isillustrated with the ∆-block in Figure 5.6.Now, the data outputs from the packagers are ready to be connected to the BRAM. For this aVerilog block is designed implementing the protocol illustrated in Figure 5.5. This block alsogenerates the BRAM addresses by incrementing the base address of the BRAM after each writeoperation. The block performing these operations is called ’write BRAM’ in Figure 5.7. A dual-
PACK 32-bit
62.5 MHz
AXI BRAM controller
AXI4-lite
BRAM
write BRAM
Figure 5.7: Illustration of the data-transfer towards the BRAM and the reading back of the datausing MicroBlaze peripherals.
Chapter 5 45
port BRAM module is used in this design, one for each data stream. One port is used for writingonly, the other port is used for reading only. At the moment, a system is available for writingdata to the BRAM. Once the BRAM has been filled, the data inside has to be transferred offthe FPGA towards a computer. This is implemented using the MicroBlaze processor. The readport of every BRAM is connected to an AXI BRAM controller which in turn is connected to thesame AXI interconnect block as in Figure 5.2 using the AXI 4-lite protocol. With the MicroBlazeprocessor, the data can now be read by a computer through the UART port connected to theUART control block from figure 5.2.
5.3 Constraining the FPGA
The compiler only knows about the hardware inside the FPGA chip. To make a functionaldesign on a board, the compiler needs additional information: requirements that must be metin the design flow. These requirements are called constraints and are passed to the compiler incommands via constraint files. There are two types of constraints:
• Physical constraints: used in implementation only because they connect circuitry on theFPGA to circuitry off chip.
• Timing constrains: used in the whole design flow because timing has to be taken intoaccount everywhere.
5.3.1 Physical constraints
The physical constraints include IO constraints and placements constraints. Examples are pinmapping, port termination, IO standard... As an example, these are the physical constraintentries for pin AB8 of the FPGA package that is connected to a LED on the Kintex7 evaluationboard expecting an LVCMOS15 IO standard:
set_property PACKAGE_PIN AB8 [get_ports led [ 0 ] ]set_property IOSTANDARD LVCMOS15 [get_ports led [ 0 ] ]
With this requirements the compiler can route the circuits using the LED[0] signal to the cor-rect package pin and package pin compliance with the LVCMOS15 IO standard will also bechecked. These constraint entries are a necessity for every signal in the FPGA design that hasto be connected the outside world.
5.3.2 Timing constraints
Physical constraints are a necessity for bitstream generation because they provide the link be-tween the FPGA chip and its connections. Timing constraints however will not influence theability to make the circuitry but they determine if the created circuitry will have the desiredfunctionality. A critical part in this design concerning timing, is the acquisition of data gener-ated by the ADCs.Path time requirements are computed based on clocks since they provide the time referencefor reliable data transfers to registers and between registers. For this reason, information about
Chapter 5 46
the clocks and their relation with the data has to be passed to the compiler using constraints.Signals of which timing is important have to be defined as soon as they enter the FPGA becauseeverything before the first definition of these signals will be ignored. If a clock enters the designthrough an input port of the FPGA it is called a primary clock. Primary clocks are constrainedby the create clock command. In this design 3 primary clocks are present: the system clockthat is generated by a crystal on the KC705 evaluation board with a frequency of 200 MHzand the 2 DCLK signals coming from the ADCs that each have a frequency of 250 MHz. Thecorresponding constraint entries are:
create_clock −period 5 .000 −name sys_clk_p −waveform 0 .000 2 .500 [get_ports sys_clk_p ]create_clock −period 4 .000 −name DCLK1_p −waveform 0 .000 2 .000 [get_ports ADC1_DCLK_p ]create_clock −period 4 .000 −name DCLK2_p −waveform 0 .000 2 .000 [get_ports ADC2_DCLK_p ]
As can be seen, only the positive pin of the differential clocks are constrained. This is enough asthe compiler recognises the signals as differential pairs when they go through the first differen-tial input buffer. As can be seen in Figure 5.6, the packagers generate output clocks. Internallythis is done by dividing the input clock DCLK using a counter register clk divide reg. Thesegenerated clocks have to be constrained using the create generated clock command. As an ex-ample, this is the constraint entry for the output clock of the packager for the rising edge of theI data input:
create_generated_clock −name pack4_1I_posedge/clk_out −source [get_pins pack4_1I_posedge/←clk_divide_reg/C ] −divide_by 4 [get_pins pack4_1I_posedge/clk_divide_reg/Q ]
Finally, also the input delay of the data signals, relative to a clock edge at the interface ofthe design has to be passed to the compiler using set input delay. This is used to define thetimespan in which the data changes in order to let the compiler know that the data cannot beclocked in during this period of time.
6Measuring System Characteristics and
Performance
For a good performance of the sampling platform, linearity is an important parameter. Toquantify the linearity of the system, IIP3 measurements are performed on the complete wire-less link from section 2.1. Next, because clock jitter has an important influence of the perfor-mance of Analog-to-Digital Converters (ADCs), phase noise measurements are performed fordifferent clock generator configurations. Finally, the performance of the ADCs, both alone andinterleaved, is analysed and an attempt is made to improve the performance of the samplingplatform by digitally post-processing its output.
6.1 Linearity of the transceivers
The complete wireless link as described in section 2.1, is considered in the measurements per-formed in this section. As explained in section 2.1, the transceiver chips have several VariableGain Amplifiers (VGAs) of which a certain attenuation can be configured by the user: the In-termediate Frequency (IF) amplifier in the transmitter (0 dB to 20 dB attenuation) and the IF (0dB to 20 dB attenuation) and baseband (0 dB to 36 dB attenuation) amplifiers in the receiver. Bychanging these attenuations, the overall gain and linearity of the link can be varied. The usercan change these settings in order to have a desired gain and it would be interesting to findthe settings that provide this gain together with the best possible linearity. In order to measuregain and linearity, IIP3 measurements are performed. A two-tone signal at 100 MHz with aseparation of 2 MHz is used for this and measurements are performed sweeping over differentconfigurations. When measuring, the distance between the transmitter and receiver is 14 cmwhich corresponds to a free-space path loss of 36 dB at 60 GHz. An example of a measurementis shown in Figure 6.1. The configuration during this measurement is: IF at Tx: 0 dB attenua-tion, IF at Rx: 0 dB attenuation, baseband at Rx: 24 dB attenuation. An IIP3 of -14.2 dB and a
47
Chapter 6 48
Pin [dBm]-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10
Pou
t [dB
m]
-140
-120
-100
-80
-60
-40
-20
0
20Processed IP3 Measurement
-1*Fc+2*Fs = 103 MHz1*Fc+0*Fs = 99 MHz0*Fc+1*Fs = 101 MHz2*Fc+-1*Fs = 97 MHz
Figure 6.1: An IIP3 measurement of the complete wireless link at 100 MHz for the followingVGA configuration: IF at Tx: 0 dB attenuation, IF at Rx: 0 dB attenuation, baseband at Rx: 24dB attenuation.
gain of 20.3 dB is measured. From all measurements, an obtainable range for the gain and IIP3is found:
−30dB < gain < 44dB
−37dB < IIP3 < −1dB
6.2 The clock signals
The clock generator has an internal structure as shown in Figure 4.1. An external clock signalserves as reference for the first Phase-Locked Loop (PLL) which has as function to relate theinput and output frequency and phase of the clock generator component. The oscillator of thefirst PLL is an external Voltage Controlled Crystal Oscillator (VCXO) which provides a veryclean input signal for a second PLL on the clock generator chip which functions as frequencymultiplier. The output of the second PLL is then distributed to the output section of the clockgenerator. The loop bandwidth of the first PLL can be tuned between 10 Hz and 100 Hz, alow bandwidth to be able to suppress jitter that is present in the clock reference. The loopbandwidth of the second PLL is tunable around 400 kHz. Apart from the loop bandwidths,there are several clock generator configurations concerning the reference that is used:
• The external reference can be an external clock generator that is connected to the samplingplatform.
• The external reference can be a clock generated by the FPGA.
• The first PLL can be disabled and the voltage control pin of the VCXO can be tied to midsupply (this can be done with a register setting of the clock generator). In this way theVCXO acts as a constant reference for the second PLL .
Chapter 6 49
For the case in which the first PLL is disabled and the VCXO is used as reference, the outputspectrum of the 500 MHz clock is shown in Figure 6.2. It can be seen that the main component
0 1 2 3 4 5 6 7 8 9 10
−60
−50
−40
−30
−20
−10
0
10
frequency [GHz]
pow
er [d
B]
Figure 6.2: Spectrum of the clock generator 500 MHz output with the first PLL disabled. TheVCXO serves as reference for the second PLL.
is at 500 MHz. Since the output waveform is a square wave, also the odd harmonics are clearlypresent in the spectrum. The waveform is however not a perfect square wave as also even har-monics and other spurs can be found in the spectrum. This can be due to duty cycle distortion,over-shoot and under-shoot.
Since the phase noise on the output signal has a big influence on the Effective Number Of Bits(ENOB), the phase noise of the 3 possibilities concerning the reference is measured. This canthen be used to estimate which configuration is the better one for the clock generator to serveas sampling clock for the ADCs. The measurement results can be seen in Figure 6.3. A firstthing to observe is that phase noise is very high when the reference clock is a 25 MHz clockgenerated by the FPGA. The output frequency is very unstable which indicates that the firstPLL has difficulties with locking on the reference signal because the reference signal has a veryhigh phase noise itself. As the loop bandwidth of the first PLL cannot be made higher than 100Hz, this issue cannot be resolved unless a more stable reference signal can be provided. If anexternal clock generator is used as external reference, the phase noise is much lower becausethis reference signal is clean enough enabling the first PLL to maintain a lock on it. If the firstPLL is disabled and the VCXO is used as reference, the phase noise is even slightly lower. Thepeak at 25 Hz that is observed in the phase noise characteristic with the external clock generatoris not present so the occurrence of this peak has to do with the first PLL . For every configura-tion, a spur is present at 70 kHz. This possibly originates from a mechanical resonance in theVCXO. From the phase noise characteristics, the integrated phase jitter is found by integratingthe phase noise curves from 10 Hz to 1 MHz. The resulting phase jitter values can be found inTable 6.1. The phase jitter values can be used to determine an upper bound on the ENOB thatcan be obtained. First, the Signal-to-Noise Ratio (SNR) can be calculated using equation (2.2)
Chapter 6 50
frequency [Hz]101 102 103 104 105 106
pow
er [d
Bc/
Hz]
-140
-120
-100
-80
-60
-40
-20
External referenceVCXO referenceFPGA reference
Figure 6.3: Phase noise of the clock generator 500 MHz output with an external 3.125 MHzreference, with the first PLL disabled and the 100 MHz VCXO output as reference and with a25 MHz reference clock from the FPGA.
phase jitter [ps]External reference 9
VCXO reference 4FPGA reference 222
Table 6.1: Integrated phase jitter (10 Hz to 1 MHz) from the considered clock signals.
and after that the ENOB can be calculated using equation (2.4). In Figure 6.4 this theoreticalupper bounds are plotted in function of input frequency for a sample rate of fs = 1 GHz as usedin this design. It is observed that a phase jitter value of 222 ps results in a loss of more than6 of the 8 available bits for input frequencies higher than 150 MHz. This means that at thesefrequencies, a 16-QAM modulation format cannot be detected. For this reason, the referenceclock signal from the FPGA is not considered in the following discussions. A phase noise of 4ps and 9 ps results in an acceptable value for the ENOB which makes them suitable for furtheruse in this design.
6.3 Performance of the ADCs
First, the performance of a single ADC on the Printed Circuit Board (PCB) is evaluated. Afirst indication of the ADC performance can be found by looking at the output spectrum of asampled waveform. In Figure 6.5, the Discrete Fourier Transform (DFT) is shown of the outputof a single ADC with a tone of 149.9 MHz at the input of the sampling platform. A Hanningwindow is applied to the samples before calculating the DFT to reduce spectral leakage. The149.9 MHz tone at the input is clearly visible in the spectrum. Next to this tone, also harmonicspurs can be seen at approximately 50 MHz, 100 MHz and 200 MHz and a DC component is
Chapter 6 51
0 50 100 150 200 250 300 350 400 450 5000
1
2
3
4
5
6
7
8
frequency [MHz]
EN
OB
4 ps9 ps222 ps
Figure 6.4: Theoretical ENOB in function of frequency for the 3 phase jitter values from the 3clock configurations.
0 50 100 150 200 250−120
−100
−80
−60
−40
−20
0
f [MHz]
20lo
g(A
)
Figure 6.5: Measured frequency spectrum of the output of a single ADC with an input tone of149.9 MHz and an external clock as clock reference.
present as well. The presence of these spurious components can be due to non-linearities in theVGA and the ADC. Next to this, the noise floor is also slightly higher than−90 dB as calculatedin section 3.3.1 for the case of an ideal ADC with the same number of samples. This extra noisecan be induced by the VGA, the ADC, the PCB and clock jitter.
The resolution performance of an ADC can be specified using ENOB. Next to the performanceof the ADC component itself, also influences of the circuit (different types of noise, clock jitter,non-linearities) are included in this number. In the following discussion, the sinewave curvefitting method [5] is used to measure the ENOB. A single frequency signal is used as an in-
Chapter 6 52
put to the system. A best-fit sinewave is computed and the rms error EM between the best-fitsinewave and the measured sinewave is calculated. Furthermore, the theoretical rms quanti-zation error is known as ET = q/
√12 where q is equal to 1 Least Significant Bit (LSB) [5]. The
ENOB for an N-bit ADC can now be calculated as:
ENOB = N − log2
(EMET
)This method is used to calculate the ENOB at several frequencies for a single ADC at a samplerate of fs = 500 MSPS and the results are shown in Figure 6.7. The resolution of a single ADCon the PCB is about 6.2 bits up to the Nyquist frequency. It is observed that the resolutionis the same whether the 4 ps clock or the 9 ps clock is used and also that the resolution ofboth ADCs on the board is more or less equal. The ADC datasheet specifies an ENOB of 7.5bits at 125 MHz. This means that an additional 1.3 bit is lost. Reasons for this are clock jitter,non-linearities (of the VGA and the ADC) and different types of noise.
6.4 Performance of the interleaved ADC system
6.4.1 Performance without error compensation
Now, the outputs of the 2 ADCs are interleaved in order to double the bandwidth of the sam-pling platform. To have a first indication of the performance of the interleaved system, a singlefrequency signal of 323.9 MHz is sampled and the DFT of the interleaved output is calculated.The spectrum can be seen in Figure 6.6. In this spectrum, the input signal is recognised at 323.9
0 50 100 150 200 250 300 350 400 450 500−120
−100
−80
−60
−40
−20
0
f [MHz]
20lo
g(A
)
Figure 6.6: Measured frequency spectrum of the interleaved output of both ADCs with aninput tone of 323.9 MHz and an external clock as clock reference.
MHz meaning that a signal beyond the Nyquist frequency of a single ADC (which is 250 MHz)is sampled successfully. However, a lot of spurious components are present in the output. Firstof all, the spurious component at 176.1 MHz indicates a 500 MHz amplitude modulation of thesignal. This amplitude modulation creates a component at 323.9 MHz + 500 MHz = 823.9 MHz
Chapter 6 53
which is mirrored to 500 MHz - 323.9 MHz = 176.1 MHz due to the sampling. As explained inChapter 3, this is caused by clock phase mismatch and unequal gain error of both ADCs. Alsoat DC and at 500 MHz, a component is present which can be caused by the presence of an offseterror in both ADCs and the inequality of the offset error of both ADCs. The other spurs in thespectrum can be caused by non-linearities in the system (caused by the VGAs and ADCs). Forthis input frequency, the ENOB as calculated by the sinewave curve fitting method is equal to4.6 bits. In Figure 6.7, the ENOB in function of frequency is plotted for the interleaved ADC sys-tem. Even at frequencies below the Nyquist frequency of a single ADC (250 MHz), the ENOB
frequency [MHz]0 50 100 150 200 250 300 350 400 450 500
EN
OB
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
84ps clock jitter, 1 ADC, 500 MSPS4ps clock jitter, 2 ADCs, 1 GSPS9ps clock jitter, 2 ADCs, 1 GSPS
Figure 6.7: Measured ENOB in function of frequency for a single ADC and for the interleavedsystem.
is lower than the ENOB of a single ADC . This is due to the effects that are described in Chapter3: clock phase mismatch and unequal gain and offset errors. Above 250 MHz, the ENOB dropsquickly because for example clock phase mismatch has more consequences at high frequencies.At the Nyquist frequency of the interleaved system, 500 MHz, only 3.2 bits are left.
6.4.2 Performance with error compensation
In the interleaved output spectrum from Figure 6.6, the spurious peak at 176.1 MHz is causedby different gain errors of the ADCs and by clock phase mismatch of the sampling clocks. Thisspurious component results in a low ENOB as shown in Figure 6.7, especially for high frequen-cies. To compensate for the errors made by interleaved sampling, the errors are estimated afterwhich the estimations are used for error compensation. Error compensation for the offset error,gain error and clock phase mismatch of single frequency signals, are discussed in the followingparagraphs.
The offset error present in the sampled output of the interleaved system can be compensatedin two ways. In a first technique, the offset error is estimated by taking the average value of theoutput of ADC 1 and ADC 2. These 2 offset error estimations are subtracted from the outputs of
Chapter 6 54
ADC 1 and ADC 2 respectively to compensate for the error. The second technique uses a highpass filter to remove the offset error. Offset error compensation turns out to have a negligibleeffect on the ENOB.
Gain error compensation is done by multiplying the output samples of ADC 2 with the ratioof the average amplitude of the ADC 1 output to the ADC 2 output, assuming that enoughsamples are taken to calculate the average. The compensation of gain error has an importantinfluence on the ENOB. A first indication of this can be seen in Figure 6.8. In Figure 6.8a, thesame output spectrum of the interleaved sampled signal is shown as in Figure 6.6 with a 323.9MHz input signal. The spurious peak caused by interleaving can be seen at 176.1 MHz witha magnitude of −46.49 dB. In Figure 6.8b, the output spectrum of the same samples is shownwith compensation for the offset error and gain error. The spurious peak has decreased inamplitude by 13.5 dB. In Figure 6.9, the ENOB in function of input frequency is shown. Up to450 MHz, the ENOB is improved substantially by the offset error and gain error compensation.
f [MHz]0 50 100 150 200 250 300 350 400 450 500
20lo
g(A
)
-140
-120
-100
-80
-60
-40
-20
0
(176.1 MHz,-46.49 dB)
(a) Without error compensation.
f [MHz]0 50 100 150 200 250 300 350 400 450 500
20lo
g(A
)
-140
-120
-100
-80
-60
-40
-20
0
(176.1 MHz,-59.99 dB)
(b) Compensation for gain and offset error.
f [MHz]0 50 100 150 200 250 300 350 400 450 500
20lo
g(A
)
-140
-120
-100
-80
-60
-40
-20
0
(176.1 MHz,-90.07 dB)
(c) Compensation for gain error, offset errorand clock phase mismatch.
Figure 6.8: Output spectra of a sampled 323.9 MHz tone. Error compensation is applied toenhance the ENOB.
In Figure 6.8b, a −59.99 dB spur is still visible as a result of the interleaving process. This
Chapter 6 55
spur can be completely removed by compensation for the clock phase mismatch as is shownin Figure 6.8c. The compensation is done using a Lagrange interpolation filter, as suggestedin [19]. It is supposed that the sample instants of ADC 1 and ADC 2 are uniform and that thesamples of ADC 2 are delayed with respect to the perfect sampling instant for ADC 2 by aconstant value. In other words, the phase between the 2 ADC clocks is not exactly 180. Thesample value of ADC 2 at the correct time instant, is found by fractional interpolation. To findwhich time shift results in the best ENOB, an iteration is performed over a certain range of timeshifts. In Figure 6.9, the ENOB in function of frequency is found with compensation for offseterror, gain error and clock phase mismatch.
frequency [MHz]0 50 100 150 200 250 300 350 400 450 500
EN
OB
3
3.5
4
4.5
5
5.5
6
6.5
1 ADC 500 MSPS2 ADCs 1GSPS: uncorrected2 ADCs 1GSPS: offset and gain correction2 ADCs 1GSPS: offset, gain and timing correction
Figure 6.9: ENOB in function of frequency for the interleaved system with and without errorcompensation.
Close to the Nyquist frequency, the ENOB remains very low, even after compensation. Thisis because at these high frequencies, the number of samples per period is close to one sampleper ADC [19]. Not enough information is available here to do a proper interpolation to correctfor clock phase mismatch. Also gain error cannot be estimated because only one sample perperiod is available from each ADC.
Conclusion and Future Work
In this master’s dissertation, a sampling platform for 60 GHz wireless communication is de-veloped with a bandwidth of 500 MHz. The Effective Number Of Bits (ENOB) of the platformis higher than 5.7 bits up to 450 MHz. A detailed discussion is found in the previous chap-ters. In the following paragraphs, a short summary of the design and the results are given andpossibilities for future work are listed.
Summary of the Design and Results
The sampling platform is developed for a commercially available wireless receiver. As a start,the performance of this receiver is measured by testing a complete wireless 60 GHz link. IIP3measurements pointed out the linearity and gain of several transceiver configurations.
To process the output of the 60 GHz receiver, a PCB is designed that digitizes the analog I andQ output signals of the receiver. The outputs are sampled with 2 time-interleaved Analog-to-Digital Converters (ADCs) that each have a sample rate of 500 MSPS and a resolution of 8 bits.By interleaving, a total sample rate of 1 GSPS is obtained with a resolution of 8 bits. The ADCoutputs are connected to an FPGA for data acquisition.
Processing of the interleaved ADC outputs confirmed what simulation results pointed out:interleaving of ADCs results in signal distortion. An ENOB of 6.2 bits is obtained for bothADCs separately. The ADC components specify an ENOB of 7.5 bits meaning that an additional1.3 bits is lost. The interleaving results in successful sampling beyond the Nyquist frequencyof a separate ADC component. However, a lot of bits are lost due to imperfections and at 500MHz, an ENOB of 3.2 bits is measured. An error compensation is applied to the samples andthe ENOB is improved up to 5.7 bits at 450 MHz.
Future Work
During the design cycle, imperfections and mistakes came to light. The following workingpoints and improvements can serve as a guideline for future work:
• The phase jitter on the clock signals limits the ENOB to 6 bits at 500 MHz. A cleaner clocksignal could lead to better performance.
56
• The I and Q signals are both sampled by 2 ADCs. For this, the power is split using aresistive power splitter and matching network. This is bad practice and a better solutionhas to be used.
• Now, data can only be saved on the FPGA and signal processing should be done on acomputer. To make a functional product, digital demodulation should be done on theFPGA.
• The performance of a 60 GHz wireless link should be still tested with the sampling plat-form.
Bibliography
[1] Nan Guo. “60-GHzMillimeter-Wave Radio: Principle, Technology, and New Results”. In:EURASIP Journal onWireless Communications and Networking (2007).
[2] Millimeterwave Transmitter 57-64 GHz. HMC6000P711E. Hittite.
[3] Millimeterwave Receiver 57-64 GHz. HMC6001LP711E. Hittite.
[4] Qizheng Gu. RF System Design of Transceivers for Wireless Communications. 2005.
[5] Analog Devices Inc. Engineering. The Data Conversion Handbook. 2005.
[6] ADC performance evolution: Thermal noise. 2012. URL: https://converterpassion.wordpress . com / 2012 / 07 / 26 / adc - performance - evolution - thermal -
noise/.
[7] Low Power, 8-Bit, Dual 500 MSPS A/D Converter. ADC08DL502. Revised March 2013. TexasInstruments. Mar. 2012.
[8] Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs. AD9523-1.Rev. C. Analog Devices. Oct. 2010.
[9] Ultra-Low Phase Noise Crystal Oscillators. CVHD-950. Rev. T. Crystek Crystals. Oct. 2015.
[10] LF to 750 MHz, Digitally Controlled VGA. AD8370. Rev. B. Analog Devices. Jan. 2004.
[11] Nick Holland. Interfacing Between LVPECL, VML, CML, and LVDS Levels. Application Re-port. Texas Instruments. Dec. 2002.
[12] 1.5-A Low Dropout Positive Regulators. LM1086. Rev. J. Texas Instruments. June 2000.
[13] 2 A SIMPLE SWITCHER Nano Module. LMZ20502. Rev. C. Texas Instruments. June 2012.
[14] Henry J. Zhang. Basic Concepts of Linear Regulator and Switching Mode Power Supplies. Ap-plication Report. Linear Technology. Oct. 2013.
[15] 5-A Low Dropout Positive Regulators. LM1084. Rev. G. Texas Instruments. Sept. 1999.
[16] KC705 Evaluation Board for the Kintex-7 FPGA. UG810. V 1.6.2. Xilinx. Aug. 2015.
[17] Hannes Ramon. “Design of a Broadband Signal Generation Platform for Fifth Generation(5G) Mobile Networks and Attocell Applications”. Ghent University, 2015.
[18] 7 Series FPGAs Memory Resources. UG473. V 1.11. Xilinx. Jan. 2011.
58
[19] Christian A. Schmidt. “Efficient Estimation and Correction of Mismatch Errors in Time-Interleaved ADCs”. In: IEEE Transactions on Instrumentation and Measurement (2016).
Appendix A
.1 Schematics
Figure 10: Schematic of the ADC .
60
Figure 11: Schematic of the clock generator.
Figure 12: Schematic of the Variable Gain Amplifier (VGA) ’s.
Figure 13: Schematic of the power supply, part 1.
Figure 14: Schematic of the power supply, part 2.
.2 Layout
Figure 15: Layout of the top layer.
Figure 16: Layout of layer 2: the ground plane.
Figure 17: Layout of layer 3: signal layer.
Figure 18: Layout of layer 4: signal layer.
Figure 19: Layout of layer 5: power plane.
Figure 20: Layout of the bottom layer.
Figure 21: Picture of the soldered PCB mounted on the KC705 evaluation board.
