Embed Size (px)
Citation preview
Digitally Controlled DC-DC Converters with Fast and Smooth Load Transient Response
by
Jing Wang
Supervisors: Wai Tung Ng and Aleksandar Prodić
A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy
Department of Electrical and Computer Engineering University of Toronto
© Copyright by Jing Wang 2013
ii
Digitally Controlled DC-DC Converters with Fast and Smooth
Load Transient Response
Jing Wang
Doctor of Philosophy
Department of Electrical and Computer Engineering University of Toronto
2013
Abstract
Modern switch-mode power supplies (SMPS) used for point-of-load (PoL) applications need to
meet increasingly stringent requirements on voltage regulation, while minimizing physical
volume and optimizing conversion efficiency. The focus of this thesis is the voltage regulation
capability of low-power PoL converters during load transients. The main objective is to
investigate converter topologies and control techniques that can achieve fast and smooth
transient performance without significant penalty in volume and efficiency. The digital control
method is used due to its ability to implement sophisticated control algorithms. The first part of
this thesis investigates a dual output stages converter, with a small auxiliary output stage
connected in parallel with the main output stage. While the main output stage is responsible for
steady-state operation and designed to achieve optimum efficiency, the auxiliary stage is
activated when a load transient occurs, to help suppress voltage deviation. Experimental results
on a 6 V-to-1 V, 3W buck converter shows 35% improvement in peak transient voltage deviation
while maintaining the same efficiency profile, compared to an equivalent buck converter. The
second part of this thesis introduces a flyback-transformer based buck (FTBB) converter. In this
topology, the conventional buck inductor is replaced with the primary winding of the flyback
transformer, an extra switch, and a set of small auxiliary switches on the secondary side. During
iii
heavy-to-light load transients the inductor current is steered away from the output capacitor to
the input port, achieving both energy recycling and savings due to reduced voltage overshoots.
The light-to-heavy transient response is improved by reducing the equivalent inductance of the
primary transformer winding to its leakage value. Compared to an equivalent buck converter,
experiment results on a 6 V-to-1 V, 3 W prototype show three times smaller maximum output
voltage deviation during load transients and, for frequently changing loads, about 7% decrease in
power losses.
iv
AcknowledgmentsAcknowledgmentsAcknowledgmentsAcknowledgments
First and foremost, I would like to express my sincere gratitude to my co-supervisors,
Professor Wai Tung Ng and Professor Aleksandar Prodić. It is my greatest honor to work with
them. And I cannot imagine a better combination of supervisors.
Professor Ng has been an excellent advisor in academia and a great mentor in life. I
really enjoy working in the Smart Power Integration and Semiconductor Devices research group
under his leadership. And our talks and conference trips together will never be forgotten. From
him there is a lot for me to learn. I always admire him being very successful in career while
having a loving family life. I always try to learn from his logical thinking and problem solving
skills. And I am thankful of him being cool under all circumstances, even when I burnt my test
chips.
I started working with Professor Prodić in my second year of study but I got to know him
since my first power electronic course. His teaching opens my eyes to the world of power
electronics and shapes my interest in it. Working with him teaches me how a little perfectionism
can make a huge difference in outcome. Our discussion has always been inspiring. And he is so
encouraging and supportive when I have doubts and/or difficulties.
I thank Professor Oliver Trescases, who is a former student of Professor Ng and Professor
Prodić and a role model of the research group long after he graduated. I feel fortunate to work
with Olivier for an extended period of time. I would like to thank him for sharing his skills and
experience. And I really appreciate his confidence in me.
I thank all my long-time friends and colleagues in the research group: Marian Chang,
Pearl Cao, Armin Fomani, Junmin Lee, Kendy Ng, Amy Shen, Andrew Shorten, Stella Tang,
Hao Wang, Gang Xie, Sherrie Xie, William Yu, Abraham Yoo, April Zhao. We collaborated on
various projects and/or volunteering works. It’s always a pleasant experience to work with them.
And their friendship makes my first few years in Toronto more than enjoyable. Special thanks to
v
Amy, Andrew, Armin and Kendy, without whom some of my work would be much more
difficult to accomplish.
Many thanks to Fuji Electric, who technically and financially support my research works.
I feel honored to work with some of their top engineers: Haruhiko Nishio-san, Masahiro Sasaki-
san and Tetsuya Kawashima-san. I am very impressed by their dedication to work and keen
focus on details. And I thank them for all valuable experience we shared in Japan.
I thank Jaro Pristupa, for his patient and timely technical support on CAD tools. I thank
my colleagues and friends in Prof. Prodić’s group: Conny Huerta Oliviares, Amir Parayandeh,
S.M. Ahsanuzzaman, Behzad Mahdavikhah, Mahmoud Shousha, for their help in my studies and
research. I also want to thank all course instructors in the Department of Electrical and
Computer Engineering, for the valuable knowledge and experience that I have received.
Last but not the least, I thank my family for their unconditional love and support all
through my PhD endeavour. I thank Oscar, for his friendship and love that has been
accompanying me even during the toughest times. We have been close friends for so many years
and I feel happy and fortunate that we finally come together. I would like to dedicate this thesis
to my parents, Xubin Wang and Yi Liu, for their love, understanding, patience and support when
I decided to move to Canada; to my loving mother, who just went through probably the hardest
time in her life but still stays so strong and is always there when I need her; to my father, who
has always been a role model, a friend, a mentor of me, who unfortunately passed away when I
was still editing this thesis and cannot witness my graduation. His love will be with me forever
and I will miss him forever. May he rest in peace.
vi
Table of ContentsTable of ContentsTable of ContentsTable of Contents
Chapter 1Chapter 1Chapter 1Chapter 1 ................................................................................................................... 1
1.1 Point-of-load Converter Fundamentals ................................................................... 2
1.1.1 Basic Architecture and Operating Principle .............................................. 3
1.1.2 Power Losses in Buck Converter .............................................................. 5
1.1.3 Load Transient Response of Buck Converter ........................................... 9
1.2 Design Requirement and Challenges .................................................................... 13
1.2.1 Small Converter Volume ......................................................................... 13
1.2.2 High Efficiency ....................................................................................... 14
1.2.3 Fast Load Transient Response ................................................................ 15
1.3 Digital Controllers ................................................................................................. 16
1.4 Design for Fast and Smooth Transient Response: Prior Arts ................................ 17
1.4.1 Time-Optimal Control Technique ........................................................... 18
1.4.2 Minimum Deviation Control Technique ................................................. 18
1.4.3 Steered-Inductor and Three-level Buck Converter ................................. 19
1.4.4 Converter Augmentation ......................................................................... 21
1.4.5 Buck Converter with Stepping Inductor ................................................. 23
1.5 Thesis Overview .................................................................................................... 24
Chapter 2Chapter 2Chapter 2Chapter 2 ................................................................................................................. 27
2.1 System Structure and Operating Principle ............................................................ 27
2.2 Steady State Compensator Design ........................................................................ 31
2.3 Controller Implementation .................................................................................... 39
2.3.1 Steady State Operation ............................................................................ 40
vii
2.3.2 Transient Detection and Load Step Estimation ....................................... 41
2.3.3 Predicting the New Steady-State Duty-cycle .......................................... 43
2.3.4 Generating the Switching Command ...................................................... 44
2.3.5 Blocking State after Transient Suppression ............................................ 45
2.3.6 Soft Starting after Power-on .................................................................... 45
2.4 Selecting the Auxiliary Stage Inductor ................................................................. 47
2.5 Sizing the Auxiliary Stage Transistors .................................................................. 51
2.5.1 Influence of Ron_A on the Inductor Current Model .................................. 51
2.5.2 Influence of Ron_A on the Dynamic Performance .................................... 53
2.5.3 Auxiliary Stage Sizing Consideration ..................................................... 56
2.6 Prototype Design and Experimental Results ......................................................... 58
2.6.1 Prototype Converter Using Discrete Output Stages ................................ 58
2.6.2 Prototype Converter Using Integrated Output Stages ............................. 63
2.7 Chapter Summary .................................................................................................. 68
Chapter 3Chapter 3Chapter 3Chapter 3 ................................................................................................................. 71
3.1 System Structure and Operating Principle ............................................................ 72
3.1.1 Steady-State Operation ............................................................................ 74
3.1.2 Heavy-to-light Load Transient Suppression ........................................... 75
3.1.3 Light-to-heavy Load Transient Suppression ........................................... 81
3.1.4 Inductor Volume ..................................................................................... 86
3.1.5 Conceptual Verification .......................................................................... 86
3.2 Steady State Controller Design ............................................................................. 90
3.3 Design of the Dual-mode Digital Control Unit ..................................................... 97
3.3.1 Heavy-to-Light Transient Operation ....................................................... 99
3.3.2 Light-to-Heavy Load Transient Operation ............................................ 100
3.3.3 Seamless Transition to Steady State ..................................................... 100
viii
3.3.4 Prevention of Undesired Mode Transitions .......................................... 102
3.4 Energy Recycling and Losses of the Auxiliary Switches ................................... 104
3.5 Prototype Design and Experimental Results ....................................................... 109
3.5.1 Prototype Implementation and Set-up ................................................... 109
3.5.2 Transient Performance .......................................................................... 112
3.5.3 Efficiency Comparison .......................................................................... 116
3.6 Chapter Summary ................................................................................................ 121
Chapter 4Chapter 4Chapter 4Chapter 4 ............................................................................................................... 123
4.1 Contributions ....................................................................................................... 123
4.2 Future Work ........................................................................................................ 126
4.2.1 Precise Load Step Estimation ................................................................ 126
4.2.2 Calibration Against Inductor Current Slew Rate Variation .................. 127
4.2.3 Design for Integration: Sizing the Auxiliary Switches ......................... 127
4.2.4 Integrated Controller ............................................................................. 128
References ............................................................................................................... 130
Appendix A ............................................................................................................... 140
Appendix B ............................................................................................................... 144
Appendix C ............................................................................................................... 147
ix
List of TablesList of TablesList of TablesList of Tables
TABLE 1.1 Typical PoL Converter Application and Critical Design Requirements 13
TABLE 1.2 Trade-offs Between Different Power Losses 14
TABLE 1.3 Trade-offs Between Converter Volume, Conversion Efficiency and Peak Load Transient Deviation 15
TABLE 2.1 Design Parameters of the Main Converter 32
TABLE 2.2 Design Parameters of ADC and DPWM Blocks 34
TABLE 2.3 Design Parameters of the Simulated Converter 54
TABLE 2.4 Component List of the Discrete Prototype 59
TABLE 2.5 Simulated On-Resistances of the Power Transistors 64
TABLE 2.6 Summary of Test Conditions 65
TABLE 2.7 Summary of Transient Performance 67
TABLE 3.1 Design Parameter of the Simulated Converter 86
TABLE 3.2 Design Parameters of the CPM Buck Converter 94
TABLE 3.3 Component List of the Prototype Converter 111
TABLE 4.1 Comparison of Converter Topology and Control Methods 124
x
List of FiguresList of FiguresList of FiguresList of Figures
Figure 1.1 Typical PoL architecture for PCB power supplies. 2
Figure 1.2 Typical buck converter topology. 3
Figure 1.3 Steady state waveforms of a conventional buck converter in continuous conduction mode. 4
Figure 1.4 A typical Vgs vs. Qg curve for a power MOSFET. 7
Figure 1.5 Turn-on and turn-off waveforms of a power MOSFET. 8
Figure 1.6 Buck converter with a voltage mode control loop. 9
Figure 1.7 Best-case heavy-to-light load transient response. 11
Figure 1.8 Transient current and voltage waveforms of a buck converter using time-optimal control method to recover a heavy-to-light load transient. 17
Figure 1.9 Transient current and voltage waveforms of a buck converter using minimum deviation control method to recover a heavy-to-light load transient. 19
Figure 1.10 Improving heavy-to-light load transient response using (a) steered inductor topology, (b) three-level buck converter and (c) buck-derived converter. 20
Figure 1.11 Improving load transient response through converter augmentation. 21
Figure 1.12 Theoretical waveforms for auxiliary stage controlled as (a) constant current source and (b) current source with adaptive slope. 22
Figure 1.13 Improving load transient response through using stepping inductor. 23
Figure 2.1 A digitally controlled DC-DC converter with an auxiliary output stage for fast load transient recovery. 28
Figure 2.2 Theoretical waveforms of load current i load(t), main stage inductor current iLM(t), auxiliary stage inductor current iLA(t) and output voltage deviation vout(t) – VREF under a heavy-to-light load transient. 29
Figure 2.3 (a) Architecture of the digital voltage mode controller for regulating steady-state output voltage, and (b) linearized model of the closed-loop system. 31
Figure 2.4 Bode plot of the uncompensated system. 35
xi
Figure 2.5 Block diagram of the digital PID compensator. clkfs is the steady-state clock signal. It is synchronized with the switching cycle of the converter. 36
Figure 2.6 Bode plots of the compensated system using (a) continuous-time domain compensator and (b) discontinuous-time domain compensator. 37
Figure 2.7 Block diagram of the controller. 39
Figure 2.8 State diagram of the digital controller. 40
Figure 2.9 Estimating load current step ∆i load from vout(t) deviation. 41
Figure 2.10 Equivalent circuit of the converter during the load current estimation period. 42
Figure 2.11 Compensate for the extra charge Q1 by increasing ton and toff. 44
Figure 2.12 Larger LM/LA ratio, e.g. smaller LA, results in smaller voltage overshoot but bigger voltage undershoot during heavy-to-light load transient recovery. 47
Figure 2.13 Capacitor and inductor currents during heavy-to-light load transient recovery. 48
Figure 2.14 Finding proper LM/LA ratio by trading off ∆vOvershoot and ∆vUndershoot during the heavy-to-light load transient recovery. 50
Figure 2.15 Finding proper LM/LA ratio by trading off ∆vOvershoot and ∆vUndershoot during the light-to-heavy load transient recovery. 50
Figure 2.16 On-resistance causes voltage drop across auxiliary stage transistor. 51
Figure 2.17 Theoretical waveforms of load current (i load), main stage inductor current (iLM), auxiliary stage inductor current (iLA) under heavy-to-light load transient taking into account the auxiliary switches' on-resistance. 52
Figure 2.18 Transient output voltage waveforms of converters using auxiliary switches with different on-resistances. 55
Figure 2.19 Transient current in the auxiliary and main stage. 56
Figure 2.20 Comparison of the active time for auxiliary output stages with different on-resistances. 57
Figure 2.21 Prototype converter to verify the transient suppression method and block diagram of the switching loads. 58
Figure 2.22 Steady-state conversion efficiency of a 6V-to-1V prototype converter. 60
Figure 2.23 Heavy-to-light load transient performance using (a) & (b) single-stage time-optimal control method and (c) proposed transient suppression method. 62
Figure 2.24 Block diagram of (a) the integrated dual output stage and (b) the gate driver. 63
xii
Figure 2.25 Micrograph of the integrated dual output stage. 64
Figure 2.26 Steady state efficiency of the integrated output stage. 65
Figure 2.27 Heavy-to-light load transient performance using (a) single-stage time-optimal control method and (b) transient suppression method using dual output stage. 66
Figure 3.1 The flyback-transformer based buck (FTBB) converter and the mixed-signal controller. 72
Figure 3.2 Equivalent circuit in steady-state operation. 74
Figure 3.3 Key current and voltage waveforms during a heavy-to-light load transient recovery process. 76
Figure 3.4 Equivalent circuit during during leakage inductance energy release (t1~t2) for large LLEAK. 77
Figure 3.5 Equivalent circuit during leakage inductance energy release (t1~t2) for small LLEAK. 78
Figure 3.6 Equivalent circuit showing that the energy in LLEAK is absorbed by the RC snubber circuit. 79
Figure 3.7 Equivalent circuit during heavy-to-light load transient recovery (t2 ~ t3). 80
Figure 3.8 Key current and voltage waveforms during a heavy-to-light load transient recovery process. 82
Figure 3.9 Equivalent circuit of the converter when current pulses in ip(t) suppress voltage undershoot (t1~t2). 83
Figure 3.10 Equivalent circuit of the converter when extra energy in LLEAK is recycled to the input power source (t2~t3). 84
Figure 3.11 Equivalent circuit of the converter when currents iLM(t) and ip(t) increase with a slew rate equal to an equivalent conventional buck converter (t3~t4). 85
Figure 3.12 Simulation waveforms of a buck converter using (a) conventional minimum-deviation control method and (b) the proposed method under a –3 A load current transient. 88
Figure 3.13 Simulation waveforms of a buck converter using (a) conventional minimum-deviation control method and (b) the proposed method under a +3 A load current transient. 89
Figure 3.14 (a) Architecture of the current mode controller that regulates the steady state operation, and (b) linearized model of the closed loop system. 90
Figure 3.15 Theoretical waveforms of the current-programmed control loop. 91
xiii
Figure 3.16 Block diagram of the digital PI compensator. 93
Figure 3.17 Bode plots of (a) the uncompensated loop transfer function and (b) the continous time-domain PI compensator. 95
Figure 3.18 Bode plots of the compensated loop transfer function using (a) continous-time PI compensator and (b) the digital PI compensator. 96
Figure 3.19 Block diagram of the controller. 97
Figure 3.20 State diagram of the digital controller. 98
Figure 3.21 Simplified equivalent circuits of the converter during the load current estimation period: (a) for a heavy-to-light load transient; (b) for a light-to-heavy load transient. 101
Figure 3.22 Simulation results for a full-load to no-load transient for the FTBB converter (left) and a buck converter (right). Top waveforms: output voltages vout(t); Middle waveforms: load currents i load(t); Bottom waveforms: input currents i in(t) of the converters. 107
Figure 3.23 Simulation results for a 100% to 33% load transient for the FTBB converter (left) and a buck converter (right). Top waveforms: output voltages vout(t); Middle waveforms: load currents i load(t); Bottom waveforms: input currents i in(t) of the converters. 108
Figure 3.24 Block diagram of the FTBB converter prototype. 109
Figure 3.25 Picture of the prototype FTBB converter. 110
Figure 3.26 Transient response of the conventional buck converter for a 3 A heavy-to-light load transient. Top: the buck-inductor current iL(t), scale 4 A/div; Middle: ac component of the output voltage vout(t), scale 100 mV/div; Bottom: load step command i load(t). Time scale is 20 µs/div. 113
Figure 3.27 Transient response of the FTBB converter for a 3 A heavy-to-light load transient. Top: the primary current ip(t), scale 4 A/div; Middle: ac component of the output voltage vout(t), scale 100 mV/div; Bottom: load step command iload(t). Time scale is 20 µs/div. 113
Figure 3.28 Transient response of the conventional buck converter for a 3 A light-to-heavy load transient. Top: the buck-inductor current iL(t), scale 4 A/div; Middle: ac component of the output voltage vout(t), scale 50 mV/div; Bottom: load step command i load(t). Time scale is 5 µs/div. 115
Figure 3.29 Transient response of the FTBB converter for a 3 A light-to-heavy load transient. Top: the primary current ip(t), scale 4 A/div; Middle: ac component of the output voltage vout(t), scale 50 mV/div; Bottom: load step command i load(t). Time scale is 5 µs/div. 115
xiv
Figure 3.30 Test setup for power consumption measurement. 116
Figure 3.31 Steady-state efficiency of the conventional single stage buck converter and the FTBB converter. 118
Figure 3.32 Dynamic power consumption of the FTBB converter and the conventional single stage buck converter. 120
Figure 3.33 Comparison of effective efficiency of the conventional buck and the FTBB converters under frequently changing load conditions. 120
Figure A.1 Ideal waveforms of load current i load(t), main stage inductor current iLM(t), auxiliary stage inductor current iLA(t) and output voltage deviation vout(t)-VREF under a heavy-to-light load transient. 140
Figure A.2 Waveforms of main stage inductor current iLM(t), auxiliary stage inductor current iLA(t) and output voltage deviation vout(t)-VREF under a heavy-to-light load transient, taking into account the transient detection and load estimation delays. 141
Figure A.3 Equivalent circuit during the current steering phase of a heavy-to-light load transient recovery with auxiliary switches' on-resistances included. 145
Figure A.4 Equivalent circuit during light-to-heavy load transient recovery with auxiliary switches' on-resistance included. 146
xv
List of AppendicesList of AppendicesList of AppendicesList of Appendices
Appendix A A Practical Calculation of Auxiliary State On/Off Times .................................. 140
Appendix B Influence of the the Auxiliary Switches' On-resistance on the Transient Performance of the Flyback-Transformer Based Buck Converter ...................... 143
Appendix C List of Publications .............................................................................................. 147
1
Chapter 1Chapter 1Chapter 1Chapter 1
IntroductionIntroductionIntroductionIntroduction
In modern low-power applications such as mobile devices, consumer electronics, and
communication equipment, point-of-load (PoL) switch-mode power supplies (SMPS) are
required to provide tightly regulated voltage with small deviation during load transients. In these
systems, usually operating with no larger than 1V supply voltage, the SMPS output voltage
deviation is typically limited to tens of millivolts, to ensure proper system performance [1]. It is
also highly desirable to minimize the volume of the SMPS reactive components, i.e. their output
filters, which in the targeted applications usually take a significant portion of the entire device.
As a guideline for the power supply designers, the Power Source Manufacturers
Association (PSMA) published the 2011 PSMA Power Technology Roadmap (PTR). For non-
isolated PoL DC-DC converters, PSMA provides an outlook on 2010-2015 technology trends
that includes but not limited to: tighter voltage set point windows; lower output voltage ripple;
faster transient response; higher efficiency and power density [2].
This thesis focuses on improving the transient response of sub-3 W PoL converters in
particular. These low-power PoL converters have wide usage in telecommunication and/or data-
communication systems as well as battery-powered systems. In Chapter 1 of this thesis, a brief
introduction to modern PoL power solutions will be provided, followed by an overview of the
research work to be presented. Chapters 2 and 3 introduce two different approaches to improve
the load transient performance of PoL converters without degrading the power conversion
efficiency. Conclusions and suggestions for future work will be given in Chapter 4.
In this introductory chapter, fundamentals on DC-DC converters will be reviewed in
Section 1.1. The design requirements proposed in the 2011 PSMA report, as well as various
challenges will be analyzed in Section 1.2. The application of digital control technique in low
2
power DC-DC converters will be briefly reviewed in Section 1.3. Prior research work focusing
on fast and smooth transient response for DC-DC converters will be summarized and discussed
in Section 1.4. An overview of the research work conducted during the progress of this thesis
will be provided in Section 1.5.
1.1 Point-of-load Converter Fundamentals
With the development of modern semiconductor technology, higher level of integration
enables electronic systems to incorporate more and more functions onto increasingly smaller
printed circuit boards (PCB) [3]-[5]. As a result, the landscape of PCB has changed from
multiple ICs with a single power supply voltage to a combination of microprocessors (µPs),
DSPs, analog and digital circuits operating with multiple supply voltages ranging from 3.3V to
less than 1V (see Figure 1.1). For power supply designers, it is inevitable to shift from the
traditional distributed power architecture to a two-stage conversion scheme, which includes an
AC-DC converter that converts the AC line voltage to an intermediate DC bus voltage, and a set
of DC-DC converters that convert the DC bus voltage to the desired value at the point-of-load
(PoL) [6]-[7]. By placing PoL converter near the load ICs, the long wiring between the DC bus
and the load can be eliminated. This enables more precise regulation of the voltage supply while
fulfilling low-voltage and high-current requirements.
Figure 1.1 Typical PoL architecture for PCB power supplies.
3
1.1.1 Basic Architecture and Operating Principle
In a typical point-of-load power supply architecture, PoL converter converts the bus
voltage into a lower voltage required by the load, as shown in Figure 1.1. The PoL converter is
usually implemented in a buck or step-down configuration as shown in Figure 1.2. Vin is the
input voltage, which can be supplied by batteries, DC bus, or other DC voltage sources. The
switch that is connected between the input source and the inductor L is called the “main switch”
(MS). It is usually implemented with a power MOSFET. The other switch connected between
the inductor L and the ground terminal is the rectifier. It can be implemented with either a power
MOSFET (synchronous rectifier, SR) or a free-wheeling diode (asynchronous rectifier). MS and
SR turn on alternatively within each switching period Ts, with a switching frequency, fs = 1/Ts.
The common node in between the MS, SR switches and inductor L is called the switching node,
which is denoted as vx.
Basic steady-state voltage and current waveforms of a conventional buck converter under
continuous conduction mode (CCM) are as shown in Figure 1.3. Within each switching period
Ts, the percentage of time when the MS is on while SR is off is denoted as the duty-cycle D. On
the other hand, the percentage of time when the MS is off while SR is on is generally denoted as
D' or 1 − D. When the MS switch is on, the switching node vx is pulled to Vin. The current iL(t)
in the inductor ramps up with a slew-rate of kD. When the MS is off, the switching node vx is
pulled to ground. The current iL(t) in the inductor ramps down with a slew-rate of kD'. The
inductor’s ripple current ∆iL is defined as half the magnitude of the peak-to-peak variation of
iL(t), which is determined by (1.1).
Figure 1.2 Typical buck converter topology [8].
4
( ) ( )1
2 2 2in out s in out
L D ss
V V DT V V Di k DT
L Lf
− −∆ = ⋅ = = (1.1)
For a buck converter operating in steady state, the inductor current iL(t) stays the same at the
beginning and the end of each switching cycle. This phenomenon is called "inductor volt-second
balance" [8], from which the relationship between the input voltage Vin and average output
voltage Vout can be derived as
' '
'
D s D s
in out outs s
out in
k DT k D T
V V VDT D T
L LV V D
⋅ = ⋅−
⇒ ⋅ = ⋅
⇒ = ⋅
. (1.2)
As shown in Figure 1.3, the actual output voltage waveform vout(t) has small ripple
superimposed on the average value Vout due to the charging and discharging of output capacitor
MS on
SR off
MS off
SR onVin
vx(t)
Iload
iL(t)
kD kD’
vout(t)
iC(t)
iL
Vout vripple
DTs D’Ts
t
t
t
t0 t0+Ts
Figure 1.3 Steady state waveforms of a conventional buck converter in continuous conduction mode.
5
Cout within each switching period. The ripple voltage ∆vripple is defined as half the peak-to-peak
variation of vout(t), which is proportional to the area of the grey triangle surrounded by the iC(t)
waveform.
1 1
2 2 2 8s L s
ripple Lout out
T i Tv i
C C
∆∆ = ⋅ ∆ = (1.3)
In steady state, vout(t) will return to the same voltage after each switching period Ts due to
"capacitor charge balance" [8], which implies that the averaged capacitor current iC within each
Ts equals zero. As a result, the following expression can be deduced for the average inductor
current IL, where I load is the steady-state load current.
L loadI I= (1.4)
1.1.2 Power Losses in Buck Converter
Understanding different sources of power losses in buck converter helps power supply
designers to analyze and optimize conversion efficiency. Mechanisms of converter's power
losses have been comprehensively studied and illustrated in [10]-[11], among which the
conduction loss, gate-drive loss and switching loss at the output power stage of the buck
converter are the dominant ones [9] and thus will be illustrated in details below.
A Conduction Loss
The conduction loss mainly results from the on-resistance of power switches (Ron,MS and
Ron,SR), equivalent series resistance (ESR) of output inductor (RL), and ESR of output capacitor
(RESR).
The conduction loss on the power switches is given by
2 2, , , , ,cond SW on MS rms MS on SR rms SRP R I R I= ⋅ + ⋅ . (1.5)
Ron,MS and Ron,SR are inversely proportional to the aspect ratio (W/L) of the power MOSFETs. For
a fixed channel length (L), power MOSFET with bigger width (W) has smaller on-resistance but
occupies a larger chip area. Irms,MS and Irms,SR are the root-mean-square (rms) drain-to-source
currents that flow through the MS and SR switches, respectively. Irms,MS and Irms,SR are evaluated
6
from the averaged inductor current (equals I load for buck converters) as well as the amount of
inductor current ripple (∆iL) defined by (1.1).
22
, ( )3L
rms MS loadi
I D I∆= + (1.6)
22
, '( )3L
rms SR loadi
I D I∆= + (1.7)
The current flowing through the output inductor is the sum of the switch currents. Thus
conduction loss on the inductor's ESR can be expressed as
22 2
, , ( )3L
cond L L rms L L loadi
P R I R I∆= ⋅ = ⋅ + . (1.8)
As shown in Figure 1.3, when a buck converter is in steady state, the current iC(t) flowing into
the output capacitor Cout contains only the ripple portion of iL(t). Thus the conduction loss on the
capacitor ESR is given by
2
, 3L
cond C ESRi
P R∆= ⋅ . (1.9)
If we define the equivalent series resistance of the buck converter to be
, ,'eq on MS on SR LR DR D R R= + + , (1.10)
the total conduction loss obtained by combining (1.5), (1.8), and (1.9) can be simplified as
22 ( )
3L
cond eq load eq ESRi
P R I R R∆= ⋅ + + . (1.11)
For a given load current I load, the first term on the right side of (1.11) can only be reduced by
selecting power MOSFETs and inductors with small series resistances. The second term,
according to (1.1), can be minimized by using a bigger inductor or switching at a higher
frequency.
7
B Gate-drive Loss
In each switching cycle, the MS and SR power switches turn on and off alternatively,
which requires periodic charging and discharging of the power MOSFETs’ gate capacitances.
The amount of power provided by the gate driver during this process is usually called "gate-drive
loss" or "gating loss". It is independent of the gate driver's driving capability, but heavily
dependent on the physical structure of the MOSFET switches and the switching frequency, fs. A
generic expression of gate-drive loss is given in (1.12) [11]
gate g gs sP Q V f= ⋅ ⋅ , (1.12)
where Vgs is the gate-to-source voltage of a power MOSFET when it is ON. In conventional
buck converters, this voltage usually equals to the input voltage Vin. In converters adopting
advanced control scheme [13]-[17], the Vgs swing can be dynamically adjusted to achieve
efficiency optimization for different load conditions. Qg is the total gate charge under a given Vgs
voltage. It is usually specified by MOSFET manufacturers using the Vgs vs. Qg curve as shown
in Figure 1.4, which assumes the gate is driven by a constant current source. There are several
aspects that influence Qg, such as the gate dielectric material and fabrication process [18]-[19],
00
5 10 15 20
2
4
6
8
10
12
Qg (nC)
Vg
s(V
)
Increasing Vds
Figure 1.4 A typical Vgs vs. Qg curve for a power MOSFET [12].
8
the layout of the MOSFET [20]-[21], and the size of the device, etc. Generally speaking, a
MOSFET with larger gate area (W×L) has bigger Qg and thus requires more gate-drive power to
turn on.
C Switching Loss
Another major source of power loss is the power dissipated on the channel of power
MOSFET switch during every turn-on and turn-off process. Due to the existence of parasitic
capacitances, the actual power MOSFET switches have finite turn-on and turn-off time. During
each switching action, both the drain-to-source voltage vds and drain-to-source current ids of the
MOSFET ramp with finite slew-rates. Theoretical ids and vds waveforms during hard turn-on and
turn-off for a power MOSFET is as shown in Figure 1.5. This is an approximation of the actual
waveforms, which usually contain a significant amount of ringing, but is still accurate enough to
estimate the switching loss. The shaded overlap areas of the ids and vds waveforms indicates
switching loss. This is usually referred to as hard-switching loss. Assuming a turn-on time of
tsw,on and a turn-off time of tsw,off, the switching loss in a conventional buck converter is given by
, ,
, ,
( )2
( )2
ds dsSW sw on sw off s
in loadsw on sw off s
V IP t t f
V It t f
⋅= +
⋅≈ +. (1.13)
ids
vds
tsw,on tsw,off
Switching loss happens in the
shaded section
Vds Ids
Figure 1.5 Turn-on and turn-off waveforms of a power MOSFET [11].
9
1.1.3 Load Transient Response of Buck Converter
The transient response of a buck converter reflects its capability to adapt to sudden
changes in input voltage (line transient) and/or load current (load transient). This work focuses
on the load transient response, which is usually evaluated by the amount of peak output voltage
deviation as well as the time it takes for the output voltage to return to its steady state value
(recovery time).
Load transient response of a conventional buck converter is mainly determined by the
control loop bandwidth, phase margin and the characteristic of output LC filter.
A typical voltage-mode control loop is as shown in Figure 1.6. This negative feed-back
scheme applies to both analog and digitally controlled buck converters. The output voltage vout
is sampled and compared with a voltage reference VREF, generating an error signal e. A
compensator module Gc is inserted to tune the closed-loop transfer function that ideally has
L
Cout
vout
iloadvx
iL
Vin
MS
SR
cMS(t) cSR(t)
Gate
Drivers
Dead-time Controllerc(t)
sample vout
VREF
eGc
ecPWMc(t)
iC
Figure 1.6 Buck converter with a voltage mode control loop.
10
infinite DC gain, wide loop bandwidth and enough phase-margin to ensure system stability. The
compensated signal ec is fed into a pulse-width modulation (PWM) block which generates a
control signal c(t) that determines the duty-cycle. The dead-time module converts c(t) into two
non-overlapping signals cMS(t) and cSR(t) to prevent simultaneous turn-on of the two power
switches.
When vout deviates from the reference voltage, the control loop reacts by modulating the
duty-cycle, i.e. the on and off time of MS and SR, trying to bring vout back to VREF. The close-
loop system's cross-over frequency fc determines how fast the modulation can be performed. A
phase margin of greater than 45˚ is usually required to ensure stability and to suppress output
voltage ringing during transient recovery. For a voltage-mode controlled converter, increasing
the close-loop bandwidth can also improve transient response provided that the phase margin is
maintained. However, the maximum close-loop bandwidth of the controller is usually limited to
1/10th to 1/5th of the switching frequency [8], beyond which the control loop design based on
small-signal linearization techniques is no longer valid and stability is difficult to guarantee [22].
For a buck converter, the recovery time after load current changes is inherently limited by
the slew-rate of inductor current. A heavy-to-light load step example is as illustrated in Figure
1.7. In this best-case transient response, the inductor current iL(t) ramps down with maximum
possible slew-rate immediately after the load step occurs. This usually cannot be achieved using
a conventional linear controller based on small-signal model due to limited close-loop
bandwidth. Instead, a number of non-linear controllers have been implemented [23]-[26] to
address this issue.
After a sudden negative load current step with amplitude ∆i load occurs at time t0, the MS
switch is turned off and the SR switch is turned on. The inductor current iL(t) ramps down with
slew-rate k1 for a time period noted as toff. At this point the SR is turned off and the MS is turned
on. The inductor current iL(t) ramps up with slew-rate k2 for a period of ton until it reaches the
new load current level. Ideally, toff and ton are set such that the output voltage vout is brought back
to its steady-state value within a single on-off switching action. In this case, it is required that
the excess charge Q1 injected to the output capacitor Cout is balanced by Q2, the amount of charge
taken out, as represented by the shaded areas in Figure 1.7.
11
The inductor current slew-rates k1 and k2 are determined by
1
2
out
in out
Vk
LV V
kL
= −
−=. (1.14)
Assuming that the magnitude of the load current step, ∆i load is much larger than the steady-state
inductor current ripple, ∆iL, the time intervals toff and ton can be calculated by equating Q1 and Q2:
1 1 2
1(1 )
1 /load
offi
tk k k
∆= +
+ (1.15)
2 1 2
1
1 /load
oni
tk k k
∆= ⋅+
(1.16)
Figure 1.7 Best-case heavy-to-light load transient response.
12
By combining (1.15) and (1.16) and replacing k1 and k2 with (1.14), the total recovery time TR is
given by:
(1 1 )load outR
out in out
i L VT
V V V
∆= + +−
. (1.17)
The best-case peak voltage deviation, ∆vout during the transient recovery can be calculated from
21
2load
outout out out
i LQv
C C V
∆∆ = = . (1.18)
Equations (1.17) and (1.18) indicate that both the best-case transient recovery time TR and the
peak voltage deviation ∆vout are directly proportional to the inductance L in the buck output
stage. It is an inherent limitation regardless of controller architecture or switching frequency.
13
1.2 Design Requirement and Challenges
TABLE 1.1 outlines some of the typical applications of point-of-load (PoL) power
converters and their critical design requirements. Generally speaking, small volume, high
efficiency and fast reaction to load transients are the top preferred characteristics of PoL
converters, although different application environment may have different emphasis on each of
these requirements. The trade-offs and design challenges will be discussed in details in the
following subsections.
1.2.1 Small Converter Volume
Continuously shrinking printed circuit board (PCB) geometry and the increasing demand
for more functions per unit area make it necessary for power converters to have high power
density and small physical size. Power-supply-in-a-package (PSiP) allows the integration of the
DC-DC controller and the output power stage into the same package [2], [30]. There has also
been a growing trend for PoL converters to be implemented with digital controllers [31]-[32].
Instead of using bulky external resistor-capacitor (RC) network as in most analog controlled
converters [33]-[34], loop compensation in a digitally controlled converter is performed through
algorithms programmed on-chip.
TABLE 1.1. TYPICAL POL CONVERTER APPLICATION AND CRITICAL DESIGN REQUIREMENTS
Applications Design Requirements
Portable electronic devices [22] Small volume, high efficiency
General purpose FPGA/µPs core power supply [27][28]
High efficiency, small volume, fast response to highly dynamic load
General purpose FPGA/µPs I/O power supply [27][28]
High efficiency, small volume
Tele/Data communication system [29]
High efficiency, fast response to highly dynamic load
Digital media system [45] Fast response to highly dynamic load, small volume,
high efficiency
14
On the other hand, virtually all commercial PoL converter ICs in the 3-W power level
require off-chip output LC filters, which take up considerable percentage of the total converter
volume [22]. Efforts have been made to reduce the size of passive components by running the
converter at very high switching frequencies (e.g. multi-MHz). However, this often leads to
increased frequency-related losses such as gate-drive loss and switching loss, which inevitably
degrade the power conversion efficiency.
1.2.2 High Efficiency
The power conversion efficiency of DC-DC converters is defined as the ratio of the
output power over the input power. The major sources of efficiency degradation include
conduction, gate-drive and switching losses, which have been introduced in Section 1.1.2.
Though the peak power-conversion efficiency of a PoL converter is typically advertised as the
primary benchmark, a good efficiency profile with high efficiency over the entire load range is
usually more desirable. For PoL converters under frequent load current changes, the overall
efficiency, taking into account both steady state and transient conditions, is also an important
specification.
Among the three major sources of power loss, the gate-drive and switching losses are
proportional to the switching frequency and the size of power switches. Conduction loss
increases with the inductor current and the ripple current. When designing a converter for high
efficiency, trade-offs among different types of power loss are usually required. TABLE 1.2
summarizes these trade-offs qualitatively.
TABLE 1.2. TRADE-OFFS BETWEEN DIFFERENT POWER LOSSES
Actions Conduction Loss Gate-Drive Loss Switching Loss
Increase switching frequency fs
Decrease due to smaller ∆iL
Increase Increase
Decrease switching frequency fs
Increase due to bigger ∆iL
Decrease Decrease
Increase channel width of power MOSFET
Decrease due to smaller Ron
Increase due to higher Qg
Increase due to longer tsw,on/off
Decrease channel width of power MOSFET
Increase due to bigger Ron
Decrease due to lower Qg
Decrease due to shorter tsw,on/off
15
1.2.3 Fast Load Transient Response
PoL converters, depending on application environment, may undergo frequent load
current changes at a high repetition rate. For example, PoL converters in telecommunication
equipment can support a load transient repetition rate of 5 ~ 10 kHz [35]; and PoL converters in
the voltage regulator module (VRM) for processors may experience a load transient repetition
rate of over 200 kHz [4][36]. In order to guarantee proper performance of the load ICs, these
PoL converters are required to provide a stable output voltage and keep the voltage fluctuation
within a tight tolerance band. They must be able to respond to a load transient quickly without
significant disturbance at the output voltage.
Equation (1.18) indicates that a large output filter capacitor Cout could help suppressing
the peak transient voltage deviation. But a large Cout normally results in higher cost and bigger
physical volume. Fast transient response in the controller allows the converter to not solely rely
on a large Cout to maintain the output voltage within a certain tolerance during load transients.
For a PoL converter using linear control methods, this usually requires the use of a small output
LC filter and switching at high frequencies to ensure a wide control-loop bandwidth. However,
the improvement in dynamic performance is usually traded-off by degradation in efficiency due
to frequency related power losses [37].
The trade-offs between converter volume, conversion efficiency and peak voltage
deviation during load transient are summarized in TABLE 1.3. These trade-offs make the design
consideration of PoL converters non-trivial. Thus new converter topologies and control
algorithms need to be explored in order to achieve an optimum performance balance.
TABLE 1.3. TRADE-OFFS BETWEEN CONVERTER VOLUME, CONVERSION EFFICIENCY AND PEAK LOAD TRANSIENT DEVIATION
Actions Volume Efficiency Peak ∆∆∆∆Vout Increase switching
frequency fs - lower smaller
Decrease output stage inductance L
smaller lower smaller
Increase output stage capacitance Cout
bigger - smaller
16
1.3 Digital Controllers
With the development of modern VLSI technology, the cost for implementing digital
integrated circuit continues to reduce over the years [1]. Digital controllers in power electronics
are also gaining interests due to their well-known advantages such as re-programmability,
flexibility, IP re-use across different fabrication technologies, quick hardware verification via
FPGA, low sensitivity to process, voltage and temperature (PVT) variations, direct interface with
digital buses and other systems, ability to implement sophisticated control algorithms and
achieve robust compensation over a wide-range of specifications [38].
Low-power digitally controlled DC-DC converters have shown steady improvement
since the first counter-based digital pulse-width modulator (DPWM) design [39]. The
introduction of the delay-line based DPWMs [40]-[41] made digital controllers a viable option in
low power portable environment. Traditional digital controller designs are intended to mimic the
functionality of analog compensators. Therefore, most digital controllers can only have similar
performance as their analog counterparts, typically at a higher implementation cost and power
consumption. The true capability of low-power digital control becomes apparent with the
introduction of more flexible designs, such as the use of segmented output stage to dynamically
adjust the size of the output transistors according to load conditions to achieve high power
conversion efficiency over a wide range of load current [16]-[17], [42]-[45], dead-time
correction schemes to continuously optimize the dead-times for the power switches [46]-[50],
digital spread-spectrum techniques that effectively suppress conductive electromagnetic
interference (EMI) [51]-[53], and digital auto-tuning techniques that can adjust compensator
parameters on-the-fly to accommodate passive component variations [54]-[58]. Digital
controllers also have the ability to switch seamlessly between operating modes, such as pulse-
width modulation (PWM), pulse-frequency modulation (PFM), pulse-skipping mode, etc. [59].
They are also capable of realizing advanced control algorithms to achieve near-optimal load
transient response.
17
1.4 Design for Fast and Smooth Transient Response:
Prior Arts
Various novel strategies were proposed to improve the load transient response of PoL
buck converters. In general, these techniques can be categorized into linear control techniques
and non-linear control techniques.
Linear control techniques in [60]-[63] are based on the small-signal model. They re-
shape the converter's close-loop transfer function during load transient to temporarily increase
the loop bandwidth. However, only a moderate improvement in transient response is observed
since the maximum loop bandwidth in these systems is still limited by the stability and phase
margin requirement.
Non-linear control techniques are gaining popularity since they enable the converters to
break the bottle-neck of control loop bandwidth, switching frequency and/or the physical
constrains of output LC filter [64]. As a result, they can drastically improve the dynamic
response of converters and, to some extent, mitigate the trade-offs in efficiency and physical
volume.
In this section, existing non-linear control techniques are reviewed. The advantages and
iload(t) Q1
Q2Q1 = Q2
iL(t)
vout(t)
k1 = -Vout/L
vout Q1Vout
toff ton
iload
Figure 1.8 Transient current and voltage waveforms of a buck converter using time-optimal control method to recover a heavy-to-light load transient.
18
disadvantages of each solution are discussed.
1.4.1 Time-Optimal Control Technique
Time-optimal control, also known as one-step recovery control, has been proven to
achieve the optimum load transient response for a given output LC filter, without modifying the
topology of the buck output stage. Time-optimal controlled buck converters based on the
capacitor charge-balance algorithm [24]-[26], [65]-[67] or state-space switching surface [68]-
[71] have been demonstrated. Ideal transient waveforms are as illustrated in Figure 1.8. The
controller responds to a load transient with a single on/off or off/on switching action. In the
heavy-to-light load transient example shown in Figure 1.8, the SR switch is kept on such that the
inductor current iL(t) ramps down till it equals to the load current i load(t). At this point the output
overshoot voltage, ∆vout reaches its peak value, which is proportional to the amount of charges
injected into the output capacitor Cout, as indicated by Q1. The turn-off (toff) and turn-on (ton)
times in a time-optimal controller are determined such that both the output voltage and inductor
current are fully restored by the end of the recovery process. This method provides the shortest-
possible recovery time and the minimum-possible transient voltage deviation for a conventional
buck converter. However, the peak output voltage deviation, ∆vout during load transient is still
limited by the inductor current slew-rate, k1, which in turn is dependent on the output stage
inductance as well as the input and output voltages of the converter [74][75].
21
12load
outout out
iQv
C C k
∆∆ = =⋅
(1.19)
1.4.2 Minimum Deviation Control Technique
Minimum deviation control provides a simpler solution compare to the time-optimal
control method, aiming at minimizing the output voltage deviation but not the transient recovery
time. A minimum deviation controlled two-phase buck converter was demonstrated in [72][73].
Similar to the time-optimal control method, minimum deviation controller also responds to a
load transient with a single on/off or off/on switching action. As shown in Figure 1.9, after a
heavy-to-light load transient occurs, the controller turns on the SR switch to recover the inductor
current iL(t) with maximum possible slew-rate, k1. After iL(t) catches up with the load current
i load(t), the controller starts to regulate the output voltage with conventional linear control
19
method, rather than trying to achieve capacitor charge balance. The peak voltage deviation ∆vout
obtained using this method is the same as (1.19), which is proportional to the amount of charge
Q1 and inherently limited by the current slew-rate k1 in the power inductor.
1.4.3 Steered-Inductor and Three-level Buck Converter
In order to overcome the physical limitation of inductor current slew-rate in conventional
buck output stages, several approaches were introduced in [76]-[79] where additional power
transistors and/or diodes are used to increase the voltage applied across the power inductor
during transient recovery.
Figure 1.10 (a) illustrates the equivalent circuit of a buck converter with steered-inductor
during heavy-to-light load transient recovery [76]-[77]. Two additional switches S0 and S1 are
used. In steady state, S0 is kept on and S1 is kept off while MS and SR transistors operate as in a
conventional buck converter. To assist heavy-to-light load transient recovery, switches MS and
S0 are turned off, SR and S1 are turned on to "steer" the inductor current back to the input voltage
source following the highlighted path. During this time period, the inductor current, iL ramps
down with a slew-rate determined by k = –Vin/L. For PoL converters with low voltage
conversion ratio, this value is usually much higher than the slew-rate, k1 in a conventional buck
converter as expressed in (1.14).
iload(t) Q1
iL(t)
vout(t)vout Q1
k1 = -Vout/Liload
Vout
Figure 1.9 Transient current and voltage waveforms of a buck converter using minimum deviation control method to recover a heavy-to-light load transient.
20
The three-level buck converter [78] makes use of the input capacitor, Cin in the buck
converter to generate an auxiliary power supply during transient recovery. As shown in Figure
1.10 (b), Cin is charged to Vin through switches S1 and S0 during steady state. During transient
recovery, the polarity of Cin is reversed through switches S2 and SR. As a result, the voltage at
switching node vx = –Vin, which allows rapid drop of inductor current iL.
A buck-derived converter was introduced in [79]. An extra switch S0 is inserted between
the ground terminal of the output LC filter and the negative terminal of the input power supply.
A power diode D0 is also connected to assist transient recovery. When a heavy-to-light load
L
Cout
vout
iload
iL
Vin
MS
SR
S0
S1
(a)
(b)
(c)
Figure 1.10 Improving heavy-to-light load transient response using (a) steered inductor topology, (b) three-level buck converter and (c) buck-derived converter.
21
transient occurs, the MS and S0 switches are turned off while the SR switch is turned on. The
inductor current, iL will flow from the ground terminal of D0 towards the output node. The
voltage at the switching node, vx is clamped to –(Vin+VD), where VD is the forward voltage drop
of the diode, D0. Therefore the inductor current slew-rate in this topology is k = –
(Vout+Vin+VD)/L.
The above-mentioned techniques aim at boosting the negative voltage across the power
inductor to achieve high current slew-rate while reducing the energy storage requirements of the
output capacitor. However, these topologies have little impact on the light-to-heavy load
transient response. More importantly, the conduction loss in steady state is increased due to the
additional switches in series with the main power conduction path.
1.4.4 Converter Augmentation
The augmented buck converter structures, connecting a small auxiliary power stage in
parallel with the main output stage, are introduced in [80]-[97]. The main converter output stage
is responsible for steady-state operation. It can be implemented with a large inductor to achieve
optimum steady-state power conversion efficiency. The auxiliary stage examples include
additional circuits consisting of power switches and an additional inductor [80]-[89], a
transformer [90]-[92], an inductor-capacitor (LC) network [93]-[94], a resistor-capacitor (RC)
network [95]-[96], or a pair of linearly controlled active clamps [97] to provide a secondary
Figure 1.11 Improving load transient response through converter augmentation.
22
conduction path with high current slew-rate. It is activated during transient recovery to help
inject or remove charge from the output capacitor and suppress transient voltage deviation.
Analog-controlled augmented converter based on a pair of hysteresis comparators have
been demonstrated in [80]-[84], [89]-[97]. Digital implementations where the auxiliary stage is
controlled as a constant current source [88] or a current source with adaptive slope [85]-[86]
were also investigated. These augmented converters achieve significant improvement in
transient voltage deviation. However, for frequent transients, the auxiliary circuit usually
negatively affects the converter efficiency due to high-frequency switching of the auxiliary
switches [87]. Moreover, these auxiliary stages were implemented with discrete components.
They took up comparable space on the circuit board as the main converter, which essentially
doubles the size of the output stage.
(a)
(b)
Figure 1.12 Theoretical waveforms for auxiliary stage controlled as (a) constant current source [88] and (b) current source with adaptive slope [85]-[86].
23
1.4.5 Buck Converter with Stepping Inductor
In [98]-[100], a stepping inductor based on switch and transformer network was applied
to a single phase voltage regulator module (VRM). A three-winding transformer replaces the
power inductor of a conventional buck converter. In steady state, the buck converter operates
using the primary winding of the transformer as the power inductor L. It has large magnetizing
inductance and thus results in low current ripple. When a load transient event is detected, the
secondary LS or the tertiary winding LT of the transformer is shorted to the input power source to
generate a constant voltage across the primary winding. This technique reduces the effective
inductance in the buck converter to a much smaller leakage inductance of the transformer, which
allows rapid changes in current flow to suppress voltage over-/undershoot. In the meantime, the
constant voltage generated across the primary winding forces the circulating current in the
magnetizing inductor to gradually catch up with the load current. The single phase VRM in
[98]-[100] effectively minimizes the transient voltage deviation with a minor increase in the
inductance volume and no extra switches added to the main conduction path. However, this
previously reported solution is not the most suitable for the targeted low-voltage applications,
due to the limitations of the power transistors’ blocking voltage. In low power applications, the
transistors are usually integrated with the controller, and implemented in a cost-effective low
voltage CMOS technology. These transistors can only handle a voltage slightly larger than the
supply, limiting the ability of the stepping inductor systems to improve heavy-to-light transient
response. During the transients the reflected auxiliary winding voltage reduces the voltage
Figure 1.13 Improving load transient response through using stepping inductor [100].
24
across the leakage inductor [100] to a very low value. As a consequence, the benefit of an
improvement in the current slew-rate using the stepping inductor is nullified. An attempt to
minimize this problem by increasing the windings turns ratio would significantly increase the
blocking voltage requirements for the auxiliary side transistors. The blocking voltage
requirement could be several times higher than the supply voltage, preventing cost-effective
implementation and possible on-chip integration.
1.5 Thesis Overview
The main goal of this thesis is to explore digital control techniques that allow PoL
converters to have fast and smooth load transient response and maintain high overall efficiency.
The majority of the research work is presented from a system-level perspective, though the
feasibility for fully integrated solutions is also investigated.
The research work in this thesis consists of two parts. In the first part, a voltage-mode
controlled buck converter with a small auxiliary output stage to improve load transient response
is investigated. The main buck output stage is responsible for steady-state operation. It is
designed to achieve high conversion efficiency using large inductor and power transistors with
low on-resistance. The auxiliary stage is responsible for transient suppression and is only active
when a load transient occurs. A digital transient suppression circuit is implemented based on the
capacitor charge balance principle [24]-[26], aiming at recovering the output voltage and current
with only one on-off switching action. A fully integrated dual-output stage is designed and
fabricated. Theoretical analysis and experiment show that the auxiliary output stage performs
well with inductor and power transistors much smaller than those of the main switching stage.
The dual output stage converter achieves well balanced power conversion efficiency and
dynamic performance with a much smaller area penalty than most previously published
augmented converters. However, the auxiliary power stage requires a separate inductor, which
results in noticeable increase in the overall inductance size and volume. To mitigate this issue, in
the second part of this research, a flyback transformer based transient suppression method is
proposed. The flyback-transformer based buck (FTBB) converter provides a simple, low-cost
solution that overcomes current slew-rate limitations of the conventional buck with a low or no
penalty in the power processing efficiency and the overall inductance volume. During load
25
transient recovery, the current slew-rate in the power stage is increased with the help of the
secondary winding of the flyback transformer and several small auxiliary switches. Peak voltage
deviation under both heavy-to-light and light-to-heavy load transients is successfully suppressed.
Oscillation between operating modes is avoided through digital control technique. Power loss
measurement shows that the proposed structure has slightly higher conduction loss compare to a
conventional single stage buck converter under steady-state heavy-load conditions. However,
for frequently changing loads, the overall averaged power loss of the proposed converter can be
less than or comparable to that of a conventional buck due to the energy recycling ability of the
flyback transformer, that sends energy back to the source during heavy-to-light transients [101].
The proposed converter has a much simpler requirement on the design of the transformer
compare to the stepping inductor [98]-[100] and dual-current pump [90]-[91] approach. The
penalty in the overall inductance volume is smaller than in other solutions [80]-[94]. The size of
the magnetic core, the largest contributor to the overall magnetic size in the low-power
applications [8], is no larger than that of the conventional buck and only a single auxiliary
winding handling much smaller average current than the primary is needed. The presented
converter does not experience problems of overly large transistor blocking voltages, an undesired
characteristic for conventional stepping inductor solutions [98]-[100]. The blocking voltage of
the power transistors is no larger than the input voltage Vin. Hence, the presented solution is
better suited for cost-effective integration.
The following 2 chapters deal with the design and implementation of the two buck
converter structures introduced above, respectively.
In Chapter 2, the design methodology of the digitally controlled dual output stage DC-DC
converter is addressed. Operating principle and design considerations of the digital control unit
is described in details. Experimental results obtained on two prototype converters built with
discrete and fully integrated dual output stages, respectively, show about 35% reduction in peak
voltage deviation during heavy-to-light load transients, compare to an equivalent conventional
time-optimal controlled [24]-[26] buck converter prototype. Practical limitations of the dual
output stage structure are discussed at the end of this chapter, which leads to the introduction of
the FTBB converter as a more comprehensive solution.
26
Chapter 3 is devoted to the implementation of the FTBB converter. Design and
implementation of the mixed-signal dual-mode controller is presented. The energy recycling
mechanism of the FTBB converter is studied. An experimental prototype is built using discrete
off-the-shelf components. About 67% reduction in peak voltage deviation during heavy-to-light
load transients and 25% reduction during light-to-heavy load transients are demonstrated, in
comparison with a conventional minimum-deviation controlled [72][73] buck converter. Under
frequent load transients, 7% reduction in averaged power loss is also observed.
Finally in Chapter 4, a summary of this thesis and future research topics are presented.
27
Chapter 2Chapter 2Chapter 2Chapter 2
Digital Digital Digital Digital ControlControlControlControl and Design and Design and Design and Design Strategy Strategy Strategy Strategy ofofofof
aaaa Buck Converter with an Auxiliary Buck Converter with an Auxiliary Buck Converter with an Auxiliary Buck Converter with an Auxiliary
Stage for Transient SuppressionStage for Transient SuppressionStage for Transient SuppressionStage for Transient Suppression
This chapter describes a digitally controlled buck converter with an auxiliary output stage
to improve transient performance without jeopardizing steady-state conversion efficiency. The
contents are organized as follows: Section 2.1 presents the system structure and briefly
introduces the operating principle of the transient suppression method. Section 2.2 is dedicated
to the design of the main output stage and the digital voltage mode controller that regulates the
output voltage during steady state. Section 2.3 addresses the design of the transient suppression
controller. Architecture and state diagram of the controller will be described in details. Design
considerations such as the selection of auxiliary stage inductor and the size of auxiliary switches
will be discussed and demonstrated with simulation results in Section 2.4 and Section 2.5,
respectively. The design of two prototype converters using discrete and integrated output stages
will be illustrated in Section 2.6. The improvement in transient performance using the proposed
structure will be verified with experimental results.
2.1 System Structure and Operating Principle
In order to achieve fast and smooth transient response while maintaining high power
conversion efficiency in steady-state, a digitally controlled buck converter with an auxiliary
output stage is investigated. The diagram of the system is as shown in Figure 2.1. It consists of
two output power stages (or dual output stage), an analog-to-digital converter (ADC) that
continuously samples the output voltage, vout(t), and a dual-mode digital controller that generates
the switching commands for the power switches in the dual output stages.
28
The dual output stages are made up of two conventional buck output stages connected in
parallel, each of which has a main switch (MS), a synchronous rectifier (SR), and a filter inductor
(L). Subscripts M and A are used to identify the main converter and the auxiliary stage,
respectively. The main output stage is responsible for steady-state operation. It is designed to
achieve high conversion efficiency, thus large inductor, LM and big power transistors with low
on-resistance are used. The auxiliary stage is responsible for transient suppression. It is only
active when a load transient is detected. The auxiliary stage is implemented with a much smaller
inductor, LA. During transient recovery, it assists in sinking or sourcing current with a higher
slew-rate than that of the main output stage and quickly brings the output voltage back to its
steady-state value.
The digital controller continuously monitors the output of the ADC and determines the
operating mode of the system. In steady state, switches MSA and SRA are kept off. The "Steady
State Compensator" regulates the output voltage as in a conventional single stage buck converter
Figure 2.1 A digitally controlled DC-DC converter with an auxiliary output stage for fast load transient recovery.
29
[8]. When a load disturbance occurs, the "Transient Suppression Circuit" takes over and
activates the auxiliary output stage. Both main and auxiliary output stages switch during
transient recovery in order to restore the output voltage, vout(t) and main stage inductor current,
iLM(t) to their desired steady-state value.
An example of the theoretical current and voltage waveforms during a heavy-to-light
transient recovery process are as illustrated in Figure 2.2. A negative load current step with a
magnitude of ∆i load occurs at time t0. It is assumed that the slew-rate of the load current step is
much higher than that of the inductor currents (k1~k3). It is also assumed that the converter
reacts immediately after the load current transient occurs.
The proposed control method involves 3 control parameters: the main stage recovery time
(TR), auxiliary stage turn-on time (ton) and turn-off time (toff), which represents the on-time for
k1
k2 k3
0
0
0
t
t
t
ton toff
0vout(t)-VREF
t
∆vOvershoot
∆vUndershoot
TR
iload(t)
iLM(t)
iLA(t)
∆iload
t0
∆iload
Figure 2.2 Theoretical waveforms of load current i load(t), main stage inductor current iLM(t), auxiliary stage inductor current iLA(t) and output voltage deviation vout(t) – VREF under a heavy-to-light load transient.
30
transistors SRM, SRA, and MSA, respectively. In the heavy-to-light load transient recovery process
shown in Figure 2.2, the inductor current, iLM(t) in the main output stage ramps down with a
slope of k1 during TR, until it reaches the targeted load current. In the mean time, during ton the
auxiliary stage inductor draws current, iLA(t) from the output capacitor with a slope of k2, and
then ramps back to zero with a slope of k3 through toff. The switching commands for both the
main and auxiliary output stages are determined based on the capacitor charge balance principle
[24]-[26], such that the amount of capacitor charge dissipated through the auxiliary stage equals
to the amount of excess charge injected from the main stage. This method aims at recovering the
output voltage to steady state within one on-off switching action. By equating the areas of the
two shaded triangles in Figure 2.2, the expressions for calculating these control parameters are
obtained as:
1
loadR
iT
k
∆= , (2.1)
3
2 3 1 2( )on loadk
t ik k k k
= ∆+
, (2.2)
2
2 3 1 3( )off loadk
t ik k k k
= ∆+
, (2.3)
where k1, k2, and k3 are the inductor current slew-rates which are determined by the averaged
input voltage, Vin and output voltage, Vout as well as the inductances in the main and auxiliary
stages.
1out
M
Vk
L= , 2
out
A
Vk
L= , 3
in out
A
V Vk
L
−= (2.4)
Provided that the system is under stable control and the variation of voltages is small
when compared to their steady-state values, both Vin and Vout can be treated as constants during
the short period of transient recovery. The same assumption also applies to k1, k2, and k3. As can
be observed in (2.1)-(2.3), the only unknown parameter that is needed to determine the switching
commands is the magnitude of load current step, ∆i load.
31
2.2 Steady State Compensator Design
When the buck converter is in steady state, the auxiliary output stage is turned off while
the main converter switches to maintain output voltage regulation. The main converter is
controlled by a conventional digital voltage mode controller, the structure of which is shown in
Figure 2.3 (a). The design guidelines for the steady-state digital controller have been widely
LM
Cout
vout(t)Vin
MSM
SRM
vxM
vout[n]
A/D
VREF[n]
∑e[n]
Gc(z)DPWMd[n]
Dead-time
c(t)
cMS(t) cSR(t)
Steady State Controller
Digital
Compensator
(a)
GDPWM Gc
d
Gvd GA/D
e
v
Digital
Compensator
DPWM
Module
Buck
Converter
A/D Convertor
and Adder
Steady State Controller
(b)
Figure 2.3 (a) Architecture of the digital voltage mode controller for regulating steady-state output voltage, and (b) linearized model of the closed-loop system.
32
investigated in literatures, such as [22], and will be briefly reviewed in this section.
The specifications of the design example are given in TABLE 2.1. The system was
optimized to achieve around 90% conversion efficiency for mid-to-heavy load current range in
[102]. The power stage parameters are selected to obtain 0.5A steady-state current ripple and
5mV voltage ripple according to the simulation results in [102].
The linearized small signal model shown in Figure 2.3 (b) is a simplified version of the
one in [22], where the output voltage, vout(t) is directly fed-back to the analog-to-digital converter
(A/D) instead of going through a voltage divider as in [22]. To design a closed-loop controller
with sufficient bandwidth and phase margin, individual transfer functions for the A/D, the digital
pulse-width modulation (DPWM) module and the buck converter need to be determined first.
The A/D converts the output voltage, vout(t) into an NA/D-bit signal, vout[n], which is then
subtracted by the digital representation of the reference voltage, VREF[n] to generate the error
signal, e[n]. According to [22], the combined transfer function of the A/D and the adder can be
expressed as
//
1 convstA D
A DG e
V−= ⋅
∆, (2.5)
TABLE 2.1. DESIGN PARAMETERS OF THE MAIN CONVERTER
Parameter Symbol Value
Input Voltage Vin 6 V
Nominal Output Voltage Vout 1 V
Output Accuracy - ±1%
Load Current i load 0.1 to 3 A
Output Inductance LM 2.2 µH
Output Capacitance Cout 200 µF
Switching Frequency fs 390 kHz
MS On-resistance Ron, MS 10 mΩ
SR On-resistance Ron, SR 10 mΩ
Inductor DC resistance RL 20 mΩ
33
where ∆VA/D is the quantization bin of the A/D and tconv is the conversion latency. The effect of
the sample-and-hold function is omitted, since when applied to the closed-loop system, it is
already incorporated with the averaged model of the buck converter Gvd [103]. To fulfill the
accuracy requirement on the output voltage, ∆VA/D needs to be sufficiently small such that
/ 1%A D REFV V∆ < ⋅ . (2.6)
For a conventional A/D with quantization range of VA/D, the minimum resolution is thus given by
/ // 2 2
/log ( 1) log ( 1)
1%A D A D
A DA D REF
V VN
V V= + ≥ +
∆ ⋅. (2.7)
The DPWM module converts an NDPWM-bit digital duty-cycle command, d[n] into a
PWM pulse, c(t). Assuming that d[n] is represented by an unsigned binary integer number and
that the duty-cycle of signal c(t) ranges between 0 and 1 (e.g. 100%), respectively, the small-
signal gain of the DPWM module can be expresses as [41]
1
2 DPWMDPWM N
K = . (2.8)
To avoid limit-cycle oscillation [104], the change in the output voltage due to one least-
significant bit (LSB) change in d[n] must be smaller than the quantization bin of the A/D under
all load conditions. As a result, the minimum DPWM resolution can be obtained from [103]
2/
log ( )inDPWM
A D
VN
V>
∆. (2.9)
Since the new duty-cycle command d[n] is usually updated at the beginning of each switching
cycle, it does not influence the duty-cycle of c(t) until the output value of the DPWM counter
[22] reaches the updated d[n]. Therefore a signal-dependent latency tDPWM is introduced by the
DPWM module and can be approximated using the steady-state duty-cycle D [105].
DPWMs
Dt
f= . (2.10)
Combining (2.8) and (2.10), the overall transfer function of the DPWM module is given by
34
1
2s
DPWM
Ds fDPWM N
G e−
= ⋅ . (2.11)
The control-to-output transfer function of the buck converter is given by [8]
2 1 1( ) (1 )
in
M outvd
eq eq
M load out M out load
V
L CG
R Rs s
L R C L C R
=+ + + +
, (2.12)
where Req is the equivalent series resistance of the converter, which can be approximated as
, ,(1 )eq on MS on SR LR DR D R R= + − + . (2.13)
The uncompensated loop transfer function is obtained by multiplying (2.5), (2.11) and (2.12).
/u vd A D DPWMT G G G= ⋅ ⋅ (2.14)
Based on the design parameters in TABLE 2.1 and 2.2, the Bode plot of the worst-case
uncompensated loop transfer function is generated as shown in Figure 2.4.
As a rule-of-thumb, the frequency response of the loop transfer function needs to have at
least 45˚ phase margin (φm) and a cross-over frequency (fc) at 1/10th to 1/5th of the switching
frequency in order to ensure proper performance. Thus loop compensation is usually required.
There are multiple approaches to design a digital compensator. The most accurate, but least
intuitive method is direct-digital design [106], where the modeling and compensator design are
TABLE 2.2. DESIGN PARAMETERS OF ADC AND DPWM BLOCKS
Parameter Symbol Value
A/D Quantization Range VA/D 2 V
A/D Quantization Bin ∆VA/D 7.85 mV
A/D Resolution NA/D 8 bits
A/D Conversion Latency tconv 240 ns
DPWM Resolution NDPWM 12 bits
35
carried out in discrete-time domain. An alternative approach, which is applied in this work, is
called “digital re-design”. The compensator is first designed in the continuous-time domain with
traditional techniques. Then the coefficients for the digital compensator are obtained using
continuous-to-discrete transformation methods such as bilinear transform and pole/zero mapping
[22], [107].
A generic compensator is designed for the closed-loop system. It has two real zeros near
the corner frequency of the output filter to compensate for the –180˚ phase shift caused by the
quadratic pole in (2.12). It also has an inverting zero so that the closed-loop system has an
infinite DC gain to eliminate the DC voltage error. The continuous-time domain transfer
function of the compensator is given in (2.15). Parameter Kc is adjusted through simulation to
achieve desired loop bandwidth.
1 2(1 ) (1 )c
ccz z
K s sG
s ω ω= ⋅ + ⋅ + (2.15)
The corresponding discrete-time transfer function of the compensator is as (2.16), where
the coefficients a, b, and c are obtained through bilinear transform of (2.15).
Ma
gn
itu
de
(dB
)P
ha
se(d
eg)
Figure 2.4 Bode plot of the uncompensated system.
36
1 2
1( )
1cd
a bz czG z
z
− −
−+ +=
− (2.16)
The digital compensator is then implemented based on the differential equation given by (2.17).
The terms ae[n], be[n-1] and ce[n-2] in (2.17) are usually generated using look-up tables (LUTs)
[103]. This provides a low-power and fast solution compare to multipliers. A popular structure
of the digital compensator is as shown in Figure 2.5.
[ ] [ 1] [ ] [ 1] [ 2]d n d n ae n be n ce n= − + + − + − (2.17)
The compensated loop transfer function using continuous-time domain compensator and
equivalent discontinuous-time domain compensator are obtained as (2.18) and (2.19). Their
Bode plots are compared in Figure 2.6 (a) and (b), respectively.
/( ) ( ) ( ) ( ) ( )c vd A D DPWM cc s jT j G s G s G s G s ωω == ⋅ ⋅ ⋅ (2.18)
/ ,( ) ( ) ( ) ( ) ( ) jd vd A D DPWM cd s j z e
T j G s G s G s G z ωωω= =
= ⋅ ⋅ ⋅ (2.19)
Figure 2.5 Block diagram of the digital PID compensator. clkfs is the steady-state clock signal. It is synchronized with the switching cycle of the converter.
37
As can be observed, the process of digital re-design introduces a loss in accuracy at frequencies
close to the switching frequency of the converter, which must be considered when designing the
Frequency (rad/s)
Magnit
ude
(dB
)P
hase
(deg
)
m=65˚ (at 61kHz)
(a)
Frequency (rad/s)
m=45˚ (at 48kHz)
(b)
Figure 2.6 Bode plots of the compensated system using (a) continuous-time domain compensator and (b) discontinuous-time domain compensator.
38
compensator. It is usually a good practice to design the continuous-time domain compensator
for a phase margin higher than 60˚ to ensure satisfactory performance when the compensator is
later on implemented digitally [22].
39
2.3 Controller Implementation
The controller shown in Figure 2.1 is responsible for generating the switching commands
for both the main and auxiliary power stages and ensuring smooth transition between steady state
and transient modes of operation.
The block diagram of the controller is as shown in Figure 2.7. It consists of an analog-to-
digital converter (A/D) and a digital control unit. The A/D quantizes the output voltage, vout(t) to
its digital equivalent, vout[n], at an oversampling frequency 16 times higher than the steady state
switching frequency, fsw. The output voltage, vout[n] is processed by the digital control unit,
where it is compared with the desired reference, VREF[n] to generate the error signal, e[n]. The
digital control unit monitors and regulates the operation of the converter based on the sampled
error signal e[n]. The main function blocks of the digital control unit include a steady-state PID
Figure 2.7 Block diagram of the controller.
40
compensator [103], transient detector, transient suppression logic, load step estimator, duty-cycle
prediction, clock selector and a switch controller for main and auxiliary switches. Operation of
the controller is described by the state diagram as shown in Figure 2.8, and will be elaborated in
the following sub-sections.
2.3.1 Steady State Operation
The error signal, e[n] is monitored by the transient detector to determine the operating
mode of the converter. When the absolute value of e[n] is smaller than a predefined threshold
eTH[n], the output, tr of the transient detector is low and the system operates in steady state.
During this period, the output voltage, vout(t) is regulated by a digital voltage mode
controller [103]. The clock selector resets the transient clock, clktr to low and the steady-state
clock, clkpid switches at frequency fsw. The PID compensator samples the error signal, e[n] with
clkpid and calculate the duty-cycle command d[n] using a conventional PID control algorithm as
expressed in (2.17). The coefficients a, b, and c are calculated following the guidelines in
Section 2.2 so that the system stability is ensured. The duty-cycle command, d[n] is sent to the
DPWM module and converted to a pulse-width modulated signal, c(t), which is then used to
Power On
Steady StateBlocking
State
Duty-ratio
Prediction
Soft Start
|e[n]|<eTH[n]
Load-Step
Estimation
Generate
Switching
Commands
Transient Suppression Mode
|e[n]|>eTH[n]
Figure 2.8 State diagram of the digital controller.
41
generate the two non-overlapping control signals, MSM and SRM for the main stage power
switches. In the meantime, the main & auxiliary switch controller sets both MSA and SRA to low
and disables the auxiliary stage.
2.3.2 Transient Detection and Load Step Estimation
When a sudden load transient occurs, the output voltage starts to deviate from its nominal
value. If the magnitude of the load step is large enough such that the absolute value of error
signal, e[n] exceeds the threshold, eTH[n], the transient detector sets the signal tr to high and the
system enters transient suppression mode. The PID compensator is suspended by resetting clkpid
to zero. And the system operates with the fast transient clock clktr.
According to the analysis in Section 2.1 and (2.1)-(2.3), the magnitude of the load current
step, ∆i load is required in order to calculate the on and/or off time of main and auxiliary switches
during transient recovery. More importantly, as will be explained in the following subsection, it
is also needed to estimate the new steady-state duty-cycle in order to achieve smooth transition
between steady-state and transient modes of operation [108]-[113].
In this work, a simple estimation method is implemented in the load step estimator
(Figure 2.7) based on the changes in the output voltage measured over one sampling period,
Figure 2.9 Estimating load current step ∆i load from vout(t) deviation.
42
∆tsense [111]-[113]. This method is based on the assumption that the steady-state inductor current
ripple is much smaller than the magnitude of load current step, such that its effect on the
accuracy of estimation is negligible.
Theoretical waveforms of the load estimation process are as shown in Figure 2.9. The
equivalent circuit of the converter is as shown in Figure 2.10. During this brief period, the main
stage inductor is modeled as a current source holding the pre-transient load current value, labeled
as Iold. For analysis simplicity, it is assumed that the output voltage deviation is significantly
smaller than its steady-state value, thus the load can be represented as a current source as well,
holding the after-transient load value, Inew.
After the load transient is detected, and before the transient suppression process activates,
the load step estimator takes two samples of output voltage, vout(t) with a predetermined time
interval, ∆tsense. As can be seen from Figure 2.9, the output voltage deviation can be expressed
as:
loadsense sense
out
iv t
C
∆∆ = ∆ . (2.20)
As a result, the magnitude of load current step can be estimated from
[ ] [ ]∆ = ∆load sensei n K e n , (2.21)
where ∆esense[n] is the difference between the two voltage samples, i.e. the error signal samples,
and parameter K is a constant that is dependent on the output capacitance, Cout, sampling
interval, ∆tsense, and the quantization bin of the A/D.
Figure 2.10 Equivalent circuit of the converter during the load current estimation period.
43
The waveforms shown in Figure 2.9 are for a heavy-to-light load transient example. Yet
it should be noted that this method applies to light-to-heavy transients as well.
2.3.3 Predicting the New Steady-State Duty-cycle
Due to the lossy elements in the power components, the actual steady-state duty-cycle
seen at the main output stage's switching node, vxM changes with different load current even if the
ratio of output voltage over input voltage remains the same. Under heavier load current
condition, in each switching cycle the MSM transistor needs to be turned on for a longer period of
time to maintain the same level of output voltage compare to that under lighter load conditions
[8].
In order to achieve a smooth transition from transient suppression mode back to steady-
state operation, the new steady-state duty-cycle after the load transient needs to be predicted and
programmed into the PID compensator before the end of transient recovery process such that the
output voltage settles to near the reference value immediately after the steady-state control takes
over [88].
The difference (∆d) in steady-state duty-cycle before and after a load transient is
approximately proportional to the magnitude of the load current step [88], as expressed in (2.22)
∆∆ = eq load
in
R id
V, (2.22)
where Vin is the input voltage and Req is the equivalent series resistance in the power path of the
converter. Req can be calibrated by comparing the actual steady-state duty-ratio (Dcal) under a
known test current (Ical) with the nominal duty-cycle (Dnom), which represents the steady-state
duty-cycle when load current is zero. In practice, calibration of Req can be performed by
connecting a test current sink in parallel with the actual load of the converter and observe the
changes in steady state duty-cycle [114].
( )− ⋅= cal nom ineq
cal
D D VR
I (2.23)
44
In this implementation, the digital representation of ∆d, ∆d[n], is calculated in advance
for different ∆i load and programmed in a look-up table (LUT). When the converter is in transient
suppression mode, ∆d[n] is obtained from the LUT according to the output of the load step
estimator and sent to the duty-cycle prediction module. The new steady-state duty-cycle is then
calculated as ∆dnew[n] = ∆dold[n]+∆d[n] for light-to-heavy load transients and ∆dnew[n] =
∆dold[n]−∆d[n] for heavy-to-light transients, where ∆dold[n] is the old steady-state duty-cycle
stored in the PID compensator prior to the load transient. During the same period, the
calculation unit inside the PID compensator is reset. The 2-to-1 multiplexer in the PID
compensator sends ∆dnew[n] to the register, whose value is updated by the set signal from the
transient suppression logic.
2.3.4 Generating the Switching Command
Based on the estimated ∆i load, the control parameters for the main and auxiliary stages,
i.e. TR, ton and toff, are obtained from a set of look-up tables (LUT), where the digital
representations of these parameters are calculated in advance following (2.1)-(2.3) for different
values of ∆i load.
The transient suppression logic generates two control signals cM_tr and cA_tr according to
Figure 2.11 Compensate for the extra charge Q1 by increasing ton and toff.
45
parameters TR[n], ton[n] and toff[n]. Signals cM_tr and cA_tr are then sent to the main and auxiliary
switch controller, where they are converted into non-overlapping gate signals MSM, SRM, MSA
and SRA.
In a practical implementation, in order to compensate for the amount of charge injected to
or taken from the output capacitor during the transient detection and load step estimation period
(from t0 to t1 in Figure 2.11), the on/off time of the auxiliary stage, ton and toff calculated from
(2.2) and (2.3), are increased by ∆ton and ∆toff, respectively, as shown in Figure 2.11. Both ∆ton
and ∆toff can be calculated based on knowledge of the error threshold eTH[n] and ∆i load[n].
Details of calculation are as described in Appendix A.
2.3.5 Blocking State after Transient Suppression
By the end of the switching sequence, the transient suppression logic reset the S-R latch
of the transient detector. The steady-state clock, clkpid is resumed. And the transient clock, clktr
is reset to zero. From this point on, the converter starts operating in steady-state mode again,
where the output voltage is regulated by the PID compensator and the auxiliary stage is disabled.
In order to prevent oscillations between different modes of operation, a brief blocking state is
initiated when the converter is forced to operate with the PID compensator until the output
voltage fully settles. This provides the system with tolerance against sub-optimal charge
balancing caused by inaccuracy in load step estimation and limited resolution in TR[n], ton[n] and
toff[n]. It should be noted that if a new load transient happens during blocking state, the output
voltage will be regulated by the PID compensator only. As a result, the length of blocking state,
e.g. the time needed for the output voltage to fully settle after a load transient, essentially limits
the maximum frequency of load transient that the transient suppression controller is able to
handle.
2.3.6 Soft Starting after Power-on
In order to limit the in-rush current and overshoot voltage during the startup period of the
converter, a soft-start module is implemented to control the power-up sequence. The system is
forced to operate with conventional voltage-mode control (VCM) during the power-up process.
The soft-start module gradually increases the digital voltage reference, VREF[n] with small steps
until it reaches the desired steady-state value [115][116]. As a result, the output voltage follows
46
the voltage reference and rises softly. After the power-up process completes and the output
voltage settles in steady state, the transient detector is enabled and the converter is ready to
process load transients.
47
2.4 Selecting the Auxiliary Stage Inductor
To minimize the penalty in the total volume of the magnetic components, it is preferable
that the inductor LA in the auxiliary stage is small. Meanwhile, small LA provides high current
slew rate when the auxiliary output stage is activated, thus voltage deviation caused by the load
current step can be quickly compensated.
However, as demonstrated in Figure 2.2 and [87], [102], difference in the slew rate of
main and auxiliary inductor currents causes the output voltage to fluctuate around the voltage
reference, displaying both voltage overshoot, ∆vOvershoot and undershoot, ∆vUndershoot during a
single transient recovery process. If LA is too small relative to the main stage inductor LM, the
undesirable output voltage fluctuation will become significant.
The influence of the auxiliary stage inductance on the transient response is studied using
MATLAB simulation. The main converter is designed using parameters in TABLE 2.1. Output
voltage deviation, vout(t) − VREF under a 3A heavy-to-light load transient obtained using different
LA inductances are plotted and compared in Figure 2.12. As can be observed, smaller LA with
respect to LM (bigger LM/LA ratio) results in lower ∆vOvershoot but increases ∆vUndershoot. Thus the
optimum LM/LA ratio should be determined by trading-off the two.
LM/LA=8.8LM/LA=4.4LM/LA=3LM/LA=2.2
Time (µs)
Increasing vOvershoot
Increasing vUndershoot
Figure 2.12 Larger LM/LA ratio, e.g. smaller LA, results in smaller voltage overshoot but bigger voltage undershoot during heavy-to-light load transient recovery.
48
In order to find a proper LM/LA ratio, it is necessary to investigate how this ratio affects
the amount of ∆vOvershoot and ∆vUndershoot. For the proposed buck converter, the peak value of
∆vOvershoot and ∆vUndershoot under certain load current step can be derived from the integration of
current iC(t) that flows into or out of the output capacitor, as shown in Figure 2.13. For
simplicity, it is assumed that the converter starts transient suppression immediately after the load
step occurs. Thus the expressions for ∆vOvershoot and ∆vUndershoot are
2
1 2
1
2load
Overshootout
iv
C k k
∆∆ = ⋅+
, (2.24)
221 3 3 2
3 1 1 1 2 3
1
2load
Undershootout
i k k k kv
C k k k k k k
∆ +∆ = ⋅ ⋅ − − , (2.25)
where Cout is the output capacitance, ∆i load is the magnitude of load current step, and k1, k2, and
k3 are inductor current slew rates as previously defined in (2.4).
Substituting (2.4) into (2.24) and (2.25), the relationship between the ratio of LM/LA and
that of ∆vUndershoot/∆vOvershoot during a heavy-to-light load transient is obtained as
Figure 2.13 Capacitor and inductor currents during heavy-to-light load transient recovery.
49
2
11
11 (1 )
1
M
Undershoot A
A MOvershoot
M A
L
v LL LDv D
D L L
+ ∆ = ⋅ −
∆ − − −
. (2.26)
As can be seen, the optimum LM/LA ratio is dependent on the nominal duty-cycle D of the
converter, thus it needs to be determined for specific input and output voltages.
For the 6V-to-1V buck converter under study, (2.26) is plotted as Figure 2.14. The four
LM/LA cases simulated for Figure 2.12 are also indicated in Figure 2.14 as color-coded dots.
During a heavy-to-light load transient recovery, to achieve relatively balanced output voltage
deviation around the reference, it is preferred to have
1Undershoot
Overshoot
v
v
∆ ≤∆
. (2.27)
Therefore, the proper range of LM/LA can be determined directly from this graph.
Similarly, the optimum LM/LA ratio for light-to-heavy load transient recovery can be
found by substituting (2.28) into (2.29)-(2.30).
1in out
M
V Vk
L
−= , 2in out
A
V Vk
L
−= , 3out
A
Vk
L= (2.28)
2
1 2
1
2load
Undershootout
iv
C k k
∆∆ = ⋅+
(2.29)
221 3 3 2
3 1 1 1 2 3
1
2load
Overshootout
i k k k kv
C k k k k k k
∆ +∆ = ⋅ ⋅ − − (2.30)
For the 6V-to-1V buck converter, the relationship between ∆vOvershoot/∆vUndershoot and LM/LA are
plotted as in Figure 2.15. Proper range of LM/LA can be determined from the graph by letting
1Overshoot
Undershoot
v
v
∆ ≤∆
. (2.31)
50
As can be observed from Figure 2.14 and Figure 2.15, the preferred ranges of LM/LA ratio
for suppressing heavy-to-light and light-to-heavy load transients do not overlap, which means
with a single auxiliary stage inductor, the system cannot provide optimum transient response for
both type of load transients. A solution to this issue is investigated in [87], where a single LA is
used for the auxiliary stage and the slew rate of iLA(t) is regulated by switching the auxiliary
stage at a high frequency with adjustable duty-cycle.
LM/LA
v Un
der
sho
ot/
v Ove
rsh
oot
LM/LA=8.8LM/LA=4.4LM/LA=3LM/LA=2.2
For Vin=6V, Vout=1V
Preferred Range
Figure 2.14 Finding proper LM/LA ratio by trading off ∆vOvershoot and ∆vUndershoot during the heavy-to-light load transient recovery.
LM/LA
For Vin=6V, Vout=1V
Preferred Range
v Ove
rsho
ot/
v Und
ersh
oot
Figure 2.15 Finding proper LM/LA ratio by trading off ∆vOvershoot and ∆vUndershoot during the light-to-heavy load transient recovery.
51
2.5 Sizing the Auxiliary Stage Transistors
For integrated implementation of the proposed converter, it is preferable to minimize the
area overhead casted by the auxiliary output stage. Since the auxiliary transistors are not in the
main power conduction path, they only need to handle occasional current pulses when the
converter is in transient suppression mode. As a result, minimizing the auxiliary stage transistors
will not degrade the steady-state conversion efficiency. However, as will be shown in this
section, the size of the auxiliary power transistors cannot be arbitrarily small due to the increased
on-resistance (Ron_A) with reduced transistor width, which would influence both the control
algorithm and the converter’s dynamic performance.
2.5.1 Influence of Ron_A on the Inductor Current Model
In the previous analysis, it is assumed that during transient recovery, the current in the
auxiliary inductor ramps with constant slopes, which is inversely proportional to the auxiliary
inductance LA. This assumption is no longer valid if the auxiliary power transistor has high on-
resistance such that the voltage drop across it becomes significant.
For the heavy-to-light load transient example shown in Figure 2.16, after the auxiliary
output stage is activated, the low-side auxiliary switch (SRA) turns on, and the auxiliary current
(iLA(t)) flows from the drain of SRA towards its source. The reference direction of iLA(t) in Figure
2.16 is opposite to the direction of the actual current flow. Thus in the following analysis iLA(t)
has a negative value.
Figure 2.16 On-resistance causes voltage drop across auxiliary stage transistor.
52
Considering the fact that SRA has an on-resistance of Ron_A, the voltage drop across SRA
increases with iLA(t), changing the slew-rate k2 of iLA(t) from (2.4) to
_ ( )( ) out on A LALA
A
V R i tdi t
dt L
+= − , (2.32)
from which the expression of iLA(t) can be solved as
_
_( ) 1 exp( )on Aout
LAon A A
RVi t t
R L
= − − −
. (2.33)
Instead of ramping up linearly, iLA(t) rises exponentially with time and has decreasing slope
dependent on the auxiliary switch’s on-resistance Ron_A. The maximum auxiliary current is also
limited by Ron_A and the output voltage of the converter.
_ max_
outLA
on A
VI
R= − (2.34)
iload
iLM
iLA
k1
0
0
0
t
t
t
i(t)
i(t)
i(t)
TR
∆iload
∆iload
k2
k3
ton toff
QM
QA
Figure 2.17 Theoretical waveforms of load current (i load), main stage inductor current (iLM), auxiliary stage inductor current (iLA) under heavy-to-light load transient taking into account the auxiliary switches' on-resistance.
53
Taking into account the new inductor current model as expressed in (2.33), the theoretical
current waveforms in Figure 2.2 are revised as in Figure 2.17. The amount of charge that needs
to be balanced between the main and auxiliary stages is represented by the shaded area
surrounded by the respective current curves. To simplify the analysis, an assumption is made
such that the main stage inductor current iLM still has a constant slew-rate as in (2.4). This is
because that the on-resistance of the main power transistors is usually low and the voltage drop
across it can be neglected. The same assumption also applies for the auxiliary current iLA during
toff when the high-side auxiliary switch (MSA) is on, because the voltage drop across MSA is small
compare to the difference between the nominal input (Vin) and output (Vout) voltages of the
converter.
Based on the above assumptions, the amount of charge from the main and auxiliary
stages can be expressed as
21
1
2load
M R loadi
Q T ik
∆≈ ∆ = , (2.35)
2
30
( )( )
2
ontLA on
A LAi t
Q i t dtk
≈ +∫ . (2.36)
The control parameters TR, ton and toff can be calculated using advanced mathematic tools such as
MATLAB to equate (2.35) and (2.36).
2.5.2 Influence of Ron_A on the Dynamic Performance
To illustrate the influence of Ron_A on the dynamic performance, a buck converter is
designed and simulated using the parameters in TABLE 2.3. The main output stage transistors
and inductor are selected to achieve 90% peak steady-state efficiency [102]. The auxiliary stage
inductor is chosen following the criteria discussed in Section 2.4, so that the undesired voltage
undershoot during a heavy-to-light load transient recovery is limited to smaller than the initial
voltage deviation (∆vOvershoot). In steady state operation, the system relies on a conventional
voltage mode controller to maintain regulation. When a load current step occurs, the system
immediately enters transient suppression mode while the turn-on and turn-off times of main and
54
auxiliary switches are determined following the revised algorithm in Section 2.5.1. By the end
of the transient recovery process the system returns to voltage mode control.
The output voltage waveforms for a −3A load transient are as shown in Figure 2.18.
Simulation results obtained using different auxiliary transistors are compared. The case with
Ron_A = 0.1 Ω has the lowest voltage overshoot (35 mV), but a 5 mV undershoot during transient
recovery is observed. For Ron_A = 0.5 Ω, the overshoot increases to 47 mV and the voltage
undershoot is eliminated. In both cases, the output voltage settles quickly after the transient
suppression process, achieving smooth transition to steady-state voltage mode control. However,
as Ron_A increases to 0.7 Ω, the peak overshoot is increased to 55 mV and a secondary voltage
bump occurs after the steady state controller takes over, which takes more than 20 additional
switching cycles to settle.
Changes in the output voltage waveform due to different Ron_A can be explained by
analyzing the current waveforms in the auxiliary and main output stages. Since the parameters
of the main power stage are fixed for the three cases under study, the amount of voltage
overshoot and undershoot during transient recovery is mainly dependent on the slew-rate of
auxiliary current iLA and the maximum auxiliary current ILA_max. As indicated in Figure 2.19,
increasing Ron_A would reduce the slew-rate of iLA, and cause it to saturate at ILA_max = Vout/Ron_A
when the voltage drop across the low-side auxiliary switch equals Vout. When Ron_A increases
TABLE 2.3. DESIGN PARAMETERS OF THE SIMULATED CONVERTER
Parameter Symbol Value
Input Voltage Vin 6 V
Nominal Output Voltage Vout 1 V
Main Inductance LM 2.2 µH
Auxiliary Inductance LA 820 nH
Output Capacitance Cout 100 µF
Switching Frequency fs 390 kHz
Main Transistor On-Resistance Ron_M 10 mΩ
Auxiliary Transistor On-Resistance Ron_A As specified
Load Current Step ∆i load -3 A
55
from 0.1 to 0.5 Ω, iLA changes much slower over time and the peak auxiliary current drops from
over 4 A to 2 A, causing higher overshoot while eliminating the undershoot of the output
voltage. The same trend continues as Ron_A increases to 0.7 Ω, where the maximum auxiliary
current is limited to 1.5 A. As can be observed, larger Ron_A results in less current
sinking/sourcing capability in the auxiliary stage, thus bigger voltage overshoot is observed. A
trade-off between the peak voltage deviation and transistor size needs to be achieved when
designing the auxiliary output stage.
Another aspect that determines the upper limit of the auxiliary switches’ on-resistance is
the relationship between the main output stage recovery time (TR) and the auxiliary output stage
active time (ton+toff), which greatly influences the settling of output voltage after the transition
from transient suppression back to steady-state voltage mode control. As can be observed from
Figure 2.19, when Ron_A equals 0.1 or 0.5 Ω, the active time of the auxiliary output stage is
shorter than, or equal to the recovery time of the main output stage. Therefore the auxiliary stage
is off when the controller switches back to voltage mode control. However, for Ron_A = 0.7 Ω,
the required active time of auxiliary output stage is longer than the main output stage recovery
time. After the mode transition happens, the voltage mode controller takes over and tries to
regulate the output voltage regardless of the fact that the auxiliary output stage is still active.
9.80E-1
9.90E-1
1.00E+0
1.01E+0
1.02E+0
1.03E+0
1.04E+0
1.05E+0
1.06E+0
2.96E-3 2.98E-3 3.00E-3 3.02E-3 3.04E-3 3.06E-3
Ron_A=0.1ohm
Ron_A=0.5ohm
Ron_A=0.7ohm
v ou
t(V
)
Figure 2.18 Transient output voltage waveforms of converters using auxiliary switches with different on-resistances.
56
The transfer function of the voltage mode control loop is temporarily disturbed since there are
now two output stages operating in parallel. The steady-state compensator will not be able to
properly compensate the control loop until the auxiliary output stage is turned off, which results
in a secondary voltage bump and longer settling time compare to the previous two cases.
2.5.3 Auxiliary Stage Sizing Consideration
The analysis in Section 2.5.2 indicates that in order to achieve a smooth mode transition,
the size of the power transistors in the auxiliary output stage should be selected to ensure that
Ron_A does not cause an excessively long auxiliary stage active time. For the buck converter
under study, the required active times of different auxiliary output stages for heavy-to-light load
-4.5
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
2.96E-3 2.98E-3 3.00E-3 3.02E-3 3.04E-3 3.06E-3
Ron_A=0.1ohm
Ron_A=0.5ohm
Ron_A=0.7ohm
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.96E-3 2.98E-3 3.00E-3 3.02E-3 3.04E-3 3.06E-3
Ron_A=0.1 and 0.5ohm
Ron_A=0.7ohm
Ron_A = 0.1Ω
Ron_A = 0.5Ω
Ron_A = 0.7Ω
Time (s)
Ron_A = 0.1Ω & 0.5Ω
Ron_A = 0.7Ω
Main Stage
Recovery Time TR
Auxiliary Stage
Active Time ton+toff
Steady State Controller
Malfunctioning
Figure 2.19 Transient current in the auxiliary and main stage.
57
transients with step magnitude ranging from 0.5 to 3.5 A are calculated and plotted in Figure
2.20. The recovery time TR of the main output stage under each transient condition is also
plotted for comparison. Based on the knowledge of the maximum possible load step, the
maximum allowable Ron_A can be estimated directly from the graph by looking at the data points
that are below the solid black curve representing TR. If, for instance, the converter is required to
handle load transients with magnitude up to 3 A, then the upper bound of Ron_A should be about
0.5 Ω, which means in this particular simulated converter, the size of the auxiliary switches can
be 50 times smaller than that of the main switches assuming the main switches have on-
resistances of 10 mΩ as listed in TABLE 2.3. If, on the other hand, the converter only needs to
handle maximum of 2 A load current steps, Ron_A can be as high as 0.7 Ω. For buck converters
with higher current handling requirement, the upper limit of Ron_A needs to be reduced
accordingly.
0.0E+0
2.0E-6
4.0E-6
6.0E-6
8.0E-6
1.0E-5
1.2E-5
0 0.5 1 1.5 2 2.5 3 3.5 4
Main State TR Ron_A=0 Ron_A=0.1
Ron_A=0.3 Ron_A=0.5 Ron_A=0.7
Tim
e(s
)
Figure 2.20 Comparison of the active time for auxiliary output stages with different on-resistances.
58
2.6 Prototype Design and Experimental Results
In order to verify the proposed transient suppression method, an experimental prototype
is built with off-the-shelf discrete components on a custom-designed printed circuit board (PCB).
An Altera Cyclone III FPGA development board is employed to implement the digital controller.
An integrated dual output stage with gate drivers is also designed and fabricated using TSMC's
0.25 µm 12 V process. Detailed design parameters, test setups, and experimental results are
presented in this section.
2.6.1 Prototype Converter Using Discrete Output Stages
The prototype converter using discrete power transistors and gate drivers is as shown in
Figure 2.21. The test board can be divided into 3 main parts. The "Dual Output Stage" includes
main and auxiliary power MOSFETs, gate drivers, inductors and output capacitors. The
"Switching Loads" compose of 4 identical resistor branches connected between ground and the
converter's output node. Each of these resistor branches is controlled by a dedicated MOSFET
switch SW[0:3]. By turning on and off the control switches, these switching loads can generate
Figure 2.21 Prototype converter to verify the transient suppression method and block diagram of the switching loads.
59
up to 4 A load current step with high slew-rate. The "A/D" converts the output voltage, vout(t)
into the digital equivalent vout[n] and feeds back to the digital controller through the pin header
on the top right corner of the board. The digital controller is implemented on the FPGA
development board. It samples vout[n] and generates the switching commands for main and
auxiliary power switches. It also controls the switching loads to mimic load transients. Detailed
list and description of components are provided in TABLE 2.4.
A Steady State Power Conversion Efficiency
In steady state, the converter operates with a conventional voltage mode controller
switching at 390 kHz. As shown in Figure 2.22, the 6V-to-1V prototype converter achieves
around 88% conversion efficiency at mid-range load current (1~2 A). Power conversion
efficiency is also examined for 2 other combinations of main stage inductance (LM) and
switching frequency (fs) by replacing the original 2.2 µH main stage inductor with an 1 µH
inductor (Rdc = 10 mΩ) from the same product series. It is observed in Figure 2.22 that for this
particular setup, using a larger main stage inductor and operating at a lower switching frequency
result in higher steady-state efficiency. For both converters operating with 390 kHz switching
TABLE 2.4. COMPONENT LIST OF THE DISCRETE PROTOTYPE
Component Value Model Number Description
Main stage inductor 2.2 µH PCMC063T DC resistance Rdc = 20 mΩ
Auxiliary inductor 0.82 µH PCMC063T DC resistance Rdc = 2.8 mΩ
Output Capacitors 100 µF ×2 GRM31CR60J Ceramic capacitor with RESR = 2 mΩ. Capacitance drops by 20% at 1 V DC voltage
MOSFETs IRF7821 Ron = 10 mΩ. All switches in this system are implemented with IRF7821.
Gate Drivers TC4426 Propagation Delay = 30 ns
A/D 10-bit AD9200 Resolution = 2 mV. 8 bits are used in steady state. 10 bits are used in transient suppression mode.
Switching Load Resistors
1 Ω WSR21R000FEA Has low series inductance (below 5 nH). Generates instantaneous current step when branch is turned on/off.
60
frequency, the one with LM = 2.2 µH has approximately 4% higher efficiency compare to the one
using LM = 1 µH.
B Transient Performance
Transient performance of the prototype converter is tested by turning on/off the control
switch of one or more switching loads and observing the output voltage waveform. For point-of-
load (PoL) buck converters with low conversion ratio, heavy-to-light load transients induce
bigger voltage variation compare to light-to-heavy load transients, and are usually more difficult
to deal with [108]. Therefore, to clearly show the effect of the proposed transient suppression
method, the experimental results obtained for heavy-to-light load transient recovery are
presented in this section.
For comparison, transient voltage waveform of a single-stage 6V-to-1V buck converter is
examined first. The power switches in the auxiliary stage of the prototype are kept off. And the
converter operates with the main output stage only. The measured output voltage waveforms are
shown in Figure 2.23 (a) and (b). The converter operates with the conventional voltage mode
controller in steady state. When a load transient occurs, the controller turns on and off the main
power switches following the time-optimal control method [24]-[26], which theoretically results
in minimum possible transient voltage deviation. The duration of the time interval when the
60
65
70
75
80
85
90
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3
Lm=2.2uH,fs=390kHz Lm=1.0uH,fs=390kHz Lm=1.0uH,fs=780kHz
Eff
icie
ncy
(%)
Figure 2.22 Steady-state conversion efficiency of a 6V-to-1V prototype converter.
61
converter operates with time-optimal control is indicated in Figure 2.23 as in between the two
dashed lines. As can be observed in Figure 2.23 (a), when the power stage inductor is 2.2 µH,
the single-stage time-optimal control method results in 85 mV peak voltage deviation during a
3A-to-1A load transient. If a smaller (1.0 µH) power inductor is used, the peak voltage deviation
can be reduced to around 60 mV, as shown in Figure 2.23 (b).
Output voltage waveform using the proposed transient suppression method is shown in
Figure 2.23 (c). The main output power stage has a 2.2 µH inductor, and the auxiliary inductor
is 0.82 µH. During transient suppression period (in between the two dashed lines), the converter
activates the auxiliary stage to suppress voltage deviation. As can be observed, the peak voltage
deviation is 55 mV, which is 35% reduction compare to the single-stage time-optimal controlled
buck converter with a 2.2 µH power inductor. On the other hand, the proposed converter
achieves similar amount of peak voltage deviation as the single-stage buck converter using a 1.0
µH power inductor. However, as shown in Figure 2.22, with a bigger main stage inductor, the
prototype has 4~8% higher steady state efficiency.
62
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.1
0 50 100 150 200 250 300 350 400
v out–
VR
EF
(V)
(a)
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.1
0 50 100 150 200 250 300 350 400
(b)
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.1
0 50 100 150 200 250 300 350 400
Time (µs)
Iload=3A Iload=1A
vout= 55mV
LM=2.2µH, LA=0.82µH, fs=390kHz
Transient Suppression
using Dual Output Stage
(c)
Figure 2.23 Heavy-to-light load transient performance using (a) & (b) single-stage time-optimal control method and (c) proposed transient suppression method.
63
2.6.2 Prototype Converter Using Integrated Output Stages
In order to verify the feasibility of the proposed transient suppression method in
integrated PoL converters, an integrated dual output stage with on-chip gate drivers is designed
and fabricated. The block diagram of the custom IC is shown in Figure 2.24. The power
transistors in the output stages are implemented with TSMC’s 0.25 µm 12 V thick oxide devices.
The gate drivers use 2.5 V devices on the input side and 12 V devices at the output in order to
interface with the output stages and the digital controller implemented on a 2.5 V FPGA chip. A
level-shifter is inserted to convert the voltage level.
The micrograph of the integrated dual output stage is as shown in Figure 2.25. Each
power transistor is divided into two identical segments with their gate drivers located in between.
Input power supply (Vin) and ground (GND) terminals are also divided into symmetrical sections
(a)
(b)
Figure 2.24 Block diagram of (a) the integrated dual output stage and (b) the gate driver.
64
and located next to the dedicated device, e.g. GND terminal near NMOS and Vin terminal near
PMOS. The main and auxiliary switching nodes (vxM and vxA) are implemented in an
interleaving structure so that the power transistor current gets evenly distributed across all
fingers.
The on-resistance of each power transistor is as listed in TABLE 2.5. The on-resistance
of the auxiliary transistors (PMOSA, NMOSA) is determined following the criteria in Section
2.5.3, such that the active time of the auxiliary stage (ton+toff) is shorter than the recovery time of
the main stage (TR) under all possible load step cases. The main stage transistors fill in rest of
TABLE 2.5. SIMULATED ON-RESISTANCES OF THE POWER TRANSISTORS
Name Design Target Simulation Results (Typical case)
Vgs = 6V Vgs = 12V
PMOSA 500 mΩ 779.7 mΩ 485.1 mΩ
NMOSA 100 mΩ 142 mΩ 90.3 mΩ
PMOSM 200 mΩ 310 mΩ 199 mΩ
NMOSM 20 mΩ 23.2 mΩ 16 mΩ
Figure 2.25 Micrograph of the integrated dual output stage.
65
the available chip area. It can be observed in Figure 2.25 that in this prototype, the auxiliary
output stage takes up less than 20% of the total area.
It should be noted that the design of the main stage power transistors in this prototype is
limited by the available chip area. As can be seen in Figure 2.26, with gate-to-source voltage
(Vgs) of 12V, which is equal to the input voltage (Vin) of the converter, the integrated main output
stage achieves higher than 85% steady-state power conversion efficiency for mid-to-heavy load
range. However, for Vgs = 6 V, a severe degradation in efficiency is observed at heavy load due
to higher on-resistance in the power transistors compare to the Vgs = 12 V case. It is expected
that with a larger chip area allowance, the size of the main stage transistors can be increased and
70
75
80
85
90
95
0 0.5 1 1.5 2 2.5 3 3.5 4
Vin = 6V, Vout = 1V Vin = 12V, Vout = 1V
Eff
icie
ncy
(%)
Figure 2.26 Steady state efficiency of the integrated output stage.
TABLE 2.6. SUMMARY OF TEST CONDITIONS
Parameter Symbol Value
Input Voltage Vin 6 V
Nominal Output Voltage Vout 1 V
Main Inductance LM 2.2 µH
Auxiliary Inductance LA 820 nH
Output Capacitance Cout 200 µF
Switching Frequency fs 390 kHz
Load Current Step ∆i load Switch from 2.25 A to 0.25 A
66
optimized to improve steady-state efficiency for low Vgs cases. The auxiliary stage transistors
can remain the same size since they have no effect on the steady-state efficiency. Thus the
overall area penalty introduced by the auxiliary stage will be even smaller than that in the current
design.
Transient performance of the prototype converter using the integrated dual output stage is
measured under the test condition specified in TABLE 2.6. The test board uses the same type of
power inductors, capacitors, switching loads and A/D converter as listed in TABLE 2.4.
Switching commands to the on-chip gate drivers is generated by the digital controller
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.1
-1.0E-4 -5.0E-5 0.0E+0 5.0E-5 1.0E-4 1.5E-4 2.0E-4
v out–
VR
EF
(V)
(a)
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.1
-1.0E-4 -5.0E-5 0.0E+0 5.0E-5 1.0E-4 1.5E-4 2.0E-4
v ou
t–
VR
EF
(V)
(b)
Figure 2.27 Heavy-to-light load transient performance using (a) single-stage time-optimal control method and (b) transient suppression method using dual output stage.
67
implemented on the FPGA development board.
As shown in Figure 2.27, output voltage waveforms under a heavy-to-light load transient
are examined for both single-stage time-optimal control method and the proposed transient
suppression method. For a 2.25A to 0.25A load transient, the single-stage time-optimal control
method results in a peak voltage deviation of 80mV. In comparison, when the proposed method
is used, the transient voltage overshoot is suppressed to 52mV. About a 35% reduction is
observed. TABLE 2.7 summarizes the key experimental results obtained from the
aforementioned prototype converters. The integrated dual output stage achieves same level of
transient deviation improvement as the discrete prototype presented in Section 2.6.1.
TABLE 2.7. SUMMARY OF TRANSIENT PERFORMANCE
Prototype Main
Inductance Auxiliary
Inductance
Load Current
Step
Peak Voltage
Deviation
Steady State
Efficiency Discrete Output Stage #1
with Time Optimal Control 2.2 µH - − 2 A 85 mV Max. 88 %
Discrete Output Stage #1 with Transient Suppression
2.2 µH 0.82 µH − 2 A 55 mV Max. 88 %
Discrete Output Stage #2 with Time Optimal Control
1.0 µH - − 2 A 60 mV Max. 85 %
Integrated Output Stage with Time Optimal Control
2.2 µH - − 2 A 80 mV Max. 92%
Integrated Output Stage with Transient Suppression
2.2 µH 0.82 µH − 2 A 52 mV Max. 92%
68
2.7 Chapter Summary
Modern point-of-load (PoL) converters are generally required to have good dynamic
performance with small voltage deviation during load transients. At the same time, they are also
required to have high power conversion efficiency. To mitigate the well-known trade-off [102]
between the steady-state efficiency and the transient response of PoL converters, a digitally
controlled buck converter with an auxiliary output stage for transient suppression is introduced in
this chapter. The design methodology and experimental results are also summarized in this
section.
The presented converter consists of a main output stage connected in parallel with an
auxiliary output stage. The main output stage is responsible for steady-state operation. It is
implemented with large inductor and power transistors with low on-resistance to achieve high
conversion efficiency in mid-to-heavy load range. The auxiliary stage is responsible for transient
suppression and is only active when a load transient occurs. It is implemented with a much
smaller inductor. When the auxiliary stage activates, it can sink or source current with a high
slew rate and quickly recovers the output voltage to its steady-state value.
A dual-mode digital controller with load step estimation and duty-cycle prediction is
implemented. In steady state, it regulates the output voltage using conventional voltage mode
control [8]. During transient recovery, it performs the transient suppression algorithm which is
based on a modified capacitor charge-balance principle [24]-[26]. The on/off times of the main
and auxiliary stage needed for charge-balancing is determined based on the estimated load
current step. The controller also predicts the post-transient steady-state duty-cycle so that a
smooth transition from transient suppression to voltage mode control can be achieved without
introducing additional voltage fluctuation.
Two prototype converters are tested to verify the proposed transient suppression method.
They are implemented with off-the-shelf discrete output stages and custom-designed integrated
output stages, respectively. Experimental results show that the proposed method achieves 35%
reduction in peak voltage deviation during a heavy-to-light load transient, compare to a
conventional single-stage time-optimal controlled buck converter using the same power stage
components. It is observed that the converter using the integrated dual output stages achieves
69
same level of transient performance improvement as the discrete counterpart. The auxiliary
stage transistors can be much smaller than the main stage transistors, only imposing less than
20% area overhead on the IC.
The proposed dual output stage converter effectively improves the heavy-to-light load
transient response without influencing the steady-state efficiency. However, it has two major
limitations.
First of all, in the targeted PoL application, for light-to-heavy load transients, the
prototype converters could not provide significant improvement in the peak voltage deviation
compare to the conventional single-stage time-optimal control method. During light-to-heavy
load transient recovery, inductor currents in both output stages have different slew rates compare
to the heavy-to-light transient cases. To achieve optimal transient response as defined in Section
2.4, different auxiliary inductors are required for heavy-to-light and light-to-heavy load
transients [117]. This limitation was addressed in [88] and [87] with a penalty in switching loss,
where the effective current slew rate in the auxiliary inductor is adjusted by switching the
auxiliary power transistors at high frequency with certain duty-cycle. In these works, the
auxiliary current, iLA is either constant [88] or has an adaptive slope [87] so that a single inductor
can be used for both heavy-to-light and light-to-heavy load transient suppression.
On the other hand, both the proposed converter and the converters in [88] and [87]
require a separate auxiliary inductor. In some cases, the improvement in transient performance
comes at the price of a noticeable increase in the overall inductance size and volume. This is a
common issue for most augmented converters, which makes them not preferable in some PoL
systems where the available PCB area is extremely limited.
To address the two limitations mentioned above, a flyback-transformer based buck
(FTBB) converter will be presented in the following chapter. As will be demonstrated later on,
the FTBB converter achieves significant improvement in both heavy-to-light and light-to-heavy
load transient response. In addition, the FTBB converter is capable of recycling energy during
heavy-to-light load transients, which results in lower averaged power loss compare to equivalent
single-stage conventional converters provided that the load transient happens frequently. The
flyback transformer in the FTBB converter only requires a small secondary winding, which can
be implemented in the same package with the primary winding without adding to the total
70
volume of magnetic component. As a result, the size and volume penalty in the FTBB converter
is much less compared to augmented converters.
71
Chapter 3Chapter 3Chapter 3Chapter 3
A MixedA MixedA MixedA Mixed----Signal Controlled FlybackSignal Controlled FlybackSignal Controlled FlybackSignal Controlled Flyback----
Transformer Based Buck ConverterTransformer Based Buck ConverterTransformer Based Buck ConverterTransformer Based Buck Converter
This chapter introduces a practical modification of a flyback-transformer based buck
(FTBB) converter and a complementary controller that are well-suited for point of load (PoL)
applications with highly dynamic loads. The presented FTBB converter has faster transient
response than the conventional buck converter, allowing for a reduction in the output capacitance
with little to no penalty in the power conversion efficiency and the overall inductance size and
volume. In this modification, the conventional buck inductor is replaced with the primary
winding of a flyback transformer, an extra power switch, and a set of small auxiliary power
switches on the secondary side. During heavy-to-light load transients the inductor current is
steered away from the output capacitor to the input port, achieving both energy recycling and
savings due to reduced voltage overshoots. The light-to-heavy transient response is improved by
reducing the equivalent inductance of the primary transformer winding to its leakage value. A
mixed-signal current-programmed mode controller regulates operation of the converter. The
controller also contains a transient suppression block that activates the auxiliary circuits during
transients and ensures seamless transitions between different modes.
This chapter is organized as follows: Section 3.1 presents the system structure and
introduces the operating principle of the FTBB converter. Section 3.2 addresses the design of
the steady-state current mode controller. The architecture and state diagram of the transient
suppression circuit will be introduced in Section 3.3, with particular focus on the seamless
transition between the transient and steady-state modes of operation. Section 3.4 discusses the
design tradeoffs, the influence of additional switches on the system efficiency, and the loss
compensation through energy recycling. This section also shows an analysis of the efficiency for
the FTBB converter as a function of the load change frequency. Details of the implementation of
72
a 6V-to-1 V, 3 W prototype converter using discrete components will be presented in Section
3.5. The improvement in load transient performance will be demonstrated with experimental
results. Power consumption of the proposed architecture under steady state and frequent load
changes will be evaluated and compared with a conventional buck converter with similar output
capability. A brief summary of the chapter will be presented in Section 3.6.
3.1 System Structure and Operating Principle
The FTBB converter and a mixed-signal controller as shown in Figure 3.1, combine the
stepping-inductor [98]-[100] and the current-steering concepts [76][77]. The inductor of the
output power stage is replaced with a conventional flyback transformer. The converter also has
an extra switch S0 on the primary side and several small switches on the secondary side of the
transformer. For frequently changing loads, the extra conduction losses introduced by the switch
vout(t)Load
LM
Cout
Digital Logic
A/D
Steady State Compensator
Transient Suppression
Circuit
D/A
MS
SR
S0
S1
S2
S3
MSSRS0
S1
S2
S3
Flyback Transformer
vx’
e[n]ictrl[n]
vctrl(t)
vsense(t)
iS2(t)iC(t)
Comp1
Comp2
1:1
VREF
LLEAK
Vin
D0
Figure 3.1 The flyback-transformer based buck (FTBB) converter and the mixed-signal controller [138].
73
S0 are partially or completely compensated by energy recycling ability of this topology that sends
energy back to the power source during heavy-to-light transients. This energy savings
mechanism can potentially extend the battery life of modern portable devices, in which most of
the loads are digital in nature and changing very frequently [45][118]. The penalty in the overall
inductance volume is smaller than in converter augmentation solutions described in Chapter 2
[80]-[91]. The size of the magnetic core, the largest contributor to the overall magnetic size in
the low-power applications [8], is no larger than that of the conventional buck. The flyback
transformer only requires a single secondary winding rated for a much smaller average current
than the primary winding, since it only needs to handle occasional current pulses during transient
recovery. The presented FTBB converter does not experience problems of requiring transistors
with overly large blocking voltage, an undesired characteristic for conventional stepping inductor
solutions [98]-[100]. The transistors are required to block voltages no larger than the input
voltage, Vin. Hence, the presented solution is better suited for cost-effective integration.
The flyback transformer in Figure 3.1 is modeled by an ideal 1:1 transformer with added
leakage and magnetizing inductances, LLEAK and LM, respectively. Therefore the total equivalent
inductance on the primary side is LM+LLEAK. A single-directional switch S0 is inserted to the
main power conduction path in series with the primary winding to assist heavy-to-light load
transient recovery. The secondary winding of the flyback transformer is connected to three
auxiliary switches, S1 ~ S3 and a free-wheeling diode, D0. The auxiliary switches are used in
pairs during transient recovery to control the voltage applied across the secondary winding,
which in turn manipulates the current flowing through the primary winding. The free-wheeling
diode D0 is employed for energy recycling and voltage clamping purposes. The leakage
inductance associated with the secondary winding is neglected in the model and analysis since it
does not have significant influence on the control and performance of the converter.
As described in the following subsections, the converter operates in three different
modes. In steady state it behaves as a conventional buck converter utilizing the primary side
inductance. During heavy-to-light load transients, it steers the magnetizing current away from
the capacitor, to the voltage source [76][77]. This minimizes the output capacitor overcharge
and, at the same time, recycles a portion of the energy that would have been lost otherwise. To
suppress light-to-heavy transients, it utilizes the stepping-inductor concept [98]-[100], where the
74
equivalent inductance on the primary side is reduced to the leakage value. In this way, the
current slew rate is improved.
A mixed-signal current-programmed mode (CPM) controller [119]-[121] governs the
operation of the converter as shown in Figure 3.1. In steady state the controller operates as a
conventional system [8]. The voltage loop processes digital signals and, through a digital-to-
analog converter (D/A), gives a reference to the analog current loop. During transients, the
controller activates the transient suppression block and the auxiliary circuits, which utilize two
different optimum-deviation algorithms to achieve recovery with minimum possible voltage
deviation.
3.1.1 Steady-State Operation
When the output voltage, vout(t) is within a pre-determined tolerance band near the
voltage reference, the system operates in steady state. Switch S0 is kept on, the auxiliary
switches S1 ~ S3 are kept off. The equivalent circuit of the output stage is as shown in Figure 3.2.
Here, all of the transistors on the secondary side are kept off to prevent possible current paths
through the body diodes.
In this mode, the converter functions as a conventional buck converter with output
Figure 3.2 Equivalent circuit in steady-state operation.
75
filtering inductance equal to LM + LLEAK. The CPM controller in Figure 3.1 indirectly regulates
the output voltage, by varying the inductor current. It uses an analog-to-digital converter (A/D)
to compare the output of the converter with the voltage reference, VREF and create a digital
equivalent of the output voltage error value, e[n]. This signal is passed to the steady state
compensator that creates a digital reference for the current loop, ictrl[n]. The current reference,
ictrl[n] is then converted into an analog equivalent, vctrl(t) through a digital-to-analog converter
(D/A). This is compared with the signal from the primary current sensing circuit with vsense(t) =
KsenseRs×ip(t), where KsenseRs is the “gain” of the current sensing circuit and ip(t) is the current
flowing through the primary winding. In this way, the output voltage, vout(t) is indirectly
regulated.
3.1.2 Heavy-to-light Load Transient Suppression
The recovery from a heavy-to-light load transient is conducted in two phases (as shown
in Figure 3.3). In the first phase, the stored energy of the leakage inductor is released without
causing a large voltage stress across transistors. In the second phase, the output voltage
deviation is suppressed through magnetizing inductor current steering, during which process the
energy of the magnetizing inductor is recycled to the power supply source. In the following sub-
sections two methods for the leakage inductance energy release (for relatively large and small
values of LLEAK) are presented as well as the subsequent current steering technique.
A Leakage Inductance Energy Release for Large LLEAK
The initial phase of a heavy-to-light load transient response for a relatively large LLEAK
can be described by the key current and voltage transient waveforms and the equivalent
converter circuits as shown in Figure 3.3 and Figure 3.4, respectively.
The converter initially operates with a load current, i load(t) = Iold. At t0, the load current
steps down to a new value Inew. Excess current from the transformer flows into the output
capacitor, Cout and forms a positive capacitor current, iC(t). Assuming that the magnitude of the
load step is much larger than the steady-state current ripple in the power stage, iC(t)
approximately equals to Iold – Inew. The output voltage, vout(t) rises due to this positive iC(t).
76
This current change is detected when the output capacitor voltage increases beyond the
upper tolerance threshold VTH_H at t = t1, causing the converter to enter transient suppression
mode. At this point, the main switch, MS, and the synchronous rectifier, SR, are switched off; S2
Iold
Inew
iload(t)
iLM(t)
iC(t)
iS2(t)
Iold
Inew
-Inew
Iold
Inew
vout(t)
t0t1t2
∆vout
∆vout for
conventional buck
kH-L_con
kH-L
0 A
0 A
VREF
Iold - Inew
VTH_H
ip(t)
0 A
LLEAK energy release
LM energy release
t3
Figure 3.3 Key current and voltage waveforms during a heavy-to-light load transient recovery process.
77
and S3 are switched on (Figure 3.1), to release the energy stored in the leakage inductance. As a
result, the body diode of the SR starts conducting, forming the equivalent circuit as shown in
Figure 3.4. In this way a virtual short-circuit is created across the magnetizing inductance LM
while the energy in LLEAK dissipates via the body diode of SR, DSR. Now, the primary current, i.e.
the leakage inductance current, ip(t), quickly drops to zero with a slew-rate of (Vout+VD)/LLEAK,
where VD is the forward voltage drop of DSR. When ip(t) reaches the zero value, DSR turns off.
At this point the energy release process is complete and only the magnetizing current iLM(t)
circulates through the transformer. If the equivalent series resistance (ESR) of Cout is small and
can be ignored, the amount of voltage overshoot, ∆vout, also reaches its peak value. It is
proportional to the integral of iC(t) over time t0 to t2, as represented by the shaded area shown in
Figure 3.3. The primary current sensing circuit detects the zero-crossing of current ip(t) and
initiates the following phase, i.e. voltage recovery and the magnetizing current steering process.
Ideally, the previously described procedure results in the leakage inductance energy
release without exposing transistors to a high voltage stress. Also, this procedure does not
require an extremely fast zero-current detection circuit, since, after the DSR turns off, the leakage
current remains zero. However, in practice, problems can arise due to the reliance on the body
diode of SR. When compared with the current slew rate, this diode is relatively slow and, as a
1:1
Figure 3.4 Equivalent circuit during during leakage inductance energy release (t1~t2) for large LLEAK [138].
78
consequence, voltage spikes might still occur. To minimize this problem, a Schottky diode can
be added in parallel with DSR. Alternatively, instead of using the body diode, the transistor SR
can be kept on during the leakage inductance recovery phase. However, such a solution would
require a very fast zero-current detection circuit and/or an RC snubber, to absorb any energy left
in the leakage inductance due to non-ideal zero-current detection.
B Leakage Inductance Energy Release for Small LLEAK
For high-quality flyback transformers with a very low LLEAK, the detection of zero
leakage current can be eliminated, by the use of a small RC snubber at the switching node in
between transistor S0 and the transformer, as indicated by node vx’ in Figure 3.1. In this
approach, the energy stored in LLEAK is directly absorbed by the RC snubber, and as will be
explained in this subsection, no additional switching action or leakage current monitoring is
required.
In this case, at t = t1, MS and S0 are switched off; S1 and S2 are switched on (Figure 3.1).
The SR is also switched on to limit the voltage stress on the transistor S0 and the circuit in Figure
3.5 is formed. As can be seen from the equivalent circuit shown in Figure 3.6, a negative voltage
Rsnub
Csnub
LM
vout(t)Vin Cout
iload(t)
iLM(t)
vP
is(t)
iC(t)
ip(t)
LLEAKvx’
Figure 3.5 Equivalent circuit during leakage inductance energy release (t1~t2) for small LLEAK [138].
79
across LLEAK is applied and the snubbing resistor, Rsnub absorbs the stored energy. To protect S0,
by ensuring that the voltage vx’ (t) never drops below –Vin, the snubber resistor, Rsnub is selected
such that Rsnub×Imax < Vin, where Imax is the maximum load current.
In addition to eliminating the need for zero leakage inductance current detection, this
circuit also has less frequent switching action than the previously shown implementation. As
will be described in the next subsection, in this approach, the state of switches is the same as in
the following phase of the transient suppression process, i.e. magnetizing current steering. Thus
the converter enters the magnetizing current steering phase automatically after the energy in
LLEAK is fully released, with no extra switching action. However, adding a snubber circuit at the
switching node of the converter normally increases switching loss [8]. Thus the Rsnub×Csnub time
constant of the snubber circuit should be small enough so that it does not significantly degrade
the steady-state efficiency of the converter. As a result, this tradeoff is favorable only for very
small LLEAK values.
C Suppressing Output Voltage Overshoot through
Current Steering
After the brief leakage inductance energy releasing phase, the transistor MS and S0 are
switched off; SR, S1 and S2 are switched on. The equivalent circuit of Figure 3.7 is formed.
Rsnub
Csnub
vout(t)Cout
ip(t)
LLEAK
Vin
vx’
vx’
Figure 3.6 Equivalent circuit showing that the energy in LLEAK is absorbed by the RC snubber circuit [138].
80
During this portion of the recovery period (t2 to t3), the energy stored in LM is recycled by
steering the current iLM(t) to the input voltage source and the load current is fully supplied by the
output capacitor Cout, allowing vout(t) to drop. As a result, the problem of a large capacitor
current causing the output voltage to overshoot in the conventional buck [72] is eliminated.
During this time, a constant voltage vp = −Vin is applied across the magnetizing inductance,
where Vin is the input voltage of the converter.
In addition to stopping the capacitor from being overcharged, the FTBB converter also
improves the current slew rate. During a heavy-to-light load transient the magnetizing current
decreases at the rate:
- / /H L P M in Mk v L V L= = − . (3.1)
This is significantly higher than that of an equivalent conventional buck converter [72]:
- _ /H L con outk V L= − , (3.2)
where L = LM + LLEAK is the output filter inductance of the conventional topology. The improved
slew rate is mostly due to the input voltage value, which is usually significantly higher than Vout.
As a result the transient recovery process is significantly faster. The resulting inductor current
LM
vout(t)Vin Cout
iload(t)
iLM(t)
vP
is(t)
iC(t)
Figure 3.7 Equivalent circuit during heavy-to-light load transient recovery (t2 ~ t3) [138].
81
and output voltage waveforms using the FTBB converter and the conventional minimum-
deviation control [72] (dashed curve) are compared in Figure 3.3. As can be seen, using the
proposed control method, the amount of charge that is injected into the output capacitor Cout
during heavy-to-light load transient is much smaller than the conventional case. As a result,
peak transient voltage deviation can be successfully suppressed.
As will be described in Section 3.3, the transient suppression circuit adopts the minimum-
deviation control principle since it does not require precise capacitor charge balance control and
thus relatively simple to implement [72]. When the magnetizing inductor current iLM(t) reaches
the new load current Inew at t3, the transient recovery process is terminated. At this point, the
steady-state mode of operation is resumed and the CPM controller reactivated.
3.1.3 Light-to-heavy Load Transient Suppression
Recovery from light-to-heavy load transients is performed using the stepping-inductance
principle [98]-[100], where a sequence of current pulses reversing the output voltage drop is
created during a gradual recovery process of the magnetizing current.
The key converter waveforms during a transient are shown in Figure 3.8. The converter
initially operates with a load current, Iold. At t0, i load(t) steps to a higher value Inew. The load
draws current from the output capacitor, Cout and causes a negative capacitor current, iC(t) which
is approximately equal to Inew – Iold. The output voltage, vout(t) therefore decreases and an
undershoot occurs. When vout(t) drops below the lower tolerance threshold, VTH_L, at t = t1, the
transient recovery mode is activated.
82
Iold
Inew
iload(t)
S2, S3
ON
OFF
tpulse
iLM(t)
ip(t)
Iold
Inew
0 AiC(t)
Iold - Inew
VTH_Lvout
vout(t)
∆vout for
conventional buck
VREF
t0t1 t2 t3 tn…...t4
kL-H1
kL-H3
kL-H2
kL-H_con
0 A
iS2(t)kL-H1 kL-H2 + kL-H3
Figure 3.8 Key current and voltage waveforms during a heavy-to-light load transient recovery process [138].
83
To suppress voltage undershoot during the light-to-heavy load transient, the SR transistor
is turned off while transistors MS and S0 are turned on. The voltage across the primary winding
is pulled to Vin – Vout to boost the primary inductor current ip(t). In the meantime, switch S2 and
S3 are also turned on over a fixed period tpulse. As a result, the equivalent converter circuit in
Figure 3.9 is formed. During tpulse, a short circuit is created across the secondary winding
through the ground terminal. Therefore the voltage across the magnetizing inductor LM is zero
and a virtual short circuit across it is formed. As a result, the equivalent inductance of the main
current path is reduced to the leakage value LLEAK, which is much smaller than the magnetizing
inductance LM. The current slew rate on the primary side of the flyback transformer is drastically
increased, to the value
- 1 ( ) /L H in out LEAKk V V L= − . (3.3)
Due to this high current slew rate, a sharp ip(t) current pulse is formed, as shown in Figure 3.8.
This pulsating current quickly compensates for the capacitor charges lost due to large load
current step [100] and suppresses the vout(t) deviation over the period t1 to t2. The equivalent
circuit in Figure 3.9 also indicates that the current iLM(t) in the magnetizing inductor remains
constant during this time period due to existence of the virtual short circuit.
Figure 3.9 Equivalent circuit of the converter when current pulses in ip(t) suppress voltage undershoot (t1~t2) [138].
84
To increase the magnetizing current iLM(t), at t = t2, switches S2 and S3 are turned off.
During this time the energy stored in LLEAK is passed through the transformer and recycled to the
input source through the free-wheeling D0 (Figure 3.1) and the body diode of S3, DS3, as shown
in the equivalent circuit in Figure 3.10. During this time, the magnetizing inductance current
increases with the slew rate
3 ( 2 ) /L H in D Mk V V L− = + , (3.4)
where VD is the forward voltage drop of diodes D0 and DS3. In the meantime, the primary current
reduces with the rate
2 ( 2 ) /L H out D LEAKk V V L− = + . (3.5)
This process continues until the currents iLM(t) and ip(t) become equal and the current is(t)
in the secondary side reaches zero, forming the equivalent circuit in Figure 3.11. This happens at
the time instant t3 (Figure 3.8). From this point on, the slew rate of the inductor current is equal
to that of the conventional buck converter kL-H_con, which is the maximum available current slew-
Figure 3.10 Equivalent circuit of the converter when extra energy in LLEAK is recycled to the input power source (t2~t3) [138].
85
rate for a conventional minimum-deviation buck converter under light-to-heavy transient
recovery, as expressed in (3.6).
- _ ( ) /( )L H con in out M LEAKk V V L L= − + (3.6)
Since ip(t) is still lower than the load current Inew by the time t3, the capacitor current is
negative again and the output voltage, vout(t) starts to drop. The converter remains in this
configuration until the output voltage drops beyond the lower threshold value VTH_L again, at t =
t4, and the secondary circuit is reactivated. The whole sequence is repeated until the magnetizing
current iLM(t) reaches the new load value Inew. At that time instant, i.e. t = tn in Figure 3.8, the
steady-state mode of operation is resumed.
As shown in Figure 3.8, the transient recovery process can be viewed as two interleaving
parts. On one hand, the magnetizing current iLM(t) gradually increases to catch up with the load
current i load(t). On the other hand, short and sharp current pulses are injected from the input
source to suppress the output voltage undershoot. The comparative waveforms of an optimum-
deviation controlled conventional buck converter [72] are also shown as dashed lines in Figure
3.8. In comparison, the FTBB converter has faster voltage recovery and much smaller output
voltage deviation, even though the inductor current recovery is slightly delayed.
Figure 3.11 Equivalent circuit of the converter when currents iLM(t) and ip(t) increase with a slew rate equal to an equivalent conventional buck converter (t3~t4) [138].
86
3.1.4 Inductor Volume
The previous discussion indicates that the inductor core volume of the FTBB converter is
no larger than that of the conventional buck converter. In steady state, the energy storage
requirements are the same, i.e. the FTBB converter requires the same inductance and current
values, allowing the core of the same size to be used. During transients, the flux through the
core used in the FTBB converter, defining its volume, is also no larger than that used in the
conventional buck converter. As can be seen from Figure 3.7, Figure 3.9 and Figure 3.10, the
action of auxiliary circuit practically results in zero net flux increase through the transformer
core. This is due to the fact that the flux from the current in the secondary winding is(t) cancels
the one created by the current ip’ (t) = ip − iLM. The FTBB converter requires only one small
additional winding to handle is(t), whose average value is much smaller than that of the primary
winding current. As a result, the total volume of the magnetic component in the FTBB converter
is comparable to that in an equivalent conventional single-stage buck converter.
3.1.5 Conceptual Verification
In order to verify the operation of the FTBB concept, a FTBB converter and an
equivalent minimum-deviation buck converter [72] having the same power stage inductance are
built in PSIM [122] and simulated.
The flyback transformer in the FTBB converter is realized using the model described in
TABLE 3.1. DESIGN PARAMETER OF THE SIMULATED CONVERTER
Parameter Symbol Value
Input Voltage Vin 6 V
Nominal Output Voltage Vout 1 V
Load Current i load(t) As specified
Magnetizing Inductance LM 4.3 µH
Leakage Inductance LLEAK 0.4 µH
Output Capacitance Cout 100 µF
Capacitor ESR RESR 1 mΩ
Switching Frequency fsw 390 kHz
87
Figure 3.1. Detailed design parameters are as listed in TABLE 3.1. The MS, SR transistors and
the auxiliary switches S0~S3 are implemented with ideal switches, with instant turn-on/turn-off
time and an on-resistance of 25 mΩ. It is also assumed that the leakage inductance of the
flyback transformer is approximately 10 times smaller than the magnetizing inductance [123].
Figure 3.12 (a) and (b) demonstrate the heavy-to-light load transient response of the
conventional minimum-deviation control method [72] and that of the FTBB converter. Both
inductor current and output voltage waveforms are compared. After a –3 A load transient
occurs, the minimum-deviation controller turns on the SR transistor so that the inductor current
drops with maximum available slew rate determined by (3.1) and achieves minimum possible
voltage deviation for the conventional buck topology. As can be observed, during transient
recovery the FTBB converter generates a much higher inductor current slew rate in comparison.
As a result, the output voltage deviation is drastically reduced, from 175 mV to 32 mV. The
time required for vout(t) to return to steady-state is also reduced by over 50 %.
Figure 3.13 (a) and (b) show the light-to-heavy load transient response of the
conventional minimum-deviation control method [72] and that of the FTBB converter. The
equivalent current in the magnetizing inductor, iLM(t), is also illustrated. The conventional
minimum-deviation converter recovers the inductor current with maximum available slew-rate
define by (3.6). For the FTBB converter, the duration of the time tpulse when auxiliary switches
S2 and S3 are in ON position is experimentally selected to be 160 ns. As can be observed from
Figure 3.13 (b), the pulsating current due to reduced effective inductance on the primary side
suppresses the deviation of vout(t) from 65 mV to 31 mV. And the inductor current ip(t) reaches
its new steady-state value within approximately the same time as the minimum-deviation
controlled buck converter.
88
(a)
(b)
Figure 3.12 Simulation waveforms of a buck converter using (a) conventional minimum-deviation control method and (b) the proposed method under a –3 A load current transient.
89
Cu
rren
t(A
)V
olt
ag
e(V
)
(a)
iLM(t)
vout(t)
ip(t)
vout(t) = 31mV
iLM(t) stays constant
when S2 and S3 are on
Time (µs)
(b)
Figure 3.13 Simulation waveforms of a buck converter using (a) conventional minimum-deviation control method and (b) the proposed method under a +3 A load current transient.
90
3.2 Steady State Controller Design
In steady state, the converter operates as a conventional buck while the secondary
winding of the transformer is open-circuited. A conventional peak current-program mode
(CPM) controller [8] is implemented to regulate the output voltage.
L
Cout vout(t)
MS
SR
vx
A/D
e[n]Gc(z)
Dead-time
c(t)
cMS(t) cSR(t)
Steady State CompensatorDigital
Compensator
Rs
RESR
D/A
ictrl[n]
vsense(t)
vctrl(t)
S
RQ
VREF
clkfs
ip(t)
vcomp1(t)
Comp1 Rload
Vin
Ksense
(a)
Gc(z)
Giv(s) GA/D(s)
Gci(s)
Digital
Compensator
A/DBuck Converter
D/A, Comparator
and Current Sensor
e
v
ictrl
ip
(b)
Figure 3.14 (a) Architecture of the current mode controller that regulates the steady state operation, and (b) linearized model of the closed loop system.
91
Architecture of the CPM controller is as shown in Figure 3.14 (a). The inductor L in the
buck-type output stage is realized by the primary winding of the flyback transformer, with a
winding inductance of L ≈ LLEAK + LM. A current sensing resistor, Rs is placed in series with the
primary side of the transformer to sense its current ip(t).
In each switching cycle of the steady-state clock signal, clkfs, an analog-to-digital
converter (A/D) compares the output voltage, vout(t) with the reference voltage, VREF and sends
the error signal, e[n] to a digital compensator, which generates the current command, ictrl[n]. A
digital-to-analog converter (D/A) converts the current command into an analog voltage, vctrl(t),
which is then compared with the signal vsense(t) = KsenseRsip(t) from the inductor current sensing
circuit, in order to determine the peak value of ip(t) within that switching cycle.
As shown in Figure 3.15, at the beginning of each switching cycle, the pulse-width
modulation (PWM) signal, c(t) is set to logic 1 by the rising edge of clkfs to turn on the MS
transistor. The inductor current, ip(t) rises and so does the output of the current sensor, vsense(t).
When vsense(t) exceeds the control voltage, vctrl(t), the output of comparator Comp1 flips and
resets the PWM signal, c(t) to logic 0. Thus the SR transistor is turned on and ip(t) decreases. In
a practical design, the PWM signal, c(t) is sent to a "Dead-Time" module [124] that generates
two non-overlapping PWM signals, cMS(t) and cSR(t), to control the MS and SR transistors,
respectively. As indicated by Figure 3.15, the peak inductor current ip(t) strictly follows the
current command, ictrl[n] in every switching cycle. Thus in small signal model, the power
Figure 3.15 Theoretical waveforms of the current-programmed control loop.
92
inductor functions as a controlled current source with an output of ip [8].
Modeling of the peak CPM controller has been investigated in various literatures [8]-
[121]. A simplified linearized model is shown in Figure 3.14 (b). Giv(s) is the control-to-output
transfer function of the CPM buck converter, which is given by [87]
(1 )( )
[1 ( ) ] (1 / )load ESR out
ivload ESR out p
R R C sG s
R R C s sω+=
+ + ⋅ +, (3.7)
where Rload is the equivalent load resistance and RESR is the equivalent series resistance of the
output capacitor, Cout. ωp is an equivalent high-frequency pole that is usually at a location near
or greater than the switching frequency, fsw. It has little impact on the overall transfer function
and can often be ignored [87]. As a result, in most cases Giv(s) can be treated as a first-order
expression. Thus it is much easier to perform loop compensation and achieve high loop
bandwidth compare to voltage mode controllers [8].
GA/D is the gain of the A/D converter, which is discussed in Chapter 2 and can be
expressed as
//
1 convstA D
A DG e
V−= ⋅
∆, (3.8)
where ∆VA/D is the quantization bin of the A/D and tconv is the conversion latency.
Gci(s) is the combined control-to-current transfer function, which includes the gain of
resistive current sensor, KsenseRs, transfer function of the D/A converter, GD/A and the delay, tPWM
introduced by the PWM comparator, Comp1. The expression for Gci(s) is as follows:
/( ) PWMstD Aci
sense s
GG s e
K R−= ⋅ , (3.9)
where GD/A is determined by the quantization bin, ∆VD/A and conversion latency, tD/A of the D/A;
tPWM is dependent on the steady-state duty-cycle D and switching frequency, fsw.
/// 1
D AstD AD A
VG e
LSB−∆= (3.10)
93
PWMsw
Dt
f= (3.11)
As previously discussed, the CPM converter has a first-order control-to-output transfer
function, thus a proportional-integral (PI) compensator is usually sufficient for loop
compensation. The continuous-time domain transfer function of a generic PI compensator is
given in (3.12), where ωL is the frequency of the inverting zero, and parameter Kc is adjusted
through simulation to achieve desired loop bandwidth.
( ) 1 Lc cG s K
s
ω = +
(3.12)
The transfer function Gc(z) and differential equation describing the digital PI
compensator are as (3.13) and (3.14).
1
1( )
1c
a bzG z
z
−
−+=−
(3.13)
[ ] [ 1] [ ] [ 1]ctrl ctrli n i n ae n be n= − + + − (3.14)
It is a common approach to design the compensator in continuous-time domain to select the zero
frequency, ωL and gain, Kc, then obtain the parameters a and b for the discrete-time domain
compensator using bilinear transform of (3.12). A practical implementation of the digital
Figure 3.16 Block diagram of the digital PI compensator.
94
compensator is as shown in Figure 3.16. Look-up tables (LUTs) are used to simplify the
hardware and avoid the calculation delay introduced by multipliers necessary for calculating
a×e[n] and b×e[n-1].
The design parameters of the CPM buck converter are as listed in TABLE 2.1. The ESR
of output capacitor includes a 20 mΩ current sensing resistor that will be used by the transient
suppression circuit. Bode plots of the uncompensated loop transfer function and the
compensator are as shown in Figure 3.17 (a) and (b), respectively. Bode plots of the
compensated system using a continuous-time compensator and a digital compensator are as
shown in Figure 3.18. A phase margin (φm) of 110˚ and loop bandwidth of 38 kHz are achieved.
TABLE 3.2. DESIGN PARAMETERS OF THE CPM BUCK CONVERTER
Parameter Symbol Value
Input Voltage Vin 6 V
Nominal Output Voltage Vout 1 V
Output Accuracy - ±1 %
Load Current i load 0.2 to 3 A
Primary Inductance LM+LLEAK 2.4 µH
Output Capacitance Cout 200 µF
Switching Frequency fsw 390 kHz
Capacitor ESR RESR ~22 mΩ
Current Sensor Gain KsenseRs 0.5 V/A
ADC Quantization Range VA/D 2 V
ADC Quantization Bin ∆VA/D 7.85 mV
ADC Resolution NA/D 8 bits
ADC Conversion Latency tconv 200 ns
DAC Output Range VD/A 2 V
DAC Quantization Bin ∆VD/A 1.95 mV
DAC Resolution ND/A 10 bits
DAC Conversion Latency tD/A ~10 ns
Frequency of Inverting Zero ωL 6000 rad/s
95
Ma
gn
itu
de (
dB
)P
ha
se
(d
eg
)
Frequency (rad/s)
Uncompensated Loop Transfer Function
Low frequency
poleHigh frequency
pole
ESR
zero
(a)
(b)
Figure 3.17 Bode plots of (a) the uncompensated loop transfer function and (b) the continous time-domain PI compensator.
96
Ma
gn
itu
de
(d
B)
Ph
ase
(d
eg
)
Frequency (rad/s)
m=110˚ (at 38.7kHz)
(a)
Magnitu
de (
dB
)P
hase
(de
g)
(b)
Figure 3.18 Bode plots of the compensated loop transfer function using (a) continous-time PI compensator and (b) the digital PI compensator.
97
3.3 Design of the Dual-mode Digital Control Unit
The controller in Figure 3.1 provides signals for the switches of the FTBB in all modes of
operation and also ensures seamless transitions between different modes. These include
transitions between steady state and transients as well as transitions during transient, as described
in the previous section.
The block diagram of the controller is as shown in Figure 3.19 and its operation is
A/Dvout(t)
VREF[n]
Transient
suppression logic
ae[n]+be[n-1]
ictrl[n-1]
RegisterD/A
ictrl[n]
vsense(t)
vctrl(t)
Dead-time
module
cMS, cSR
Comp2
is(t)iC(t)
cS0 to cS3
Clock
divider
clk8fsw (8 fsw)clkfsw
clk8fsw
Comp1
MS & SR sw. selector
Steady state. PI compensator &
Transient current estimator
e[n]
clk
vout[n]
ictrl[n]
|e[n]|>eTH[n]
S
R Q
Tr. detector
tr
1
0
e[n]
Clock selector
K(e[n]-e[n-1])K
clk
clk
0
1
clk
tr
e[n]
tr
tr
en
K
rst
msc
clk
S
R
Qclk
tr
0
1
rst
msc
vcomp2
vcomp1
vcomp1
Figure 3.19 Block diagram of the controller [138].
98
described by the state diagram in Figure 3.20. It consists of two comparators, an analog-to-
digital converter, a digital-to-analog converter, and fairly simple digital logic. The main
functional blocks of the digital part are transient detector, PI compensator & transient current
estimator, MS & SR switch selector, clock selector, and transient suppression logic.
The output voltage of the FTBB converter, vout(t), is quantized to its digital equivalent,
vout[n], by the analog-to-digital converter (A/D) at a sampling rate 8 times higher than the
switching frequency, fsw. This digital value is then compared with the desired reference, VREF[n],
to obtain the voltage error signal, e[n]. This error is monitored by the transient detector that
determines the mode of operation. The converter operates in steady-state mode of operation
when there are no load transients, or disturbances are small, so the error voltage is smaller than
the predefined threshold, eTH[n]. Here, the threshold is a design parameter that, as described in
the next section, is determined experimentally. Alternatively, a dedicated analysis could
potentially be conducted to find the exact relation between the threshold setting and voltage
overshoot values. Such an analysis would need to take into account the size and the slope of the
Figure 3.20 State diagram of the digital controller [138].
99
load current steps, position of the step with respect to the state of the converter switches, system
delays, filter component values, as well as influence of the output capacitor’s equivalent series
resistance (ESR) and other parasitic.
In this mode, the output of the transient detector, tr, is low and the controller operates as a
mixed-signal current programmed mode (CPM) system [119]-[121]. During this state the clock
selector produces clk pulses at fsw and the PI compensator & transient current estimator block
implements a conventional PI control algorithm [8] to calculate ictrl[n], as described in Section
3.2. In the next step, ictrl[n] is converted into a proportional voltage value vctrl(t) and compared
with the signal vsense(t) = KsenseRs×ip(t), from the primary current sensing circuit, to form an input
for the MS & SR switch selector. This produces the control signals for switches MS and SR
(Figure 3.1), labeled as cMS and cSR, respectively.
A transient is detected when e[n] exceeds the maximum allowable deviation, i.e. for |e[n]|
> eTH[n]. At that point the S-R latch of the transient detector is triggered and, consequently, the
signal, tr that is used to initiate a transient mode is set. Now, the transient suppression logic is
activated. The clock selector produces clk signal at 8 times fsw. Also, in this mode, the PI
compensator changes its structure and becomes an estimator of the primary current. As
described later, this estimation is used to provide a seamless return to the steady state [125].
The transient suppression logic produces control signals for auxiliary switches S0 to S3
(Figure 3.1), labeled as cS0 to cS3, and indirectly controls the operation of the main switches, MS
and SR, through a 2-bit main switch control signal, msc. As described in the following
subsections, the operation of transient suppression logic depends on the type of transient and, in
addition to controlling all switches of the FTBB converter, this logic also ensures seamless mode
transitions. After the transient is suppressed, the transient suppression logic resets the transient
detector and the controller returns to the steady-state mode of operation.
3.3.1 Heavy-to-Light Transient Operation
The operation of the transient suppression logic during a heavy-to-light transient is fairly
simple. It is mainly governed by the pulses of the comparators Comp1 and Comp2 and can be
described by looking at Figure 3.3 to Figure 3.7. Upon a transient the register keeping value
ictrl[n] is reset and a two-phase recovery sequence is performed, as described in Section 3.1.2.
100
The end of the leakage current energy release period, i.e. zero crossing of inductor current ip(t), is
detected with Comp1 and this process is followed by the magnetizing inductor current steering
period (t2 to t3 in Figure 3.3). The primary winding of the flyback transformer is now an open
circuit and the load current is fully supplied by the output capacitor, Cout, thus i load(t) = −iC(t).
This period ends when the magnetizing current reaches the new load value, i.e. is(t) = −iC(t),
detected by Comp2. At this time instance, the ictrl[n-1] register of the PI compensator (Figure
3.19) is updated with the new current estimate, the transient detector is reset, and the steady-state
mode of operation resumed.
To further minimize the transient voltage deviation, the transient detector in Figure 3.19
can be replaced by an asynchronous threshold detector as reported in [66], such that the inherent
detection delays are practically eliminated.
3.3.2 Light-to-Heavy Load Transient Operation
For light-to-heavy transients, depicted in Figure 3.8 to Figure 3.11, the analog-to-digital
converter and the comparator Comp2 produce the main control signals. As described in Section
3.1.3, as soon as a positive transient is detected, a virtual short across the primary winding is
created over a fixed tpulse period, to form the rising slope of the short current pulse in Figure 3.8.
After this period, the S2 and S3 (Figure 3.1) are turned off, so the equivalent circuits in Figure
3.10 and Figure 3.11 can be formed. The switches remain in this state until the voltage drop, i.e.
e[n], exceeds the pre-defined threshold, and the new pulse is initiated. The end of the light-to-
heavy transient recovery mode is sensed when the magnetizing current reaches the new load
value. This is performed through the detection of the capacitor current zero crossing during the
mode of operation shown in Figure 3.11. Since in this mode the secondary current is(t) is zero,
Comp2 can be used for zero crossing detection.
3.3.3 Seamless Transition to Steady State
To achieve smooth transitions to steady state from transient modes, the current command
ictrl[n] of the PI compensator is updated such that the steady state starts with an ictrl[n] value that
matches the new load current value [125]. This value is obtained with a relatively simple
estimation method, using the output voltage measurement and the transient current estimator in
Figure 3.19, which shares the same hardware with the PI compensator. To describe the method,
101
Figure 3.21 and the analysis shown as follows can be used. For simplicity, in this analysis, it is
assumed that the output voltage deviation is significantly smaller than the dc output voltage
value and, consequently, that the load can be represented as a current source.
The estimation of the new load current during a heavy-to-light load transient is performed
during the time when the circuit in Figure 3.7 is valid. Figure 3.21 (a) shows a simplified
equivalent circuit during that period, where Inew is the new load value.
It can be seen that, during this phase, the load current is fully supplied by the output
capacitor, and the output voltage deviation, ∆vout over one sampling period, Tsample can be
represented as
sampleout new
out
Tv I
C∆ = − . (3.15)
Based on this equation, the new current command, ictrl_new[n] can be estimated as
_ [ ] ( [ ] [ 1])ctrl newi n K e n e n= − − . (3.16)
where e[n]−e[n–1] is the difference between two successive voltage samples. It is proportional
to the output voltage deviation. K is a constant that depends on the quantization bin of the A/D,
the gain of the primary current sensing circuit, Tsample, and Cout. In a practical implementation,
e[n] and e[n–1] are taken with a slight delay after a transient occurs, in order to eliminate the
influence of voltage ringing caused by the capacitor's equivalent series inductance (ESL).
(a) (b)
Figure 3.21 Simplified equivalent circuits of the converter during the load current estimation period: (a) for a heavy-to-light load transient; (b) for a light-to-heavy load transient [138].
102
To estimate the new current command after a light-to-heavy load transient, two vout(t)
samples are taken right after the transient is detected, and before the auxiliary switches are
activated (during the t0 to t1 time interval in Figure 3.8). During this brief period, the equivalent
circuit of the converter can be modeled as shown in Figure 3.21 (b). Here the inductor is
replaced with a current source whose value is equal to the pre-transient load current, labeled as
Iold. Now the output voltage deviation over one sampling period is
( )sampleout new old
out
Tv I I
C∆ = − − , (3.17)
and the equivalent expression for the new current command value becomes
_ _[ ] ( [ ] [ 1]) [ ]ctrl new ctrl oldi n K e n e n i n= − − + , (3.18)
where ictrl_old[n] is the old steady-state current command that was stored in the PI compensator
prior the transient. Equations (3.15) and (3.17) indicate that the accuracy of the estimation and
the value of factor K can be affected by variations in the output capacitance. To eliminate this
problem, a self-calibration method can be employed [54][114]. For example, the current
estimator can be tuned according to its response to a small known current step, as described in
the sensor-less current programmed mode controlled system reported in [114].
To handle multiple nested light-to-heavy load transients the A/D of this circuit can be
modified as demonstrated in [126].
3.3.4 Prevention of Undesired Mode Transitions
Multi-mode controllers based on threshold voltage monitoring tend to suffer from
undesired mode transitions when the output voltage gradually settles after a transient event. This
problem is avoided by introducing a transient blocking state after the transient suppression
process is complete. As illustrated in Figure 3.20, during this time, the converter is forced to
operate with the steady state CPM controller, until the output voltage settles to the nominal value
and the error signal e[n] is no larger than one quantization step of the A/D converter.
Meanwhile, the difference between consecutive samples of the error signal, e[n] – e[n-1], is
monitored, to determine whether a new load transient has occurred. If the controller detects a
103
sudden change that results in (e[n] – e[n-1]) > eTH[n], a new transient suppression process is
activated.
104
3.4 Energy Recycling and Losses of the Auxiliary
Switches
The auxiliary switches, S0 to S3 (Figure 3.1) of the presented FTBB system inevitably
introduce extra conduction and switching losses and result in lower steady-state efficiency when
compared to the conventional buck converter. However, these losses can be partially or fully
compensated, due to the ability to recycle energy in the FTBB converter. As will be
demonstrated in Section 3.5, for frequent load transients that are characteristic for PoL
applications, the efficiency of the FTBB system can be even better than that of the conventional
buck converter. The range of operation where the FTBB converter has a higher efficiency than
the conventional buck converter can be estimated using simulations and the following analysis.
As illustrated in Figure 3.3, when the auxiliary switches S1 and S2 are turned on and S0 is
turned off during a heavy-to-light transient recovery, magnetizing current, iLM(t) is steered back
to the input source through the secondary winding of the transformer. As it can be seen from the
simulation results in Figure 3.22 and Figure 3.23, the current steering has two positive effects.
First, a portion of energy stored in the inductance is always recycled. Second, reduced voltage
overshoots also result in power savings. This is because during overshoots, larger than nominal
power is unnecessarily delivered to the load.
The amount of energy savings obtained with the FTBB converter strongly depends on the
load transient values and the control methods used. The simulation results of Figure 3.22 and
Figure 3.23 show dynamic responses of the conventional buck and the FTBB converters for
different load transients. Both converters are regulated with optimum deviation control [72],
have the same equivalent output filter inductances, and the same output capacitance values.
For heavy to a no-load transient (Figure 3.22) both the conventional buck and the FTBB
converters recycle the entire energy stored in the inductor back to the source and no saving is
achieved, even though the voltage overshoot of the FTBB converter is much smaller.
For heavy-to-light and heavy-to-medium load transients the energy savings become
noticeable. As shown in Figure 3.23, a smaller amount or no energy is recycled by the buck
converter while the FTBB converter recycles a significant amount of energy. The amount of
105
energy recycled through this mechanism can be calculated numerically from simulation or
measurement results, as
0
( )ist
rec in negW V i t dt= ∫ , (3.19)
where tis is the inductor current settling time, Vin is the input voltage, and ineg(t) is the negative
portion of the input current.
In addition, for the buck converter, significantly larger than the nominal energy is
delivered to the load, due to the larger overshoot. This excess energy, i.e. overshoot energy, can
be calculated as:
2 2
0
( )stout REF
osnew
v t VW dt
R
−= ∫ , (3.20)
where ts is the output voltage settling time, VREF is the desired output value, and Rnew is the new
load value.
Based on the previous analysis, the energy savings of the FTBB converter obtained
through current steering can be calculated as:
_ _ _ _( ) ( )rec FTBB rec buck os buck os FTBBW W W W W= − + − , (3.21)
where Wrec_FTBB and Wrec_buck are the energy recycled through the inductor current steering for the
FTBB and buck converters, respectively. The terms Wos_FTBB and Wos_buck represent extra energy
consumed during the overshoot for both topologies.
On the other hand, the additional power loss caused by the auxiliary switches can be
expressed as
3 32
_ _ _0 0
Aux on n rms n SW nn n
P R I P= =
= × +∑ ∑ , (3.22)
106
where ΣRon_n×Irms_n2 represents the total conduction losses of switches S0 to S3 and the term
ΣPSW_n accounts for all additional switching losses (including gate drive losses). In the first term,
the conduction losses of S0 are dominant, since this switch is inside the main current conduction
path and is active most of the time. In the second term, the switching losses of S2 and S3 are
dominant, due to multiple switching actions during light-to-heavy load transients.
For frequent load changes, which are typical for PoL applications, the introduced FTBB
converter is more efficient than the conventional buck converter if the following equation is
satisfied:
load AuxW f P⋅ > . (3.23)
where fload is load changing frequency.
107
(a)
Cu
rren
t(A
)V
olt
ag
e(V
)
Time (ms)
vout(t)
iLoad(t)
iin(t)
Curr
ent
(A)
iLoad = Iload_nom
vout(t) = 21%VREF
Energy recycling
(b)
Figure 3.22 Simulation results for a full-load to no-load transient for the FTBB converter (a) and a buck converter (b). Top waveforms: output voltages vout(t); Middle waveforms: load currents i load(t); Bottom waveforms: input currents i in(t) of the converters [138].
108
(a)
(b)
Figure 3.23 Simulation results for a 100% to 33% load transient for the FTBB converter (a) and a buck converter (b). Top waveforms: output voltages vout(t); Middle waveforms: load currents i load(t); Bottom waveforms: input currents i in(t) of the converters [138].
109
3.5 Prototype Design and Experimental Results
In order to verify the functionality and performance of the FTBB converter, a 6 V-to-1 V,
3 W, 390 kHz experimental prototype was designed based on the diagrams as shown in Figure
3.24 using discrete off-the-shelf components. An FPGA development board based on Altera's
Cyclone IV FPGA chip is used to implement the digital logic as shown in Figure 3.19 and Figure
3.20. Also, for comparison, a conventional buck converter with identical components (excluding
auxiliary circuit) was built and tested. Detailed design parameter and test set-ups will be covered
in this section. Measurement results on load transient performance and power consumption will
be presented.
3.5.1 Prototype Implementation and Set-up
Figure 3.24 Block diagram of the FTBB converter prototype.
110
Both prototype converters are implemented on custom-designed printed circuit boards
(PCB). The block diagram of the FTBB converter prototype is as shown in Figure 3.24. It is
based on the system block diagram as shown in Figure 3.1.
Current sensing in the prototype is performed by placing sensing resistors in the current
paths of interest, where the sense resistors for is(t) and iC(t) are well-matched to provide accurate
comparison. The voltages across the resistors are then amplified. The gain of each current
sensor is labeled as Kiv. To minimize the influence of current ringing due to the action of the
switches, short blanking periods immediately following the switching actions are also
introduced.
The PCB of the FTBB converter prototype is as shown in Figure 3.25. The PCB carries
the output stage, A/D, D/A, resistive current sensing circuits for primary current, ip(t), capacitor
current, iC(t) and secondary winding current, is(t), comparators, and switching loads that are used
to generated load current steps. The digital logic on the FPGA board communicates with the
PCB via ribbon cables. It samples the 8-bit error signal, e[0:7] and monitors the output of
comparators Comp1 and Comp2 to generate the current command, ictrl[0:9] and the switching
Output
Stage
Vin
Switching
Loads
D/A
A/D
e[0:7]
vcomp1(t)
vcomp2(t)
ictrl[0:9]
Digital
Logic on
FPGA
Switching Commands for Main & Auxiliary
Switches and Switching Loads
Figure 3.25 Picture of the prototype FTBB converter.
111
commands for main and auxiliary switches. Detailed list and description of important
components can be found in TABLE 2.4.
The flyback transformer selected for this prototype has a rated continuous current of 4.9
A and a footprint of 12.5 mm×12.5 mm, which is comparable to the size of the conventional
buck inductor with the same current rating [123][127]. The turns-ratio of the primary and
secondary winding is 1:1. This is selected based on the following two considerations: First, an
1:1 turns-ratio guarantees that the maximum blocking voltage on all MOSFETs are limited to the
magnitude of input voltage Vin(t) under both steady-state and transient-recovery operating
modes. They can be realized using the same type of transistor and/or the same fabrication
process, which makes it feasible for on-chip implementation and eliminates the needs for over-
designing the system to accommodate voltage stress significantly higher than Vin(t). Second, as
explained in Section 3.3, 1:1 turns-ratio ensures the current is(t) in the secondary winding of the
transformer equals to the magnetizing current, iLM(t) of the primary winding, which facilitates
current sensing and comparison to determine the end of the transient suppression process.
TABLE 3.3. COMPONENT LIST OF THE PROTOTYPE CONVERTER
Component Value Model Number Description
Flyback transformer 4.7 µH WE-DD 744873004
Rdc = 24 mΩ. Magnetizing inductance ≈ 4.3 µH. Leakage inductance ≈ 0.4 µH. Saturation current = 10 A per winding.
Output Capacitors 100 µF ×2 GRM31CR60J Ceramic Capacitor with RESR ≈ 2 mΩ. Capacitance drops by 20% at the application voltage.
MOSFETs - IRF7821 Ron = 10 mΩ. All switches in this system are implemented with IRF7821.
A/D 10-bit AD9215 Effective resolution = 8 mV. 8 bits are used.
D/A 10-bit AD9740 Effective resolution = 2 mV .
Comparators - LT1719 Rail-to-rail. Input offset 0.4 mV.
Switching Load Resistors
0.5-5 Ω WSR Series
Has low series inductance (0.5 nH to 5 nH). Generates near instantaneous current step when branch is turned on/off
Current Sensing Resistor
20 mΩ ERJ-M1WSF20MU ±1% resistance tolerance
112
3.5.2 Transient Performance
Transient performance of the prototype converters is examined following the same
manner as Section 2.6.1 in Chapter 2. The control switches of one or more switching loads are
periodically turned on/off to generate load transients.
In order to demonstrate the effect of the FTBB converter, transient response of a
conventional buck converter prototype is also examined for comparison. Operation of both
converters in steady state is regulated with the identical current-programmed mode controllers
and both converters utilize minimum deviation control [72] during transients, resulting in the
smallest possible output voltage deviation for a given power stage. In the experiments presented
in this subsection, the transient detection error threshold, eTH[n] for both converters is set to 4
A/D quantization steps. In this case, due to unknown delays and parasitic components of the
system, the threshold value is determined experimentally. Ideally, for a zero-delay FTBB
converter with very small leakage inductance, the top threshold value could be the same as the
maximum allowable voltage excitation during a heavy-to-light load transient.
Figure 3.26 and Figure 3.27 compare the –3 A heavy-to-light load transient responses of
the FTBB converter with that of the conventional buck converter. The results show that the
FTBB converter almost instantaneously reduces the primary current of the transformer, i.e.
capacitor charging current, to zero. This drastically reduces the output voltage overshoot from
210 mV to 70 mV, allowing for a proportional reduction in the output capacitance value. As
described in Section 3.1.2, the sudden reduction in the capacitor charging current is achieved by
redirecting the magnetizing current back to the input voltage source, and in the same process, the
energy stored in the inductor is recycled.
113
Figure 3.26 Transient response of the conventional buck converter for a 3 A heavy-to-light load transient. Top: the buck-inductor current iL(t), scale 4 A/div; Middle: ac component of the output voltage vout(t), scale 100 mV/div; Bottom: load step command i load(t). Time scale is 20 µs/div [138].
Figure 3.27 Transient response of the FTBB converter for a 3 A heavy-to-light load transient. Top: the primary current ip(t), scale 4 A/div; Middle: ac component of the output voltage vout(t), scale 100 mV/div; Bottom: load step command iload(t). Time scale is 20 µs/div [138].
114
Figure 3.28 and Figure 3.29 demonstrate the responses of both converters for a +3 A
light-to-heavy load transient verifying the fact that the FTBB topology produces a 25% smaller
voltage deviation. It can be seen, as described in Section 3.1.3, the output voltage deviation is
reduced by lowering the effective inductance of the primary side of the transformer to its leakage
value and producing a set of current pulses that reverse the capacitor discharging process. It
should be noted that for converters with relatively small step down conversion ratios and/or
higher output voltages the improvement in light-to-heavy load transient response could be even
larger.
115
Figure 3.28 Transient response of the conventional buck converter for a 3 A light-to-heavy load transient. Top: the buck-inductor current iL(t), scale 4 A/div; Middle: ac component of the output voltage vout(t), scale 50 mV/div; Bottom: load step command i load(t). Time scale is 5 µs/div [138].
Figure 3.29 Transient response of the FTBB converter for a 3 A light-to-heavy load transient. Top: the primary current ip(t), scale 4 A/div; Middle: ac component of the output voltage vout(t), scale 50 mV/div; Bottom: load step command i load(t). Time scale is 5 µs/div [138].
116
3.5.3 Efficiency Comparison
As discussed in Section 3.4, the proposed FTBB topology introduces extra conduction
losses that can be compensated through the energy recycling capability. To verify these trade-
offs, the efficiency and power losses of the conventional buck and the FTBB converters are
measured and compared both in steady state and for frequent load transients. The power
consumed by both converters are measured using the setup as shown in Figure 3.30. In this
experiment, only the power consumption of the output stages and the gate drivers for power
MOSFETs are taken into account, since they are the most critical elements that determine the
system’s efficiency [9]-[11]. The common parts of the two converters used in the prototypes,
e.g. A/D, D/A, current sensor and the FPGA board, are general purpose devices. Their power
consumption does not reflect the actual power consumption of the equivalent components that
are optimized for PoL applications [135]-[136]. As a result, the power consumption of these
devices is excluded in the efficiency measurements. It should also be noted that these
components, when they are specially designed for PoL converters, consumes only small amount
of power which is usually much less than the power losses in the output stage [135]-[136]. As a
result, excluding their power consumption in the efficiency measurements would not
significantly influence the conclusion of this work.
The input of the converter is connected to a DC power supply that provides a constant
Figure 3.30 Test setup for power consumption measurement.
117
voltage of 6 V. The input voltage, Vin(t) is measured at the input terminal of the PCB to exclude
the voltage drop on power cables. The input current, i in(t) is measured using a Tektronix
TCP312 current probe. A 470 µF capacitor is connected across the input terminal of the PCB,
which helps filtering out high frequency element in the input current waveform so that i in(t)
represents the averaged current drawn from the power supply.
The output of the converter is connected to a Hewlett Packard 6051A electronic load. To
evaluate the steady-state output power, the switching loads on the prototype PCB are disabled
and the electronic load sets the DC load current. The output current, iout(t) is also measured
using the current probe. To examine the dynamic power consumption under load transients, the
electronic load is disconnected and the on-board switching loads are activated. The output
current is estimated based on the resistance of each switching loads as well as the duty-cycle at
which the loads switch.
Steady-state efficiency and power consumption of the converter is calculated based on
the measurement results of averaged input and output power, which is given by
( ) ( )
( ) ( )out out
in in
v t i tEfficiency
v t i t
⋅=⋅
, (3.24)
( ) ( ) ( ) ( )loss in in out outP v t i t v t i t= ⋅ − ⋅ . (3.25)
A Steady-state Efficiency
Steady-state efficiency measurement result over a 10% to 100% of the output load range
is as shown in Figure 3.31. It can be seen that at light load, the FTBB converter achieves similar
efficiency compare to the conventional buck converter. As output current increases, efficiency
degradation is observed. At full load, the FTBB converter has 2% lower efficiency compare to
the conventional buck converter.
Lower steady-state efficiency in the FTBB converter is caused by the on-resistance of the
extra switch S0 (Figure 3.1) in the main power conduction path. Since S0 is always kept on in
steady state, it introduces additional conduction loss that is approximately proportional to the
118
square of output current. When the output current is small, the amount of power lost on switch
S0 is negligible, but it becomes more noticeable with higher output current.
B Dynamic Power Consumption
To measure the dynamic power consumption under frequent changing load, the load
current is periodically switched between 2.5 A and 0.5 A with 50% duty-cycle with the
frequency ranging from 100 Hz to 12.4 kHz, which results in an averaged output current of 1.5
A. The input voltage vin(t), input current i in(t) and output voltage vout(t) are measured and
averaged over a period of 100ms. The power losses and the effective efficiency of both
converters are calculated from (3.24) and (3.25).
Figure 3.32 and Figure 3.33 confirm that, for frequently changing loads, the effect of
additional conduction losses can be compensated by the energy recycling mechanism. As can be
observed, when the frequency of load transient is low, the FTBB converter has more power loss
due to the extra conduction loss on switch S0. However, as load transient happens more
frequently, dynamic power consumption of the two converters becomes comparable. When the
frequency of load changes is higher than 4 kHz, the losses of the FTBB converter are smaller
75
77
79
81
83
85
87
89
91
93
95
0 0.5 1 1.5 2 2.5 3 3.5
Conventional Buck FTBB Converter
Eff
icie
ncy
(%)
Figure 3.31 Steady-state efficiency of the conventional single stage buck converter and the FTBB converter [138].
119
than that of the conventional buck converter, fully compensating for the losses of the extra
auxiliary elements. For a load changing frequency of 12.3 kHz, the FTBB converter achieves
7% reduction in power loss, thus 1.5% improvement in effective efficiency, compare to the buck
converter prototype. For PoL converters operating at higher switching frequencies and
undergoing more frequent load changes, it can be expected that this recycling mechanism can
provide even greater energy savings.
120
0.2
0.22
0.24
0.26
0.28
0.3
0.32
0.34
0.36
0.38
0.4
0.42
0 2000 4000 6000 8000 10000 12000
Conventional Buck FTBB Converter
Ave
rag
ed P
ow
er L
oss
(W)
Figure 3.32 Dynamic power consumption of the FTBB converter and the conventional single stage buck converter [138].
76
78
80
82
84
86
88
90
0 2000 4000 6000 8000 10000 12000
Conventional Buck FTBB Converter
Figure 3.33 Comparison of effective efficiency of the conventional buck and the FTBB converters under frequently changing load conditions [138].
121
3.6 Chapter Summary
To achieve fast and smooth load transient response, inductor current in a buck converter
needs to swiftly follow the changing load current. To overcome the current slew-rate limitations
of the conventional buck converter, a mixed-signal controlled buck converter with a flyback
transformer is introduced.
The proposed FTBB converter is implemented based on a modified buck output stage.
The power inductor is replaced by the primary winding of a flyback transformer, with
approximately the same magnetic core size as a conventional buck inductor. The secondary
winding of the transformer is connected to a set of auxiliary switches.
During heavy-to-light load transients the magnetizing current is steered back to the input
voltage source. In this way, the overcharging of the output capacitor is eliminated and the
voltage overshoot is drastically reduced. At the same time, the energy stored in the magnetic
component is recycled. Both of these improvements significantly reduce energy losses
associated with the transient operation. The transient switching sequence is performed such that
the maximum blocking voltage of all switching components in the circuit is no larger than the
input voltage. The combination of limited blocking voltage and energy recycling ability makes
the FTBB converter well-suited for PoL applications. With a frequently changing load, the
losses caused by the additional switches can be partially or fully compensated. During light-to-
heavy load transients the equivalent inductance, seen at the transformer primary winding, is
reduced to its leakage inductance value, allowing a significant increase in the current slew rate.
The operation of the FTBB converter is governed by a modified mixed-signal current
programmed mode (CPM) controller that provides minimum voltage deviation and seamless
transitions between the modes. The smooth transition between steady state and transient modes
is achieved through a simple transient current estimation, based on the analysis of the difference
between the output voltage error samples.
The effectiveness of the FTBB concept is verified through a 6 V to 1 V, 3 W prototype
converter and comparison with an equivalent buck converter. Experimental results show about
67% reduction in peak voltage deviation for heavy-to-light load transient and 25% reduction for
122
light-to-heavy load transient compared to the minimum-deviation controlled buck converter.
The footprint of the flyback transformer is comparable to that of a conventional buck inductor
with the same current rating. The proposed FTBB converter has half the size of inductive
component and drastic improvement in transient performance compared to the buck converter
with an auxiliary stage [128] discussed in Chapter 2.
Study also shows that the flyback transformer allows the FTBB converter to recycle
energy during heavy-to-light load transients. As a result, under frequent load current changes,
the FTBB converter induces less average power loss compare to the conventional buck
converter, thus improved dynamic power conversion efficiency.
The main factors that limit the switching frequency of the experimental prototype are the
delays of discrete components. These include the delays of the current sensing circuits, analog-
to-digital converter, and the FPGA system. Possible on-chip implementation of this system
would allow operation at much higher switching frequency and minimize delay effects. It could
be based on the architectural solutions presented in [126] demonstrating an on-chip integrated 10
MHz buck converter regulated by a mixed-signal CPM controller.
123
Chapter 4Chapter 4Chapter 4Chapter 4
ConclusionsConclusionsConclusionsConclusions and Future Workand Future Workand Future Workand Future Work
Modern switch-mode power supplies (SMPS) used for point-of-load (PoL) applications
need to meet increasingly stringent requirements on voltage regulation. VLSI manufacturers
typically impose tight tolerance on the supply voltage to ensure proper performance [1][129]-
[131]. To satisfy these, SMPS are usually required to have small output voltage deviation during
load transients. The preference for high conversion efficiency and small physical volume makes
the design of SMPS even more challenging.
4.1 Contributions
Fast and smooth load transient response in a buck-type PoL converter requires rapid
changes of inductor current following sudden load steps. In this thesis, two transient suppression
methods are explored aiming at breaking the bottleneck of inductor current slew rate in
conventional buck converters. The technical specs and limitations of the two methods are
compared with some representatives of the prior arts in TABLE 4.1. The single-stage minimum
deviation converter [72] is used as a comparison baseline.
In the first approach, a small auxiliary output stage is connected in parallel with the main
buck output stage. While the main output stage is responsible for steady-state operation and
designed to achieve optimum efficiency, the auxiliary stage is activated when a load transient
occurs, to help quickly sinking/sourcing current from/to the output capacitor. A digital controller
is designed to control both output stages. In steady state, the converter operates in digital voltage
control mode (VCM). When a load step is detected, transient recovery is performed with a
single on/off switching action governed by the capacitor charge balance principle [25]. The
digital controller predicts the new steady-state duty-cycle based on the magnitude of load current
124
step and applies it by the end of transient recovery process in order to achieve a seamless mode
transition.
Experimental result shows that the system reduces the peak voltage deviation during a
heavy-to-light load transient by 35% while maintaining similar steady-state efficiency when
comparing to a conventional single-stage time-optimal [25]-[26] controlled buck converter. It is
also proved that the dual output stage structure performs well with fully integrated output stages.
The auxiliary stage imposes less than 20% area over head, which is a much smaller area penalty
than previously published dual-output-stage converters [83]-[84].
TABLE 4.1. COMPARISON OF CONVERTER TOPOLOGY AND CONTROL METHODS
Converter Topology
Minimum Deviation Converter
[72]
FRDB converter [84]
Auxiliary phase with adaptive slope control
[87]
Dual output stage converter
in this work
FTBB converter in this work
Control Method Digital Analog Digital Digital Digital Theoretical
Current Slew Rate During
Transient
14 1+LM/LA 1+LM/LA 1+LM/LA 1+LM/LLEAK
Output Stage Implementation
Discrete Discrete Discrete Integrated Discrete
Number of Magnetic
Components
14 2 2 2 1
Output Capacitance1
14 LA/(LM+LA) LA/(LM+LA) LA/(LM+LA) LLEAK/(LM+LLEAK)
Efficiency 14 1 in steady state, degradation under frequent load transient
1 in steady state, under frequent load transient the efficiency is better than [84] and [87] due to less switching actions
0.98 in steady state2, 1.015 under frequent load transient3
Limitations Limited inductor current slew rate
Requires multiple switching actions during transient recovery, extra switching loss degrades efficiency
Minor improvement on light-to-heavy load transient recovery
Lower steady state efficiency due to extra conduction loss
Note 1: Assume the converters achieve the same amount of peak output voltage deviation under the same load current step, estimated based on (1.19)
Note 2: Obtained in experiment at 3.3 A load current
Note 3: Obtained in experiment with ±2 A periodic load current steps
Note 4: Normalized value to ease comparison
125
The dual output stage converter structure achieves a well-balanced steady-state power
conversion efficiency and dynamic performance. However, there exist two inherent issues:
Firstly, for converters using capacitor charge balance control during transient recovery,
the optimum current slew rates in the auxiliary inductor in order to suppress heavy-to-light and
light-to-heavy load transients are different [85]. As a result, suppression of both type of load
transients cannot be simultaneously achieved with one fixed auxiliary inductance. Alternative
control methods have been investigated by other researchers during the progress of this work
[86]-[88], where the effective current slew rate in the auxiliary inductor is adjusted by switching
the auxiliary switches at high frequency. These methods successfully suppresses both heavy-to-
light and light-to-heavy load transients, yet with the penalty of higher power consumption under
frequent load changes.
Secondly, as described in TABLE 4.1, a separate inductor is required for the auxiliary
output stage. It takes up extra PCB real estate and essentially doubles the volume of the
magnetic components. In some cases, the reduction in output capacitance achieved by boosting
the current slew rate via the auxiliary stage comes at the price of a noticeable increase in the total
volume of inductors. As a result, the overall volume of the converter is comparable or even
bigger than the conventional single stage buck converter, since buck inductors usually have a
much lower energy density compare to capacitors [132].
The second approach investigated in this thesis provides a solution to both
aforementioned issues. The conventional buck output stage is modified such that the buck
inductor is replaced by the primary winding of a compact flyback transformer. The secondary
winding of the transformer is then connected between the input power supply and the ground via
a set of small auxiliary switches. In steady state, the secondary winding is open circuited. The
converter operates as a conventional buck converter using peak current program mode (CPM)
control. During load transient recovery, the secondary winding and the auxiliary switches are
activated to boost the current slew rate in the primary winding, which greatly suppresses
transient voltage deviation and, in the meantime, achieves energy recycling through current
steering.
Experimental results on a discrete prototype converter shows about 67% reduction in
peak voltage deviation during heavy-to-light load transients and 25% reduction during light-to-
126
heavy load transients, compare to a conventional minimum-deviation controlled [72] buck
converter. Since the flyback transformer requires 1:1 turns ratio, it has simple structure and can
be implemented in a relatively small package. The size of flyback transformer used for the
prototype is comparable to that of a conventional buck inductor with the same current rating.
Thus the proposed architecture has half the size of magnetic component compared to the buck
converter with an auxiliary output stage.
Steady-state efficiency of the proposed flyback transformer based buck (FTBB) converter
is slightly lower than that of a conventional buck converter due to an extra switch in series with
the main power conduction path. However, the flyback transformer allows the converter to
recycle energy during heavy-to-light load transients. As verified by experiments, when load
transients happen frequently, the amount of recycled energy can partially or fully compensate for
the extra energy burnt on the auxiliary switches, resulting in higher effective efficiency compare
to the conventional buck converter. Thus the proposed FTBB converter is well-suited for PoL
application where frequent load changes are expected.
4.2 Future Work
4.2.1 Precise Load Step Estimation
For both the dual output stage converter introduced in Chapter 2 and the FTBB converter
introduced in Chapter 3, precise load step estimation is required to determine the new duty-cycle
(for the voltage mode controller in Chapter 2) or the new current command (for the current
program mode controller in Chapter 3) in order to achieve a seamless transition back to steady-
state operation.
In this work, load step estimation is accomplished by sensing the difference between two
output voltage samples over a fixed time period after the load transient occurs. The accuracy of
voltage sensing and current step estimation is inevitably limited by the resolution of the A/D
converter that samples the output voltage and variations in the output capacitance.
To improve sensing accuracy without using an expensive high-resolution A/D converter,
pre-amplification can be applied [25] to the error voltage, Vout(t)−VREF(t) before feeding it to the
A/D converter. On the other hand, to eliminate the influence of Cout variation on the accuracy of
127
current step estimation, the sensor-less self-calibration method described in [57] can be
employed, where a small known current step is injected to the output port of the converter in
order to test and tune the response of the controller. An alternate solution is to put a dedicated
sample-and-hold current sensor to sense the load current directly [125]. It results in the best
accuracy yet with a slightly higher price in hardware implementation.
4.2.2 Calibration Against Inductor Current Slew Rate
Variation
For the dual output stage converter introduced in Chapter 2, which utilizes the capacitor
charge balance principle, the on/off times of the main and auxiliary stages during transient
recovery are calculated in advance for each load current step, based on the assumption that the
current slew rates (k1~k3 in (2.4)) in the power stages are known constants. In practice, these
parameters tend to deviate from their respective theoretical values due to multiple aspects such as
parasitic components of PCB traces, variation of power stage inductance with different load
conditions, etc.
Due to the variations and non-idealities in output stage inductance, the control method
proposed in Chapter 2 inevitably subjects to accuracy uncertainty, which may result in non-
optimal transient recovery. A possible solution is presented in [87], where an on-line calibration
block is implemented to compensate for the inductance variation. The actual inductor current
slew rate is estimated by measuring the time ∆tcal needed for the current to change by a known
amount ∆ical. The on/off times for each power transistor is then recalculated and updated based
on the new current slew rate values.
4.2.3 Design for Integration: Sizing the Auxiliary
Switches
In the experimental prototype of the FTBB converter introduced in Chapter 3, the power
switches MS, SR and auxiliary switches S0 ~ S3 are implemented with the same type of NMOS
transistors. From a practical design point of view, it is preferred that the auxiliary switches to be
small so that the total volume of the output stage is not significantly larger than a conventional
buck converter. The PCB real estate occupied by the converter can be further reduced if all the
128
switches are integrated in the same package so that some of the PCB routing can be realized on
silicon to achieve miniaturization.
As discussed in Chapter 3, the FTBB converter is designed and controlled in such a way
that the maximum blocking voltage on all power switches are limited to the magnitude of input
voltage, Vin(t). As a result, the FTBB topology is well-suited for cost-effective integration. On
the other hand, shrinking the size of auxiliary switches inevitably results in higher on-resistance.
The sizing criteria of auxiliary switches and the effect that finite auxiliary switches' on-
resistances have on the transient performance of the converter can be found in Appendix B.
Another potential issue for a fully integrated implementation of the FTBB converter is
the presence of negative switching node voltage vx’ = − (Vin − Vout) during the current-steering
phase of a heavy-to-light load transient recovery (Figure 3.3). This negative voltage would cause
the source/drain to substrate junction of switch S0 in Figure 3.1 to become forward biased. This
problem could be solved if silicon-on-insulator (SOI) technology is available. However, cost
and thermal resistance issues would have to be considered. An alternative is to use a substrate
bias that is lower than vx’ , but this would introduce other non-ideal requirements such as an extra
negative bias voltage and power devices with breakdown voltage that is at least twice as high.
Another possible option to circumvent this issue is to implement switch S0 on a separate die.
This would allow both the separation of its substrate connection from the rest of the converter
and a cost-effective implementation in a low voltage process.
4.2.4 Integrated Controller
The transient suppression method proposed in this work can be expanded to a custom
designed IC.
The digital control logic implemented for the experimental prototypes is based on Verilog
HDL. For the FTBB converter, compilation result obtained using Altera Quartus II software
shows that the digital logic unit only consumes 1597 combinational logic elements and 267
registers. It can be easily synthesized and converted to on-chip implementation using automated
placement-and-route tools.
129
Research work has also been done on fully integrated mixed-signal controllers, where
low-power DAC and/or ADC are implemented [126][133]-[136]. The compact delay-line based
window ADC in [126] occupies a chip area as small as 0.0029mm2 in 0.13 µm process.
A challenge for on-chip implementation of the FTBB converter would be the requirement
for a relatively large number of current sensing circuits compared to the conventional buck
converter. Since not all current sensing circuits operate at the same time, a potential solution for
minimizing their number could be task-based multiplexing. In this case, the sensing circuits for
ip(t) and is(t) in Figure 3.24 would be replaced by sense FETs [137] in parallel with switch S0 and
S2, respectively.
130
ReferencesReferencesReferencesReferences [1] “International technology roadmap for semiconductors, 2010 update.”
http://www.itrs.net/reports.html.
[2] "PSMA power technology roadmap 2011 summary", https://ieeetv.ieee.org/conference-highlights/psma-power-technology-roadmap-2011-summary.
[3] Maxim, “Maxim app notes 280: power supplies for telecom systems”, Application note, 2000, http://www.maxim-ic.com/.
[4] F. C. Lee and Q. Li, "Survey of trends for integrated point-of-load converters", Int. Workshop on Power Supply on Chip, Sep. 2008, http://www.powersoc.org/PwrSOC08/presentations.html.
[5] Q. Li, M. Lim, J. Sun, A. Ball, Y. Ying, F. C. Lee, and K. D. T. Ngo, "Technology road map for high frequency integrated dc-dc converter", Proc. IEEE Applied Power Electronic Conf., Feb. 2010, pp. 533-539.
[6] A. Bindra, “It’s time to standardize point-of-load converters”, Power Electronics Technology, Aug. 2003, http://powerelectronics.com/mag/power_time_standardize_pointofload/.
[7] P. Greenland, "Developments in point of load regulation", White paper, Semtech Corporation, http://www.semtech.com/images/promo/Developments-in-Point-of-Load-Regulation.pdf.
[8] R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, 2nd ed. Springer, 2001.
[9] S. Deuty, "Optimizing transistor performance in synchronous rectifier buck converters", Proc. IEEE Applied Power Electronic Conf., Feb. 2000, Vol. 2, pp. 675-678.
[10] M. Gildersleeve, H. P. Forghani-zadeh, and G. A. Rincon-Mora, “A comprehensive power analysis and a highly efficient, mode-hopping dc-dc converter”, Proc. IEEE Asia-Pacific Conf. on ASIC, Aug. 2002, pp. 153-156.
[11] Fairchild, "AN-6005: Synchronous buck MOSFET loss calculations with Excel model", Application note, 2006, www.fairchildsemi.com/an/AN/AN-6005.pdf.
[12] “IRF7821PbF: HEXFET Power MOSFET”, Datasheet, International Rectifier, 2007, http://www.irf.com/.
[13] A. Stratakos, “High-efficiency, low-voltage dc–dc conversion for portable applications,” Ph.D. dissertation, Univ. California, Berkeley, 1999.
[14] V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, “Low-voltage swing monolithic dc–dc conversion,” IEEE Trans. Circuits Syst. II: Express Briefs, vol. 51, pp. 241–248, May 2004.
[15] M. Mulligan, B. Broach, and T. Lee, “A constant frequency method for improving light-load efficiency in synchronous buck converters,” Power Elec. Letters, vol. 3, pp. 24–29, March 2005.
131
[16] A. Parayandeh, A. Prodić, “Digitally controlled low-power dc-dc converter with segmented output stage and gate charge based instantaneous efficiency optimization”, Proc. IEEE Energy Conversion Congress and Expo., Sep 2009, pp 3870-3875.
[17] A. Parayandeh, B. Mahdavikkhah, S. M. Ahsanuzzaman, A. Radić, and A. Prodić, "A 10MHz mixed-signal CPM controlled dc-dc converter IC with novel gate swing circuit and instantaneous efficiency optimization", Proc. IEEE Energy Conversion Congress and Expo., Sep 2011, pp 1229-1235.
[18] W. Saito, T. Nitta, Y. Kakiuchi, Y. Saito, K. Tsuda, I. Omura, and M. Yamaguchi, "Suppression of dynamic on-resistance increase and gate charge measurements in high-voltage GaN-HEMTs with optimized field-plate structure", in IEEE Trans. Electron Devices, vol. 54, no. 8, pp. 1825-1830, Aug. 2007.
[19] M. Granato, "The GaN opportunity - higher performances and new challenges", Power Electronics Europe, 2011, no. 6, http://www.power-mag.com/pdf/feature_pdf/1319704820_National0611_Layout_1.pdf.
[20] A. Yoo, M. Chang, O. Trescases, and W. T. Ng, "High performance low-voltage power MOSFETs with hybrid waffle layout structure in a 0.25µ standard CMOS process", Proc. Int. Symp. Power Semiconductor Devices and ICs, May 2008, pp. 95-98.
[21] W. T. Ng, A. Yoo, "Advanced lateral power MOSFETs for power integrated circuits", Proc. IEEE Int. Conf. on Solid-State and Integrated Circuit Technology, Nov. 2010, pp 859-862.
[22] O. Trescases, "Integrated power supplies for portable applications", Ph.D. dissertation, Univ. Toronto, 2007.
[23] P.Y. Wu, and P.K.T. Mok, “A monolithic buck converter with near-optimum reference tracking response using adaptive-output-feedback”, IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2441-2450, Nov 2007.
[24] Z. Zhao, and A. Prodić, “Continuous-time digital controller for high-frequency dc-dc converters”, IEEE Trans. Power Electronics, vol. 23, no. 2, pp. 564-573, Mar. 2008.
[25] E. Meyer, Z. Zhang, and Y.-F. Liu, "An optimal control method for buck converters using a practical capacitor charge balance technique", IEEE Trans. Power Electronics, vol. 23, no. 4, pp. 1802-1812, Jul. 2008.
[26] V. Yousefzadeh, A. Babazadeh, B. Ramachandran, E. Alarcon, L. Pao, and D. Maksimović, “Proximate time-optimal digital control for synchronous buck dc-dc converters,” IEEE Trans. Power Electronics, vol. 23, pp. 2018–2026, Jul. 2008.
[27] “Power supply technical application note for altera’s FPGA”, Application note, Bellnix Co., http://www.bellnix.com/.
[28] “Power management considerations for FPGAs and ASICs”, Application note, Texas Instrument, 2007, http://www.ti.com/.
[29] B. C. Narveson, and A. Harris, “Power-management solutions for telecom systems improve performance, cost, and size”, Analog Application Journal, Texas Instrument, 2007, http://www.ti.com/.
[30] “LTM4602: 6A high efficiency dc/dc µmodule”, Datasheet, Linear Technology, 2007, http://www.linear.com/.
132
[31] “Power supplies go digital”, White paper, Ericsson, 2010, http://www.ericsson.com/.
[32] "Digital power management ICs: a global strategic business report", Global Industry Analysis, Inc., Apr. 2011, http://www.strategyr.com/Digital_Power_Management_ICs_Market_Report.asp.
[33] “FAN2108: TinyBuck, 3-24V input, 8A, high-efficiency, integrated synchronous buck regulator”, Datasheet, Fairchild Semiconductor, 2008, http://www.fairchildsemi.com/.
[34] “ISL8502: 2.5A synchronous buck regulator with integrated MOSFETs”, Datasheet, Intersil, 2008, http://www.intersil.com/cda/home/.
[35] “12V Pico TLynxTM 3A: non-isolated dc-dc power modules”, Datasheet, Lineage Power, 2010, http://www.lineagepower.com/.
[36] “Voltage regulator module (VRM) and enterprise voltage regulator-down (EVRD) 11.1 Design Guidelines”, Design guidelines, Intel, 2009, http://www.intel.com/.
[37] J. Formenti, R. Martinez, "Design trade-offs for switch-mode battery charger", Workbook, Texas Instrument, 2004, http://www.ti.com/lit/ml/slyp089/slyp089.pdf.
[38] D. Maksimović, "Digital control of power: a researcher's perspective", Plenary presentation, IEEE Applied Power Electronic Conf, Feb. 2007.
[39] W. Gu-Yeon and M. Horowitz, “A low power switching power supply for self-clocked systems,” Proc. Int. Symp. Low Power Electronics and Design, Aug. 1996, pp. 313-317.
[40] A.P. Dancy and A.P. Chandrakasan, “Ultra low power control circuits for PWM converters,” Proc. Power Electronic Specialist Conf., June 1997, pp. 21-27.
[41] B.J. Patella, A. Prodić, A. Zirger, and D. Maksimović, “High-frequency digital PWM controller IC for dc-dc converters,” IEEE Trans. Power Electronics, vol. 18, no. 1, pp. 438-446, Jan. 2003.
[42] S. Musuniri and P. Chapman, “Improvement of light load efficiency using width-switching scheme for CMOS transistors”, Power Electronics Letters, vol. 3, no. 3, pp. 105–110, Sep. 2005.
[43] O. Trescases, W.T. Ng, H. Nishio, M. Edo and T. Kawashima, “A digitally controlled dc-dc converter module with a segmented output stage for optimized efficiency,” Proc. Int. Symp. Power Semiconductor Devices and ICs, June 2006, pp. 373-376.
[44] H.-W. Huang, K.-H. Chen, and S.-Y. Kuo, "Dithering skip modulation, width and dead time controllers in highly efficient dc-dc converters for system-on-chip applications", IEEE Jour. Solid-State Circuits, vol. 42, no. 11, pp. 2451-2465, Nov. 2007.
[45] O. Trescases, G. Wei, A. Prodić, and W.T. Ng, “Predictive efficiency optimization for dc-dc converters with digital electronic loads”, IEEE Trans. Power Electronics, vol. 23, no. 4, pp. 1859-1869, Jul. 2008.
[46] V. Yousefzadeh, and D. Maksimović, “Sensorless optimization of dead-times in dc-dc converters with synchronous rectifiers,” IEEE Trans. Power Electronics, vol. 21, no.4, pp. 994-1002, Jul. 2006.
[47] A. V. Peterchev, and S. R. Sanders, "Digital multimode buck converter control with loss-minimizing synchronous rectifier adaptation", IEEE Trans. Power Electronics, vol. 21, no. 6, pp. 1588-1599, Nov. 2006.
133
[48] A. Pizzutelli, A. Carrera, M. Ghioni, and S. Saggini, "Digital dead time auto-tuning for maximum efficiency operation of isolated dc-dc converters", Proc. Power Electronic Specialist Conf., Jun. 2007, pp. 839-845.
[49] A. Zhao, A. A. Fomani, and W. T. Ng, "One-step digital dead-time correction for dc-dc converters", Proc. IEEE Applied Power Electronic Conf., Feb. 2010, pp. 132-137.
[50] A. Zhao, A. Shorten, H. Nishio, and W.T. Ng, "An integrated dc-dc converter with digital one-step dead-time correction", Int. Sym. Power Semiconductor Devices and ICs, Jun.. 2010, pp. 57-60.
[51] O. Trescases, G. Wei, A. Prodić, and W.T. Ng, “An EMI reduction technique for digitally controlled SMPS”, IEEE Trans. Power Electronics, vol. 22, no. 4, pp. 1560-1565, Jul. 2007.
[52] G. M. Dousoky, M. Shoyama, and T. Ninomiya, "FPGA-based spread-spectrum schemes for conducted-noise mitigation in dc-dc power converters: design, implementation and experimental investigation", IEEE Trans. Industrial Electronics, vol. 58, no. 2, pp 429-435, Feb. 2011.
[53] S. M. Ahsanuzzaman, A. Radić, and A. Prodić, "Adaptive switching frequency scaling digital controller for improving efficiency of battery powered dc-dc converters", Proc. IEEE Applied Power Electronic Conf., Mar. 2011, pp. 910-915.
[54] G. Garcea, S. Saggini. D. Zambotti, and M. Ghioni, "Digital auto-tuning system for inductor current sensing in VRM applications", IEEE Applied Power Electronic Conf., Mar. 2006, pp. 493-498.
[55] M. Shirazi, R. Zane, D. Maksimović, L. Corradini, and P. Mattavelli, “Autotuning techniques for digitally-controlled point-of-load converters with wide range of capacitive loads”, Proc. IEEE Applied Power Electronic Conf., Feb. 2007, pp. 14-20.
[56] Z. Zhao, A. Prodić, “Limit-cycle oscillations based auto-tuning system for digitally controlled dc-dc power supplies,” IEEE Trans. Power Electronics, vol. 24, no. 6, pp. 2211-2222, Nov. 2007.
[57] Z. Lukic, S. M. Ahasanuzzaman, Z. Zhao, A. Prodić, “Self-tuning sensorless digital current-mode controller with accurate current sharing for multi-phase dc-dc converters", Proc. IEEE Applied Power Electronic Conf., Feb. 2009, pp. 264-268.
[58] J. Morroni, R. Zane, and D. Maksimović, "Design and implementation of an adaptive tuning system based on desired phase margin for digitally controlled dc-dc converters", IEEE Trans. Power Electronics, vol. 24, no. 2, pp. 559-564, Feb. 2009.
[59] O. Trescases, Y. Wen, "A survey of light-load efficiency improvement techniques for low-power dc-dc converters", Proc. IEEE Int. Conf. Power Electronics and ECCE Asia, May 2011, pp. 326-333.
[60] D. Ma, and W. H. Ki, “Fast-transient PCCM switching converter with freewheel switching control”, IEEE Trans. Circuits and Systems II: Express Briefs, Vol. 54, no. 9, pp. 825-829, Sep. 2007.
[61] O. Abdel-Rahman, and I. Batarseh, “Dynamic PWM ramp signal to improve load transient in DCM and mode hoping operation”, Proc. IEEE Power Electronics Specialists Conf., Jun. 2007, pp. 2016-2022.
134
[62] V. Arikatla, J. A. Abu Qahouq, "An adaptive digital PID controller scheme for power converters", Proc. IEEE Energy Conversion Congress and Expo., Sep. 2010, pp. 223-227.
[63] V. Arikatla, J. A. Abu Qahouq, "Dynamic response improvement of power converter using an adaptive frequency control law", Proc. IEEE Energy Conversion Congress and Expo., Sep. 2011, pp. 2952-2956.
[64] A. Soto, P. Alou, and J. A. Cobos, “Non-linear digital control breaks bandwidth limitations, Proc. IEEE Applied Power Electronics Conf., Mar. 2006, pp. 724-730.
[65] J. Alico and A. Prodic, “Multiphase optimal response mixed-signal current-programmed mode controller,” Proc. IEEE Applied Power Electronic Conf., Feb. 2010, pp. 1113–1118.
[66] E. Meyer, Z. Zhang, and Y. Liu, "Digital charge balance controller to improve the loading/unloading transient response of buck converters," IEEE Trans. Power Electronics, vol.27, no.3, pp. 1314-1326, Mar. 2012.
[67] S. Kapat, and P. Krein, "Improved time optimal control of a buck converter based on capacitor current," IEEE Trans. Power Electronics, vol.27, no.3, pp.1444-1454, March 2012.
[68] A. Babazadeh, L. Corradini, and D. Maksimović, "Near time-optimal transient response in dc-dc buck convertes taking into account the inductor current limit", Proc. IEEE Energy Conversion Congress. and Expo., Sep. 2009, pp. 3328-3335.
[69] L. Corradini, A. Costabeber, P. Mattavelli, and S. Saggini, “Parameter-independent time-optimal digital control for point-of-load converters,” IEEE Trans. Power Electronics, vol. 24, pp. 2235–2248, Oct. 2009.
[70] A. Babazadeh, and D. Maksimović, " Hybrid digital adaptive control for fast transient response in synchronous buck dc-dc converters", IEEE Trans. Power Electronics, vol. 24, pp. 2625-2638, Nov. 2009.
[71] L. Corradini, A. Babazadeh, A. Bjeletic, and D. Maksimović, “Current-limited time-optimal response in digitally controlled dc-dc converters,” IEEE Trans. Power Electronics, vol. 25, pp. 2869–2880, Nov. 2010.
[72] A. Radic, Z. Lukic, A. Prodic, and R. de Nie, “Minimum deviation digital controller IC for single and two phase dc-dc switch-mode power supplies,” Proc. IEEE Applied Power Electronic Conf., Feb. 2010, pp. 1–6.
[73] A. Radić, and A. Prodić, "Buck converter with merged active charge-controlled capacitive attenuation," IEEE Trans. Power Electronics, vol.27, no.3, pp.1049-1054, March 2012.
[74] R. Redl, B. P. Erisman, and Z. Zansky, “Optimizing the load transient response of the buck converter”, in Proc. IEEE Applied Power Electronics Conf., pp. 170-176, vol. 1, Feb. 1998.
[75] A. V. Peterchev, and S. R. Sanders, “Low conversion ratio VRM design”, in Proc. IEEE Power Electronics Specialists Conf., pp. 1571-1575, vol. 4, Jun. 2002.
135
[76] A. Stupar, Z. Lukic, and A. Prodic, “Digitally-controlled steered-inductor buck converter for improving heavy-to-light load transient response”, Proc. IEEE Power Electronics Specialists Conf., Jun. 2008, pp. 3950-3954.
[77] S. M. Ahsanuzzaman, A. Parayandeh, A. Prodic, and D. Maksimović, "Load-interactive steered-inductor dc-dc converter with minimized output filter capacitance", Proc. IEEE Applied Power Electronic Conf., Feb. 2010, pp. 980-985.
[78] Z. Zhao, and A. Prodic, "A three-level buck converter and digital controller for improving load transient response", Proc. IEEE Applied Power Electronic Conf., Feb. 2010, pp. 1256-1260.
[79] L. Shi, M. Ferdowsi, and M.L. Crow, "Dynamic response improvement in a buck type converter using capacitor current feed forward control", Proc. IEEE Industrial Electronics Conf., Nov. 2010, pp. 445-450.
[80] H. L. Massie, "DC-to-DC converter with transient suppression", U. S. Patent 6 285 175 B1, Sep. 4, 2001.
[81] X. Wang, Q. Li, and I. Batarseh, "Transient response improvement in isolated dc-dc converter with current injection circuit", Proc. IEEE Applied Power Electronic Conf., Mar. 2005, vol. 2, pp. 706-710.
[82] W. J. Lambert, R. Ayyanar, and S. Chickamenahalli, "Fast load transient regulation of low-voltage converters with the low-voltage transient processor", IEEE Trans. Power Electronics, vol.24, no.7, pp. 1839-1854, Jul. 2009.
[83] O. Abdel-Rahman, and I. Batarseh, “Transient response improvement in dc-dc converters using output capacitor current for faster transient detection”, Proc. IEEE Power Electronics Specialists Conf., Jun. 2007, pp. 157-160.
[84] A. Barrado, A. Lazaro, R. Vazquez, V. Salas, and E. Olias, “The fast response double buck dc-dc converter (FRDB): operation and output filter influence”, IEEE Trans. Power Electronics, vol. 20, no. 6, pp. 1261-1270, Nov. 2005.
[85] Y. Wen, and O. Trescases, “Nonlinear control of current-mode buck converter with an optimally scaled auxiliary phase”, IEEE Int. Conf. Industrial Technology, Mar. 2010, pp. 783-788.
[86] Y. Wen, and O. Trescases, "DC-DC converter with digital adaptive slope control in auxiliary phase to achieve optimal transienet response", Proc. IEEE Applied Power Electronic Conf., Mar. 2011, pp. 331-337.
[87] Y. Wen, "DC-DC converter with improved dynamic response and efficiency using a calibrated auxiliary phase", M. A. Sc. thesis, Univ. Toronto, 2011.
[88] E. Meyer, Z. Zhang, and Y.-F. Liu, “Controlled auxiliary circuit to improve the un-loading transient response of buck converters,” IEEE Trans. Power Electronics, vol. 25, pp. 806–819, Apr. 2010.
[89] X. Wang, I. Batarseh, S. Chickamenahalli, and E. Standford, “Vr transient improvement at high slew rate load-active transient voltage compensator,” IEEE Trans. Power Electronics, vol. 22, pp. 1472–1479, Jul. 2007.
136
[90] P.-J. Liu, Y.-K. Lo, H.-J. Chiu, and Y.-J. Chen, "Dual-current pump module for transient improvement of step-down dc-dc converters", IEEE Trans. Power Electronics, vol. 24, pp. 985-990, Apr. 2009.
[91] P.-J. Liu, H.-J. Chiu, Y.-K. Lo, and Y.-J. Chen, “A fast transient recovery module for dc-dc converters,” IEEE Trans. Industrial Electronics, vol. 56, pp. 2522–2529, Jul. 2009.
[92] S. Kapat, and P. T. Krein, "Null resonse to a large signal transient in an augmented dc-dc converter: a geometric approach", Proc. IEEE Control and Modeling of Power Electronics Workshop, Jun. 2010, pp. 1-6.
[93] T. Senanayake, T. Ninomiya, and H. Tohya, "Fast-response load regulation of dc-dc converter by means of reactance switching", Proc. IEEE Power Electronis Specialist Conf., Jun. 2003, vol. 3, pp. 1157-1162.
[94] G. E. Pitel, and P. T. Krein, "Transient reduction of dc-dc converters via augmentation and geometric control", Proc. IEEE Power Electronis Specialist Conf., Jun. 2007, pp. 1652-1657.
[95] L. Amoroso, M. Donati, X. Zhou, and F.C. Lee, "Single shot transient suppressor (SSTS) for high current high slew rate microprocessor", Proc. IEEE Applied Power Electronic Conf., Mar. 1999, vol. 1, pp. 284-288.
[96] T. A. Jochum, M. M. Walters, C. E. Hawkes, and M. Harris, "DC-DC converter having dynamic regulator with current courcing and sinking means", U. S. Patent 5 926 384, Jul. 20, 1999.
[97] A. M. Wu and S. R. Sanders, "An active clamp circuit for voltage regulation module (VRM) applications," IEEE Trans. Power Electronics, vol. 16, no. 5, pp. 623-634, Sep. 2001.
[98] N. K. Poon, C. P. Li, and M. H. Pong, “A low cost dc-dc stepping inductance voltage regulator with fast transient loading response,” Proc. IEEE Applied Power Electronic Conf., Mar. 2001, vol. 1, pp. 268-272.
[99] X. Cao, and R. Oruganti, “Fast response control of stepping inductance voltage regulator module,” Proc. IEEE Power Electronis Specialist Conf., Jun. 2005, pp. 382–388.
[100] D. D.-C. Lu, J. Liu, F. Poon, and B. M. H. Pong, “A single phase voltage regulator module (VRM) with stepping inductance for fast transient response,” IEEE Trans. Power Electronics, vol. 22, pp. 417–424, Mar. 2007.
[101] Z. Moussaoui, "DC-DC converter having active transient response compensation circuit employing flyback inductor", U. S. Patent 6 903 914 B1, Jun. 7, 2005.
[102] K. Ng, "A digitally controlled dual output stage buck converter with transient suppression", M. A. Sc. thesis, Univ. Toronto, 2009.
[103] A. Prodić, D. Maksimović, "Design of a digital PID regulator based on look-up tables for control of high-frequency dc-dc converters", Proc. IEEE Workshop on Computers in Power Electronics, Jun. 2002, pp. 18-22.
[104] A. Peterchev, S. Sanders, "Quantization resolution and limit cycling in digitally controlled PWM converters", IEEE Trans. Power Electronics, vol. 18, no. 1, pp. 301-308, Jan. 2003.
137
[105] A. Prodić, D. Maksimović, and R. W. Erickson, "Design and implementation of a digital PWM controller for a high-frequency switching dc-dc power converter", Proc. IEEE Conf. Industrial Electronics, Nov. 2001, vol. 2, pp. 893-898.
[106] M. Elbuluk, G. Verghese, and J. Kassakian, "Sampled-data modeling and digital control of resonant converters", IEEE Trans. Power Electronics, vol. 3, no. 3, pp. 344-357, 1988.
[107] A. Prodić, "Digital control of switching converters: design and DSP/VLSI implementation", Ph.D. dissertation, Univ. Colorado at Boulder, 2003.
[108] A. Stupar, "Implementation of fast transient response digital converters for high frequency switch-mode power supplies", M. A. Sc. thesis, Univ. Toronto, 2008.
[109] E. Meyer, Y.-F. Liu, "A quick capacitor charge balance control method to achieve optimal dynamic response for buck converters", Proc. Power Electronic Specialist Conf., Jun. 2007, pp. 1549-1555.
[110] Z. Zhao, "Design and practical implementation of digital auto-tuning and fast-response controllers for low-power switch-mode power supplies", Ph.D. dissertation, Univ. Toronto, 2008.
[111] G. Feng, W. Eberle, and Y.-F. Liu, “A new digital control algorithm to achieve optimal dynamic performance in dc-to-dc converters”, Proc. Power Electronic Specialist Conf., Jun. 2005, pp. 2744-2749.
[112] G. Feng, E. Meyer and Y.-F. Liu, "High performance digital control algorithms for dc-dc converters based on the principle of capacitor charge balance", Proc. Power Electronic Specialist Conf., Jun. 2006, pp. 1740-1746.
[113] E. Meyer, G. Feng and Y.-F. Liu, "Novel digital controller improves dynamic response and simplifies design process of voltage regulator module", Proc. IEEE Applied Power Electronic Conf, Feb. 2007, pp. 1447-1453.
[114] Z. Lukić, S. M. Ahasanuzzaman, Z. Zhao, and A. Prodić, "Sensorless self-tuning digital CPM controller with multiple parameter estimation and thermal stress equalization", IEEE Trans. Power Electronnics, vol. 26, no. 12, pp. 3948–3963, Dec. 2011.
[115] C.-Y. Hsieh, Y.-C. Chuang, and K.-H Chen, “A novel precise step-shaped soft-start technique for integrated dc-dc converter”, Proc. IEEE. Int. Conf. Electronics, Circuits and Systems, Dec. 2007, pp. 771-774.
[116] J. Lu, X.-B. Wu, X.-Z. Shen, L. Qin, "On-chip soft-start cell for dc-dc converter", Proc. Int. Conf. Engineers and Computer Scientist, Mar. 2010, pp. 1193-1195.
[117] Y. Wen, O. Trescases, "Non-linear control of current-mode buck converter with an optimally scaled auxiliary phase", Proc. IEEE. Int. Conf. Industrial Technology, Mar. 2010, pp. 783-788.
[118] L.-Y. Zhao, and J.-R. Qian, "DC-DC power conversion and system design considerations for battery operated system", Texas Instrument Seminar, online at www.ti.com.
[119] S. Saggini and M. Ghioni, “An innovative digital control architecture for low-voltage high-current dc–dc converters with tight load regulation”, IEEE Trans. Power Electronnics, vol. 19, no. 1, pp. 210–218, Jan. 2004.
138
[120] O. Trescases, Z. Lukić, W.-T. Ng, and A. Prodić, "A low power mixed-signal current-mode dc–dc converter using a one-bit delta sigma DAC", Proc. IEEE Applied Power Electronic Conf., Mar. 2006, pp. 700–704.
[121] O. Trescases, A. Prodić, and W.-T. Ng, “Digitally controlled current-mode dc-dc converter IC”, IEEE Trans. Circuits and Systems I, vol. 58, no. 1, pp. 219–231, Jan. 2011.
[122] Powersim Inc., PSIM Version 7.1.2, 2008, computer software, available from http://www.powersimtech.com/.
[123] Würth Elektronik, “744873004: specification for release”, Power-choke WE-DD device datasheet, online at http://katalog.we-online.de/kataloge/eisos/media/pdf/744873004.pdf.
[124] A. Zhao, A. Shorten, H. Nishio, and W.T. Ng, "An integrated DC-DC converter with digital one-step dead-time correction", in Proc. Int. Sym. Power Semiconductor Devices and ICs, Jun. 2010, pp. 57-60.
[125] J. Alico, "Multiphase optimal response mixed-signal current program mode controller", M. A. Sc. thesis, Univ. Toronto, 2009.
[126] A. Parayandeh, O. Trescases, and A. Prodić, "10 MHz peak current mode dc-dc converter IC with calibrated current observer", Proc. IEEE Applied Power Electronic Conf., Mar. 2011, pp. 897-903.
[127] Würth Elektronik, “74456047: specification for release”, Power-choke WE-PD 4 device datasheet, online at http://katalog.we-online.de/kataloge/eisos/media/pdf/74456047.pdf.
[128] J. Wang, K. Ng, T. Kawashima, M. Sasaki, H. Nishio, A. Prodić and W.T. Ng "A digitally controlled integrated DC-DC converter with transient suppression," Proc. Int. Symp. Power Semiconductor Devices and ICs, June 2010, pp. 277-280.
[129] “DC and switching characteristics for Stratix V devices”, Device Handbook, Altera Corp., http://www.altera.com/literature/hb/stratix-v/stx5_53001.pdf.
[130] Xilinx Corporation, "Virtex 5 FPGA data sheet: dc and switching characteristics", Virtex 5 device data sheet ver. 5.3, http://www.xilinx.com/support/documentation/virtex-5.htm.
[131] National Semiconductor Corporation, "Power management considerations for FPGAs and ASICs", Application note, Power DesignerSM no. 102, http://www.national.com/assets/en/appnotes/PowerDesigner102_FPGAs.pdf.
[132] M. D. Seeman, V. W. Ng, H-P. Le, M. John, E. Alon, and S. R. Sanders, “A comparative analysis of switched-capacitor and inductor-based dc-dc conversion technologies”, Proc. IEEE Control and Modeling for Power Electronics Workshop, Jun. 2010, pp. 1-7.
[133] O. Trescases, Z. Lukic, W.T. Ng and A. Prodić, "A low-power mixed-signal current-mode dc-dc converter using a one-bit ∆Σ DAC", Proc. IEEE Applied Power Electronic Conf., Mar. 2006, pp. 700-704.
[134] O. Trescases, N. Rahman, A. Prodić and W.T. Ng, "A 1V buck converter IC with hybrid current-mode control and a charge-pump DAC", Proc. IEEE Power Electronis Specialist Conf., Jun. 2008, pp 1122-1128.
139
[135] A. Parayandeh, P. Chu, and A. Prodić, "Digitally controlled low-power dc-dc converter with instantaneous on-line efficiency optimization", Proc. IEEE Applied Power Electronic Conf., Feb. 2009, pp. 159-163.
[136] A. Parayandeh, A. Prodić, "Programmable analog-to-digital converter for low-power dc-dc SMPS", IEEE Trans. Power Electronics, vol. 23, no. 1, pp. 500-505, Jan. 2008.
[137] W. Yan, W. Li, and R. Liu, "A noise-shaped buck dc–dc converter with improved light-load efficiency and fast transient response," IEEE Trans. Power Electronics, vol.26, no.12, pp.3908-3924, Dec. 2011.
[138] ©2013 IEEE. Reprinted, with permission, from J. Wang, A. Prodić, and W.T. Ng, "Mixed-signal controlled flyback-transformer based buck converter with improved dynamic performance and transient energy recycling", IEEE Trans. Power Electronics, vol. 28, no. 2, pp. 970-984, Feb. 2013.
140
AppAppAppAppendiendiendiendix Ax Ax Ax A
A Practical CalcuA Practical CalcuA Practical CalcuA Practical Calculation of Auxiliary lation of Auxiliary lation of Auxiliary lation of Auxiliary
State On/Off TimesState On/Off TimesState On/Off TimesState On/Off Times
In the dual-output stage buck converter presented in Chapter 2, the recovery time (TR in
Figure 2.2) of the main stage is determined such that the main inductor current iLM(t) reaches the
new load current value by the end of TR. Meanwhile, the on/off time (ton and toff) of the auxiliary
k1
k2 k3
0
0
0
t
t
t
ton toff
0vout(t)-VREF
t
TR
iload(t)
iLM(t)
iLA(t)
∆iload
t0
∆iloadQ1
Q2Q2 = Q1
Figure A.1 Ideal waveforms of load current i load(t), main stage inductor current iLM(t), auxiliary stage inductor current iLA(t) and output voltage deviation vout(t)-VREF under a heavy-to-light load transient.
141
stage are calculated so that capacitor charge balance is achieved (Q2 = Q1 in Figure 2.2). In the
ideal case as shown in Figure 2.2 the three parameters can be expressed in terms of the
magnitude of load current step ∆i load and the slew-rates k1~k3 of inductor current, as explained in
Chapter 2.
1
loadR
iT
k
∆= (A1.1)
3
2 3 1 2( )on loadk
t ik k k k
= ∆+
(A1.2)
2
2 3 1 3( )off loadk
t ik k k k
= ∆+
(A1.3)
k1
k2 k3
0
0t
t
0t
iLM(t)
vout(t)
iLA(t)
VREF
iload(t) ∆iload
t0 t1
Iold
Inew
TR
ton+toff ∆ton+∆toff
Q3
Q4 = Q3
vout_t2 = Q3/Cout
Q1
Q2
Q2 = Q1
VTH
tsense
vsense
t2
Figure A.2 Waveforms of main stage inductor current iLM(t), auxiliary stage inductor current iLA(t) and output voltage deviation vout(t)-VREF under a heavy-to-light load transient, taking into account the transient detection and load estimation delays.
142
In a practical implementation, due to the extra time required for the control unit to detect
the load transient and estimate the magnitude of ∆i load, the amount of charge that needs to be
balanced through the auxiliary stage is larger than that of the ideal case. As shown in the heavy-
to-light load transient example in Figure A.2 after the load transient occurs at t0, the output
voltage rises due to excess charge injected by the main stage. At t = t1, the deviation of vout(t)
exceeds the threshold ∆VTH, and the converter enters transient suppression mode. Between time
t1 and t2, the converter takes samples of vout(t) to estimate ∆i load, and then activates the auxiliary
stage at t = t2. As a result, the total amount of charge injected from the main stage is increased
by Q3 compare to Figure 2.2. It can be seen that Q3 = ∆vout_t2×Cout, where ∆vout_t2 is the deviation
of output voltage at time t2.
In order to achieve charge balance, the on/off time of the auxiliary stage needs to be
increased by ∆ton and ∆toff compare to (A1.2) and (A1.3), respectively. And the new on/off time
can be calculated by letting Q1+Q3 = Q2+Q4, which results in the following expressions:
2_ 2on on load out tt t A i B v+ ∆ = ∆ + ∆ , (A1.4)
2
3( )off off on on
kt t t t
k+ ∆ = + ∆ . (A1.5)
Parameter A and B are constants determined by the output capacitance and slew-rates of inductor
current, as expressed below:
3
1 2 2 3( )
kA
k k k k=
+, (A1.6)
3
2 2 3
2
( )outk C
Bk k k
=+
. (A1.7)
In the experimental prototype implemented for this work, a simple approximation method
is used to simplify the on-the-fly calculations. It is assumed that the converter starts load step
estimation immediately after the deviation of vout(t) reaches ∆VTH, and the conversion delay of
the A/D can be neglected due to over-sampling. As a result, ∆vout_t2 in (A1.4) is replaced by
143
_ 2load sense
out t TH sense THout
i tv V v V
C
∆ ∆∆ = ∆ + ∆ = ∆ + . (A1.8)
Thus the digital representation of ton+∆ton and toff+∆toff can be calculated in advance for different
∆i load based on the knowledge of ∆VTH, Cout and ∆tsense as well as parameter A and B, and
programmed into look-up tables using ∆i load[n], the digital representation of ∆i load, as the index.
144
AppAppAppAppendiendiendiendix Bx Bx Bx B
Influence of the the Auxiliary Influence of the the Auxiliary Influence of the the Auxiliary Influence of the the Auxiliary
Switches' OnSwitches' OnSwitches' OnSwitches' On----resistance on the resistance on the resistance on the resistance on the
Transient Performance of the FlybackTransient Performance of the FlybackTransient Performance of the FlybackTransient Performance of the Flyback----
Transformer Based BucTransformer Based BucTransformer Based BucTransformer Based Buck Converterk Converterk Converterk Converter
In a practical implementation of the flyback transformer based buck (FTBB) converter, it
is preferred that the auxiliary switches to be small, which inevitably leads to non-zero on-
resistance. To better understand the sizing criteria of auxiliary switches, it is necessary to study
the effect that finite auxiliary switches' on-resistances have on the dynamic performance of the
converter.
Figure A.3 shows the equivalent circuit of the output stage when the converter is under a
heavy-to-light load transient recovery. The auxiliary switches S1 and S2 (Figure 3.1) are modeled
by their respective on-resistances, Ron1 and Ron2, in parallel with their body-diodes DS1 and DS2.
Magnetizing current iLM(t) circulates in the primary winding of the flyback transformer and
induces current iS2(t) flowing in the direction as shown. Assuming that the forward voltage drop
VD of diodes DS1 and DS2 are identical, the voltage across the secondary winding of the
transformer becomes
-
2 1,2
2 1 2 2 1,2
2 , ( )
( ) ( ), ( )
S S S
in D S on D
in S on on S on D
v v v
V V I t R V
V i t R R I t R V
+= −− − ⋅ >= − − ⋅ + ⋅ <
. (A2.1)
As a result, the negative voltage vP across the primary winding of the transformer has a larger
magnitude when compared to the case discussed in Chapter 3, which is equal to Vin. Higher vp
145
causes iLM(t) to drop at a higher slew rate than kH-L = –Vin/LM, which is the current slew rate when
S1 and S2 have zero on-resistance as in Chapter 3.
With a higher current slew rate, less time is needed for the magnetizing current iLM(t) to
reach the new load current level. Thus a small on-resistance from switches S1 and S2 actually
helps to reduce the voltage deviation during heavy-to-light load transients. However, as
explained in Section 3.4 of Chapter 3, higher on-resistance in S1 and S2 reduces the amount of
energy that can be recycled during the current steering phase of the load transient recovery,
which results in lower dynamic efficiency. What is more, since the maximum voltage across the
secondary winding of the transformer is clamped by the switches' body diodes of the switches,
further increase in Ron1 and Ron2 will not infinitely boost current slew rate but will cause extra
power losses in the auxiliary switches.
In case of a light-to-heavy load transient recovery, the influence of the on-resistances
mainly takes effect when the auxiliary switches S2 and S3 are turned on. The equivalent circuit
during this time period is as shown in Figure A.4. According to Section 3.1.3 of Chapter 3, the
primary current ip(t) ramps up very fast and becomes much higher than the magnetizing current
Figure A.3 Equivalent circuit during the current steering phase of a heavy-to-light load transient recovery with auxiliary switches' on-resistances included.
146
iLM(t). The equivalent current iwind_p(t) circulating in the flyback transformer can be solved from
a simple KCL equation
_ ( ) ( ) ( )wind p p LMi t i t i t= − . (A2.2)
This circulating current iwind_P(t) causes the current is(t) in the secondary winding of the
transformer to flow in the direction as indicated in Figure A.4. Thus the voltage drop vS across
the secondary winding of the transformer can be expressed as
2 3 2
3 2
( ) ( ), ( )
( ) , ( )s on on s on D
ss on D s on D
i t R R i t R Vv
i t R V i t R V
⋅ + ⋅ <= ⋅ + ⋅ >
. (A2.3)
Therefore, instead of having a virtual short circuit across the magnetizing inductor, LM is
now shorted by a virtual voltage source vp = vs. As a result, both current ip(t) and iLM(t) ramp up
with slew rates determined by (A2.4) and (A2.5), respectively.
- ( ) /L H in out p LEAKk V V v L= − − (A2.4)
Figure A.4 Equivalent circuit during light-to-heavy load transient recovery with auxiliary switches' on-resistance included.
147
/LM p Mk v L= (A2.5)
The virtual voltage source vp forces the magnetizing current iLM(t) to ramp up during the
time period when S2 and S3 are on, rather than staying constant as explained in Section 3.1.3 of
Chapter 3. Thus the total time needed for iLM(t) to catch up with the load current is reduced.
On the other hand, the existence of vp reduces the slew-rate of ip(t) when compared to
(3.3). To ensure successful transient suppression, kL-H must be greater than the maximum current
slew-rate kL-H_con for a conventional buck converter during light-to-heavy transient recovery, as
determined by (3.6). Meanwhile, ip(t) must ramp faster than iLM(t) to ensure the equivalent
circuit of Figure A.4 to be valid.
- - _L H L H conk k> (A2.6)
-L H LMk k> (A2.7)
Substitute the expressions of current slew rates into (A2.6) and (A2.7), the upper limit of
voltage vp can be found as
( )Mp in out
M LEAK
Lv V V
L L< −
+. (A2.8)
Let Ipeak be the maximum expected current iwind_p(t), the upper limit of the on-resistance
Ron3 of switch S3 can be derived as
31
( )1 /
in outon D
peak LEAK M
V VR V
I L L
−< ⋅ −+
. (A2.9)
_ maxin out
peak pulse loadLEAK
V VI t I
L
−≈ ⋅ + (A2.10)
The above analysis indicates that the FTBB converter can achieve fast transient response
with auxiliary switches that are much smaller than the main power transistors. However, as
smaller switch has higher on-resistance and thus more power loss during transient recovery, there
exists a trade-off between the chip area and dynamic efficiency of the converter.
148
AppAppAppAppendiendiendiendix x x x CCCC
List of PublicationsList of PublicationsList of PublicationsList of Publications
[1] J. Wang, A. Prodić, and W.T. Ng, "Mixed-signal controlled flyback-transformer based buck converter with improved dynamic performance and transient energy recycling", IEEE Trans. Power Electronics, vol. 28, no. 2, pp. 970-984, Feb. 2013.
[2] J. Wang, A. Prodić, and W.T. Ng, "Flyback transformer based transient suppression method for digitally controlled buck converters", Proc. IEEE Energy Conversion Congress and Expo., Sep. 2011, pp. 3354-3361.
[3] J. Wang, W.T. Ng, and O. Trescases, "Versatile capabilities of digitally controlled integrated DC-DC converters", Proc. IEEE Int. Symp. Circuits and Systems, May 2011, pp. 293-296.
[4] J. Wang, K. Ng, T. Kawashima, M. Sasaki, H. Nishio, A. Prodić and W.T. Ng "A digitally controlled integrated DC-DC converter with transient suppression," Proc. Int. Symp. Power Semiconductor Devices and ICs, June 2010, pp. 277-280.
[5] J. Wang, K. Ng, T. Kawashima, M. Sasaki, H. Nishio, A. Prodić and W.T. Ng, “Integrated DC-DC converter with an auxiliary output stage for transient suppression", Proc. IEEE Electron Devices and Solid-State Circuits, Nov. 2009, pp. 380-383.
PatentPatentPatentPatent [1] W. T. Ng, J. Wang, K. Ng, H. Nishio, M. Sasaki, T. Kawashima, “Digitally controlled
integrated DC-DC converter with transient suppression”, University Of Toronto, U.S. Patent 20110298439, Dec.2011.
