Implementing RISC-V Processor in Hardware · MIT 6.004 Fall 2019 Implementing RISC-V Processor in Hardware October 24, 2019 L14-1

MIT 6.004 Fall 2019

Implementing RISC-V Processor in Hardware

October 24, 2019 L14-1

MIT 6.004 Fall 2019

The von Neumann Model

§ Almost all modern computers are based on the von Neumann model (John von Neumann, 1945)

§ Components:

§ Main memory holds programs and their data§ Central processing unit accesses and processes memory

values§ Input/output devices to communicate with the outside

world

CentralProcessing

Unit

MainMemory

Input/Output

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MIT 6.004 Fall 2019

Key Idea: Stored-Program Computer

§ Express program as a sequence of coded instructions§ Memory holds both data and instructions§ CPU fetches, interprets, and executes successive

instructions of the program

CentralProcessing

Unit

instructioninstructioninstruction

datadatadata

Main Memory

op rd rs rt

rd

MIT 6.004 Fall 2019

registers

operations

Anatomy of a von Neumann Computer

ControlUnitDatapathInt

erna

l st

orag

e

Main Memory

control

status

instructionsdata

…

dest

asel

fn

bsel

CCsALU

PC 1101000111011

• Instructions coded as binary data

• Program Counter or PC: Address of the instruction to be executed

• Logic to translate instructions into control signals for datapath

R1 ←R2+R3

addressaddress

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MIT 6.004 Fall 2019

Instructions§ Instructions are the fundamental unit of work

Fetch instruction

Decode instruction

Read src operands

Execute

Write dst operand

Compute next PC

§ Each instruction specifies:§ An operation or opcode to be

performed§ Source operands and destination

for the result§ In a von Neumann machine,

instructions are executed sequentially§ CPU logically implements this loop:§ By default, the next PC is current

PC + size of current instructionunless the instruction says otherwise

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MIT 6.004 Fall 2019

Approach: Incremental Featurism

We’ll implement datapaths for each instruction class individually, and merge them (using MUXes, etc)

Steps:1. ALU instructions

2. Load & store instructions

3. Branch & jump instructions

DataMemory

WD

A

RD

R/W

InstructionMemory

A

D

Memories

Component Repertoire:

Registers

0 1 Muxes

ALUA B “Black box” ALU

RegisterFile

(3-port)

RA1 RA2

WA

WE

WD

RD1 RD2

Register File

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MIT 6.004 Fall 2019 L14-7October 24, 2019

DQ

1 0 s

Q

D

EN

clk

Multi-Ported Register File

RegisterFile

(3-port)

RA1 RA2

WA

WE

WD

RD1 RD2

5

32

CLK

Write Enable

Write Address

Write Data

(independent Read addresses)

(Independent Read Data)

32 32

2 combinational READ ports*,1 clocked WRITE port

*internal logic ensures Reg[0] reads as 0

5 5

…

WA

RA1 RA2

ENCLK

ENCLK

ENCLK

ENCLK

clk

ReadPort 1

ReadPort 2

Write Port

Load-enabled register


Register File Timing

CLK

WE

WA

WD

RA

RD

A

Reg[A]

A

new Reg[A]

2 combinational READ ports, 1 clocked WRITE port

What if WA=RA1?RD1 reads “old” value of Reg[RA1] until next clock edge!

new Reg[A]

ts th

tPD tPD

Write enable

Write address

Write data

Read address

Read data

MIT 6.004 Fall 2019

Memory Timing

§ For now (lab 6), we will assume that our memories behave just like our register file in terms of timing.§ Loads are combinational – data is returned in the same

clock cycle as load request.§ Stores are clocked§ In lab 6, you will see the memory module referred to as a

magic memory since its not really realistic.

§ Next week we will learn about various different memory models and their tradeoffs.

§ In the design project, we will use realistic memories for our processor.

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MIT 6.004 Fall 2019

ALU Instructions

§ What RISC-V instruction is represented by these 32 bits?

§ Reference manual specifies the fields as follows:§ opcode = 0110011 § funct3 = 000§ funct7 = 0000000§ rd = 00011§ rs1 = 00010§ rs2 = 00001

=> opCode Op, R-type encoding=> ADD

=> x3=> x2

opcode

00000000000100010000000110110011

rs1rs2

funct3funct7

rd

=> x1

ADD x3, x2, x1

October 24, 2019 L14-10


Instruction Fetch/Decode

INSTRUCTIONWORDFIELDS

+4

InstructionMemory

A

D

Control Logic

CONTROL SIGNALS

PC 00

Opcode: Inst[6:0]Funct3: Inst[14:12]Funct7: Inst[31:25]

• Use PC as memory address

• Add 4 to PC, load new value at end of cycle

• Fetch instruction from memory

• Decode instruction:• Use some instruction

fields directly (register numbers, immediate values)

• Use opcode, funct3, and funct7 bits to generate control signals

32

32

32

Use a counter to FETCH the next instruction: PROGRAM COUNTER (PC)

01

Reset

RESET

Inst[31:0]rd: Inst[11:7]

rs1: Inst[19:15]

rs2: Inst[20:24]

MIT 6.004 Fall 2019

ALU InstructionsDiffer only in the ALU op to be performedInstruction Description Execution

ADD rd, rs1, rs2 Add reg[rd]


+4

Register-Register ALU Datapath

RegisterFile

RA1 RA2

RD1 RD2WA WD

WE

rd: Inst[11:7]

rs2: Inst[24:20]rs1: Inst[19:15]

Control Logic

AluFunc

ALUA B

AluFunc

32 32

32

Inst[31:0]


Opcode => Itype0110011 => Op type

Reg-Reg ALU

WERF

InstructionMemory

A

D

funct3, Inst[30] => AluFuncInst[30]: Add/SubInst[30]: Srl/Sra

funct7 rs2 rs1 f3 rd 011001131 2524 20 15 1119 14 12 67 0

PC 00

WERF

Op type: Reg[rd] ß Reg[rs1] op Reg[rs2]


+4

Register-Register ALU Datapath

RegisterFile

RA1 RA2

RD1 RD2WA WD

WE

rd: Inst[11:7]

rs2: Inst[24:20]rs1: Inst[19:15]

Control Logic

AluFunc

ALUA B

AluFunc

32 32

32

Inst[31:0]


WERF

InstructionMemory

A

D

funct7 rs2 rs1 f3 rd 011001131 2524 20 15 1119 14 12 67 0

PC 00Op type: Reg[rd] ß Reg[rs1] op Reg[rs2]

AluFunc

1

WERF

MIT 6.004 Fall 2019

ALU Instructions with one Immediate operandInstruction Description Execution

ADDI rd, rs1, immI Add Immediate reg[rd]


+4

Register-Immediate ALU Datapath

RegisterFile

RA1 RA2

RD1 RD2WA WD

WE

rd: Inst[11:7]

rs2: Inst[24:20]rs1: Inst[19:15]

Control Logic

AluFunc

ALUA B

AluFunc

32 32

32

Inst[31:0]


WERF

InstructionMemory

A

D

PC 00

imm[11:0] rs1 f3 rd 001001131 20 15 1119 14 12 67 0

funct3, Inst[30] => AluFuncInst[30]: Srli/Srai

Opcode => Itype0010011 => OpImm type

Reg-Imm ALU

Reg[rd] ß Reg[rs1] shift_op (imm[4:0])Op Imm type: Reg[rd] ß Reg[rs1] op SXT(imm[11:0])

WERF


+4


RegisterFile

RA1 RA2

RD1 RD2WA WD

WE

rd: Inst[11:7]

rs2: Inst[24:20]rs1: Inst[19:15]

Control Logic

AluFunc

ALUA B

AluFunc

32

32

Inst[31:0]


WERF

InstructionMemory

A

D

PC 00

imm[11:0] rs1 f3 rd 001001131 20 15 1119 14 12 67 0

Reg[rd] ß Reg[rs1] shift_op (imm[4:0])

BSEL

Op Imm type: Reg[rd] ß Reg[rs1] op SXT(imm[11:0])

BSEL01

SXT(Inst[31:20])32

WERF


+4


RegisterFile

RA1 RA2

RD1 RD2WA WD

WE

rd: Inst[11:7]

rs2: Inst[24:20]rs1: Inst[19:15]

Control Logic

AluFunc

ALUA B

AluFunc

32

32

Inst[31:0]


WERF

InstructionMemory

A

D

PC 00

imm[11:0] rs1 f3 rd 001001131 20 15 1119 14 12 67 0

Reg[rd] ß Reg[rs1] shift_op (imm[4:0])

BSEL

Op Imm type: Reg[rd] ß Reg[rs1] op SXT(imm[11:0])

AluFunc

1

WERF

BSEL01

SXT(Inst[31:20])32

1

MIT 6.004 Fall 2019

Load and Store InstructionsInstruction Description Execution

LW rd, immI(rs1) Load Word reg[rd]


+4

Load Instruction

RegisterFile

RA1 RA2

RD1 RD2WA WD

WE

rd: Inst[11:7]

rs2: Inst[24:20]rs1: Inst[19:15]

Control Logic

AluFunc

AluFunc

32

32

ALUA B

Inst[31:0]


WERF

InstructionMemory

A

D

PC 00

imm[11:0] rs1 010 rd 000001131 20 15 1119 14 12 67 0

BSEL

Load: Reg[rd] ß Mem[Reg[rs1] + SXT(imm[11:0])

WERF

Data MemoryRD

WD R/W

Adr

MWR

WDSEL0 1 2

32

32MWR

WDSEL

0000011 => lw

AluFunc = Addi

BSEL01

SXT(Inst[31:20])32


+4

Load Instruction

RegisterFile

RA1 RA2

RD1 RD2WA WD

WE

rd: Inst[11:7]

rs2: Inst[24:20]rs1: Inst[19:15]

Control Logic

AluFunc

AluFunc

32

32

ALUA B

Inst[31:0]


WERF

InstructionMemory

A

D

PC 00

imm[11:0] rs1 010 rd 000001131 20 15 1119 14 12 67 0

BSEL

WERF

Data MemoryRD

WD R/W

Adr

MWR

WDSEL0 1 2

32

32MWR

WDSEL

R

A+B

2

1

Load: Reg[rd] ß Mem[Reg[rs1] + SXT(imm[11:0])

BSEL01

SXT(Inst[31:20])32

1


+4

Store Instruction

RegisterFile

RA1 RA2

RD1 RD2WA WD

WE

rd: Inst[11:7]

rs2: Inst[24:20]rs1: Inst[19:15]

Control Logic

AluFunc

32

32

ALUA B

Inst[31:0]


WERF

InstructionMemory

A

D

PC 00

imm[11:5] rs2 rs1 010 imm[4:0] 010001131 20 15 1119 14 12 67 0

Store: Mem[Reg[rs1] + SXT(imm[11:0]) ß Reg[rs2]immS

Data MemoryRD

WD R/W

Adr

MWR

WDSEL0 1 2

32

32

AluFunc

BSEL

WERF

WDSEL

MWR

2524

AluFunc = Addi

0100011 => sw

321 BSEL01

SXT(Inst[31:20])32

SXT({Inst[31:25],Inst[11:7])}

2


+4

Store Instruction

RegisterFile

RA1 RA2

RD1 RD2WA WD

WE

rd: Inst[11:7]

rs2: Inst[24:20]rs1: Inst[19:15]

Control Logic

AluFunc

32

32

ALUA B

Inst[31:0]


WERF

InstructionMemory

A

D

PC 00

imm[11:5] rs2 rs1 010 imm[4:0] 010001131 20 15 1119 14 12 67 0

Store: Mem[Reg[rs1] + SXT(imm[11:0]) ß Reg[rs2]immS

Data MemoryRD

WD R/W

Adr

MWR

WDSEL0 1 2

32

32

AluFunc

BSEL

WERF

WDSEL

MWR

2524

W

A+B

32

0

--

BSEL01

SXT(Inst[31:20])32

SXT({Inst[31:25],Inst[11:7])}

2 2

MIT 6.004 Fall 2019

Branch Instructionsdiffer only in the aluBr operation they perform Instruction Description Execution

BEQ rs1, rs2, immB Branch = pc

MIT 6.004 Fall 2019

ALU for Branch Comparisons

func- GT, LT, EQ, ...

branch

ba

ALU Br

Like ALU but returns a Bool

AluFunc

32

ALUA B

ALU BrBrFuncbranch

October 24, 2019 L14-25


+4

Branch Instructions

RegisterFile

RA1 RA2

RD1 RD2WA WD

WE

rd: Inst[11:7]

rs2: Inst[24:20]rs1: Inst[19:15]

Control Logic

AluFunc

32

32

ALUA B

Inst[31:0]


WERF

InstructionMemory

A

D

PC 00

imm[12|10:5] rs2 rs1 f3 i[4:1|11] 110001131 20 15 1119 14 12 67 0

Branch: branch = (Reg[rs1] brFunc Reg[rs2])

immB = SXT({imm[12:1],1’b0})

pc Branch type

ALU BrBrFuncbranch

+ immB32

brTarget

PCSEL 01234

branch

PCSEL

immS

2 BSEL01

immI32

2

0

MIT 6.004 Fall 2019

Remaining InstructionsInstruction Description Execution

JAL rd, immJ Jump and Link

reg[rd]


+4

Jalr Instruction

RegisterFile

RA1 RA2

RD1 RD2WA WD

WE

rd: Inst[11:7]

rs2: Inst[24:20]rs1: Inst[19:15]

Control Logic

AluFunc

32

32

ALUA B

Inst[31:0]


WERF

InstructionMemory

A

D

PC 00Jalr: immI = SXT(imm[11:0])

Reg[rd] ß pc + 4

pc ß {(Reg[rs1] + immI)[31:1],1’b0}

Data MemoryRD

WD R/W

Adr

MWR

WDSEL0 1 2

32

32

AluFunc

BSEL

WERF

WDSEL

MWR

32

1100111 => Jalr type

ALU BrBrFuncbranch

+ immB32

brTarget

PCSEL 01234

branch

PCSEL

imm[11:0] rs1 000 rd 110011131 20 15 1119 14 12 67 0

32

PC+4

JT

JT[31:1],1’b0

immS

2 BSEL01

immI32

2


+4

Jalr Instruction

RegisterFile

RA1 RA2

RD1 RD2WA WD

WE

rd: Inst[11:7]

rs2: Inst[24:20]rs1: Inst[19:15]

Control Logic

AluFunc

32

32

ALUA B

Inst[31:0]


WERF

InstructionMemory

A

D

PC 00Jalr: immI = SXT(imm[11:0])

Reg[rd] ß pc + 4

pc ß {(Reg[rs1] + immI)[31:1],1’b0}

Data MemoryRD

WD R/W

Adr

MWR

WDSEL0 1 2

32

32

AluFunc

BSEL

WERF

WDSEL

MWR

32

ALU BrBrFuncbranch

+ immB32

brTarget

PCSEL 01234

branch

PCSEL

imm[11:0] rs1 000 rd 110011131 20 15 1119 14 12 67 0

32

PC+4

JT

JT[31:1],1’b0

0

1

2

immS

2 BSEL01

immI32

2

1

MIT 6.004 Fall 2019

Single-Cycle RISC-V Processor

InstMemory

Decode

Register File

DataMemory

PC

2 read & 1 write ports

separate Instruction &

Data memories

Execute

pc

rs1rs2

Reg[rs1]Reg[rs2]nextPc

Decode_inst

rd wr_data

instrpc addr

data Mem[addr]

October 24, 2019 L14-30

MIT 6.004 Fall 2019

Instruction decoder§ We need a function to extract the instruction

type and the various fields for each type from a 32-bit instruction

§ Fields we have identified so far are:§ Instruction type: OP, OPIMM, BRANCH, JAL, JALR,

LUI, LOAD, STORE, Unsupported§ Function for alu: aluFunc§ Function for brAlu: brFunc§ Register fields: rd, rs1, rs2§ Immediate constants: immI(12), immB(12),

immJ(20), immU(20), immS(12) but each is used as a 32-bit value with proper sign extension

Notice that no instruction has all the fields

October 24, 2019 L14-31

MIT 6.004 Fall 2019

Execute Function

§ Inputs:§ Values read from register file§ Decoded instruction fields§ PC

§ Logic:§ ALU§ BrALU§ NextPC generation

§ Outputs:§ Destination register§ Data to write to register file or memory§ Address for load and store operations§ NextPC

October 24, 2019 L14-32

MIT 6.004 Fall 2019

Is that all there is to building a

processor???

No.You’ve gotta print up all those little“RISC-V Inside”

stickers.

RISC-V Inside

October 24, 2019 L14-33

Documents

Implementing RISC-V Processor in Hardware · MIT 6.004 Fall 2019 Implementing RISC-V Processor in Hardware October 24, 2019 L14-1