INSTRUCTION SET ARCHITECTURE - ULisboa · Instruction Set Architecture (ISA) Machine vs Assembly code An instruction in machine code generally corresponds to a set of bits that can

INSTRUCTION SET

ARCHITECTURE Slides by: Pedro Tomás Additional reading: Computer Architecture: A Quantitative Approach”, 5th edition, Appendix A, John L. Hennessy and David A. Patterson, Morgan Kaufmann, 2011

ADVANCED COMPUTER ARCHITECTURES ARQUITECTURAS AVANÇADAS DE COMPUTADORES (AAC)

Advanced Computer Architectures, 2013

Outline

Instruction Set Architecture (ISA)

Classes of ISA

RISC vs CISC architectures

Memory addressing modes and data organization

Typical set of instructions

2



Machine vs Assembly code

An instruction in machine code generally corresponds to

a set of bits that can be generally structured as:

OPCODE – Identification of the operation

OPERANDS – Set of source and/or destination operands

MODE (optional) – Addressing mode of the operation

CONDITION (optional) – Instruction execution condition

The same operation can be represented in assembly

code as:

<Mnemonic> <operand listing>

OPCODE MODE CONDITION OPERANDS

3



CLASSES 4

Instructions can be divided into the following classes:

1. Stack

2. Accumulator

3. Register-Memory

4. Register-Register / Load-Store

Modern architectures typically support multiple classes of

ISAs

Further details…


Instruction Set Architecture (ISA) Classes

STACK 5

Stack architectures typically have no explicit operands, since operation on the stack is implicit

There are two basic operations:

PUSH into the stack

POP out of the stack

Operations on the stack require:

1. POP operands

2. Compute operation

3. PUSH result

SPStack Pointer

(1) – Empty Stack

ASP

Stack Pointer

A

(2) – After pushing a value into the stack

PUSH

AB

SPStack Pointer

B

(3) – After pushing another value into the stack

PUSH

A+BSP

Stack Pointer

(4) – After an addition operation

ADD

ALU

SPStack Pointer

(5) – After taking a value from the stack

POP

A+B



ACCUMULATOR 6

ALU

ACC

OperationSelect

X2

Memory

X1

(1) – Acummulator-based architecture

ALU

13ACC

LOAD

X2

13

-5

Memory

X1

(2) – After loading a value to the accumulatorLOAD A

ALU

8ACC

ADD

X2

13

-5

Memory

X1

(3) – After adding a value with the accumulatorADD B

ALU

8ACC

X2

13

-5

8

Memory

X1

(4) – Storing the result back into memorySTORE C

ABC

ABC

ABC

Architectures based

on an accumulator

typically have:

An implicit operand,

the accumulator

(ACC)

An explicit operand,

which can be an

immediate (constant

value) or a memory

address

The destination

operand is typically

the accumulator



REGISTER-MEMORY 7

Register-memory ISAs:

Typically have two operands,

where one is a register and the

other a memory address

May allow multiple addressing

modes:

Immediate

Register

Direct

Register indirect

Indexed

Implicit

(next slides…)

Example:

MOV Ra,A ; Ra M[A]

ADD Ra,B ; Ra Ra + M[B]

MOV C,Ra ; M[C] Ra

ALU

OperationSelect

X2

Memory

X1

Register memory architecture

Registers



REGISTER-REGISTER / LOAD-STORE 8

Register-register (also known

as load/store) ISAs:

Typically have one destination

operand plus two source

operands

All operands are registers

Access to the memory is

available only through LOAD or

STORE instructions

Require additional general-use

registers

Leads to longer programs and

larger memory sizes

Example:

LD Ra,A ; Ra M[A]

LD Rb,B ; Rb M[B]

ADD Rc,Ra,Rb ; Rc Ra + Rb

ST C,Rc ; M[C] Rc

ALU

OperationSelect

X2

Memory

X1

Register-register / Load-Store architecture

RegistersLOAD

STORE



RISC vs CISC 9

Based on a register-register /

load store class of ISA

Lower number of instructions

and addressing modes

Fixed-size (#bits) instructions

Instructions can be executed in

a single clock cycle

Higher instruction throughput

Can support multiple classes of ISAs, including stack, register-memory and register-register

Higher number of instructions and addressing modes

Variable-size (#bits) instructions

Reduces the required length of Assembly code

Modern CISC processors (e.g., Intel) operate as RISC by performing

real-time translation from CISC to a reduced set of micro-operations


Instruction addressing modes

Depending on the architecture implementation, some addressing modes may required the use of additional

special-purpose register. In this example, the auto-increment, auto-decrement and scaled addressing

modes require the use of an additional register to store the value d.

10

Mode Example Meaning

REGISTER ADD R4,R3 r[4] r[4] + r[3]

IMMEDIATE ADD R4,#3 r[4] r[4] + 3

DIRECT ADD R4,(1001) r[4] r[4] + M[ 1001 ]

REGISTER INDIRECT ADD R4,(R3) r[4] r[4] + M[ r[3] ]

DISPLACEMENT ADD R4,100(R3) r[4] r[4] + M[ 100 + r[3] ]

INDEXED ADD R4,(R1+R3) r[4] r[4] + M[ r[1] + r[3] ]

MEMORY INDIRECT ADD R4,@(R3) r[4] r[4] + M[ M[ r[3] ] ]

AUTO-INCREMENT ADD R4,(R3)+ r[4] r[4] + M[ r[3] ]

r[3] r[3] + d

AUTO-DECREMENT ADD R4,-(R3) r[3] r[3] - d

r[4] r[4] + M[ r[3] ]

SCALED ADD R4,100(R2)[R3] R[4] R[4] + M[ 100 + r[2] + r[3]*d]


Miss-alignments in memory access

11

When the addressed object is longer (in #bits) than the memory

width miss-alignments can occur

Consider the typical memory

organization where each memory

address stores an 8-bit object

Accessing a single byte never

generates a miss-alignment

8002h

Memory

8003h

8001h

8000h

8004h

8006h

8005h

8008h

8007h

Aligned

Aligned

8-bits

8-bits



12



A miss-aligned memory access may require two clock cycles to

complete (depends on the processor word width)




Accessing a half-word (2 bytes)

generates a miss-alignment whenever

the address is not even (i.e., multiple of 2)

8002h

Memory

8003h

8001h

8000h

8004h

8006h

8005h

8008h

8007h

16-bits

16-bits

Miss-aligned

Aligned



13



A miss-aligned memory access may require two clock cycles to

complete (depends on the processor word width)




Accessing a word (4 bytes) generates a

miss-alignment whenever the address

is not multiple of 4

8002h

Memory

8003h

8001h

8000h

8004h

8006h

8005h

8008h

8007h

32-bits

32-bits

Miss-aligned

Aligned



14

To simplify memory access some processors do not allow miss-

aligned memory addressing.

In such cases the processor may use more than the required

memory space to store the variable.

E.g., for an 32-bit architecture (i.e., with 32-bit registers) storing one char

(byte) in memory may use 32 bits (depends on the compiler).

Some compilers also avoid using miss-aligned memory addresses to

increase processing speed.


Data organization in memory

15

Consider storing a 32-bit hexadecimal number in memory:

06AB434Ch

The word the number can be divided into the 4 bytes:

06h ABh 43h 4Ch

Storing the value in memory organized

can be done as follows:

Little Endian:

Store less significant byte in the

lower address

Big Endian:

Store most significant byte in the

lower address

8002h

Memory

8003h

8001h

8000h

8004h

8006h

8005h

8008h

8007h

06h

ABh

43h

4Ch

8002h

Memory

8003h

8001h

8000h

8004h

8006h

8005h

8008h

8007h

4Ch

43h

ABh

06h

Big Endian style

Little Endian style



16

Consider storing a 32-bit hexadecimal number in memory:

06AB434Ch

The word the number can be divided into the 4 bytes:

06h ABh 43h 4Ch

Storing the value in memory organized

can be done as follows:

Little Endian:

Store less significant byte in the

lower address

Big Endian:

Store most significant byte in the

lower address

8002h

Memory

8003h

8001h

8000h

8004h

8006h

8005h

8008h

8007h

06h

ABh

43h

4Ch

8002h

Memory

8003h

8001h

8000h

8004h

8006h

8005h

8008h

8007h

4Ch

43h

ABh

06h

Big Endian style

Little Endian style

06h ABh 43h 4Ch

Address 3 2 1 0

4Ch 43h ABh 06h Big

Endian

Little

Endian



17

Example of Endian-ness in computer architectures:

MIPS and Microblaze are big endian

Intel x86, x86_64 are little endian

ARM is bi-endian (i.e., supports both modes) (in ARM architectures endian-ness is defined by the interconnection network to the main memory)

IMPORTANT NOTICE:

Endian-ness is just the translating of data from memory to registers; in

registers endian-ness has no meaning


Description Assembly Operation

Register/Memory Memory/Register

Move MOV opA,opB opA opB

Exchange ou SWAP XCH opA,opB opA opB , opB opA

Register Memory

Load LD opA,opB opA M[opB]

Store ST opA,opB M[opA] opB

Stack Register/Memory

Push PUSH opA (defined in following slides)

Pop POP opA (defined in following slides)

I/O Register/Memory

Input IN opA,Porto opA peripheral

Output OUT Porto,opB peripheral opB


Example data transfer operations 18



Increment INC opA,opB opA opB + 1

Decrement DEC opA,opB opA opB – 1

Add ADD opA,opB,opC opA opB + opC

Subtract SUB opA,opB,opC opA opB – opC

Multiply MUL opA,opB,opC opA opB x opC

Divide DIV opA,opB,opC opA opB / opC

Negate NEG opA,opB opA - opB

Some processors define operations conditioned to state bits. Example:

ADD.NZ opA,opB,opC ; se S(Z)=0 opA opB + opC

; se S(Z)=1 NOP


Example arithmetic operations 19


Status register

The status register stores information regarding the previously

executed instructions

Example:

Not all instructions change the status register, e.g., logic instructions

do not update the overflow bit

Previous result gave an overflow

Previous result had carry out

Previous result was negative

Previous result was zero

STATUS

REGISTER:

20



Clear CLR opA opA 0

Complement NOT opA,opB opA ! opB

And AND opA,opB opA opA ˄ opB

Or OR opA,opB opA opA ˅ opB

Exclusive-or XOR opA,opB opA opA opB

Clear Carry CLC S(C) 0

Set Carry STC S(C) 1

Complement Carry CMC S(C) ! S(C)


Example logic operations 21



Logic shift left (LSL) SHL opA opA LSL opA

Logic shift right (LSR) SHR opA opA LSR opB

Arithmetic shift left (ASL) SHLA opA opA ASL opA

Arithmetic shift right (ASR) SHRA opA opA ASR opB

Rotate left (ROL) ROL opA opA ROL opA

Rotate Right (ROR) ROR opA opA ROR opB

Rotate left with Carry (ROLC) ROLC opA opA ROLC opA

Rotate Right with Carry (RORC) RORC opA opA RORC opB


Example shift operations 22



Branch BR.cond opA Relative jump (PC PC + OpA)

Jump JMP.cond opA Absolute jump (PC OpA)

Test & Branch TB.cond ... Test and relative jump

Test & Jump TJ.cond ... Test and absolute jump

Skip next instruction SKP.cond ... Skip instruction

Jump and Link JMPL.cond opA Function call in RISC processors

Call procedure CALL.cond opA Function call in CISC processors

Return RET.cond Return from function call (CISC)

Test instruction to be used before a condicional Jump or Branch instruction

Compare (Escrita dos bits de estado)

CMP opA,opB Operand compare through subtraction (updates status register bits Z,N,C,V)

Test (Escrita dos bits de estado)

TEST opA,opB Operand compare through logic AND (updates status register bit Z)

All control instructions can be conditional or inconditional; some processors also implement conditional data insctructions.


Example control operations 23


Description Assembly Example

If zero, S(Z)=1 .Z ADD.Z

If not zero, S(Z)=0 .NZ BR.NZ

If Negative, S(N)=1 .N BR.Z

If not Negative, S(N)=0 .NN JMP.NZ

If Carry, S(C)=1 .C CALL.C

If not Carry, S(C)=0 .NC CALL.NC

If Overflow, S(V)=1 .V RET.V

If not Overflow, S(V)=0 .NV SKP.NV


Example status-based conditions 24


Description Assembly Condition

If higher .H opA > opB

If higher or equal .HE opA ≥ opB

If Lower .L opA < opB

If Lower or equal .LE opA ≤ opB

If equal .E opA = opB

If not equal .NE opA ≠ opB

Description Assembly Condition

If greater .G opA > opB

If greater or equal .GE opA ≥ opB

If Less .L opA < opB

If Less or equal .LE opA ≤ opB

CONDITIONS FOR SIGNED NUMBERS


Example test conditions 25

Hardware implementation of a RISC processor

MIPS ISA

Designing a simple MIPS-like processor

Next lesson 26

Documents

INSTRUCTION SET ARCHITECTURE - ULisboa · Instruction Set Architecture (ISA) Machine vs Assembly code An instruction in machine code generally corresponds to a set of bits that can