MOS: Device Operation & Large Signal Modelaries.ucsd.edu/NAJMABADI/CLASS/ECE65/12-W/Slides/ECE65_W12-M… · Operational Basis of a Field-Effect Transistor (2) If we apply a voltage

MOS: Device Operation & Large Signal Model

Lecture notes: Sec. 4

Sedra & Smith (6th Ed): Sec. 5.1-5.3 Sedra & Smith (5th Ed): Sec. 4.1-4.3

F. Najmabadi, ECE65, Winter 2012

Operational Basis of a Field-Effect Transistor (1)


P-type semiconductor

Insulator

Metal

Dopent ions

Holes (majority carries)

Consider the hypothetical semiconductor below: (constructed similar to a parallel plate capacitor)

Electrical contact


If we apply a voltage v1 between electrodes, a charge Q = C v1 will appear on each capacitor plate. o The electric field is strongest at the interface with the

insulator and charge likes to accumulate there.

Holes are pushed away from the insulator interface forming a “depletion region”.

Depth of depletion region increases with v1.


Depletion Region (no majority carrier)

If we increase v1 above a threshold value (Vt), the electric field is strong enough to “pull” free electrons to the insulator interface. As the holes are repelled in this region, a “channel” is formed which contains electrons in the conduction band (“inversion layer”).

Inversion layer is a “virtual” n-type material.

Depletion Region (no majority carrier)

Inversion layer (“channel”)



With inversion layer (v1 > Vt):

A current will flow in the channel

Current will be proportional to electron charge in the channel or (v1 − Vt )

Magnitude of Current i2 is controlled by voltage v1 (a Transistor!)

We apply a voltage across the p-type semiconductor: (Assume current flows only in the n-type material, ignore current flowing in the p-type semiconductor)

No inversion layer (v1 < Vt):

No current will flow



We need to eliminate currents flowing in the p-type, i.e., current flows only in the “channel” which is a virtual n-type.

Channel width (L) is the smallest feature on the chip surface


MOSFET implementation on a chip

MOSFET “cartoons” for deriving MOSFET characteristics MOSFET (or MOS): Metal-oxide field effect transistor

NMOS: n-channel enhancement MOS

NMOS i-v Characteristics (1)


To ensure that body-source and body-drain junctions are reversed bias, we assume that Body and Source are connected to each other and vDS ≥ 0. o We will re-examine this assumption later

Without a channel, no current flows (“Cut-off”).

For vGS > Vtn, a channel is formed. The total charge in the channel is

)SiO(for F/m 1045.39.3

insulator ofy permitivit :insulator of Thickness :

areaunit per eCapacitanc :

211

0−×==

=

===

εε

ε

ε

ox

ox

ox

ox

oxox

ox

tnGSox

tt

C

LWCC) -VWL (vCCV|Q|



vGS > Vtn : a channel is formed!

Apply a “small” voltage, vDS between drain & source.

A current flow due to the “drift” of electrons in the n-channel:

DSOVoxnD

DSntGSoxnD

vVL

WC i

vVvL

WCi

)( ,

µ

µ

=

−=

MOS acts as a resistance with its conductivity controlled by VOV (or vGS).

VL

WCgv gi OVoxnDSDSDSD with µ==

Overdrive Voltage:

tnGSOV VvV −=



When vDS is increased the channel becomes narrower near the drain (local depth of the channel depends on the difference between VOV and local voltage).

Triode Mode

[ ]25.0 DSDSOVoxnD vvVL

WCi −= µ

When vDS is increased further such that vDS = VOV , the channel depth becomes zero at the drain (Channel “pinched off”).

When vDS is increased further, vDS > VOV , the location of channel pinch-off remains close to the drain and iD remains approximately constant.

Saturation Mode 25.0 OVoxnD V

LWCi µ=



For a given vGS (or VOV)

NMOS i-v Characteristics Plot (1)


NMOS i-v characteristics is a surface

* Plot for Vt,n = 1 V and µnCox (W/L) = 2.0 mA/V2

),( DSGSD vvfi =

NMOS i-v Characteristics Plot (2)


Looking at surface with vGS axis pointing out of the paper*

*Note: surface is truncated (i.e., vGS < 5 V)

NMOS i-v Characteristics Plots


Channel-Width Modulation


The expression we derived for saturation region assumed that the pinch-off point remains at the drain and thus iD remains constant.

In reality, the pinch-off point moves “slightly” away from the drain: Channel-width Modulation

( )

A

DSOVoxnD

V

vVL

WCi

/1

1 5.0 2

=

+=

λ

λµ

Body Effect

Recall that Drain-Body and Source-Body diodes should be reversed biased. o We assumed that Source is connected to the body (vSB = 0) and vDS = vDB > 0

In a chip (same body for all NMOS), it is impossible to connect all sources to the body (all NMOS sources are connected together.

Thus, the body (for NMOS) is connected to the largest negative voltage (negative terminal of the power supply).

Doing so, changes the threshold voltage (called “Body Effect”)


( )|2||2| 0, FSBFtntn VVV φφγ −++=

In this course we will ignore body effect as well as other second-order effects such as velocity saturation.

p-channel Enhancement MOS (PMOS)


A PMOS can be constructed analogous to an NMOS: (n-type body), heavily doped p-type source and drain.

A virtual “p-type” channel is formed in a P-MOS (holes are carriers in the channel) by applying a negative vGS.

i-v characteristic equations of a PMOS is similar to the NMOS with the exception: o Voltages are negative (we switch the terminals to have positive voltages:

use vSG instead of vGS ).

o Use mobility of holes, µp , instead of µn in the expression for iD

MOS Circuit symbols and conventions


PMOS NMOS

MOS i-v Characteristics Equations: iD (vGS , vDS ) & iG = 0

F. Najmabadi, ECE65, Winter 2012 *Note: S&S defines |VOV |= vSG – |Vt,p| and uses |VOV |in the PMOS formulas.

PMOS (VOV = vSG – |Vtp|, λ = 1 / |VA| )*

[ ]

[ ]SDOVoxpDOVSDOV

SDSDOVoxpDOVSDOV

DOV

vVL

WCiVvV

vvVL

WCiVvV

iV

λµ

µ

+=≥≥

−=≤≥

=≤

1 5.0 and 0 :Saturation

25.0 and 0 :Triode

0 0 :Off-Cut

2

2

NMOS (VOV = vGS – Vtn, λ = 1 / VA)

[ ]

[ ]DSOVoxnDOVDSOV

DSDSOVoxnDOVDSOV

DOV

vVL

WCiVvV

vvVL

WCiVvV

iV

λµ

µ

+=≥≥

−=≤≥

=≤

1 5.0 and 0 :Saturation

25.0 and 0 :Triode

0 0 :Off-Cut

2

2

MOS operation is “Conceptually” similar to a BJT -- iD & vDS are controlled by vGS


Controller part: Circuit connected to GS sets vGS (or VOV )

Controlled part: iD & vDS are set by transistor state (& outside circuit)

A similar solution method to BJT:

o Write down GS-KVL and DS-KVL, assume MOS is in a particular state, solve with the corresponding MOS equation and validate the assumption.

MOS circuits are simpler to solve because iG = 0 ! o However, we get a quadratic equation to solve if MOS in triode (check MOS

in saturation first!)


Example 1: In the circuit below, RD = 1 k, and VDD = 12 V. Compute vo for vi = 0, 6, and 12 V. (µnCox (W/L) = 0.5 mA/V2 , Vt = 2 V, and λ = 0 )

DSDDSDDDD

GSi

viviRVvv

+=+==

=

10 12 :KVL-DS

:KVL-GS3

V 12 0 10 12 :KVL-DS

0 off-Cut V2 0 :KVL-GS3 ==→+×=

=→→=<==

DSoDS

DtGSi

vvviVvv

correct Assumption V 4V 0.8V 0.8 104 10 12 :KVL-DS

mA 0.44105.05.0 5.0

V 4 :Saturation Assume

33

232

→=>===→+××=

=×××==

=≥

−

−

OVDS

DSoDS

OVoxnD

OVDS

Vvvvv

VL

WCi

Vv

µ

Part 1: vi = 0

V4 off-Cutin Not V2 6 :KVLGS

=−=→=>==−

tGSOV

tGSi

VvVVvv

Part 2: vi = 6 V

o DSvv =



DSDDSDDDD

GSi

viviRVvv

+=+==

=

10 12 :KVL-DS

:KVL-GS3

incorrect Assumption V 10V 13V .13 100.25 10 12 :KVL-DS

mA 0.2510105.05.0 5.0

V 10 :Saturation Assume

33

232

→=>−=−=→+××=

=×××==

=≥

−

−

OVDS

DSDS

OVoxnD

OVDS

Vvvv

VL

WCi

Vv

µ

V10 off-Cutin Not V2 12 :KVL-GS

=−=→=>==

tGSOV

tGSi

VvVVvv

Part 3: vi = 12 V

o DSvv =



DSDDSDDDD

GSi

viviRVvv

+=+==

=

10 12 :KVL-DS

:KVL-GS3

[ ]

04824

]20[ 105.05.0 1012

10 12 :KVL-DS

25.0

V 10 :Triode Assume

2

23-3

3

2

=+−

+−××××=

+×=

−=

=<

DSDS

DSDSDS

DSD

DSDSOVoxnD

OVDS

vvvvv

vi

vvVL

WCi

Vv

µ

V10 =−= tGSOV VvV

Part 3 (cont’d): vi = 12 V

o DSvv =

mA 8.9 10 12

V 10 V 2.2)(incorrect V 8.21

3 =→+×=

=<====

DDSD

OVDSo

DSo

iviVvv

vv

NMOS Transfer Function (1)


),( DSGSD

DSDDDD

iGS

vvfiviRV

vv

=+=

=

For vGS < Vt , NMOS is in cutoff: iD = 0

DDDDDDDSo ViRVvv =−==

vi can be applied directly to MOS There is no need for a RG .



),( DSGSD

DSDDDD

iGS

vvfiviRV

vv

=+=

=

For vGS < Vt , NMOS is in cutoff: iD = 0

DDDDDDDSo ViRVvv =−==

vi can be applied directly to MOS There is no need for a RG .



To the right of point A, vGS >Vt, and NMOS is ON.

Just to the right of point A: o VOV = vGS − Vt is small. So iD is

also small and vDS is close to VDD .

o Thus, vDS > VOV and NMOS is in saturation.

22

2

5.0

5.0

OVDOVoxnDDDS

OVoxnD

VRVL

WCVv

VL

WCi

−=

=

µ

µ



As vGS increase: o VOV = vGS − Vt becomes larger;

o vDS becomes smaller.

At point B, vDS = VOV = vGS − Vt

To the right of point B, vDS < VOV = vGS − Vt and NMOS enters triode.

Point B is called the “Edge of Saturation”

Exercise: Use NMOS i-v characteristics (and DS-KVL) to find VGS|B and VDS|B

Graphical analysis of NMOS Transfer Function


NMOS iD (vGS , vDS ) is a surface in the 3-D (iD , vGS , vDS ) space.

DS-KVL is a plane in this space.

Intersection of KVL plane with the iv characteristic surface is a line.

NMOS operating point is on this line (depending on the value of vGS.)

If we look from the side (with vGS axis pointing into the paper, we see contour plots of NMOS iD (vGS , vDS )

Graphical analysis of NMOS Transfer Function

Every point on the load line corresponds to a specific vGS value.

As vGS increases, NMOS moves “up” the load line.

A

B

C

We see the transfer function if we look this way!


NMOS Functional circuits

Similar to a BJTSin the active mode, NMOS behaves rather “linearly” in the saturation region (we discuss NMOS amplifiers later)

Transition from cut-off to triode can be used to build NMOS switch circuits. o Voltage at point C (see graph)

depends on NMOS parameters and the circuit (in BJT vo = Vsat)!

We can also built NMOS logic gate similar to a RTL. But there is a much better gate based on CMOS technology!


Complementary MOS (CMOS) is based on NMOS/PMOS pairs

Maximum signal swing: Low State: 0, High State: VDD o Independent of MOS device parameters!

o Wide noise margin.

Zero “static” power dissipation (iD = 0 in each state).

Higher speed compare to a “RTL-type” NMOS inverter


NMOS Inverter

Replace RD with a PMOS

“Effective” RD seen by Q1 is controlled by vi : o “Infinite” RD when Q1 is ON o “Very small” RD when Q1 is OFF

CMOS Inverter

Analysis of CMOS Inverter (1)


21

21

12

22

1

:KVL2&DS1 :KVLGS2

:KVLGS1

SDDDDSo

DD

DSSDDD

iDDSGiSGDD

iGS

vVvvii

vvVvVvvvV

vv

−===

+=−−=→+=−

=−

Case 1: vi = 0

ON Q2

0 OFF Q1 0

2

11

→>=−=↓

=→→<==

| |VVvVv

iVvv

tpDDiDDSG

DtniGS

0 ON Q2

0 OFF Q1 0

22

11

=→>=−=↓

=→→<==

DtpDDiDDSG

DtniGS

i| |VVvVv

iVvvKCL

?

A MOS in ON and iD = 0 only if MOS is in triode and vDs = 0


MOS ON: VOV > 0

MOS in saturation: incorrect!

MOS in triode:

0 0 5.0 2 =→== OVOVoxnD VVL

WCi µ

[ ] 0 025.0 2 =→=−= DSDSDSOVoxnD vvvVL

WCi µ

When is iD = 0 ?

MOS is OFF (VOV < 0) o No channel is formed, no iD can flow

MOS is ON (VOV > 0) o A channel is formed, and iD can flow

but iD = 0 because no voltage is applied to drive iD !



21

21

12

22

1

:KVL2&DS1 :KVLGS2

:KVLGS1

SDDDDSo

DD

DSSDDD

iDDSGiSGDD

iGS

vVvvii

vvVvVvvvV

vv

−===

+=−−=→+=−

=−

Case 1: vi = 0

0 & Triodein Q2 0 ON Q2

0 OFF Q1 0

222

111

=→=→=−=↑↓

==→→<==

SDDDDiDDSG

DDDSDtniGS

viVvVv

VviVvv

For vi = 0, vo = vDS1 = VDD (iD1 = 0, iD2 = 0 ) Gate remains in this state as long as vi < Vtn (Q1 OFF)

0 ON Q2

0 OFF Q1 0

22

11

=→=−=↓

=→→<==

DDDiDDSG

DtniGS

iVvVv

iVvv

0 OFF Q2 || 0

ON Q1

22

1

=→→<=−=↑

→>==

DtpiDDSG

tnDDiGS

iVvVv

VVvv



Case 2: vi = VDD

21

21

12

22

1

:KVL2&DS1 :KVLGS2

:KVLGS1

SDDDDSo

DD

DSSDDD

iDDSGiSGDD

iGS

vVvvii

vvVvVvvvV

vv

−===

+=−−=→+=−

=−

0 OFF Q2 || 0


222

111

DDSDDtpiDDSG

DSDtnDDiGS

VviVvVv

viVVvv

==→→<=−=↓↑

=→=→>==

For vi = VDD, vo = vDS1 = 0 (iD1 = 0, iD2 = 0 ) Gate remains in this state as long as vi > VDD − |Vtp| (Q2 OFF)

0 OFF Q2 || 0

0 ON Q1

22

11

=→→<=−=↑

=→>==

DtpiDDSG

DtnDDiGS

iVvVv

iVVvv

Transfer function of a CMOS inverter

Transfer function is “symmetric” for matched transistors: Vtn=|Vtp| & µn (W/L)n = µp (W/L)p

During transition from one state to another, iD > 0


CMOS NAND Gate


Truth Table

v1 = 0 v2 = 0: vo = VDD

v1 = 0 v2 = VDD : vo = VDD

v1 = VDD v2 = 0 : vo = VDD

v1 = VDD v2 = VDD : vo = 0

Analysis of CMOS NAND Gate (1)


GS2-KVL

GS3-KVL

GS4-KVL GS1-KVL: 11 vvGS =

GS2-KVL:

122

122

DSGS

DSGS

vvvvvv

−=→+=

GS3-KVL:

13

13

vVvvvV

DDSG

SGDD

−=→+=

GS4-KVL:

24

24

vVvvvV

DDSG

SGDD

−=→+=

KCL: 4321 DDDD iiii +==

DS-KVL:

43

124

SDSD

DSDSSDDD

vvvvvV

=++=

34

21

SDDDSDDDo

DSDSo

vVvVvvvv

−=−=+=



2134 DSDSSDDDSDDDo vvvVvVv +=−=−=

0 & Triodein Q4 0 ON Q4 ||

0 & Triodein Q3 0 ON Q3 || 0 ? Q2 0 OFF Q1 0

4424

3313

21122

111

=→=→>=−=

=→=→>=−==→−=−==→→<==

SDDtpDDDDSG

SDDtpDDDDSG

DDSDSGS

DtnGS

viVVvVvviVVvVv

ivvvviVvv

ON Q4 ||

ON Q3 || ? Q2

0 OFF Q1 0

24

13

1122

111

→>=−=

→>=−=→−=−=

=→→<==

tpDDDDSG

tpDDDDSG

DSDSGS

DtnGS

VVvVvVVvVv

vvvviVvv

0 ON Q4 ||

0 ON Q3 || 0 ? Q2 0 OFF Q1 0

424

313

21122

111

=→>=−=

=→>=−==→−=−==→→<==

DtpDDDDSG

DtpDDDDSG

DDSDSGS

DtnGS

iVVvVviVVvVvivvvviVvv

For v1 = 0 & v2 = 0, vo = VDD (iD1 = iD2 = iD3 = iD4 = 0)

Case 1: v1 = 0 & v2 = 0

DDSDDDo VvVv =−= 4

Note: Since vDS1 ≥ 0, we can say vGS2 =vDS1 < Vtn and Q2 is OFF!

4321 DDDD iiii +==



2134 DSDSSDDDSDDDo vvvVvVv +=−=−=

0 & Triodein Q4 0 ON Q4 | |

0 OFF Q3 || 0 0 OFF Q2


4424

313

21122

1111

=→=→>=−=

=→→<=−==→→<−=−=

=→=→>==

SDDtpDDDDSG

DtpDDSG

DtnDSDSGS

DSDtnDDGS

viVVvVviVvVviVvvvv

viVVvv

Case 2: v1 = VDD & v2 = 0

DDSDDDo VvVv =−= 4

ON Q4 | |

0 OFF Q3 || 0 0 OFF Q2

ON Q1

24

313

21122

11

→>=−=

=→→<=−==→→<−=−=

→>==

tpDDDDSG

DtpDDSG

DtnDSDSGS

tnDDGS

VVvVviVvVviVvvvv

VVvv

0 ON Q4 | |

0 OFF Q3 || 0 0 OFF Q2

0 ON Q1

424

313

21122

111

=→>=−=

=→→<=−==→→<−=−==→>==

DtpDDDDSG

DtpDDSG

DtnDSDSGS

DtnDDGS

iVVvVviVvVviVvvvviVVvv

4321 DDDD iiii +==

For v1 = VDD & v2 = 0, vo = VDD (iD1 = iD2 = iD3 = iD4 = 0)

Exercise: Complete the analysis of the truth table of this NAND gate

Documents

MOS: Device Operation & Large Signal Modelaries.ucsd.edu/NAJMABADI/CLASS/ECE65/12-W/Slides/ECE65_W12-M… · Operational Basis of a Field-Effect Transistor (2) If we apply a voltage