SN6501 Transformer Driver for Isolated Power Supplies

SN6501 Transformer Driver for Isolated Power Supplies

1 Features• Push-pull driver for small transformers• Single 3.3-V or 5-V supply• High primary-side current drive:

– 5-V Supply: 350 mA (Max)– 3.3-V Supply: 150 mA (Max)

• Low ripple on rectified output permits small outputcapacitors

• Small 5-Pin SOT-23 Package

2 Applications• Isolated interface power supply for CAN, RS-485,

RS-422, RS-232, SPI, I2C, Low-Power LAN• Industrial automation• Process control• Medical equipment

3 DescriptionThe SN6501 is a monolithic oscillator/power-driver,specifically designed for small form factor, isolatedpower supplies in isolated interface applications. Thedevice drives a low-profile, center-tapped transformerprimary from a 3.3-V or 5-V DC power supply. Thesecondary can be wound to provide any isolatedvoltage based on transformer turns ratio.

The SN6501 consists of an oscillator followed by agate drive circuit that provides the complementaryoutput signals to drive the ground referenced N-channel power switches. The internal logic ensuresbreak-before-make action between the two switches.

The SN6501 is available in a small SOT-23 (5)package, and is specified for operation attemperatures from –40°C to 125°C.

Device InformationPART NUMBER(1) PACKAGE BODY SIZE (NOM)

SN6501 SOT-23 (5) 2.90 mm x 1.60 mm

(1) For all available packages, see the orderable addendum atthe end of the datasheet.

Simplified Schematic

Output Voltage and Efficiency vs Output Current

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents1 Features............................................................................12 Applications..................................................................... 13 Description.......................................................................1Revision History................................................................. 24 Pin Configuration and Functions...................................45 Specifications.................................................................. 5

5.1 Absolute Maximum Ratings........................................ 55.2 Handling Ratings.........................................................55.3 Recommended Operating Conditions.........................65.4 Thermal Information....................................................65.5 Electrical Characteristics.............................................65.6 Switching Characteristics............................................65.7 Typical Characteristics................................................ 7

6 Parameter Measurement Information.......................... 127 Detailed Description......................................................13

7.1 Overview................................................................... 137.2 Functional Block Diagram......................................... 13

7.3 Feature Description...................................................137.4 Device Functional Modes..........................................14

8 Application and Implementation.................................. 158.1 Application Information............................................. 158.2 Typical Application.................................................... 16

9 Power Supply Recommendations................................2810 Layout...........................................................................29

10.1 Layout Guidelines................................................... 2910.2 Layout Example...................................................... 29

11 Device and Documentation Support..........................3011.1 Device Support........................................................3011.2 Trademarks............................................................. 3011.3 Electrostatic Discharge Caution.............................. 3011.4 Glossary.................................................................. 30

12 Mechanical, Packaging, and OrderableInformation.................................................................... 30

Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (July 2019) to Revision I (January 2021) Page• Added a short-circuit protection note to Section 8.2.2.1 .................................................................................. 16• Removed duplicate equation labeled as (5) in Revision H .............................................................................. 19

Changes from Revision G (July 2014) to Revision H (July 2019) Page• Added HCT-SM-1.3-8-2 transformer to Recommended Isolation Transformers Optimized for SN6501Table

8-3 table............................................................................................................................................................21• Added EPC3668G-LF transformer to Recommended Isolation Transformers Optimized for SN6501Table 8-3

table.................................................................................................................................................................. 21• Added DA2303-AL transformer to Recommended Isolation Transformers Optimized for SN6501Table 8-3

table.................................................................................................................................................................. 21• Added DA2304-AL transformer to Recommended Isolation Transformers Optimized for SN6501Table 8-3

table.................................................................................................................................................................. 21

Changes from Revision F (August 2013) to Revision G (July 2014) Page• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device

Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layoutsection, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Informationsection ............................................................................................................................................................... 1

Changes from Revision E (January 2013) to Revision F (August 2013) Page• Added Figure 5-13 and Figure 5-14 ...................................................................................................................7• Added Figure 5-17 through Figure 5-18 ............................................................................................................ 7• Added Figure 5-23 through Figure 5-24 ............................................................................................................ 7• Changed Table 8-3 - Recommended Isolation Transformers Optimized for SN6501.......................................21

Changes from Revision D (September 2012) to Revision E (January 2013) Page• Changed Figure 5-23 .........................................................................................................................................7

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Changes from Revision C (March 2012) to Revision D (September 2012) Page• Changed fOSC, Oscillator frequency To: fSW, D1, D2 Switching frequency ........................................................ 6• Added graphs Figure 5-3 through Figure 5-4 .................................................................................................... 7• Changed the title of Figure 5-30 From: D1, D2 Oscillator Frequency vs Free-Air Temperature To: D1, D2

Switching Frequency vs Free-Air Temperature...................................................................................................7• Added section: Recommended Transformers.................................................................................................. 21• Changed the location and title of Figure 8-7 ....................................................................................................21

Changes from Revision B (March 2012) to Revision C (March 2012) Page• Changed the fOSC Oscillator frequency values .................................................................................................. 6• Changed Equation 4 ........................................................................................................................................ 19

Changes from Revision A (March 2012) to Revision B (March 2012) Page• Changed Feature From: Small 5-pin DBV Package To: Small 5-pin SOT23 Package.......................................1• Changed Figure 8-7 title................................................................................................................................... 21

Changes from Revision * (February 2012) to Revision A (March 2012) Page• Changed the device From: Product Preview To: Production.............................................................................. 1• Changed Equation 9 ........................................................................................................................................ 19• Changed Equation 10 ...................................................................................................................................... 19• Changed Table 8-4, From: Wuerth-Elektronik / Midcom To: Wurth Electronics Midcom Inc.............................23• Changed Figure 8-16 .......................................................................................................................................23

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4 Pin Configuration and Functions

1 5

2

3 4

D1

VCC

D2

GND

GND

Figure 4-1. 5-Pin SOT-23 DBV Package Top View

Table 4-1. Pin FunctionsPIN

DESCRIPTIONNAME NUMBER TYPE

D1 1 OD Open Drain output 1. Connect this pin to one end of the transformer primary side.

VCC 2 P Supply voltage input. Connect this pin to the center-tap of the transformer primary side. Buffer thisvoltage with a 1 μF to 10 μF ceramic capacitor.

D2 3 OD Open Drain output 2. Connect this pin to the other end of the transformer primary side.

GND 4,5 P Device ground. Connect this pin to board ground.





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5 Specifications5.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNITVCC Supply voltage –0.3 6 V

VD1, VD2 Output switch voltage 14 V

ID1P, ID2P Peak output switch current 500 mA

PTOT Continuous power dissipation 250 mW

TJ Junction temperature 170 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage to the device. These are stress ratings onlyand functional operation of the device at these or any other conditions beyond those indicated under Section 5.3 is not implied.Exposure to absolute-maximum-rated conditions for extended periods affects device reliability.

5.2 Handling RatingsMIN MAX UNIT

Tstg Storage temperature range –65 150 °C

V(ESD) Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, allpins(1) –4 4

kVCharged device model (CDM), per JEDEC specificationJESD22-C101, all pins(2) –1.5 1.5

Machine Model JEDEC JESD22-A115-A –200 200 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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5.3 Recommended Operating ConditionsMIN TYP MAX UNIT

VCC Supply voltage 3 5.5 V

VD1, VD2 Output switch voltageVCC = 5 V ± 10%, When connected to Transformer with

primary winding Center-tapped0 11

VVCC = 3.3 V ± 10% 0 7.2

ID1, ID2D1 and D2 output switchcurrent – Primary-side

VCC = 5 V ± 10%VD1, VD2 Swing ≥ 3.8 V,see Figure 5-32 for typicalcharacteristics

350

mA

VCC = 3.3 V ± 10%VD1, VD2 Swing ≥ 2.5 V,see Figure 5-31 for typicalcharacteristics

150

TA Ambient temperature –40 125 °C

5.4 Thermal Information

THERMAL METRICSN6501

UNITDBV 5-PINS

θJA Junction-to-ambient thermal resistance 208.3

°C/W

θJCtop Junction-to-case (top) thermal resistance 87.1

θJB Junction-to-board thermal resistance 40.4

ψJT Junction-to-top characterization parameter 5.2

ψJB Junction-to-board characterization parameter 39.7

θJCbot Junction-to-case (bottom) thermal resistance N/A

5.5 Electrical Characteristicsover full-range of recommended operating conditions, unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RON Switch-on resistanceVCC = 3.3 V ± 10%, See Figure 6-4 1 3

ΩVCC = 5 V ± 10%, See Figure 6-4 0.6 2

ICC Average supply current(1)VCC = 3.3 V ± 10%, no load 150 400

µAVCC = 5 V ± 10%, no load 300 700

fST Startup frequency VCC = 2.4 V, See Figure 6-4 300 kHz

fSW D1, D2 Switching frequencyVCC = 3.3 V ± 10%, See Figure 6-4 250 360 550

kHzVCC = 5 V ± 10%, See Figure 6-4 300 410 620

(1) Average supply current is the current used by SN6501 only. It does not include load current.

5.6 Switching Characteristicsover operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITtr-D D1, D2 output rise time VCC = 3.3 V ± 10%, See Figure 6-4 70 ns

VCC = 5 V ± 10%, See Figure 6-4 80

tf-D D1, D2 output fall time VCC = 3.3 V ± 10%, See Figure 6-4 110 ns

VCC = 5 V ± 10%, See Figure 6-4 60

tBBM Break-before-make time VCC = 3.3 V ± 10%, See Figure 6-4 150 ns

VCC = 5 V ± 10%, See Figure 6-4 50





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5.7 Typical CharacteristicsTP1 Curves are measured with the Circuit in Figure 6-1; whereas, TP1 and TP2 Curves are measured withCircuit in Figure 6-3 (TA = 25°C unless otherwise noted). See Table 8-3 for Transformer Specifications.

80 10090

5

40 60200

ILOAD - mA

VO

UT

-V

30 50 7010

4

3

2

0

1

TP1

T1 = 760390011 (2.5kV)

VIN = 3.3V, VOUT = 3.3V

Figure 5-1. Output Voltage vs Load Current

10

20

30

40

50

60

70

80

90

0

Eff

icie

nc

y-

%

TP1

80 1009040 60200

ILOAD - mA

30 50 7010

T1 = 760390011 (2.5kV)

VIN = 3.3V, VOUT = 3.3V

Figure 5-2. Efficiency vs Load Current

VO

UT

-V

6

5

4

3

2

0

1

TP1

T1 = 760390012 (2.5kV)

VIN = 5V, VOUT = 5V

80 1009040 60200

ILOAD - mA

30 50 7010

Figure 5-3. Output Voltage vs. Load Current

10

20

30

40

50

60

70

80

90

0

Eff

icie

nc

y-

%

TP1

80 1009040 60200

ILOAD - mA

30 50 7010

T1 = 760390012 (2.5kV)

VIN = 5V, VOUT = 5V


VO

UT

-V

6

5

4

3

2

0

1

TP1

T1 = 760390013 (2.5kV)

VIN = 3.3V, VOUT = 5V

80 1009040 60200

ILOAD - mA

30 50 7010


10

20

30

40

50

60

70

80

90

0

Eff

icie

nc

y-

%

TP1

80 1009040 60200

ILOAD - mA

30 50 7010

T1 = 760390013 (2.5kV)



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VO

UT

-V

5

4

3

2

0

1

TP1

TP2

T1 = 760390014 (2.5kV)

VIN = 3.3V, VOUT = 3.3V

80 1009040 60200

ILOAD - mA

30 50 7010


10

20

30

40

50

60

70

80

90

0

Eff

icie

nc

y-

%

TP1

TP2

80 1009040 60200

ILOAD - mA

30 50 7010

T1 = 760390014 (2.5kV)

VIN = 3.3V, VOUT = 3.3V


1

2

3

4

5

6

7

8

0

VO

UT

-V TP2

TP1

T1 = 760390014 (2.5kV)

VIN = 5V, VOUT = 5V

80 1009040 60200

ILOAD - mA

30 50 7010


10

20

30

40

50

60

70

80

90

0E

ffic

ien

cy

-%

TP1

TP2

80 1009040 60200

ILOAD - mA

30 50 7010

T1 = 760390014 (2.5kV)

VIN = 5V, VOUT = 5V


1

2

3

4

5

6

7

0

VO

UT

-V TP2

TP1

T1 = 760390015 (2.5kV)


80 1009040 60200

ILOAD - mA

30 50 7010

Figure 5-11. Output Voltage vs Load Current Figure 5-12. Efficiency vs Load Current

VO

UT

-V

5

4

3

2

0

1

TP1

TP2

80 1009040 60200

ILOAD - mA

30 50 7010

T1 = 750313710 (2.5kV)

VIN = 5V, VOUT = 3.3V


10

20

30

40

50

60

70

80

90

0

Eff

icie

nc

y-

%

TP1

TP2

80 1009040 60200

ILOAD - mA

30 50 7010

T1 = 750313710 (2.5kV)







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80 10090

6

5

40 60200

ILOAD - mA

VO

UT

-V

30 50 7010

4

3

2

0

1

TP1

T1 = 750313734 (5kV)

VIN = 3.3V, VOUT = 3.3V


10

20

30

40

50

60

70

80

0

Eff

icie

nc

y-

%

TP1

80 9040 60200 30 50 7010

T1 = 750313734 (5kV)

VIN = 3.3V, VOUT = 3.3V

90

100


VO

UT

-V

6

5

4

3

2

0

1

TP1

T1 = 750313734 (5kV)

VIN = 5V, VOUT = 5V

80 1009040 60200

ILOAD - mA

30 50 7010


10

20

30

40

50

60

70

80

90

0E

ffic

ien

cy

-%

TP1

80 1009040 60200

ILOAD - mA

30 50 7010

T1 = 750313734 (5kV)

VIN = 5V, VOUT = 5V


Figure 5-19. Output Voltage vs Load Current Figure 5-20. Efficiency vs Load Current6

VO

UT

-V

5

4

3

2

0

1

TP1

TP2

T1 = 750313638 (5kV)

VIN = 3.3V, VOUT = 3.3V

80 1009040 60200

ILOAD - mA

30 50 7010


10

20

30

40

50

60

70

80

90

0

Eff

icie

nc

y-

%

TP1

TP2

T1 = 750313638 (5kV)

VIN = 3.3V, VOUT = 3.3V

80 1009040 60200

ILOAD - mA

30 50 7010


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1

2

3

4

5

6

7

8

0

VO

UT

-V TP2

TP1

T1 = 750313638 (5kV)

VIN = 5V, VOUT = 5V

80 1009040 60200

ILOAD - mA

30 50 7010


10

20

30

40

50

60

70

80

90

0

Eff

icie

nc

y-

%

TP1

TP2

T1 = 750313638 (5kV)

VIN = 5V, VOUT = 5V

80 1009040 60200

ILOAD - mA

30 50 7010


1

2

3

4

5

6

7

8

0

VO

UT

-V TP2

TP1

T1 = 750313626 (5kV)


80 1009040 60200

ILOAD - mA

30 50 7010


10

20

30

40

50

60

70

80

90

0

TP1

TP2

T1 = 750313626 (5kV)


80 1009040 60200

ILOAD - mA

30 50 7010

Figure 5-26. Efficiency vs Load Current6

VO

UT

-V

5

4

3

2

0

1

TP1

TP2

80 1009040 60200

ILOAD - mA

30 50 7010

T1 = 750313638 (5kV)



10

20

30

40

50

60

70

80

90

0

Eff

icie

nc

y-

%

TP1

TP2

80 1009040 60200 30 50 7010

T1 = 750313638 (5kV)



50

100

150

200

250

300

350

0

I CC

–S

up

ply

Cu

rre

nt

-µ

A

105 12525 65-15

TA - Free Air Temperature -oC

5 45 85-35-55

VCC = 3.3V

VCC = 5V

Figure 5-29. Average Supply Current vs Free-AirTemperature

340

360

380

400

420

440

460

320105 12525 65-15

TA - Free Air Temperature -oC

5 45 85-35-55

VCC = 3.3V

VCC = 5V

f-

Fre

qu

en

cy

-k

Hz

Figure 5-30. D1, D2 Switching Frequency vs Free-Air Temperature





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ID1, ID2 - Switching Current - mA

0 100 20015050

3.30

3.25

3.20

3.15

3.10

3.00

3.05

VD

1,

VD

2-

Vo

ltag

eS

win

g-

VVCC = 3.3V

Figure 5-31. D1, D2 Primary-Side Output SwitchVoltage Swing vs Current

ID1, ID2 - Switching Current - mA

0 200 400300100

5.00

4.95

4.90

4.85

4.65

4.55

4.60VD

1,

VD

2-

Vo

ltag

eS

win

g-

V

4.80

4.70

4.75

VCC = 5V

Figure 5-32. D1, D2 Primary-Side Output SwitchVoltage Swing vs Current

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6 Parameter Measurement Information

1 Fµ

VIN

MBR0520L

MBR0520L

T13

1

SN6501

5

2

4

TP1

0.1µF

D2

D1

VCC

GND

GND

Figure 6-1. Measurement Circuit for Unregulated Output (TP1)

Figure 6-2. Timing Diagram

Figure 6-3. Measurement Circuit for regulated Output (TP1 and TP2)

50W

VIN

10µF

3

1

SN6501

5

2

4D2

D1

VCC

GND

GND50W

Figure 6-4. Test Circuit For RON, FSW, FSt, Tr-D, Tf-D, TBBM





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7 Detailed Description7.1 OverviewThe SN6501 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC converters utilizingthe push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary outputsignals which alternately turn the two output transistors on and off.

The output frequency of the oscillator is divided down by an asynchronous divider that provides twocomplementary output signals with a 50% duty cycle. A subsequent break-before-make logic inserts a dead-timebetween the high-pulses of the two signals. The resulting output signals, present the gate-drive signals for theoutput transistors. As shown in the functional block diagram, before either one of the gates can assume logichigh, there must be a short time period during which both signals are low and both transistors are high-impedance. This short period, known as break-before-make time, is required to avoid shorting out both ends ofthe primary.

7.2 Functional Block Diagram

OSC

Q

Q

SN6501

Gate

Drive

D1

VCC

D2

GNDGND

7.3 Feature Description7.3.1 Push-Pull Converter

Push-pull converters require transformers with center-taps to transfer power from the primary to the secondary(see Figure 7-1).

C

CR1

CR2

Q1Q2

VIN

VOUT

RL C

CR1

CR2

Q1Q2

VIN

VOUT

RL

Figure 7-1. Switching Cycles of a Push-Pull Converter

When Q1 conducts, VIN drives a current through the lower half of the primary to ground, thus creating a negativevoltage potential at the lower primary end with regards to the VIN potential at the center-tap.

At the same time the voltage across the upper half of the primary is such that the upper primary end is positivewith regards to the center-tap in order to maintain the previously established current flow through Q2, which nowhas turned high-impedance. The two voltage sources, each of which equaling VIN, appear in series and cause avoltage potential at the open end of the primary of 2×VIN with regards to ground.

Per dot convention the same voltage polarities that occur at the primary also occur at the secondary. Thepositive potential of the upper secondary end therefore forward biases diode CR1. The secondary current

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starting from the upper secondary end flows through CR1, charges capacitor C, and returns through the loadimpedance RL back to the center-tap.

When Q2 conducts, Q1 goes high-impedance and the voltage polarities at the primary and secondary reverse.Now the lower end of the primary presents the open end with a 2×VIN potential against ground. In this case CR2is forward biased while CR1 is reverse biased and current flows from the lower secondary end through CR2,charging the capacitor and returning through the load to the center-tap.

7.3.2 Core Magnetization

Figure 7-2 shows the ideal magnetizing curve for a push-pull converter with B as the magnetic flux density and Has the magnetic field strength. When Q1 conducts the magnetic flux is pushed from A to A’, and when Q2conducts the flux is pulled back from A’ to A. The difference in flux and thus in flux density is proportional to theproduct of the primary voltage, VP, and the time, tON, it is applied to the primary: B ≈ VP × tON.

RDS

B

H

A

A’VIN VP

VDS

VIN= VP+VDS

Figure 7-2. Core Magnetization and Self-Regulation Through Positive Temperature Coefficient of RDS(on)

This volt-seconds (V-t) product is important as it determines the core magnetization during each switching cycle.If the V-t products of both phases are not identical, an imbalance in flux density swing results with an offset fromthe origin of the B-H curve. If balance is not restored, the offset increases with each following cycle and thetransformer slowly creeps toward the saturation region.

Fortunately, due to the positive temperature coefficient of a MOSFET’s on-resistance, the output FETs of theSN6501 have a self-correcting effect on V-t imbalance. In the case of a slightly longer on-time, the prolongedcurrent flow through a FET gradually heats the transistor which leads to an increase in RDS-on. The higherresistance then causes the drain-source voltage, VDS, to rise. Because the voltage at the primary is thedifference between the constant input voltage, VIN, and the voltage drop across the MOSFET, VP = VIN – VDS, VPis gradually reduced and V-t balance restored.

7.4 Device Functional ModesThe functional modes of the SN6501 are divided into start-up, operating, and off-mode.

7.4.1 Start-Up Mode

When the supply voltage at Vcc ramps up to 2.4 V typical, the internal oscillator starts operating at a startfrequency of 300 kHz. The output stage begins switching but the amplitude of the drain signals at D1 and D2 hasnot reached its full maximum yet.

7.4.2 Operating Mode

When the device supply has reached its nominal value ±10% the oscillator is fully operating. However variationsover supply voltage and operating temperature can vary the switching frequencies at D1 and D2 between 250kHz and 550 kHz for VCC = 3.3 V ±10%, and between 300 kHz and 620 kHz for VCC = 5 V ±10%.

7.4.3 Off-Mode

The SN6501 is deactivated by reducing VCC to 0 V. In this state both drain outputs, D1 and D2, are high-impedance.





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8 Application and ImplementationNote

Information in the following applications sections is not part of the TI component specification, and TIdoes not warrant its accuracy or completeness. TI’s customers are responsible for determiningsuitability of components for their purposes, as well as validating and testing their designimplementation to confirm system functionality.

8.1 Application InformationThe SN6501 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC converters utilizingthe push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary outputsignals which alternately turn the two output transistors on and off.

Vcc

GNDGND

D2

SN6501

D1S

S

G2

G1

fOSC Freq.

DividerOSC

BBM

LogicQ1

Q2

Q1 on Q2 on

Q2 off

tBBM

Q1 off

Figure 8-1. SN6501 Block Diagram And Output Timing With Break-Before-Make Action

The output frequency of the oscillator is divided down by an asynchronous divider that provides twocomplementary output signals, S and S, with a 50% duty cycle. A subsequent break-before-make logic inserts adead-time between the high-pulses of the two signals. The resulting output signals, G1 and G2, present the gate-drive signals for the output transistors Q1 and Q2. As shown in Figure 8-2, before either one of the gates canassume logic high, there must be a short time period during which both signals are low and both transistors arehigh-impedance. This short period, known as break-before-make time, is required to avoid shorting out bothends of the primary.

fOSC

S

S

G1

G2

Q1

Q2

Figure 8-2. Detailed Output Signal Waveforms

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8.2 Typical Application

Figure 8-3. Typical Application Schematic (SN6501)

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 8-1 as design parameters.

Table 8-1. Design ParametersDESIGN PARAMETER EXAMPLE VALUE

Input voltage range 3.3 V ± 3%

Output voltage 5 V

Maximum load current 100 mA

8.2.2 Detailed Design Procedure

The following recommendations on components selection focus on the design of an efficient push-pull converterwith high current drive capability. Contrary to popular belief, the output voltage of the unregulated converteroutput drops significantly over a wide range in load current. The characteristic curve in Figure 5-11 for exampleshows that the difference between VOUT at minimum load and VOUT at maximum load exceeds a transceiver’ssupply range. Therefore, in order to provide a stable, load independent supply while maintaining maximumpossible efficiency the implementation of a low dropout regulator (LDO) is strongly advised.

The final converter circuit is shown in Figure 8-7. The measured VOUT and efficiency characteristics for theregulated and unregulated outputs are shown in Figure 5-1 to Figure 5-28.

8.2.2.1 SN6501 Drive Capability

The SN6501 transformer driver is designed for low-power push-pull converters with input and output voltages inthe range of 3 V to 5.5 V. While converter designs with higher output voltages are possible, care must be takenthat higher turns ratios don’t lead to primary currents that exceed the SN6501 specified current limits.

Unlike SN6505 devices, SN6501 does not have soft-start, internal current limit, or thermal shutdown (TSD)features. Therefore to address possible unregulated or large currents, there is a limit to the maximum capacitiveload that can be connected to an SN6501 system. Loads exceeding 5uF appear as short circuits to SN6501during power up and may affect the device’s long-term reliability. When using SN6501, it is recommended tokeep capacitive loads below 5uF or incorporate LDOs with low short-circuit current limits or soft-start features toensure excessive current is not drawn from SN6501.

8.2.2.2 LDO Selection

The minimum requirements for a suitable low dropout regulator are:

• Its current drive capability should slightly exceed the specified load current of the application to prevent theLDO from dropping out of regulation. Therefore for a load current of 100 mA, choose a 100 mA to 150 mALDO. While regulators with higher drive capabilities are acceptable, they also usually possess higher dropoutvoltages that will reduce overall converter efficiency.

• The internal dropout voltage, VDO, at the specified load current should be as low as possible to maintainefficiency. For a low-cost 150 mA LDO, a VDO of 150 mV at 100 mA is common. Be aware however, that this




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lower value is usually specified at room temperature and can increase by a factor of 2 over temperature,which in turn will raise the required minimum input voltage.

• The required minimum input voltage preventing the regulator from dropping out of line regulation is givenwith:

VI-min = VDO-max + VO-max (1)

This means in order to determine VI for worst-case condition, the user must take the maximum values for VDOand VO specified in the LDO data sheet for rated output current (i.e., 100 mA) and add them together. Alsospecify that the output voltage of the push-pull rectifier at the specified load current is equal or higher thanVI-min. If it is not, the LDO will lose line-regulation and any variations at the input will pass straight through tothe output. Hence below VI-min the output voltage will follow the input and the regulator behaves like a simpleconductor.

• The maximum regulator input voltage must be higher than the rectifier output under no-load. Under thiscondition there is no secondary current reflected back to the primary, thus making the voltage drop acrossRDS-on negligible and allowing the entire converter input voltage to drop across the primary. At this point thesecondary reaches its maximum voltage of

VS-max = VIN-max × n (2)

with VIN-max as the maximum converter input voltage and n as the transformer turns ratio. Thus to prevent theLDO from damage the maximum regulator input voltage must be higher than VS-max. Table 8-2 lists the maximumsecondary voltages for various turns ratios commonly applied in push-pull converters with 100 mA output drive.

Table 8-2. Required Maximum LDO Input Voltages for Various Push-Pull ConfigurationsPUSH-PULL CONVERTER LDO

CONFIGURATION VIN-max [V] TURNS-RATIO VS-max [V] VI-max [V]3.3 VIN to 3.3 VOUT 3.6 1.5 ± 3% 5.6 6 to 10

3.3 VIN to 5 VOUT 3.6 2.2 ± 3% 8.2 10

5 VIN to 5 VOUT 5.5 1.5 ± 3% 8.5 10

8.2.2.3 Diode Selection

A rectifier diode should always possess low-forward voltage to provide as much voltage to the converter outputas possible. When used in high-frequency switching applications, such as the SN6501 however, the diode mustalso possess a short recovery time. Schottky diodes meet both requirements and are therefore stronglyrecommended in push-pull converter designs. A good choice for low-volt applications and ambient temperaturesof up to 85°C is the low-cost Schottky rectifier MBR0520L with a typical forward voltage of 275 mV at 100-mAforward current. For higher output voltages such as ±10 V and above use the MBR0530 which provides a higherDC blocking voltage of 30 V.

Lab measurements have shown that at temperatures higher than 100°C the leakage currents of the aboveSchottky diodes increase significantly. This can cause thermal runaway leading to the collapse of the rectifieroutput voltage. Therefore, for ambient temperatures higher than 85°C use low-leakage Schottky diodes, such asRB168M-40.

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Forward Voltage, V - VF

0.2 0.3 0.4 0.5

1

Fo

rwa

rd C

urr

en

t, I

-A

F

0.01

0.1

T = 125°CJ 25°C75°C -40°C

Forward Voltage, V - VF

0.20.1 0.3 0.4 0.5

1

Fo

rwa

rd C

urr

en

t, I

-A

F

0.01

0.1

T = 100°CJ 75°C 25°C-25°C

0°C

Figure 8-4. Diode Forward Characteristics for MBR0520L (Left) and MBR0530 (Right)





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8.2.2.4 Capacitor Selection

The capacitors in the converter circuit in Figure 8-7 are multi-layer ceramic chip (MLCC) capacitors.

As with all high speed CMOS ICs, the SN6501 requires a bypass capacitor in the range of 10 nF to 100 nF.

The input bulk capacitor at the center-tap of the primary supports large currents into the primary during the fastswitching transients. For minimum ripple make this capacitor 1 μF to 10 μF. In a 2-layer PCB design with adedicated ground plane, place this capacitor close to the primary center-tap to minimize trace inductance. In a 4-layer board design with low-inductance reference planes for ground and VIN, the capacitor can be placed at thesupply entrance of the board. To ensure low-inductance paths use two vias in parallel for each connection to areference plane or to the primary center-tap.

The bulk capacitor at the rectifier output smoothes the output voltage. Make this capacitor 1 μF to 10 μF.

The small capacitor at the regulator input is not necessarily required. However, good analog design practicesuggests, using a small value of 47 nF to 100 nF improves the regulator’s transient response and noiserejection.

The LDO output capacitor buffers the regulated output for the subsequent isolator and transceiver circuitry. Thechoice of output capacitor depends on the LDO stability requirements specified in the data sheet. However, inmost cases, a low-ESR ceramic capacitor in the range of 4.7 μF to 10 μF will satisfy these requirements.

8.2.2.5 Transformer Selection8.2.2.5.1 V-t Product Calculation

To prevent a transformer from saturation its V-t product must be greater than the maximum V-t product appliedby the SN6501. The maximum voltage delivered by the SN6501 is the nominal converter input plus 10%. Themaximum time this voltage is applied to the primary is half the period of the lowest frequency at the specifiedinput voltage. Therefore, the transformer’s minimum V-t product is determined through:

max IN-maxmin IN-max

min

T VVt V =

2 2 f³ ´

´ (3)

Inserting the numeric values from the data sheet into the equation above yields the minimum V-t products of

.

min

min

3.6 VVt = 7.2 Vμs for 3.3 V, and

2 250 kHz

5.5 VVt = 9.1Vμs for 5 V applications

2 300 kHz

³

´

³

´ (4)

Common V-t values for low-power center-tapped transformers range from 22 Vμs to 150 Vμs with typicalfootprints of 10 mm x 12 mm. However, transformers specifically designed for PCMCIA applications provide aslittle as 11 Vμs and come with a significantly reduced footprint of 6 mm x 6 mm only.

While Vt-wise all of these transformers can be driven by the SN6501, other important factors such as isolationvoltage, transformer wattage, and turns ratio must be considered before making the final decision.

8.2.2.5.2 Turns Ratio Estimate

Assume the rectifier diodes and linear regulator has been selected. Also, it has been determined that thetransformer choosen must have a V-t product of at least 11 Vμs. However, before searching the manufacturerwebsites for a suitable transformer, the user still needs to know its minimum turns ratio that allows the push-pullconverter to operate flawlessly over the specified current and temperature range. This minimum transformationratio is expressed through the ratio of minimum secondary to minimum primary voltage multiplied by a correctionfactor that takes the transformer’s typical efficiency of 97% into account:

VS-min must be large enough to allow for a maximum voltage drop, VF-max, across the rectifier diode and stillprovide sufficient input voltage for the regulator to remain in regulation. From the LDO SELECTION section, thisminimum input voltage is known and by adding VF-max gives the minimum secondary voltage with:

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VS-min = VF-max + VDO-max + VO-max (5)

Q

VIN

VF

RL

RDSVDS

VDO

VP

VI VO

VS

Figure 8-5. Establishing the Required Minimum Turns Ratio Through Nmin = 1.031 × VS-min / VP-min

Then calculating the available minimum primary voltage, VP-min, involves subtracting the maximum possibledrain-source voltage of the SN6501, VDS-max, from the minimum converter input voltage VIN-min:

VP-min = VIN-min – VDS-max (6)

VDS-max however, is the product of the maximum RDS(on) and ID values for a given supply specified in theSN6501 data sheet:

VDS-max = RDS-max × IDmax (7)

Then inserting Equation 7 into Equation 6 yields:

VP-min = VIN-min - RDS-max x IDmax (8)

and inserting Equation 8 and Equation 5 into Equation 9 provides the minimum turns ration with:

F-max DO-max O-maxmin

IN-min DS-max D-max

V + V + Vn = 1.031

V R I´

- ´ (9)

Example:

For a 3.3 VIN to 5 VOUT converter using the rectifier diode MBR0520L and the 5 V LDO TPS76350, the datasheet values taken for a load current of 100 mA and a maximum temperature of 85°C are VF-max = 0.2 V,VDO-max = 0.2 V, and VO-max = 5.175 V.

Then assuming that the converter input voltage is taken from a 3.3 V controller supply with a maximum ±2%accuracy makes VIN-min = 3.234 V. Finally the maximum values for drain-source resistance and drain current at3.3 V are taken from the SN6501 data sheet with RDS-max = 3 Ω and ID-max = 150 mA.

Inserting the values above into Equation 9 yields a minimum turns ratio of:

min

0.2V + 0.2V + 5.175 Vn = 1.031 = 2

3.234 V 3 Ω 150 mA´

- ´ (10)

Most commercially available transformers for 3-to-5 V push-pull converters offer turns ratios between 2.0 and 2.3with a common tolerance of ±3%.





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8.2.2.5.3 Recommended Transformers

Depending on the application, use the minimum configuration in Figure 8-6 or standard configuration in Figure8-7.

1 Fµ

VIN

MBR0520L

MBR0520L

T13

1

SN6501

5

2

4

TP1

0.1µF

D2

D1

VCC

GND

GND

Figure 8-6. Unregulated Output for Low-CurrentLoads With Wide Supply Range

Figure 8-7. Regulated Output for Stable Suppliesand High Current Loads

The Wurth Electronics Midcom isolation transformers in Table 8-3 are optimized designs for the SN6501,providing high efficiency and small form factor at low-cost.

The 1:1.1 and 1:1.7 turns-ratios are designed for logic applications with wide supply rails and low load currents.These applications operate without LDO, thus achieving further cost-reduction.

Table 8-3. Recommended Isolation Transformers Optimized for SN6501TurnsRatio

V x T(Vμs)

Isolation(VRMS)

Dimensions(mm) Application LDO Figures Order No. Manufacturer

1:1.1 ±2% 7

2500 6.73 x 10.05 x 4.19

3.3 V → 3.3 V

No

Figure 5-1Figure 5-2 760390011

WurthElectronics/

Midcom

1:1.1 ±2%

11

5 V → 5 V Figure 5-3Figure 5-4 760390012

1:1.7 ±2% 3.3 V → 5 V Figure 5-5Figure 5-6 760390013

1:1.3 ±2% 3.3 V → 3.3 V5 V → 5 V

Yes

Figure 5-7Figure 5-8Figure 5-9Figure 5-10

760390014

1:2.1 ±2% 3.3 V → 5 V Figure 5-11Figure 5-12 760390015

1.23:1 ±2% 5 V → 3.3 V Figure 5-13Figure 5-14 750313710

1:1.1 ±2%

11 5000 9.14 x 12.7 x 7.37

3.3 V → 3.3 V

No

Figure 5-15Figure 5-16 750313734

1:1.1 ±2% 5 V → 5 V Figure 5-17Figure 5-18 750313734

1:1.7 ±2% 3.3 V → 5 V Figure 5-19Figure 5-20 750313769

1:1.3 ±2% 3.3 V → 3.3 V5 V → 5 V

Yes

Figure 5-21Figure 5-22Figure 5-23Figure 5-24

750313638

1:2.1 ±2% 3.3 V → 5 V Figure 5-25Figure 5-26 750313626

1.3:1 ±2% 5 V → 3.3 V Figure 5-27Figure 5-28 750313638

1:1.3 ±3% 11 5000 10.4 x 12.2 x 6.1 3.3 V → 3.3 V5 V → 5 V No N/A HCT-SM-1.3-8-2 Bourns

1:1.1 ±2% 9.2 2500 7.01 x 11 x 4.19 3.3 V → 3.3 V5 V → 5 V No N/A EPC3668G-LF PCA Electronics

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Table 8-3. Recommended Isolation Transformers Optimized for SN6501 (continued)TurnsRatio

V x T(Vμs)

Isolation(VRMS)

Dimensions(mm) Application LDO Figures Order No. Manufacturer

1:1.5 ±3% 34.4 2500 10 x 12.07 x 5.97 3.3 V → 3.3 V5 V → 5 V Yes N/A

DA2303-ALCoilcraft

1:2.2 ±3% 21.5 2500 10 x 12.07 x 5.97 3.3 V → 5 V DA2304-AL





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8.2.3 Application Curve

See Table 8-3 for application curves.

8.2.4 Higher Output Voltage Designs

The SN6501 can drive push-pull converters that provide high output voltages of up to 30 V, or bipolar outputs ofup to ±15 V. Using commercially available center-tapped transformers, with their rather low turns ratios of 0.8 to5, requires different rectifier topologies to achieve high output voltages. Figure 8-8 to Figure 8-11 show some ofthese topologies together with their respective open-circuit output voltages.

n

VINVOUT+ = n·VIN

VOUT- = n·VIN

Figure 8-8. Bridge Rectifier With Center-TappedSecondary Enables Bipolar Outputs

n

VINVOUT =2n·VIN

Figure 8-9. Bridge Rectifier Without Center-TappedSecondary Performs Voltage Doubling

n

VIN

VOUT+ =2n·VIN

VOUT- =2n·VIN

Figure 8-10. Half-Wave Rectifier Without Center-Tapped Secondary Performs Voltage Doubling,

Centered Ground Provides Bipolar Outputs

n

VIN

VOUT =4n·VIN

Figure 8-11. Half-Wave Rectifier Without CenteredGround and Center-Tapped Secondary PerformsVoltage Doubling Twice, Hence Quadrupling VIN

8.2.5 Application Circuits

The following application circuits are shown for a 3.3 V input supply commonly taken from the local, regulatedmicro-controller supply. For 5 V input voltages requiring different turn ratios refer to the transformermanufacturers and their websites listed in Table 8-4.

Table 8-4. Transformer ManufacturersCoilcraft Inc. http://www.coilcraft.com

Halo-Electronics Inc. http://www.haloelectronics.com

Murata Power Solutions http://www.murata-ps.com

Wurth Electronics Midcom Inc http://www.midcom-inc.com

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http://www.haloelectronics.com

http://www.murata-ps.com

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Figure 8-12. Isolated RS-485 Interface





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Figure 8-13. Isolated Can Interface

Figure 8-14. Isolated RS-232 Interface

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Figure 8-15. Isolated Digital Input Module

Figure 8-16. Isolated SPI Interface for an Analog Input Module With 16 Inputs





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Figure 8-17. Isolated I2C Interface for an Analog Data Acquisition System With 4 Inputs and 4 Outputs

VCC1 VCC2

GND1 GND2

INA

8

7

6

4 54

XOUT

XIN

5

6

2

MSP430

G2132

OUTA

1

2

3ISO7421

DVSS

DVCC

INB OUTB

P3.0

P3.1

11

12

10 �F

VS

0.1 �F

MBR0520L

MBR0520L

1:1.33

0.1 �F

3

1

D2

SN6501

D1

VCC

4, 5

2

GND

3.3 V

IN

EN GND

OUT1 5

23

TPS7633310 �F

3.3VISO

10 �F

ISO-BARRIER

0.1 �F 0.1 �F0.1 �F

0.1 �F

3

VD

COMA

BASELOW10

8ERRLVL

DBACK

16

DIN

DAC161P997

OUT9

C1

14

15

VA

COMD

2

C2

13

C3

12

3 × 22 nF

5

4

20 0.1 �F

22

0.1 �F 1 �F

LOOP±

LOOP+

1

Figure 8-18. Isolated 4-20 mA Current Loop

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9 Power Supply RecommendationsThe device is designed to operate from an input voltage supply range between 3.3 V and 5 V nominal. This inputsupply must be regulated within ±10%. If the input supply is located more than a few inches from the SN6501 a0.1 μF by-pass capacitor should be connected as possible to the device VCC pin, and a 10 μF capacitor shouldbe connected close to the transformer center-tap pin.





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10 Layout10.1 Layout Guidelines• The VIN pin must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended

capacitor value can range from 1 μF to 10 μF. The capacitor must have a voltage rating of 10 V minimum anda X5R or X7R dielectric.

• The optimum placement is closest to the VIN and GND pins at the board entrance to minimize the loop areaformed by the bypass-capacitor connection, the VIN terminal, and the GND pin. See Figure 10-1 for a PCBlayout example.

• The connections between the device D1 and D2 pins and the transformer primary endings, and theconnection of the device VCC pin and the transformer center-tap must be as close as possible for minimumtrace inductance.

• • The connection of the device VCC pin and the transformer center-tap must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF. Thecapacitor must have a voltage rating of 16 V minimum and a X5R or X7R dielectric.

• The device GND pins must be tied to the PCB ground plane using two vias for minimum inductance.• The ground connections of the capacitors and the ground plane should use two vias for minimum inductance.• The rectifier diodes should be Schottky diodes with low forward voltage in the 10 mA to 100 mA current range

to maximize efficiency.• The VOUT pin must be buffered to ISO-Ground with a low-ESR ceramic bypass-capacitor. The recommended

capacitor value can range from 1μF to 10 μF. The capacitor must have a voltage rating of 16 V minimum anda X5R or X7R dielectric.

10.2 Layout Example

Figure 10-1. Layout Example of a 2-Layer Board (SN6501)

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11 Device and Documentation Support11.1 Device Support11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOTCONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICESOR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHERALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 TrademarksAll trademarks are the property of their respective owners.11.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits maybe more susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.

11.4 GlossaryTI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.




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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

SN6501DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 6501

SN6501DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 6501

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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PACKAGE OPTION ADDENDUM

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Addendum-Page 2

OTHER QUALIFIED VERSIONS OF SN6501 :

• Automotive: SN6501-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

SN6501DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3

SN6501DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN6501DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0

SN6501DBVT SOT-23 DBV 5 250 180.0 180.0 18.0

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 2

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PACKAGE OUTLINE

C

0.220.08 TYP

0.25

3.02.6

2X 0.95

1.9

1.450.90

0.150.00 TYP

5X 0.50.3

0.60.3 TYP

80 TYP

1.9

A

3.052.75

B1.751.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005ASMALL OUTLINE TRANSISTOR

4214839/F 06/2021

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice.3. Refernce JEDEC MO-178.4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side.

0.2 C A B

1

34

5

2

INDEX AREAPIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

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EXAMPLE BOARD LAYOUT

0.07 MAXARROUND

0.07 MINARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/F 06/2021


NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE:15X

PKG

1

3 4

5

2

SOLDER MASKOPENINGMETAL UNDER

SOLDER MASK

SOLDER MASKDEFINED

EXPOSED METAL

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

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EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP


4214839/F 06/2021

NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

1

3 4

5

2

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