Switched-current wave group delay equalisers

Y. Xie and B.M. Al-Hashimi

Abstract: To improve the elliptic filter step response, group delay equalisers are often cascadedwith the filters. The paper describes the design of switched-current (SI) group delay equalisers usingthe wave synthesis technique. This design is based on a new all-pass circuit, where the poles aregenerated using wave structures. Simulation results are included demonstrating that the 3rd-orderSI group delay equaliser can reduce the amount of overshoot in the 100kHz elliptic low-pass filterstep response byZ50%. This is as a result of reducing the filter group delay variation from 2.29msto 0.32ms when the group delay equaliser is employed.

1 Introduction

Switched-current (SI) is becoming a viable alternative toswitched-capacitor technology, particularly in low voltageanalogue circuit design [1]. Numerous design methods forSI filters have been reported [2–6]. Communicationsapplications often call for filters with high stop-bandattenuation and linear phase or flat group delay (derivateof phase with respect to frequency) response in the pass-band. To design sharp filters with low component count,elliptic approximation is normally used. However, ellipticfilters have nonlinear phase and non-flat group delayresponse, resulting in excessive overshoot in the filter stepresponse. For example, it was reported in [7] that the stepresponse of 7th-order elliptic low-pass filters with stop-bandattenuation of 445dB has 430% overshoot when it isdriven by a 100kHz square waveform. Such an overshoot isoften unacceptable in most communication applications.An approach to improve the filter step response (i.e. reducethe overshoot) is to cascade filters with a group delayequaliser or an all-pass circuit. The function of the all-passcircuit is to flatten the filter group delay response withoutchanging the magnitude of the filter characteristics.

While much research has been carried out in SI filterdesigns [2–6], very little work has been reported on thedesign of group delay equalisers using SI technology. Torealise the full potential of SI technology in analogue signalprocessing, design methods for SI group delay equalisationsare needed. Recently, an integrator-based design methodfor SI group delay equalisers derived from LC prototypeswas reported [8]. However, the application of the wavesynthesis technique [9] to design SI filters provides circuitsthat can be easily implemented [5, 6] when compared withintegrator-based filters [2, 3]. This is because SI wave filtersconsist of only delay cells and wave adaptors, which arereadily available in SI technology. The aim of this paper isto investigate the design of SI group delay equalisers basedon the wave synthesis technique.

2 New all-pass wave circuit architecture

The general z-domain transfer function of an Nth-ordergroup delay equaliser is [10]

HðzÞ ¼ � aN zN þ aN�1zN�1 þ � � � þ a1zþ 1

zN þ a1zN�1 þ � � � þ aN�1zþ aN

¼�

PN

k¼0akzk

PN

k¼0akzN�k

; a0 ¼ 1

ð1Þ

where the poles and zeros of H(z) are reciprocals of oneanother. According to ladder-based realisation of the all-pass filter [11], the general z-domain transfer function H(z)can be rearranged as

HðzÞ ¼ 1� 2

1þ Y ðzÞ ð2Þ

where Y(z) is a polynomial function which can be expandedinto a continued fraction [11].

Numerous implementations of (2) have been reported,including OTA-C [7] and switched-capacitor realisation [10].In this paper, SI implementation of (2) is proposed asshown in Fig. 1. The circuit operates as follows.

ini

M1 M3M2 M5M4

oi

1 : 2 : 1 1 : 1

M8M7

Y (z)

1i

M6

:11 : 1

Fig. 1 SI wave all-pass circuit architecture

Y. Xie was with the School of Electronics and Computer Science, University ofSouthampton, UK and is now with Infineon Technology, Xi’an, People’sRepublic of China

B.M. Al-Hashimi is with the Electronics System Design Group, School ofElectronics and Computer Science, University of Southampton, Highfield,Southampton SO17 1BJ, UK

r IEE, 2004

IEE Proceedings online no. 20040501

doi:10.1049/ip-cds:20040501

Paper first received 12th May and in revised form 22nd December 2003.Originally published online: 22nd September 2004

IEE Proc.-Circuits Devices Syst., Vol. 151, No. 6, December 2004 551

The circuit input current iin is inverted and multiplied bya gain of 2 through current mirror (M1–M2). This amplifiedcurrent is summed with the output of block Y(z) and fedinto the current mirror M6, M7–M8. One inverted currentcopy of this current mirror is sent to the input of block Y(z),whose output is fed back into current mirror M6–M8.Another inverted current copy is summed with the invertedcurrent copy of iin and sent to current mirror (M4–M5),whose output is current io. The architecture operation canbe summarised by the following equations:

�2iin � i1Y ðzÞ ¼ i1 ð3Þfrom which we obtain

i1 ¼ �2iin=ð1þ Y ðzÞÞ ð4ÞThe circuit output current is

io ¼ iin þ i1 ð5ÞSubstituting (3) into (5) produces the all-pass transferfunction (2), confirming that Fig. 1 realises (2).

Since Y(z) can be expanded into continued fractions [8,10, 11], (6), it is analogous to a driving-point admittance,which can be synthesised as an LC ladder circuit, Fig. 2:

Y ðzÞ ¼ C1lþ1

L2lþ 1

..

.

1CN l

ð6Þ

where l¼ (2/T )(1�z�1)(1+z�1) and Ci, Li40,i¼ 1,2,y N.

The circuit in Fig. 1 realises an all-pass function, wherethe order and pole positions are determined by Y(z). In thispaper, we propose to convert the LC ladder network ofFig. 2 to an SI circuit using a wave synthesis technique. Thisis because the resultant SI circuit has the benefits ofimplementation simplicity and the elimination of integratorsas outlined in [5, 6]. The wave synthesis technique simulatesthe behaviour of LC networks through the use of wavequantities instead of port voltages and current. The wavevariables Ak (incident wave) and Bk (reflected wave) aredefined as linear combinations of the corresponding portcurrent Ik and voltage Vk:

Ak ¼ Vk þ IkRk ð7aÞ

Bk ¼ Vk � IkRk ð7bÞwhere Rk is the port resistance, and is chosen arbitrarily tosimplify the wave model. For the passive components R, L

and C, their port resistances are R, 2L/T and T/2C,respectively.

Wave adaptors model the reflections caused by theparallel or series connections of the passive componentswithin the prototype filter. Figure 3 shows the Nth-orderequivalent wave structure of the LC ladder network inFig. 2 (the reader can refer to [9] for more details on wavefilter design).

This wave structure consists of delay cells, and series andparallel adaptors, where gij is the coefficient of port j inadaptor i. The wave adaptor coefficients g are calculatedusing the following expressions, which must be satisfied foreach M-port adaptor:

XM�1

k¼0gk ¼ 2 ð8Þ

M-port series adaptors:

g0R0¼ g1

R1¼ � � � ¼ gM�1

RM�1ð9Þ

M-port parallel adaptors:

g0G0¼ g1

G1¼ � � � ¼ gM�1

GM�1ð10Þ

where Rk and Gk are the port resistance and conductance ofport k.

3 Design of SI wave group delay equalisers

The design flow of the SI wave group delay equalisers isshown in Fig. 4. It consists of four steps.

Step 1 involves finding an all-pass circuit transferfunction, H(z), given by (1), whose delay response equalisesthe filter group delay variation by minimising the groupdelay ripple of the combined filter and group delayequaliser. The inputs of the first step are: filter group delayvariation to be equalised specified in the form of data points

NC

N−1L2L

1C 3C . . .Y (z)

Fig. 2 Nth-order LC ladder network

Step 1

Step 2

Step 3

Step 4

wave adaptor coefficients of SI groupdelay equaliser

z-domain allpass transferfunction identification

derivation of Y (z)from H (z)

synthesis of Y (z)

conversion of LC towave structure

filter equaliserorder

required groupdelay ripplegroup delay

Fig. 4 Design flow for SI wave group delay equaliser

. . .00

γ02γ

01γ

10 γ

12γ

11γ

T

1C

T

2L

TT

T

N−2C

N−1L

NC(N−3)2

delay cellnegativedelay cell

3-portseries adaptor

3-portparallel adaptor

Y (z) γ

(N−2)0γ (N−2)1

γ (N−3)0

γ (N−3)1γ

Fig. 3 Y(z) realisation using wave synthesis technique

552 IEE Proc.-Circuits Devices Syst., Vol. 151, No. 6, December 2004

(frequency, delay), the order of equaliser N, and therequired final group delay ripple. The transfer function ofthe all-pass circuit is produced using an optimisationalgorithm based on a curve-matching approximation asoutlined in [7]. To facilitate the optimisation process, the all-pass transfer function is expressed in terms of magnitude Rand phase y , and then rearranged into the form of (1). Forthe 1st-order and 2nd order all-pass sections, the groupdelay expressions are:

t1ðoÞ ¼T ð1� R2Þ

1þ 2R cosðoT Þ þ R2ð11aÞ

t2ðoÞ ¼T ð1� R2Þ

1� 2R cosðoT � yÞ þ R2

þ T ð1� R2Þ1� 2R cosðoT þ yÞ þ R2

ð11bÞ

where T is the sampling period and Ro1.The group delay of the equaliser is the sum of the

individual group delays in (11):

tðoÞ ¼ t1ðoÞ þXk

i¼1t2iðoÞ ð12Þ

where the order of H(z) is N¼ 2k+1.Step 2 involves obtaining Y(z) from H(z) according to (2),

whilst step 3 carries out the synthesis of Y(z) to obtain theLC values of the ladder network (C1, L2,y,CN) – equation(6). Step 4 derives the wave adaptor coefficients of the SIwave equaliser using (9) from the LC component valuesproduced by Step 3. To automate the design process of SIwave group delay equalisers, the design flow of Fig. 4 hasbeen incorporated into MATLAB.

To demonstrate the design flow, three different groupdelay equalisers have been designed to equalise the groupdelay variation of the 3rd-order normalised low-pass ellipticSI filter. The group delay and frequency data of the low-pass filter are fed into step 1 of the design process. Table 1shows the optimisation result of different group delayequalisers. It can be seen that the combined ripple of thefilter and group delay equaliser decreases as the order of theequaliser increases, as expected.

As an example of the z-domain transfer function H(z) ofthe group delay equaliser, (13) shows the transfer functionof the 7th-order equaliser is

HðzÞ

¼ z�7þa1z�6þa2z�5þa3z�4þa4z�3þa5z�2þa6z�1þa7

a7z�7þa6z�6þa5z�5þa4z�4þa3z�3þa2z�2þa1z�1þ1ð13Þ

where a1¼�2.7, a2¼ 3.684, a3¼�3.378, a4¼ 2.176,a5¼�0.921, a6¼ 0.226, and a7¼�0.024.

Figure 5 gives a z-domain pole–zero plot of this equaliser.As can be seen, the poles and zeros are reciprocals of oneanother, confirming the correct theoretical design of thegroup delay equaliser. The wave adaptor coefficients of thegroup delay equaliser are derived from the obtained H(z)according to the design flow. The results are given inTable 2.

4 Simulation examples

Elliptic filter step response often has excessive overshoot,mainly because such filters have large variations (ripple) intheir group delay response. To demonstrate the effectivenessof the design method outlined in Section 3, considerreducing the group delay ripple of the 3rd-order 100kHzlow-pass elliptic SI filter (1MHz sampling frequency) from42ms to o0.35ms when a suitable group delay equaliser iscascaded with the filter. Using the design flow presented inSection 3, it is found that a 3rd-order group delay equaliseris needed to achieve the required delay ripple. The equaliser

Table 1: Optimisation result of different order equalisers

Third-order low-pass elliptic SI filter, cutoff frequency¼0.1Hz,normalized (T¼1s) group delay ripple¼ 2.294s (DC to cutofffrequency)

3rd-order equaliser Combined filter and equaliser ripple¼0.275s

5th-order equaliser Combined filter and equaliser ripple¼0.193s

7th-order equaliser Combined filter and equaliser ripple¼0.162s

1.0

1.0 1.5 2.0

0.5

0.5

0

0

−0.5

−1.0

−1.0 −0.5

imag

inar

y pa

rt

real part

Fig. 5 z-plane pole–zero plot of 7th-order group delay equaliser

Table 2: Adaptor coefficients of 7th-order group delayequaliser

gN¼ 0.8 g01¼ 0.8 g02¼0.4

g10¼0.6 g11¼ 0.6 g12¼0.8

g20¼0.533 g21¼ 0.533 g22¼0.934

g30¼0.51 g31¼ 0.51 g32¼0.98

g40¼0.5 g41¼ 0.1 g42¼1.4

g50¼0.054 g51¼ 1.946

io−1

ini1i

−1

CM

(−1)/(−2 ) 2

1C

Y(z)

1i Y(z)−00γ

02γ

01γ

2LT3C

T10 γ11γ

T

Fig. 6 Block diagram of 3rd-order SI wave equaliser

IEE Proc.-Circuits Devices Syst., Vol. 151, No. 6, December 2004 553

transfer function is

HðzÞ ¼ z�3 þ a1z�2 þ a2z�1 þ a3

a3z�3 þ a2z�2 þ a1z�1 þ 1ð14Þ

where a1¼�0.3314, a2¼�0.686, a3¼ 0.38.From which the adaptor coefficients of the wave

structure are calculated as g00¼ 1.0536, g01¼ 0.838,

g02¼ 0.1084, g10¼ 0.1314 and g11¼ 1.8686. Figure 6 showsthe block diagram of the equaliser, where the block‘CM(�1)/(�2)’ means a current mirror with two outputs:(�1) and (�2), corresponding to Fig. 1.

Based on first-generation delay cells [12] and waveadaptors in [13], Fig. 7 gives the SI realisation of the 3rd-order wave equaliser. The input to wave block Y(z) is

1 1: : 2

ini oi

2 1

00γ 01γ 02γ 1 1: : 1 1: :1 1: :

2 φ1φ 2φ

φ φ

1φ

1 1: : 1 1: :10γ 11

γ

1 1: 1: 1 1:

1 1:1 1:1 1:

1 1:

1 1:

1: 1:

1: 1:

1:

waveconverters

input-outputcurrent mirrors

3-port parallel adaptor

delay cell delay cell

delay cell

2-port parallel adaptor

Fig. 7 Transistor level circuit of 3rd-order SI wave equaliser

554 IEE Proc.-Circuits Devices Syst., Vol. 151, No. 6, December 2004

characterised by wave quantities Ak and Bk. However, asFig. 1 shows, the all-pass circuit architecture requirescurrent signal input to the block Y(z). So the waveconverter is added to Fig. 7 for converting the currentsignal to the wave quantities of block Y(z). To improve theequaliser performance, cascode current mirrors wereemployed throughout the equaliser SI design. Figure 8ashows a cascode current mirror, while Fig. 8b shows acascode based first-generation delay cell. To reduce clock-feedthrough effects in the SI equaliser, CMOS switches wereused. Fig. 8c shows the circuit used for the switches in thetransistor-level circuit of a 3rd-order group delay equaliser,Fig. 7. The wave adaptor coefficients are implementedthrough the ratio aspects (W/L) of the current mirrors asshown in Table 3.

Figure 9 shows SCNAP4 [14] simulation of the groupdelay response of the filter, equaliser, and combined filterand equaliser. As can be seen, the filter alone has groupdelay variation of almost 2.29ms between DC and 100kHz.Cascading the filter with the individual equalisers show thatthe combined filter and equaliser group delay ripple reducesto 0.32ms. Note the simulated filter was designed using theSI technology outlined in [6].

It has been demonstrated that group delay equalisersderived from a ladder-based structure have low amplitudesensitivity [10]. Since the design method given in this paperstarts with ladder-based circuits, it is expected that thegroup delay wave equaliser has similar low amplitude

sensitivity to that reported in [10]. Filters with large groupdelay variations or nonlinear phase lead to waveformdistortion in the form of overshoot in the step response.Using typical 1.2mm CMOS process parameters providedby AMS, SPICE level 2 transistor models, bias current of100mA, and VDD¼ 3.3V, Fig. 10, trace (i) shows a PSPICEstep response of the 3rd-order elliptic SI filter when it isdriven by a 10mA input step signal. The response hasalmost 15% overshoot in this case. Trace (ii) shows thesame filter step response but in this case the 3rd-orderequaliser circuit discussed earlier has been cascaded with thefilter. It can be seen that the equaliser has resulted inreducing the amount of overshoot present in the filter stepresponse by more than 50%.

4.1 High order group delay equalisersTo obtain higher order SI equalisers using the proposed all-pass circuit architecture (Fig. 1) than the third orderconsidered only requires replacing the driving-point admit-tance Y(z) of Fig. 3 with the required order of wavestructure generated as outlined in Fig. 4. Expanding Y(z)

DDV+ DDV+

:1 1

144/7.2 144/7.2

117/3.6

144/3.6

72/7.2 72/7.2

144/3.6

117/3.6

1.85v

0.3v

2v oi oi

outi

ini ini

ini

102/10.2

2v 2v

0.3v 0.3v

1.85v 1.85v

144/3.6

94.8/3.6

144/7.2

94.8/3.6

144/3.6

102/10.2

144/7.2

94.8/3.6

144/3.6

102/10.2

144/7.2

2.4/1.2

3.6/1.2

2,1φ

2,1φ φ

φ

nMOS

pMOS

(n+1)2

1

n

φ 1 φ 2

a b

c

Fig. 8 Cascode current mirror, delay cell and CMOS switcha Cascode current mirrorb Current delay cellc CMOS switch and clock phase

Table 3: Coefficients and W/L of 3rd-order SI waveequaliser

Port gij W/L

g00 1.0536 76/7.2

g01 0.838 60.3/7.2

g02 0.1084 7.8/7.2

g10 0.1314 9.5/7.2

g11 1.8686 134.5/7.2

Other transistors in current mirror have W/L¼ 72mm/7.2mm

filter

frequency, kHz0 80 100604020

4

10

6

2

8

grou

p de

lay,

µs

0 80 1006040209.7

9.8

9.9

10.0

3rd-order equaliser

filter cascade with 3rd-order equaliser

Fig. 9 Group delay response of filter, equaliser and filter cascadewith 3rd-order equaliser

IEE Proc.-Circuits Devices Syst., Vol. 151, No. 6, December 2004 555

into 5th and 7th-order wave structures, the circuits of 5thand 7th-order SI wave equalisers are designed andsimulated, as shown in Fig. 11. It can be seen that thecombined group delay variation is reduced to 0.196 ms and0.164ms for the 5th and 7th-order SI wave equalisers,respectively. Note that the inclusion of a group delayequaliser with a filter increases the propagation delay of thefilter, for example the filter propagation delay is B15.4mswhen the 7th-order equaliser is connected (Fig. 11, com-pared to 2.1 ms when no equaliser is connected (Fig. 9). Thisincrease in propagation delay needs to be consideredcarefully in certain applications, and may be reduced duringStep 1 of the design flow of Fig. 4, if the delay is input as aconstraint in the optimisation process.

To give insight into the complexity of SI equalisersobtained from the proposed all-pass circuit, expressions forpredicting the transistor count of a given order equaliserhave been developed. The SI circuit complexity depends onthe order of equaliser, N, and the details are given inTable 4.

This Table shows the input–output current mirror blocksand wave converters are required for the all-pass circuits. Asoutlined in Section 4, one positive delay cell, implementedwith the first-generation cascode structure, has 16 transis-tors. The transistor numbers of one negative delay cell, 3-port series adaptor, 3-port parallel adaptor and 2-port seriesadaptor are 24, 76, 52 and 36, respectively. It can becalculated that the number of transistors in an even order SIequaliser is (84N�28). Similarly, the number of transistorsin an odd order SI equaliser is (84N�52). For example, ifthe order of SI wave equaliser is 6, its total transistor count

is 476. The power consumption of this simulated 3rd-orderSI equaliser circuit is 18.6mW.

5 Conclusions

This paper has presented a design method for group delayequalisers derived from an all-pass ladder circuit using wavesynthesis technique and implemented in SI technology. Thismethod is based on introducing a new all-pass circuit, wherewave structures are employed to generate circuit transferfunctions. Detailed simulation results based on cascode SIdelay cells and wave adaptors for different equaliser ordershave been included confirming the effectiveness of thepresented design method in improving the step response oflow-pass elliptic filters.

6 Acknowledgments

The authors wish to thank the Engineering and PhysicalResearch Council (EPSRC) for funding this researchproject, under grant reference number GR/N31900.

7 References

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2 Fiez, T.S., and Allstot, D.J.: ‘CMOS switched-current ladder filters’,IEEE J. Solid-State Circuits, 1990, 25, (6), pp. 1360–1367

3 De Queiroz, A.C.M., and Pinheiro, P.M.: ‘Bilinear switched-currentladder filters using Euler integrators’, IEEE Trans. Circuits Syst. II,Analog Digit. Signal Process., 1996, 43, (1), pp. 66–70

4 Hughes, J.B.: ‘Top-down design of a switched-current video filter’,IEE Proc., Circuits Devices Syst., 2000, 147, (1), pp. 73–81

5 Yufera, A., Rueda, A., and Huertas, J.L.: ‘Switched-current waveanalogue filters’. Proc. ISCAS, 1998, pp. 1471–1474

6 Lancaster, J.D., Al-Hashimi, B.M., andMoniri, M.: ‘Efficient SI waveelliptic filters based on direct and inverse Bruton transformations’,IEE Proc., Circuits Devices Syst., 1999, 146, (5), pp. 235–241

7 Al-Hashimi, B.M., Dudek, F., and Moniri, M.: ‘Current-mode groupdelay equalization using pole-zero mirroring technique’, IEE Proc.,Circuits Devices Syst., 2000, 147, (4), pp. 257–263

8 Ng, A.E.J., and Sewell, J.I.: ‘Synthesis of switched-current ladderderived group delay equalisers’. Proc. IEE Analogue Signal ProcessingSymp., Oxford, UK, 1 November 2000, pp. 9/1–9/8

9 Fettweis., A.: ‘Wave digital filter: theory and practice’, Proc. IEEE,1986, 74, (2), pp. 270–327

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13 Jonsson, B., and Eriksson, S.: ‘Current-mode N-port adaptors forwave SI filters’, Electron. Lett., 1993, 29, (10), pp. 925–926

14 Shang, Z.Q., and Sewell, J.I.: ‘SCNAP4 user’s guide version 1.9’.Dept. of Electronics and Electrical Engineering, University ofGlasgow, UK

0 5 10 15 20 25

time, µs

12

8

4

0

−4

curr

ent,

µA(i)

(ii)

Fig. 10 Step response of filter and filter cascade with 3rd-orderequaliser

frequency, kHz0 80 100604020

14

11

12

13

grou

p de

lay,

µs

15

0 80 100604020

8 80 100604020

15.3

15.4

filter cascade with 5th-order equaliser

filter cascade with 7th-order equaliser

15.5

10.76

10.84

10.68

Fig. 11 Group delay response of filter cascade with 5th and 7th-order filter

Table 4: Complexity of SI wave equaliser for order N

SI element Even Odd Transistor count

Positive delay* N/2 (N+3)/2 16

Negative delay* N/2 (N–3)/2 24

3-portseries adaptor* N/2 (N–3)/2 76

3-portparallel adaptor* N/2 (N–3)/2 52

2-portparallel adaptor* 1 1 36

Input–output 1 1 32current mirror

Wave converter 1 1 32

*components of Y(z)

556 IEE Proc.-Circuits Devices Syst., Vol. 151, No. 6, December 2004