Click here to load reader

Xilinx Design 2

  • View
    18

  • Download
    0

Embed Size (px)

Text of Xilinx Design 2

Introduction to FPGA DesignGetting Started with Xilinx FPGAs Version 2. 1i

1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-1No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

Outl ineHier chical Des ar ign Sy nchronous Design f Xil or inxFPGAs Summar y

1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-9No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

Synchronous DesignW hy Synchronous Design? Xil FPGA Design Tips inx

1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-10No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

W hy Synchronous Design?Sy nchronous circuits are m ore rel e iabl Events are triggered by clock edges which occur at welldef ined intervals Outputs f rom one logic stage have a f clock cycle to ull propagate to the nex stage t Sk bet ew ween dat ariv t a r al imesist at wit t s oler ed hin he ameclockper iod

Asynchronous circuits are l rel e ess iabl A delay may need to be a specif amount ( g. ic e. 12ns) Multiple delays may need to hold a specif relationship ( g. ic e. DATA arrives 5ns bef SELECT) ore

1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-11No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

Case StudiesThe design I did two y ears ago no l onger works.W hat did Xil change in their FPGAs? inx SRAM process improvements and geometry shrinks increase speed Normal variations between waf l er ots

My design was working,but I re-routed m y FPGA and now m y design f s.W hat is happening? ail Logic pl acement has changed,which af f ects internal routing del ays

My design passes a back-annotated tim ing sim ul ation but f s in circuit.Is the tim ing sim ul ail ation accurate? Yes,the simul ation is accurate Timing simul ation uses worstcase del ays Actual board-evel l conditions are usual better l y 1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-12No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

Design TipsXil FPGA Design inxReduce cl ock skew Cl ock dividers Avoid gl itches on cl ocks and asynchronous set/ reset signal s The Gl obalSet/ Reset network Sel a state m achine encoding schem e ect Access carry l ogic Buil eficient counters d f

1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-13No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

Cl ock SkewINPUT 3. 1 D Q_A 3. D Q_B 1 3. D Q_C 3 3. 0 B C CLOCK 3. 0 A

12. 5

This shif register wil not work because ofcl t l ock skew!2 cy cles 3 cy clesClock Q_A Q_B Q_C A&C Clock B Clock

Expect oper ion ed at

Q_A Q_B Q_C

Clocks ewed v s k er ion

1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-14No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

Use Gl obalBufers to Reduce f Cl ock SkewGl obalbufers are connected to dedicated routing f This routing network is balanced to minimize skew

Al Xil FPGAs have gl l inx obalbufers f Diferent types ofgl f obalbufers f XC4000E/ and Spartan hav 4 BUFGPs and 4 BUFGSs L e XC4000EX/ XV hav 8 BUFGLSs XL/ e Virtexhas 4 BUFGs or BUFGDLLs

You can al s use a BUFG sy boland the sof way m tware wil choose an appropriate bufer type l f Most sy nthesis tools can inf global buf onto clock er f ers signals 1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-15No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

TraditionalCl ock DividerIntroduces cl ock skew between CLK1 and CLK2 Uses an extra BUFG to reduce skew on CLK2

D

Q

D

Q

CLK2BUFG

CLK1BUFG 1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-16No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

Recom m ended Cl ock DividerNo cl ock skew between fip-fops l l

CLK2 CE _D Q

D CE

Q

CLK1BUFG

1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-17No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

Avoid Cl ock Gl itchesBecause fip-fops in today FPGAs are very f l l s ast,they can respond to very narrow cl ock pul ses Never source a cl ock signalf rom com binatoriall ogic Also known as gating the clockMSB

0111 0111

1111

1000 tans ion can become r it 1000 due t f t MSB o aser

MSB

Shorter routing

FFLSB

Gl h ma oc ur here itc y c

Bina ry Counter 1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-18No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

Avoid Cl ock Gl itches:AnswerCom pl in the circuit to create the sam e f ete unction, but without gl itches on the cl ockD

I NPUT

D

Q3 Q2 Q1 Q0 CE Q

FF

CLOCKCo n e u tr

1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-21No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

Avoid Set/ Reset Gl itchesGl itches on asynchronous cl or preset inputs can ear l ead to incorrect circuit behaviorFFAsy nchronous Cl ear

I NPUT

D

Q

Bi a y nr Co n e u trQ[ ] x Q[ ] 0

CLR

RES ET

CLOCK

1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-22No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

Avoid Set/ Reset Gl itchesConvert to synchronous set or reset when possibl eFFSy nchronous Reset

I NPUT

D

Q

Bi a y nr Co n e u trQ[ ] x Q[ ] 0

R

RES ET

CLOCK

1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-23No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx