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Chapter No 5 Basic Computer Organization And Design

Chapter No 5 Basic Computer Organization And Design

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Text of Chapter No 5 Basic Computer Organization And Design

  • Chapter No 5Basic Computer OrganizationAndDesign

  • Figure 5-1 Stored Program Organization

  • Figure 5-2 Direct and Indirect AddressAddressOpcodeI011121415(a) Instruction FormatOperand457457MemoryAdd022AC1350300351Operand1350Memory300AddACDirect addressIndirect address

  • Table 5-1 List Of RegisterRegistersymbol

  • Figure 5-3 Basic Computer Register and memory.

  • Figure 5-4 Computer Register Connect to Common Bus

  • Figure 5-5 Basic Computer Instruction Formats

  • Table 5-2 Basic Computer Instruction

  • Input-Output Instructions: D7IT3 = p (common to all input-output instructions)

    IR(n) = Bn [ bit in IR(6-11) that specifies the instructions)

    P:SC 0 INPpB11:AC(0-7) INPR, FGI 0 1111 1000 0000 0000 F800 OUTpB10:OUTR AC(0-7), FGO 0 1111 0100 0000 0000 F400 SKIpB9:If (FGI =1) then (PC PC+1) 1111 0010 0000 0000 F200SKOpB8:If (FGO =1)then (PC PC+1) 1111 0001 0000 0000 F100IONpB7:IEN 1 1111 0000 1000 0000 F080

    IOFpB6:IEN 0 1111 0000 0100 0000 F040

  • Memory- Reference Instructions:Symbol:Decoder:RTL:Direct: Indirect: ANDD0AC AC M[AR] 00001000

    ADDD1AC AC + M[AR], E Cout00011001LDAD2AC M[AR]00101010STAD3M[AR] AC00111011BUND4PC AR01001100BSAD5M[AR] PC, PC AR + 101011101ISZD6M[AR] M[AR] +1,01101110If M[AR] + 1 = 0 then PC PC + 1

  • Register-Reference Instructions:Binary Codes....Hex. Oper. B11: 7800 CLAB10: 7400 CLEB9: 7200 CMAB8: 7100 CMEB7: 7080 CIR B6: 7040 CILB5: 7020 INCB4: 7010 SPAB3: 7008 SNAB2: 7004 SZAB1: 7002 SZEB0: 7001 HLT

    0 1 1 10 1 0 00 0 0 00 0 0 00 1 1 10 0 0 00 0 0 00 0 1 00 1 1 10 0 0 10 0 0 00 0 0 00 1 1 10 0 0 01 0 0 00 0 0 00 1 1 10 0 0 00 0 0 00 1 0 00 1 1 11 0 0 00 0 0 0 0 0 0 00 1 1 10 0 0 00 0 1 00 0 0 00 1 1 10 0 0 00 0 0 10 0 0 00 1 1 10 0 0 00 0 0 01 0 0 00 1 1 10 0 0 00 0 0 00 1 0 0 0 1 1 10 0 0 00 0 0 00 0 1 00 1 1 10 0 0 00 0 0 00 0 0 1

  • Table 5-2 Basic Computer Instruction:Hexadecimal CodeSymbolI = 0I = 1 DescriptionSNA7008Skip next instruction if AC negativeSZA7004Skip next instruction if AC zeroSZE7002Skip next instruction if E zeroHLT7001Halt computer

    INPF800Input character to ACOUTF400Output character from ACSKIF200Skip on input flagSKOF100Skip on output flagIONF080Interrupt onIOFF040Interrupt on

  • Instruction Set Completeness:Arithmetic, logical, and shift Instruction.

    Instruction for moving information to register.

    Program control Instruction.

    Input-output Instruction.

  • Figure 5-6 Control Unit Of Basic Computer

  • Figure 5-7 Control Timing SignalToT1T2T3T4ToclockToT1T2T3T4ToCLR SC

  • Figure 5-8 Register Transfer PhaseS2S1S0

    Memory Unit

    ARPCIRToT1ReadLDINCLDAddress7125common busBUS

  • Figure 5-9Instruction Cycle Flowchart(Initial Config)StartSC 0AR PCIR M [AR] , PC PC + 1Decode operation code in IR (12-14)AR IR (0-11) , I IR (15)D7IIExecuteRegister referenceInstructionSC 0ExecuteInput - outputInstructionSC 0AR M [AR]NothingExecuteMemory referenceInstructionsSC 0(Register or I/O) =1= 0 (Memory reference) I/O =1=0 (register)(indirect) = 1= 0 (direct)T0T1T2T3T3T3T3

  • Table 5-3 Execution Of Register Reference InstructionsD7 I T3= r ( Common All Register Instruction)IR(I)= Bi [011 that Specifies The Instruction]r:SC 0Clear SCCLArB11 :AC 0Clear ACCLErB10 : E 0Clear ECMArB9 :AC ACComplement ACCMErB8 :E EComplement ECIRrB7 :AC shr AC, AC (15) E, E AC(0)Circulate rightCIlrB6 :AC shl AC, AC (0) E, E AC(15)Circulate leftINCrB5 :AC AC + 1Increment ACSPArB4 :if(AC(15) = 0) then (PC PC + 1)Skip if positiveSNArB3 :if(AC(15) = 1) then (PC PC + 1)Skip if negativeSZArB2 :if (AC = 0) then (PC PC + 1)Skip if AC is zeroSZErB1 :if (E = 0) then (PC PC + 1)Skip if E is zeroHLTrB0 :S 0 (S is a start-stop flip flop )Halt Computer

  • Table 5-4 Memory Reference InstructionOperationSymboldecoderSymbolic descriptionANDD0AC AC ^ M[AR]ADDD1AC AC + M[AR], E CcutLDAD2AC M[AR]STAD3 M[AR] AC BUND4PC ARBSAD5M[AR] PC , PC AR +1ISZD6M[AR] M[AR] + 1if M[AR] + 1 = 0 then PC PC +1

  • Figure 5-10 Example BSA Instruction ExecutionMemory20PC= 21AR= 135136(a) Memory, PC, and AR at time T4Memory20 21 135PC=136(a) Memory and PC after execution

    0 BSA 135Next Instruction

    21Subroutine

    1 BUN 135

  • Figure 5-11 Flow Chart for memory Reference Instructions:Memory reference instructionPC ARSC 0M [AR] PCDR M [AR]DR M [AR]DR M [MAR]DR M [AR]M[AR] ACSC 0AC AC ^ DRSC 0AC AC+DRE CoutSC 0AC DRSC 0ANDADDLDASTAD0T4D1T4D2T4D3T4D0T5D1T5D2T5BUNBSAISZD4T4D5T4D6T4PC ARSC 0D5T5DR DR+1D6T5M [AR] DRIf (DR=0)Then (PC PC + 1)SC 0D6T6

  • Figure 5-12 Input-Output Configuration.I/O TerminalSerial communicationinterfaceComputer registers and Flip-FlopFGOPrinterReceiver InterfaceOUTRACINPRTransmitterInterfaceFGIKeyboard

  • Table 5-5 Input-Output InstructionD7IT3 =p (Common Input Output Instruction)IR(I) =bi [Bit in IR(6 -11) that specifies instruction)p:SC 0Clear SCINPpB11 :AC(0-7) INPRInput characterOUTpB10 :OUTR AC (0-7), FGO 0Output characterSKIpB9 :If( FGI = 1) then ( PC PC + 1)Skip on input flagSKOpB8 :If( FGO = 1) then ( PC PC + 1)Skip on output flagIONpB7 :IEN 1Interrupt enable onIOFpB6 :IEN 0Interrupt enable off

  • Figure 5-13 Flowchart for Interrupt CycleR=0=1Instruction CycleInterrupt CycleFetch and decodeInstructionExecuteInstructionIEN=0FGI=1R 1FGO=0Store return addressIn location 0M[0] PCBranch to location 1PC 1IEN 0R 0=0=1=1

  • Figure 5-14 Demonstration of the Interrupt Cycle.Memory011120(a) Before interrupt255PC=256Memory0PC=11120(a) After interrupt255256

    0 BUN 1120Main programI/OProgram

    1 BUN 0

    2560 BUN 1120Main programI/OProgram

    1 BUN 0

  • Interrupt Cycle:RT0 :AR 0, TR PCRT1 :M [AR] TR, PC 0RT2 :PC PC + 1, IEN 0, R 0, SC 0Storing Return AddressCondition for R flip-flopT0 T1 T2 (IEN) (FGI + FGO): R 1

  • Figure 5-15 Flowchart for computer OperationStartSC 0, IEN 0, R 0RAR PCR T0IR M[AR], PC PC + 1AR 0,TR PCR T1RT0M[AR] TR, PC 0RT1PC PC+1, IEN 0R 0, SC 0RT2AR IR(011), I IR (15)D0 D7 Decode IR(12-14) D7=0I=0=1AR M[AR]NothingD7 I T3D7 I T3ExecuteMemory-reference Instruction=1IExecuteRegister-referenceinstructionExecuteI/Oinstruction=0=1R T2Interrupt Cycle=1=0Instruction Cycle(direct)(Indirect)(Memory-reference)(I/O- reference)D7 I T3D7 I T3

  • Figure 5-16 Control Gates With ARARFrom BusTo BusLDINRCLRD7IT3T2RT0D5T4

  • Figure 5-17 Control Single Flip-Flop:pB7: IEN 1pB6: IEN 0RT2: IEN 0IENJKD7IT3PRT2B6B7Q

  • Table 5-17Encoder for Bus Selection circuits.InputsOutputsRegister selectedx1x2x3x4x5x6x7S2S1S0for bus0000000000None1000000001AR0100000010PC0010000011DR0001000100AC0000100101IR0000010110 TR0000001111 Memory

  • Figure 5-18 Encoder for Bus SelectionENCODERMULTIPLEXERBUS SELECTINPUTSS2S1S0X1X2X3X4X5X6X7

  • Figure 5-19 Circuits associated with ACACTo BusAdderLogicCircuitsControl Gates161616FROM INPRFROM DRLDINRCLRCloak168

  • Figure 5-20 Gates controlling the Ld,INR, and CLR OF ACACTo BUSAdder logicLDINRCLRANDADDDRINPRCOMSHRSHLINCCLRrB7B6B5B11pB11D2T5D1D0T5B916

  • Figure 5-21 One stage of adder and logic circuitsJKQAC (i)LD

    FA

    ADDCiANDCi + 1DRINPRCOMSHRSHLFrom INPRBit (i)AC (i + 1)AC (i - 1)DR (i)AC (i)