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Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

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Page 1: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Chapter 15

Timer and Counter Instructions

Page 2: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Objectives

Describe the function of an on-delay timer.

Describe the function of an off-delay timer.

Describe in what instances one would use a retentive timer.

Describe the function of an up counter.Describe the function of a down counter.

Page 3: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Objectives (cont’d.)

Describe in what instances one would use an up counter versus a down counter.

Define preset, accumulative value, and the timer or counter address.

Explain how the various timers and counters are reset.

Page 4: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

T4, Timer FileThe timer file stores only timer

elements.An element is a word or group of words

that work together as a unit.A timer is made of of three pieces or

words:Preset valueAccumulated valueStatus bits

Page 5: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

T4, Timer File (cont’d.)

The preset value and accumulated value are 16-bit signed integers.

Status bits are single bits that make up one 16-bit word.

These three words work together as a unit.

Page 6: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

One Timer Element Is Made of Three 16-Bit Words

Page 7: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Timer Addressing

Sample timer element addressT4:2T4 = timer file 4:2 = timer element #2 (0-255

timer elements per file)

Page 8: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Sub-Element

A sub-element is part of an element addressable as a unit.

The preset value and accumulated value are sub-elements of a timer:T4:0.PRET4:0.ACC

Page 9: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Timer Status Bits

Timers have three status bits.Done bit (DN) is true when the

accumulated value and preset are equal.

Timer timing bit (TT) is true when the timer is timing.

Enable bit (EN) is true when the timer instruction is enabled or true.

Page 10: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Timer Bit Addressing

Status bit addresses for timer file 4, timer element 2 (T4:2) are listed below:T4:2/DN is the address for the done bit.T4:2/EN is the address for the enable

bit.T4:2/TT is the address for the timer

timing bit.

Page 11: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Timer File T4

Page 12: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

C5, Counter FileThe counter file stores only counter

elements.An element is a word or group of

words that work together as a unit.A counter is made of of three pieces

or words:Preset valueAccumulated valueStatus bits

Page 13: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

C5, Counter File (cont’d.)

The preset value and accumulated value are 16-bit signed integers.

Status bits are single bits that make up one 16-bit word.

These three words work together as a unit.

Page 14: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

One Counter Element Is Made of Three 16-Bit Words

Page 15: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Counter Addressing

Sample counter element address C5:2C5 = timer file 5:2 = counter element #2 (0-255

timer elements per file)

Page 16: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Sub-Element

A sub-element is part of an element addressable as a unit.

The preset value and accumulated value are sub-elements of a counter:C5:0.PREC5:0.ACC

Page 17: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Counter Status Bits

Counters have five status bits.Done bit (DN) is true when the

accumulated value and preset are equal.

Count up enable bit (CU) is true when the up counter is true or enabled.

Count down enable bit (CD) is true when the count down counter is enabled or true.

Page 18: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Counter Status Bits (cont’d.)

The overflow bit (OV) is true when the up counter has overflowed above +32767.

The underflow bit (UN) is true when the down counter has underflowed below -32768.

The update accumulator bit (UA) is a high-speed counter status bit for fixed SLC 500 PLCs.

Page 19: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Counter Status Bit Addressing

Status bit addresses for counter file 5, counter element 0 (C5:0) are listed below:

C5:0/DN is the address for the done bit.

C5:0/CU is the address for the count up enable bit.

Page 20: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Counter Status Bit Addressing (cont’d.)

C5:0/CD is the address for the count down enable bit.

C5:0/OV is the address for the count up overflow bit.

C5:0/UN is the address for the count down underflow bit.

Page 21: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Counter File C5

Page 22: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

SLC 500 On-Delay Timer

Page 23: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

SLC 500 Timer Instructions

Page 24: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

SLC 500 On-Delay Timer and Associated Status Bits

Page 25: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

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SLC 500 Off-Delay Timer

Page 26: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

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SLC 500 Retentive Timer

Page 27: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

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Retentive Timer and Its Reset Instruction

Page 28: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

SLC 500 Counters

Page 29: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

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SLC 500 Count Up Counter

Page 30: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

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SLC 500 Count Down Counter

Page 31: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

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SLC 500 Count Down Counter Instruction

Page 32: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Reset Instruction to Reset Counter C20:7

Page 33: Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions

Copyright © 2002 Delmar Thomson Learning

Using the Clear Instruction to Clear C5:0.ACC and

C5:1.Acc