EECS 141 – S02 Timingbwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s02/...» 58 cm final driver width Local inverters for latching Conditional clocks in caches to reduce power More

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Digital Integrated Circuits © Prentice Hall 2000Timing

EECS 141 – S02Timing


Project 2: A Random NumberGenerator

The Linear-Feedback Shift Register

S0 S1 S2

R R R

1 0 00 1 01 0 11 1 01 1 10 1 10 0 11 0 0

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Project Goal

� Design a 4-bit LFSR� SPEED, SPEED, SPEED!� Feel free to use:

» Logic style

» Register style

» Clocking style

� No layout, only schematics and simulation


4-bit LFSR

R R R R

A0 A1 A2 A3

Pseudo-Random number generator.

+ additional circuitry for asynchronous reset to a seed

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Constraints

� TECHNOLOGY: 0.25 µm CMOS technology� SUPPLY: 2.5 V� PERFORMANCE METRIC: VOH, VOL: The output

signals should settle to within 10% of their final valuebefore the next clock event can be introduced!!!

� NOISE MARGINS: The noise margins should be atleast 10% of the voltage swing.

� LOAD CAPACITANCE: Each output bit of thegenerator should have a 20 fF load.

� CLOCKS: You are given a primary clock signal with arise and fall time of 50 psec and a duty cycle of 50%.

� NO RACES!!!!!!!!!!!!!!!


Reporting

� No written report

� Submit a short summary of your results onMay 6

� Poster presentation on afternoon of Tu May 7(9 power-point slides)» Tell your story in 5 minutes!» And convince us that your design is the best

� And submit your poster electronically

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Latch Parameters

D

Clk

Q

D

Q

Clk

TClk-Q

TH

PWmTSU

TD-Q

Delays can be different for rising and falling data transitions


Flip-Flop Parameters

D

Clk

Q

D

Q

Clk

TClk-Q

TH

PWm

TSU

Delays can be different for rising and falling data transitions

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The Clock Distribution Challenge

20 Clocks

90,000tracks

Local, parallel operationsHigh bandwidthLow latency &Low power

Global operationsLow bandwidthHigh latency &High power

Source: Bill Dally, Stanford


Example Clock System

Courtesy of IEEE Press, New York. 2000

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Clock Nonidealities

� Clock skew» Spatial variation in temporally equivalent clock

edges; deterministic + random, tSK

� Clock jitter» Temporal variations in consecutive edges of the

clock signal; modulation + random noise» Cycle-to-cycle (short-term) tJS

» Long term tJL

� Variation of the pulse width» for level sensitive clocking


Clock Skew and Jitter

� Both skew and jitter affect the effective cycle time

� Only skew affects the race margin

Clk

Clk

tSK

tJS

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Clock Skew

# of registers

Clk delayInsertion delayMax Clk skew

Earliest occurrenceof Clk edgeNominal – Tsk/2

Latest occurrenceof Clk edge

Nominal + Tsk/2

Tsk


Sources of skew and jitter

Clock Generation

Devices

Power Supply

InterconnectCapacitive Load

TemperatureCoupling to Adjacent Lines7

1

2

3

4

5

6

8


Positive and Negative Skew

R CL R CL RData

φ

CL

R CL R CL RData

CL

φ

(a) Positive skew

(b) Negative skew


Constraints on Skew

R1 R2

φ’ φ’’δ

tr,min + tl,min

(a) Race between clock and data.

R1 R2

φ’ φ’’+ Pδ

tr,max + tl,max i

(b) Data should be stable before clock pulse is applied.

tφ’ tφ’’ = tφ’ + δ

tφ’ tφ’’ + T =

data

data

φ’’

tφ’ + T + δ

Late

Early

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Clock Constraints in Edge-Triggered Logic

δδδδ tr min,,,, ti tl min,,,,+ +≤≤≤≤

T tr max,,,, ti tl max,,,, δδδδ–+ +≥≥≥≥

Maximum Clock Skew Determined by Minimum Delay between Latches

Minimum Clock Period Determined by Maximum Delay between Latches


Impact of Jitter

CLK

-tji tter

TC LK

t j itter

CLK

InCombinat ional

Logic

tc-q , tc-q, cdt log ict log ic, cdtsu, thold

REGS

tjitter

1

2

3 4

5

6

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Longest Logic Path inEdge-Triggered Systems

Clk

T

TSU

TClk-QTLM

Latest pointof launching

Earliest arrivalof next cycle

Unger and TanTrans. on Comp.10/86

TJI - δ


Clock Constraints inEdge-Triggered Systems

If launching edge is late and receiving edge is early, the data will not be too late if:

Minimum cycle time is determined by the maximum delays through the logic

Tc-q + TLM + TSU < T – TJI,1 – TJI,2 + δδδδ

Tc-q + TLM + TSU - δδδδ + 2 TJI < T

Jitter always works negatively

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Shortest Path

ClkTClk-Q TLm

Earliest pointof launching

Data must not arrivebefore this time

ClkTH

Nominalclock edge


Clock Constraintsin Edge-Triggered Systems

Minimum logic delay

If launching edge is early and receiving edge is late:

Tc-q + TLM – TJI,1 < TH + TJI,2 + δδδδ

Tc-q + TLM < TH + 2TJI+ δδδδ

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How to counter Clock Skew?

RE

G

φR

EG

φR

EG

φ

.

RE

G

φ

log Out

In

Clock Distribution

Positive Skew

Negative Skew

Data and Clock Routing


Flip-Flop – Based Timing

Flip-flop

Logic

φ

φ = 1φ = 0

Flip-flopdelay

Skew

Logic delay

TSU

TClk-Q

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Flip-Flops and Dynamic Logic

φ = 1φ = 0

Logic delay

TSU

TClk-Q

φ = 1φ = 0

Logic delay

TSU

TClk-Q

PrechargeEvaluateEvaluatePrecharge

Flip-flops are used only with static logic


Latch timing

D

Clk

Q

tD-Q

tClk-Q

When data arrivesto transparent latch

When data arrivesto closed latch

Data has to be ‘re-launched’

Latch is a ‘soft’ barrier

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Single-Phase Clock withLatches

Latch

Logic

φ

Clk

P

PW

Tskl Tskl TsktTskt

Unger and TanTrans. on Comp.10/86


Latch-Based Design

L1Latch

Logic

Logic

L2Latch

φ

L1 latch istransparentwhen φ= 0

L2 latch is transparentwhen φ= 1

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Slack-borrowing

QDIn CLB_A QD QD

CLK1

L1 L2 L1

CLK2 CLK1

CLB_Btpd,A tpd,B

CLK1

CLK2

TCLK

321 4

a b c d e

tpd,A

a valid b valid

tD Qtpd,B

c valid d valid

tDQ

e valid

slack passed to next stage


Latch-Based Timing

L1Latch

Logic

Logic

L2Latch

φ

φ = 1

φ = 0

L1 latch

L2 latch

Skew

Can tolerate skew!

Longpath

Shortpath

Static logic

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Clock Distribution

CLOCK

H-Tree Network

Observe: Only Relative Skew is Important


More realistic H-tree

[Restle98]

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Clock Network with DistributedBuffering

Module

Module

Module

Module

Module

Module

CLOCK

main clock driver

secondary clock drivers

Reduces absolute delay, and makes Power-Down easier

Sensitive to variations in Buffer Delay

Local Area


The Grid System

Driver

Driver

Dri

ver

Driv

er

GCLK GCLK

GCLK

GCLK

•No rc-matching•Large power

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Example: DEC Alpha 21164

Clock Frequency: 300 MHz - 9.3 Million Transistors

Total Clock Load: 3.75 nF

Power in Clock Distribution network : 20 W (out of 50)

Uses Two Level Clock Distribution:

• Single 6-stage driver at center of chip

• Secondary buffers drive left and right sideclock grid in Metal3 and Metal4

Total driver size: 58 cm!


21164 Clocking

� 2 phase single wire clock,distributed globally

� 2 distributed driver channels» Reduced RC delay/skew» Improved thermal distribution» 3.75nF clock load

» 58 cm final driver width

� Local inverters for latching� Conditional clocks in caches to

reduce power� More complex race checking� Device variation

trise = 0.35ns tskew = 150ps

tcycle= 3.3ns

Clock waveform

Location of clockdriver on die

pre-driver

final drivers

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Clock Drivers


Clock Skew in Alpha Processor

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� 2 Phase, with multiple conditionalbuffered clocks

» 2.8 nF clock load

» 40 cm final driver width

� Local clocks can be gated “off” tosave power

� Reduced load/skew� Reduced thermal issues� Multiple clocks complicate race

checking

trise = 0.35ns tskew = 50ps

tcycle= 1.67ns

EV6 (Alpha 21264) Clocking600 MHz – 0.35 micron CMOS

Global clock waveform

PLL


21264 Clocking

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EV6 Clock Results

GCLK Skew(at Vdd/2 Crossings)

ps5

101520253035404550

ps300305310315320325330335340345

GCLK Rise Times(20% to 80% Extrapolated to 0% to 100%)


EV7 Clock Hierarchy

GCLK(CPU Core)L

2L_C

LK

(L2

Cac

he)

L2R

_CL

K(L

2C

ache

)

NCLK(Mem Ctrl)

DLL

PL

L

SYSCLK

DL

L

DL

L

+ widely disperseddrivers

+ DLLs compensatestatic and low-frequency variation

+ divides design andverification effort

- DLL design andverification is addedwork

+ tailored clocks

Active Skew Management and Multiple Clock Domains

Documents

EECS 141 – S02 Timingbwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s02/...» 58 cm final driver width Local inverters for latching Conditional clocks in caches to reduce power More