Fig. 5-1 4-Bit Register M. Morris Mano & Charles R. Kime ...islab.soe.uoguelph.ca/sareibi/TEACHING_dr/ENG241... · LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated. 5-15 J C K

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

5-1

•

•

•

D

C

R

•D

C

R

•D

C

R

•D

C

R

•

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

•

•

•

(a) Logic diagram

Clock

(d) Timing diagram

Load

C inputs

• C inputs (clock inputsof flip-flops)

(c) Load control input

LoadClock

(b) Symbol

REG

Clear

D0

•Q0

D2 Q2

D3 Q3

D1 Q1

Fig. 5-1 4-Bit Register


5-2

••

Load

D0

D1

D2

D3

Clock

Q0

Q1

Q2

Q3

•

•

•

•

•

•

•

•

•

D

C

D

C

D

C

D

C

•

•

•

•

•

Fig. 5-2 4-Bit Register with Parallel Load


5-3

(b) Symbol

Sl

SRG 4Clock

SO

(a) Logic diagram

D

C

Serialinput SI

Clock

D

C

D

C

D

C

Serialinput S0

• • •

Fig. 5-3 4-Bit Shift Register


5-4

(a) Block diagram

(b) Timing diagram

T1 T2 T3 T4

Clock

Shift

C Input

Sl

C

Register A

SO0

SRG 4

Sl

C

Register B

SO

SRG 4

ShiftClock ••

Fig. 5-4 Serial Transfer


5-5

TABLE 5-1Example of Serial Transfer

Timingpulse Shift Register A Shift Register B

Initial valueAfter T1After T2After T3After T4

10000

01000

10100

11010

01101

00110

10011

01001

Table 5-1 Example of Serial Transfer


5-6

Reset

Reset

Reset

Sl

Register A

SO

SRG 4

FA

X

Y

Z

S

C

Full Adder(Figure 3-27)

Carry

C

D

R

Sl

Clear

Register B

SO

SRG 4

Shift

Clock

Serialinput

Clear

C

C•

••

Fig. 5-5 Serial Addition


5-7

••

•D

C

D

C

D

C

D

C

(b) Symbol

SHR 4

Shift

Load

Sl

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Shift

Load

Serialinput

D0

•

••

•

•

•

•

•

••

•

•

•

•

•

•

••

•

•

•

•

•

•

D1

D2

D3

Clock

Q0

Q1

Q2

Q3

•

•

•

•

Fig. 5-6 Shift Register with Parallel Load


5-8

TABLE 5-2Function Table for the Register of Figure 5-6

Shift Load Operation

001

01�

No changeLoad parallel dataShift down from Q0 to Q3

Table 5-2 Function Table for the Register of Figure 5-6


5-9

D

C

D

C

D

C

(b) Symbol

SHR 4

S1

S0

LSI

D0

D1

D2

D3

Q0

Q1

Q2

Q3

RSI

Mode S1

Mode S0

Left serial input

Right serial input

Clock

•

•

•

•

•

S1

S0

Di

MUX

S1

S0

0

1

2

3

Clock

Qi – 1

Qi

Qi + 1

(a) Logic diagram of one typical stage

Fig. 5-7 Bidirectional Shift Register with Parallel Load


5-10

TABLE 5-3Function Table for the Register of Figure 5-7

Mode controlRegisterOperationS1 S0

0011

0101

No changeShift downShift upParallel load

Table 5-3 Function Table for the Register of Figure 5-7


5-11

J

C

KR

J

C

KR

J

C

KR

J

C

KR

Clock pulses

Logic 1

Q0

Q1

Q2

Q3

•

•

••

•

•

•

•

•

•

•

•

•Clear

•

•

•

•

•

•

•

•

Fig. 5-8 4-Bit Ripple Counter


5-12

TABLE 5-4Counting Sequence of Binary Counter

Upward Counting Sequence Downward Counting Sequence

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

0000000011111111

0000111100001111

0011001100110011

0101010101010101

1111111100000000

1111000011110000

1100110011001100

1010101010101010

Table 5-4 Counting Sequence of Binary Counter


5-13

TABLE 5-5State Table and Flip-Flop Inputs for Binary Counter

Present state

Nextstate Flip-flop inputs

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 JQ3 KQ3 JQ2 KQ2 JQ1 KQ1 JQ0 KQ0

0000000011111111

0000111100001111

0011001100110011

0101010101010101

0000000111111110

0001111000011110

0110011001100110

1010101010101010

00000001��

��00000001

0001��0001��

��0001��0001

01��01��01��01��

��01��01��01��01

1�1�1�1�1�1�1�1�

�1�1�1�1�1�1�1�1

Table 5-5 State Table and Flip-Flop Inputs for Binary Counter


5-14

KQ3 = Q0Q1Q2

1

X XX X

X XX X00

01

00 01Q1Q0

Q3Q2

Q1

Q0

Q3

11 10

11

10

Q2

1

X XX X

JQ3 = Q0Q1Q2

X XX X

KQ2 = Q0Q1JQ2 = Q0Q1

KQ1 = Q0JQ1 = Q0

1

X XX X

X XX X

1

1

XX

XX

X X

X X

1

1

1

1

X X

X X

1

X XX X

X XX X

1

XX

X

X

1

1

1

Fig. 5-9 Maps for Input Equations of a Binary Counter


5-15

J

C

K

J

C

K

J

C

K

J

C

KCount enable EN

Clock

Carryoutput CO

Q0

Q1

Q2

Q3

• •

••

•

•

•

•

••

•

•

••

(b) Symbol

CTR 4

EN•Q1

Q2

Q3

CO

Q0

(a) Logic diagram

•

Fig. 5-10 4-Bit Synchronous Binary Counter


5-16

EN •

••

••

•

• • • •

Q0

Q1

C1

Q2

C2

C3

CO

Q3

(b) Parallel gating

D

C

D

C

D

C

D

C

•

•

•

•

•

•

•

•

•

•

•

•

•

•

Count enable EN

Clock

Carryoutput CO

Q0

Q1

Q2

Q3

(a) Serial gating

•

Fig. 5-11 4-Bit Binary Counter with D Flip-Flops


5-17••

•

•

•

•

J

C

K

J

C

K

J

C

K

J

C

K

Count

Load

D0

D1

D2

D3

Q0

Q1

Q2

Q3

CarryOutput CO

•

••

•

•

•

•

••

•

•

•

•

•

•

•

••

•

•

•

•

•

(b) Symbol

CTR 4

Load

Count

D0

D1

D2

D3

Q0

Q1

Q2

Q3

CO

Clock

(a) Logic diagram

•

•

•

•

Fig. 5-12 4-Bit Binary Counter with Parallel Load


5-18

Present State Next State Output Flip-Flop Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 Y TQ8 TQ4 TQ2 TQ1

0000000011

0000111100

0011001100

0101010101

0000000110

0001111000

0110011000

1010101010

0000000001

0000000101

0001000100

0101010100

1111111111

TABLE 5-6State Table and Flip-Flop Inputs for BCD Counter

Table 5-6 State Table and Flip-Flop Inputs for BCD Counter


5-19

CTR 4

Load

Count

D0

D1

D2

D3

Q0

Q1

Q2

Q3

CO

Clock

1

(Logic 0)

Q0

Q1

Q2

Q3

•

••

Fig. 5-13 BCD Counter


5-20

TABLE 5-7State Table and Flip-Flop Inputs for BCD Counter

Present State Next State Output Flip-Flop Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 Y TQ8 TQ4 TQ2 TQ1

0000000011

0000111100

0011001100

0101010101

0000000110

0001111000

0110011000

1010101010

0000000001

0000000101

0001000100

0101010100

1111111111

Table 5-7 State Table and Flip-Flop Inputs for BCD Counter


5-21

(b) State diagram

111

001 110

010 101

100 011

000

(a) Logic diagram

•Clock

JC

K JC

KJC

K

•

•

• •

•

A B C

Logic-1

•

Fig. 5-14 Counter with Arbitrary Count


5-22

TABLE 5-8State Table and Flip-Flop Inputs for Counter

PresentState Next State Flip-Flop Inputs

A B C A B C JA KA JB KB JC KC

000111

001001

010010

001110

010010

100100

001��

��001

01�01�

��1��1

1�01�0

�1��1�

Table 5-8 State Table and Flip-Flop Inputs for Counter


5-23

-- 4-bit Shift Register with Reset-- (See Figure 5-3)library ieee;use ieee.std_logic_1164.all;

entity srg_4_r isport(CLK, RESET, SI : in std_logic;

Q : out std_logic_vector(3 downto 0);SO : out std_logic);

end srg_4_r;

architecture behavioral of srg_4_r issignal shift : std_logic_vector(3 downto 0);beginprocess (RESET, CLK) begin

if (RESET = '1') thenshift <= "0000";

elsif (CLK’event and (CLK = '1')) thenshift <= shift(2 downto 0) & SI;

end if;end process;

Q <= shift;SO <= shift(3);

end behavioral;

Fig. 5-15 Behavioral VHDL Description of 4-bit Left Shift Register with Direct Reset


5-24

-- 4-bit Binary Counter with Reset-- (See Figure 5-10)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity count_4_r is port(CLK, RESET, EN : in std_logic; Q : out std_logic_vector(3 downto 0); CO : out std_logic);end count_4_r;

architecture behavioral of count_4_r issignal count : std_logic_vector(3 downto 0);beginprocess (RESET, CLK)begin if (RESET = '1') then count <= "0000"; elsif (CLK’event and (CLK = '1') and (EN = '1')) then count <= count + "0001"; end if;end process;Q <= count; CO <= '1' when count = "1111" and EN = '1' else '0';end behavioral;

Fig. 5-16 Behavioral VHDL Description of 4-bit Binary Counter with Direct Reset


5-25

// 4-bit Shift Register with Reset// (See Figure 5-3)

module srg_4_r_v (CLK, RESET, SI, Q,SO); input CLK, RESET, SI; output [3:0] Q; output SO;

reg [3:0] Q;

assign SO = Q[3];

always@(posedge CLK or posedge RESET)begin if (RESET) Q <= 4'b0000; else Q <= {Q[2:0], SI};endendmodule

Fig. 5-17 Behavioral Verilog Description of 4-bit Left Shift Register with Direct Reset


5-26

// 4-bit Binary Counter with Reset// (See Figure 5-10)

module count_4_r_v (CLK, RESET, EN, Q, CO); input CLK, RESET, EN; output [3:0] Q; output CO;

reg [3:0] Q;

assign CO = (count == 4'b1111 && EN == 1’b1) ? 1 : 0; always@(posedge CLK or posedge RESET) begin if (RESET)

Q <= 4'b0000; else if (EN)

Q <= Q + 4'b0001; endendmodule

Fig. 5-18 Behavioral Verilog Description of 4-bit Binary Counter with Direct Reset

Documents

Fig. 5-1 4-Bit Register M. Morris Mano & Charles R. Kime ...islab.soe.uoguelph.ca/sareibi/TEACHING_dr/ENG241... · LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated. 5-15 J C K