NAME Europe THE QUARTERLY JOURNAL FOR XILINX …china.xilinx.com/publications/archives/xcell/Xcell22.pdf · 2. How many people read your copy of XCell? _____ 2. What amount of time

Issue 22Third Quarter 1996

GENERALFawcett: Reconfigurable Computing ...... 2Guest Editorial ........................................ 3Customer Success Stories

GPT Video Systems ........................ 6-7BICOM .............................................. 7

Xilinx Funds Seiko-Epson Foundry ............ 8New Data Book Now Available ...............8What’s New on WebLINX ........................ 9Training Update .......................................9Financial Results .................................... 10New Product Literature ......................... 10Upcoming Events .................................. 10

PRODUCTSXC5200 Prices Down, Value Up ........... 11XC7300 Best 44-Pin PLD ................... 12-13XC8100 Family Discontinued ................ 13Production Begins for XC4000EX .......... 14Faster -2 Speed Grade for XC4000E ...... 14

DEVELOPMENT SYSTEMSSynopsys’ FPGA Express .................. 15-16LogiCore PCI Initiator Debuts ............... 17Foundation Introduction Successful ...... 17

HINTS & ISSUESXC9500 CPLD Pin-Locking .............. 18-21XC9500 Slew Rate Controls ................. 22Using XC5200 Carry Logic ................ 23-25Advantages of Select-RAM ................26-27Power, Package & Performance ........ 28-29Metastability Recovery in FPGAs ...... 30-31XACTstep on Alternate Systems ............ 32E-Mail Group Monitors Xilinx Products . 33New Technical Support Choices ....... 34-35Questions & Answers ........................ 36-37Component Availability Chart ........... 38-39Development Systems Chart ................. 40Programming Support Charts ............ 41-43Alliance Program Charts .................... 44-46Reader Survey ....................................... 47Fax Response Form ............................... 48

The ProgrammableLogic CompanySM

Inside This Issue:

T H E Q U A R T E R L Y J O U R N A L F O R X I L I N X P R O G R A M M A B L E L O G I C U S E R S

R

40

FAX in Your Comments and SuggestionsTo: Brad Fawcett, XCELL Editor Xilinx Inc. FAX : 408-879-4676

From: ________________________________________ Date: ____________

❏❏❏❏❏ Please add my name to the XCELL mailing list.

NAME

COMPANY

ADDRESS

CITY/STATE/ZIP

PHONE

❏❏❏❏❏ I’m interested in having my company’s design featured in a future edition ofXCELL as a Customer Feature.

Comments and Suggestions:_______________________________________________________

_______________________________________________________________________________

_______________________________________________________________________________

_______________________________________________________________________________

_______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Please use this form to FAX in your comments and suggestions, or to request an addition to theXCELL mailing list. Please feel free to make copies of this form for your colleagues.

U.S. PostagePAID

First ClassPermit No. 2196

San Jose, CA2100 Logic DriveSan Jose, CA 95124-3450

FAX RESPONSE FORM-XCELL 22 3Q96 XCELLCorporateHeadquartersXilinx, Inc.2100 Logic DriveSan Jose, CA 95124Tel: 408-559-7778Fax: 408-559-7114

EuropeXilinx, Ltd.Suite 1B, Cobb HouseOyster LaneByfleetSurrey KT147DUUnited KingdomTel: 44-1-932-349401Fax: 44-1-932-349499

JapanXilinx, KKDaini-Nagaoka Bldg. 2F2-8-5, Hatchobori,Chuo-ku, Tokyo 104JapanTel: 81-3-3297-9191Fax: 81-3-3297-9189

Asia PacificXilinx Asia PacificUnit 4312, Tower IIMetroplazaHing Fong RoadKwai Fong, N.T.Hong KongTel: 852-2424-5200Fax: 852-2494-7159

R

PRODUCT INFORMATION

XC5200 FPGAs:Prices Go Down andPerformance Goes Up

Pinlocking & XC9500 CPLDsIn further proof that designers must consider morethan just the expected specifications, XC9500TM CPLDshave proven themselves to be the best choice formaintaining pinouts during design iterations...

See Page 18

Using XC5200 FPGA Carry LogicTips for using this simple, but flexible, feature...

See Page 23

Process improvements and record saleshave helped to knock as much as 50% offthe price on XC5200TM family FPGAs, whileboosting performance by as much as 30%...

See Page 11

DESIGN TIPS & HINTS

Synopsys IntroducesFPGA ExpressAlliance partner Synopsys has built on thestrengths of its FPGA Compiler to create aWindows 95 and NT product that includes allof the hottest new Xilinx products...

See Page 15

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

FROM THE FAWCETT

Reconfig

ComiBy BRA

R

XCELLPlease direct all inquiries,comments and submissions to:

Editor: Bradly Fawcett

Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124Phone: 408-879-5097FAX: 408-879-4676E-Mail: [email protected]

©1996 Xilinx Inc.All rights reserved.

XCELL is published quarterly forcustomers of Xilinx, Inc. Xilinx, theXilinx logo and XACT are registeredtrademarks; all XC-designatedproducts, HardWire, FoundationSeries, and XACTstep are trademarks;and “The Programmable LogicCompany” is a service mark of Xilinx,Inc. All other trademarks are theproperty of their respective owners.

2 This past June, Xilinx held its fiReconfigurable Computing Develop

Program Conferenhotel in Santa Clarfar from company quarters. Planned an annual event, conference broughtogether represenfrom 11 of the mo20 companies thatparticipants in theDeveloper’s Progra

The Reconfigurable Computing (Developer’s Program was founded mid-1995 to proactively spur commdevelopment of reconfigurable comapplications and products (see XCell #page 35). The program is designed commercial companies through tecmarketing and, insome cases, finan-cial assistance.In this context,reconfigurablecomputing isloosely defined asthe practice ofusing in-system-configurableFPGAs as computing elements to ate operations in general-purposeers. In these systems, FPGAs are ured during system operation to pvariety of operations directly in haoff-loading the host processor andcally increasing system performan

Each company attending the mgave a short presentation about thucts it has developed or is developSeveral companies brought demo

❝Theprovided into the but grow

ba

u

nD

re

cahtth

tare

Rie

th

a rer cee

n

sn

s

rable Computing:

g of AgeLY FAWCETT ◆◆◆◆◆ Editor

47

Continued on page 4

str’s

e at a, notead-

o bee

ttives than

are

m.C)

nrcial

puting19,o aidnical,

cceler-comput-econfig-rform adware,dramati-e.eting prod-

ing.stration

systems to the meeting. The conferencewas an ideal forum for letting representa-tives of the member companies interactwith Xilinx R&D personnel and each other.

The conference provided some valuableinsights into the nature of the nascent butgrowing market for RC-based products.Among this small sampling, there weretwo main business models. Some compa-nies specialize in providing hardwareand software tools to OEM accounts thatdevelop their own products, while othermember companies are focused on theirown specific end applications.

The first category includes AnnapolisMicro Systems (Annapolis, MD), VirtualComputer Corp. (Reseda, CA), and GigaOperations (Berkeley, CA). All are makingsignificant strides in the development ofRC-based hardware platforms and soft-

ware tools. Oneof the mostinteresting as-pects of theirpresentationswas the mentionof the types oflarge corporateOEM accountsthat are using or

evaluating those products — names likeBoeing, Ericsson, Loral, NTT, Delco,E-Systems and TRW.

Other companies are using RC-basedsystems in their end products to tackle awide variety of high-performance comput-ing tasks, ranging from satellite communi-cations to automated searches of DNAsequences to 3-D graphic rendering forvideo games.

conferenceome valuable insightsature of the nascenting market for RC-ed products.❞

Dear Reader,XCell is intended to provide you, our users, with the latestinformation about Xilinx products and their applications. Inthis issue, we’d like to get your feedback on the effective-ness of this publication. By answering the following ques-tions, you’ll help us determine which articles are the mostuseful to you. In addition, we’d like your suggestions on howto improve the distribution of the XCell newsletter. Our goalis to make XCell a source of information to help you get themost out of Xilinx products and services.

After marking your choices, please tearoff or copy the page and send it to:

6. How would you rank the usefulness of the categories ofinformation in XCell listed below?(circle one; 1=not useful at all; 5=extremely useful)

Not VeryGENERAL FEATURES useful useful

From The Fawcett: 1 2 3 4 5Editorial comments on issues of significancein the programmable logic industry.

Guest editorial: 1 2 3 4 5Xilinx senior staff members highlightthe companies strategies and directions.

Customer success story: 1 2 3 4 5Applications that currently use Xilinx products.

General interest features: 1 2 3 4 5Updates on new product literature,technical conferences, financial status

Not VeryPRODUCT INFORMATION useful useful

Components: 1 2 3 4 5New product introductions, new speed grades, etc.

Development systems: 1 2 3 4 5Additions to our development system product line.

Design hints and issues 1 2 3 4 5

Recurring, informational charts 1 2 3 4 5Current availability of components, development systemsand third-party programmers and software.

XCell 3Q96 Reader Survey

Jan HoutsXilinx Inc.2100 Logic DriveSan Jose, CA 95124Fax: 408-879-4676

Of course, any additional comments are welcome.

To: Jan Houts, XilinxFax: 408-879-4676From: _________________________

(optional)

Company: _______________________________

1. Do you read every issue of XCell? ❏ Yes ❏ No

2. How many people read your copy of XCell? __________

2. What amount of time do you generally spend readingan issue of the XCell newsletter?❏ 5-15 min. ❏ 15-30 min. ❏ 30-60 min ❏ Over 1 hour

3. XCell is mainly distributed quarterly as a hard copymagazine. Do you receive it consistently?❏ Yes ❏ No

4. Technology makes other XCell formats possible. Pleaserank these five options according to your preference.(rank most preferred format as 1, second most as 2, etc.)

_______Access via the Xilinx Website_______E-mailed to you_______CD-ROM mailed to you_______Faxed to you_______Hard copy (as it is now)

5. Do you have access to the Xilinx website?❏ Yes ❏ No

✁✁

CU

T HER

E AND

MAIL O

R FAX

✁✁

COMMENTS: _________________________________________________________________________________________________

____________________________________________________________________________________________________________

____________________________________________________________________________________________________________

____________________________________________________________________________________________________________

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

GUEST EDITORIAL

3

46

Xilinx Takes the Lead in ISPStandardization EffortBy NEIL G. JACOBSON ◆ Manager, JTAG Research & Development

In-system programming (ISP) allows users to program and re-program partsthat are already soldered on a system board to facilitate prototyping, streamlinemanufacturing flows and enable remote system updating.

As ISP proliferates, end-users are strained by the difficulty of finding thirdparty applications solutions that address the system-level issues for the widevariety of ISP parts available. In addition, their own test and diagnostic softwaredevelopment costs escalate as new devices come on-line, requiring extensiveprogramming algorithm re-work.

At the last IEEE 1149.1 (JTAG) working group meeting, it was recognizedthat the use of the 4-pin 1149.1 test access port (TAP) as the platform for ISPdevelopment is becoming a de facto standard among most PLD manufacturers.(For example, XC9500 family CPLDs are always programmed through the TAP, andXC4000 series FPGAs optionally can be programmed through the TAP). The workinggroup chose to take a active role in bringing an ISP extension to 1149.1 under itspurview, with Xilinx taking the lead in this effort.

Xilinx and Hewlett Packard organized a meeting of more than 30 participantsfrom about 20 companies. This first ‘study group’ meeting was held on April 19 atHewlett Packard’s Manufacturing Test Division in Loveland, CO.The attendees included PLD manufacturers such as Xilinx, Altera,Lattice, AMD, Cypress and IBM; third-party tool manufacturerssuch as Asset Intertech, Corelis, Intellitech and APG Test Con-sultants; automatic test equipment manufacturers such as HP,GenRad and Teradyne; and ISP end-users such as Cisco Systemsand HP.

There was broad agreement that the value of standardizationwas great. Immediate applications could be envisioned in fieldsas diverse as emulation technologies and remote field test anddiagnostics. The vendor approaches to ISP were close enough toone another for the development of a standard approach to bemeaningful. General consensus seems to be forming in thefollowing areas:

A. The IDCODE and USERCODE registers are a vital part of any ISP device andwill probably be made mandatory.The XC9500 CPLD architecture already includes these optional 1149.1 functions.Indeed, not supporting these part, program content and version identification

❝As ISP proliferates, end-

users are strained by the difficulty

of finding third party applications

solutions that addresss the system-

level issues for the wide variety

of ISP parts available.❞

XILINX ALLIANCE-EDA CONTACTS-AUGUST 1996COMPANY NAME CONTACT NAME PHONE NUMBER E-MAIL ADDRESS

Accolade Design Automation Dave Pellerin (800) 470-2686 [email protected]

ACEO Technology, Inc. Ray Wei (510) 656-2189 [email protected]

Acugen Software, Inc. Nancy Hudson (603) 881-8821

Aldec David Rinehart (702) 456-1222 x12 [email protected]

ALPS LSI Technologies, Inc. David Blagden 441489571562

Alta Group Baruch Deutsch (408) 523-4137 [email protected]

Aptix Corporation Henry Verheyen (408) 428-6209 [email protected]

Aster Ingenierie S.A. Christopher Lotz +33-99537171

Cadence Ann Heilmann (408) 944-7016 [email protected]

Capilano Computing Chris Dewhurst (604) 522-6200 [email protected]

Chronology Corporation MikeMcClure (206) 869-4227 x116 [email protected]

CINA-Computer Integrated Network Analysis Brad Ashmore (415) 940-1723 [email protected]

Compass Design Automation Marcia Murray (408) 474-5002

Epsilon Design Systems, Inc. Cuong Do (408) 934-1536 [email protected]

Escalade Rod Dudzinski (408) 654-1651

Exemplar Logic Shubha Shukla (510) 337-3741 [email protected]

Flynn Systems Matt Van Wagner (603) 598-4444 [email protected]

Fujitsu LSI Masato Tsuru +81-4-4812-8043

Harmonix Corporation Shigeaki Hakusui (617) 935-8335

IK Technology Co. Tsutomu Someya +81-3-3839-0606 [email protected]

IKOS Systems Brad Roberts (408) 366-8509 [email protected]

INCASES Engineering GmbH Christian Kerscher +49-89-839910 [email protected]

ISDATA Ralph Remme +49-72-1751087 [email protected]

ITS Frank Meunier (508) 897-0028

Logic Modeling Corp. (Synopsis Division) Marnie McCollow (503) 531-2412 [email protected]

Logical Devices David Mot (303) 279-6868 x209

Mentor Graphics Sam Picken (503) 685-1298 [email protected]

MINC Kevin Bush (719) 590-1155

Minelec Marketing Department +32-02-4603175

Model Technology Greg Seltzer (503) 526-5465 [email protected]

OrCAD Mike Jingozian (503) 671-9500 [email protected]

Protel Technology Luise Markham (408) 243-8143

Quad Design Technology, Inc. Britta Sullivan (805) 988-8250

SimuCad Richard Jones (510) 487-9700 [email protected]

Sophia Sys & Tech Tom Tilbon (408) 232-4764

Summit Design Corporation Ed Sinclair (503) 643-9281

Synario Design Automation Jacquelin Taylor (206) 867-6257 [email protected]

Synopsys Lynn Fiance (415) 694-4289 [email protected]

Synplicity, Inc. Alisa Yaffa (415) 961-4962 [email protected]

Teradyne Mike Jew (617) 422-3753 [email protected]

The Rockland Group Rocky Awalt (916) 622-7935 [email protected]

Tokyo Electron Limited Shige Ohtani +81-3-334-08198 [email protected]

TopDown Design Solutions Art Pisani (603) 888-8811

Trans EDA Limited James Douglas +44-703-255118

VEDA DESIGN AUTOMATION INC Kathie O’Toole (408) 496-4515

Veribest Loren Lacy (303) 581-2330 [email protected]

Viewlogic John Dube (508) 480-0881 [email protected]

Visual Software Solutions, Inc. Andy Bloom (305) 423-8448

Zuken Makato Ikeda +81-4-594-27787

Zycad Mike Hannig (201) 989-2900

Inquiries about the Xilinx Alliance Program can be e-mailed to [email protected].

○○

○○

○○

○○

R

of a sys-

xt page

instructions makes ISP impractical since the revision level and contents tem would be otherwise unobtainable.

Continued on the ne

4

GUEST EDITORIAL

Continued from the previous pageB. The system-level issues related to ISP

(i.e., safe pin states during ISPoperations, describing how parts cansafely initialize after ISP is completed,etc.) must be addressed.The XC9500 ISPEN and ISPEX instruc-tions provide a framework for protectingthe user’s system during ISP operations.This type of functionality is absolutelycritical for developing a truly workableISP-based system — Xilinx has it now.

C. The interchange of informationshould be included as part of the

Products that have already reached themarketplace include Digital Wings forAudio from Metalithic Systems (Sausalito,CA), satellite ground station communica-tions systems from TSI Telsys (Columbia,

MD), the DeCypher II ‘Ge-netics Supercomputing PC’from Time Logic (InclineVillage, NV), and the X-CIMline of DSP accelerationmodules from MiroTechMicrosystems (Saint Laurent,Quebec, Canada).

• Available soon in retailmusic equipment stores,Digital Wings is a 128-track

audio authoring system that operates inthe Windows environment on a PC (seeXCell #20, page 42). Metalithic Systems

overall st(SVF), suserve asThe EZTato describ

D. The RUN“action” sor erase This is exfunction.

A final reworking grouConference be decided separate stawork or as astandard.

Either wathe new XC9best JTAG/ISing the nexttesting stan

THE FAWCETT

Continued from page 2

is targetinmarket wdevelopinthe cons

• TSI Telsysatellite ‘gMarshall will suppoStation p

• Time Logdesigned data, is pmaceuticaresearch multi-milli

• MiroTechthe FPGAaccelerati

❝Either way, Xilinx hasalready equipped the new XC9500 family withthe industry’s best JTAG/ISP capabilities and is

spearheading the next generation ofprogramming and testing standards.❞

❝The enormouspotential of reconfigurable

computing is beginning to

attract the attention of the

CAE tool vendors.❞

-

p

i

d

u

S

r

i

andard. Serial vector formatitably modified, might bestthat vehicle.g software generates SVF filese all XC9500 ISP operations.

TEST/IDLE state is thetate in which programminglatency times are spent.actly the way XC9500 parts

ort will be made to the 1149.1p at the International Testn October. At that time, it willwhether to pursue this as andard within the 1149 frame-n application of the 1149.1

y, Xilinx has already equipped500 family with the industry’sP capabilities and is spearhead-

generation of programming andards.◆

g the ‘music enthusiasts’ith this product, and isg a lower-cost version former market.

s recently sold several of itsateway’ systems to NASA’space Flight Center, where itrt programs such as the Spaceoject.

c’s DeCypher II system,for screening DNA sequenceroving popular with both phar-l companies and medicalfacilities, where it outperformson-dollar supercomputers.

Microsystems is addressing-based DSP market. Its DSPon modules are fully

2K/3

K/XC

CPLD

UN

IPL

ATFO

RMS

CO

MP

AN

Y N

AM

EP

RO

DU

CT N

AM

EV

ER

SIO

NF

UN

CT

ION

DE

SIG

NK

IT4K

5200

7K9K

LIBPC

SUN

RS60

00HP

7

VE

DA D

ES

IGN A

UTO

MA

TIO

N IN

CV

ulca

n4.

5S

imul

atio

nX

ILIN

X T

ool K

it✓

✓✓

Ver

ibes

tV

erib

est V

HD

L14

.0S

chem

atic

Ent

ryXi

linx F

PGA

Des

ign K

it3k

,4k

✓✓

✓✓

Ver

ibes

t Ver

ilog

14.0

Sim

ulat

ion

Xilin

x FPG

A D

esig

n Kit

3k,4

k✓

✓✓

✓V

eriB

est S

imul

ator

14.0

Sim

ulat

ion

Xilin

x FPG

A D

esig

n Kit

3k,4

k✓

✓✓

✓✓

DM

M14

.xD

esig

n M

anag

emen

tXi

linx F

PGA

Des

ign K

it3k

,4k

✓✓

✓✓

✓V

eriB

est S

ynth

esis

14.0

Syn

thes

isXi

linx F

PGA

Des

ign K

it3k

,4k

✓✓

✓✓

✓S

ynov

atio

n12

.2S

ynth

esis

Xilin

x FPG

A D

esig

n Kit

3k,4

k✓

✓✓

✓P

LDS

yn12

.0D

esig

n E

ntry

Syn

thes

is✓

7k✓

✓✓

Ver

Bes

t Des

ign

Cap

ture

14.x

Des

ign

Cap

ture

Xilin

x FPG

A D

esig

n Kit

3k,4

k✓

✓✓

✓✓

Acc

olad

e D

esig

n A

utom

atio

nP

eak

FP

GA

Plu

s2.

2H

DL,

Syn

thes

is, S

imul

atio

nIn

clud

ed✓

✓✓

✓✓

AC

EO

Tec

hnol

ogy,

Inc.

Asy

n3.

3S

ynth

esis

Incl

uded

✓✓

✓✓

✓✓

✓S

oftw

ire3.

3M

ulti-

FP

GA

Par

titio

ning

Incl

uded

✓✓

✓✓

✓✓

✓G

atra

n3.

3A

SIC

to F

PG

A N

etlis

t Map

ping

Incl

uded

✓✓

✓✓

✓✓

✓

Acu

gen

Sof

twar

e, In

c.S

harp

eye

2.60

Tes

tabi

lity

Ana

lysi

sA

ALC

A in

terf

ace

✓✓

7k✓

✓✓

ATG

EN

2.60

Aut

omat

ic T

est G

ener

atio

nA

ALC

A in

terf

ace

✓✓

7k✓

✓✓

ALP

S L

SI T

echn

olog

ies,

Inc.

Edw

ay D

esig

n S

yste

ms

Syn

thes

is/S

imlu

latio

n✓

✓✓

Apt

ix C

orpo

ratio

nS

yste

m E

xplo

rer

2.1

Sys

tem

Em

ulat

ion

Axe

ss 2

.Yes

✓

Apt

ix C

orpo

ratio

nA

SIC

Exp

lore

r2.

3A

SIC

Em

ulat

ion

Axe

ss 2

.34K

✓✓

Ast

er In

geni

erie

S.A

.X

ILLA

S4.

1LA

SA

R m

odel

gen

erat

ion

Wor

st C

ase

Sim

ulat

ion

✓7k

✓✓

✓

Chr

onol

ogy

Cor

pora

tion

Tim

ingD

esig

ner

3.0

Tim

ing

Spe

cific

atio

n an

d A

naly

sis

Incl

uded

✓✓

7k,9

k✓

✓✓

✓Q

uick

Ben

ch1.

0V

isua

l Tes

t Ben

ch G

ener

ator

Incl

uded

✓✓

7k,9

k✓

✓✓

✓

CIN

A-C

ompu

ter

Sm

artV

iew

er1.

0cS

chem

atic

XN

F In

terf

ace

✓7k

✓In

tegr

ated

Net

wor

k A

naly

sis

Eps

ilon

Des

ign

Sys

tem

sLo

gic

Com

pres

sor

Syn

thes

is o

ptim

izat

ion

✓✓

✓✓

✓✓

Fly

nn S

yste

ms

Pro

be3.

0T

esta

bilit

y A

naly

sis

Xili

nx K

it✓

✓7k

✓FS

-ATG

3.0

Tes

t Vec

tor G

ener

atio

nX

ilinx

Kit

✓✓

7k✓

CK

TSIM

3.0

Logi

c A

naly

sis

Xili

nx K

it✓

✓7k

✓FS

-SIM

3.0

Sim

ulat

ion

Xili

nx K

it✓

✓7k

✓

Fuj

itsu

LSI

PR

OV

ER

DT

op-D

own

Des

ign

Sys

tem

Incl

uded

3k,4

k✓

Har

mon

ix C

orpo

ratio

nP

AR

THE

NO

N2.

3S

ynth

esis

4k7k

✓✓

MIN

CP

LDes

igne

r-XL

3.3

Syn

thes

isX

ilinx

Des

ign

Mod

ule

✓✓

✓✓

Ter

adyn

eLa

sar

6S

imul

atio

nX

ilinx

I/F

Kit

✓✓

✓

The

Roc

klan

d G

roup

One

-Hot

Sta

te M

achi

ne L

ib.

Gra

phic

Des

ign

for O

ne-H

ot S

tate

Mac

hine

sX

ilinx

Kit

✓✓

✓✓

✓✓

✓

Tok

yo E

lect

ron

Lim

ited

Vie

wC

AD

1.2

FLD

L to

XN

F tr

ansl

ator

XN

FGE

N✓

Tra

ns E

DA

Lim

ited

Tran

sPR

O1.

2S

ynth

esis

Xili

nx L

ibra

ry✓

✓✓

Zuk

enTs

utsu

jiS

ynth

esis

/Sim

ulat

ion

XN

F In

terf

ace

3k,4

k✓

✓✓

Zyc

adP

arad

igm

RP

Rap

id P

roto

typi

ng✓

✓✓

Par

adig

m X

PG

ate-

leve

l Sim

✓✓

✓

EMERALDRUBY

Allia

nce

Prog

ram

Cat

egor

ies:

Dia

mon

d: T

hese

par

tner

s ha

ve s

trong

stra

tegi

c re

latio

nshi

ps w

ith X

ilinx

and

have

a di

rect

impa

ct o

n ou

r re

leas

es.

Typi

cally

, Xi

linx

is d

irect

ly in

volv

ed in

the

dev

el-

opm

ent

and

test

ing

of t

he i

nter

face

to

XAC

Tst

ep s

oftw

are

for

thes

e pr

oduc

ts.

Rub

y: T

hese

par

tner

s ha

ve a

hig

h de

gree

of

com

patib

ility

and

have

rep

eate

dly

show

n th

emse

lves

to

be s

igni

fican

t co

ntrib

u-to

rs t

o ou

r us

ers’

dev

elop

men

t so

lutio

ns.

Emer

ald:

Pro

ven

Xilin

x co

mpa

tibilit

y

XIL

INX

ALL

IAN

CE

-ED

A C

OM

PAN

IES

& P

RO

DU

CTS

-AU

GU

ST

1996

-2 O

F 2

45

44

5

Continued from theprevious page

❝this conference was their firstchance to talk with the early adopters of

reconfigurable computing technology; it iscertain not inconceivable that some cooperative

product development efforts will eventuallyresult from this meeting.❞

compliant with Texas InstrumentModules (TIM) specifications and aresupported by a library of common DSPfunctions. MiroTech has signed an OEMagreement with a major manufacturer ofDSP boards.

The remaining companies at the confer-ence previewed products in development.enVia Inc. (Menlo Park, CA) is developingconsumer telecommunications equipmentthat uses reconfigurable FPGAs to addressthe growing problem of incompatiblewireless telecommunications standards.Octree Corp. (Cupertino, CA) has imple-mented 3D volume rendering systems onAnnapolis Micro Systems and Giga Opera-tions platforms, and is developing productsfor both medical equipment and videogame manufacturers. Start-up AdaptiveCAD Technologies (Sunnyvale, CA) andconsulting firm Memec Design Services(Garden Valley, CA) also attended, andare applying RC technology in some newapplication areas (but it’s too early toreveal them).

Another encouraging sign was thepresence of representatives from several ofthe CAE companies in the Xilinx AllianceProgram. The enormous potential ofreconfigurable computing is beginning

to attract the attention of the CAE toolvendors. For many of these vendors, thisconference was their first chance to talkwith the early adopters of reconfigurablecomputing technology; it is certainly notinconceivable that some cooperative prod-uct development efforts will eventuallyresult from this meeting.

In summary, reconfigurable computingtechnology is continuing to ‘come of age,’with several companies already garneringrevenue from a wide variety of RC-basedproducts, penetration of RC technologyinto large, well-known electronic equip-ment manufacturers, and the attentionof leading design tool vendors. I’malready looking forward to nextyear’s conference.◆

Sharp-eyed readers may notice a slight change to the format of XCell inthis issue. The tables listing component availability, Xilinx software status, Alliancepartner information, and device programmer status have been moved from the“General Information” section to the last few pages of the newsletter. As a fewreaders have suggested, this will make the tables easier to find as well as providingfor better continuity for those who read the whole journal front-to-back.

We are always interested in reader feedback. This issue includes a short readersurvey on page 47. We would greatly appreciate if you would take a few minutes tofill out this questionnaire and mail or FAX it back to us. Alternatively, you can sendyour comments directly to me via E-mail at [email protected]. We’re lookingforward to hearing from you.◆

2K/3

K/XC

CPLD

UN

IPL

ATFO

RMS

CO

MP

AN

Y N

AM

EP

RO

DU

CT N

AM

EV

ER

SIO

NF

UN

CT

ION

DE

SIG

NK

IT4K

5200

7K9K

LIBPC

SUN

RS60

00HP

7

Ald

ecA

ctiv

e-C

AD

2.0

Sche

mat

ic E

ntry

& S

imul

atio

n &

HD

L Ed

itor

Incl

uded

✓✓

✓✓

✓

Cad

ence

Ver

ilog

2.4

Sim

ulat

ion

Xili

nx F

ront

End

✓✓

7k✓

✓✓

✓C

once

pt2.

1S

chem

atic

Ent

ryX

ilinx

Fro

nt E

nd✓

7k✓

✓✓

✓F

PG

A D

esig

ner

9504

Top

dow

n F

PG

A S

ynth

esis

Cal

l Xili

nx✓

✓7k

✓✓

✓✓

Syn

ergy

2.3

FPG

A S

ynth

esis

Cal

l Xili

nx✓

✓7k

✓✓

✓✓

Com

pose

r4.

4S

chem

atic

Ent

ryX

ilinx

Fro

nt E

nd✓

7k✓

✓✓

✓

Men

tor G

raph

ics

Aut

olog

icB

.xS

ynth

esis

Xili

nx S

ynth

esis

Lib

.✓

✓7k

✓✓

✓✓

Des

ign

Arc

hite

ctB

.xS

chem

atic

Ent

ryC

all X

ilinx

✓✓

7k✓

✓✓

✓Q

uick

Sim

IIB

.xS

imul

atio

nC

all X

ilinx

✓✓

7k✓

✓✓

✓Q

uick

HD

LB

.xS

imul

atio

nC

all X

ilinx

✓✓

7k✓

✓✓

✓

OrC

AD

Sim

ulat

e (W

in)

6.10

Sim

ulat

ion

Cal

l Xili

nx✓

✓7k

✓V

ST

386

+ (D

OS

)1.

2S

imul

atio

nC

all X

ilinx

✓7k

✓✓

Cap

ture

(Win

)7.

0S

chem

atic

Ent

ryC

all X

ilinx

✓✓

7k✓

✓S

DT

386

+ (D

OS

)1.

2S

chem

atic

Ent

ryC

all X

ilinx

✓7k

✓✓

PLD

386

+ (D

OS

)2.

0S

ynth

esis

Cal

l OrC

AD

✓7k

✓

Syn

ario

Des

ign

Aut

omat

ion

ABEL

6.2

Syn

thes

is, S

imul

atio

nX

EP

LD F

itter

✓✓

✓S

ynar

io2.

2S

chem

atic

Ent

ry, S

ynth

esis

& S

imul

atio

nS

YN

-LC

A✓

✓✓

✓✓

Syn

opsy

sF

PG

A C

ompi

ler

3.4b

Syn

thes

isC

all X

ilinx

✓✓

✓✓

✓✓

✓VS

S3.

4bS

imul

atio

nC

all X

ilinx

✓✓

✓✓

✓✓

✓D

esig

n C

ompi

ler

3.4b

Syn

thes

isC

all X

ilinx

✓✓

✓✓

✓✓

✓FP

GA

Exp

ress

1.0

Syn

thes

isC

all X

ilinx

✓✓

✓

Vie

wlo

gic

Wor

kVie

w O

ffice

7.1.

2/7.

2S

chem

/Sim

/Syn

thC

all X

ilinx

✓X

AC

T6✓

✓✓

✓✓

✓P

roS

ynth

esis

5.02

Syn

thes

isC

all X

ilinx

✓X

AC

T67k

✓✓

✓✓

✓P

roS

im6.

1S

imul

atio

n, T

imin

g A

naly

sis

Cal

l Xili

nx✓

XA

CT6

7k✓

✓✓

✓✓

Pro

Cap

ture

6.1

Sch

emat

ic E

ntry

Cal

l Xili

nx✓

XA

CT6

7k✓

✓✓

✓✓

Pow

erV

iew

6.0

Sch

em/S

im/S

ynth

/Tim

ing

Ana

lC

all X

ilinx

✓✓

✓✓

✓✓

✓

Cap

ilano

Com

putin

gD

esig

n W

orks

3.1

Sch

emat

ic E

ntry

/Sim

XD

-1✓

✓✓

Com

pass

Des

ign

AS

IC N

avig

ator

Sch

emat

ic E

ntry

Xili

nx D

esig

n K

it✓

✓7k

✓✓

Aut

omat

ion

X-S

ynS

ynth

esis

✓✓

✓Q

Sim

Sim

ulat

ion

✓✓

7k✓

✓

Esc

alad

eD

esig

nBoo

k2.

0D

esig

n E

ntry

✓✓

✓✓

Exe

mpl

ar L

ogic

Gal

ileo

3.2

Syn

thes

is/T

imin

g A

naly

sis

Sim

ulat

ion

Incl

uded

✓✓

✓✓

✓✓

✓

IK T

echn

olog

y C

o.IS

HIZ

UE P

RO

FES

SIO

NA

LS1.

05.0

2S

chem

atic

Ent

ry/S

imul

atio

nX

ilinx

Des

ign

Kit

✓✓

✓✓

IKO

S S

yste

ms

Voy

ager

2.11

Sim

ulat

ion

Xili

nx T

ool K

it✓

✓✓

INC

AS

ES

Eng

inee

ring

Gm

bHTh

eda

4.0

Sch

emat

ic E

ntry

Xili

nx K

it✓

✓

ISD

ATA

LOG

/iC C

lass

ic4.

2S

ynth

esis

LCA

-PP

✓7k

✓✓

✓✓

LOG

/iC2

4.2

Syn

thes

is S

imul

atio

nX

ilinx

Map

per

✓✓

7k✓

✓✓

✓

Logi

c M

odel

ing

Cor

p.S

mar

t Mod

elS

imul

atio

n M

odel

sIn

Sm

art M

odel

Lib

.✓

✓7k

,9k

✓✓

✓✓

(Syn

opsi

s D

ivis

ion)

LM12

00H

ardw

are

Mod

eler

Xili

nx L

ogic

Mod

ule

✓7k

,9k

✓✓

✓

Mod

el T

echn

olog

yV

-Sys

tem

/VH

DL

4.4j

(PC

)S

imul

atio

n✓

✓✓

✓✓

✓4.

6a (W

S)

Pro

tel T

echn

olog

yA

dvan

ced

Sch

emat

ic3.

1S

chem

atic

Ent

ry/C

lient

Ser

ver

Xili

nx In

terf

ace

✓7k

✓

Qua

d D

esig

n T

echn

olog

yM

otiv

e4.

3T

imin

g A

naly

sis

XN

F2M

TV

✓✓

✓✓

✓

Sim

uCad

Silo

s III

95.1

00S

imul

atio

nIn

clud

ed✓

✓✓

Sop

hia

Sys

& T

ech

Van

guar

d5.

31S

chem

atic

Ent

ryX

ilinx

I/F

Kit

✓✓

✓✓

✓

Sum

mit

Des

ign

Cor

p.V

isua

l HD

L3.

0G

raph

ical

Des

ign E

ntry

/Sim

ulat

ion/

Deb

ugE

DIF

Inte

rfac

e✓

✓✓

✓✓

✓✓

✓

Syn

plic

ity, I

nc.

Syn

plify

-Lite

2.6a

Syn

thes

isX

ilinx

Map

per

✓✓

9k✓

✓✓

✓S

ynpl

ify2.

6aS

ynth

esis

incl

uded

✓✓

9k✓

✓✓

✓

Top

Dow

n D

esig

n S

olut

ions

V-B

AK

1.1

XN

F to

VH

DL

tran

slat

orX

NF

inte

rfac

e✓

✓✓

✓✓

✓

DIAMOND RUBY

XIL

INX

ALL

IAN

CE

-ED

A C

OM

PAN

IES

& P

RO

DU

CTS

-AU

GU

ST

1996

-1 O

F 2

6

CUSTOMER SUCCESS STORIES

GPT Video Systems (Maidenhead,Berks, U.K.) designs and manufactureshigh-quality videoconferencing solutionsunder the brand name FOCUS. GPT VideoSystems is a long time user of Xilinx prod-ucts; its designers use FPGA technology tomaintain the flexibility and rapid time-to-market required in the fast moving multi-media market.

The flexibility of FPGA technologywas evident in the design of the latestFOCUS videoconferencing systems, whereXC4000TM series FPGAs were used for bothprototyping and production applications.

During system proto-typing, three

XC4013devices

wereused to

develop andtest the function-

ality required for alarge ASIC device. Mean-

while, XC4010 FPGAs wereused to implement key data rout-

ing and timing generation functions inthe production version of the video pro-cessing module.

An audio, video and data multiplexerdesign targeted for a semi-custom gatearray implementation was prototyped withthree XC4013 devices. The developmentwas carried out using Cadence Verilogsoftware running on a Sun SparcStation.The FPGAs provided a fast and flexibledevelopment route, culminating in a fully-functional ASIC on the first try. The ASICdevice holds about 30,000 gates of logic,with a 20 MHz system clock rate. Verifyingthe design with the FPGAs saved signifi-cant additional NRE costs and developmenttime that would have been incurred ifchanges to the design had been required

afmvethumac

ofuleFPvidvidthsigda16onofha

tafainsetefobethca

prprvaopstawrfro

a ABwiPCthat

Videoconferencing with XC400
teore
c

e

t-e

sccmxrn

ep

oore

i

c

t

r

43

PROGRAMMER SUPPORT FOR XILINX XC7300 CPLDS-AUGUST 1996

WHITE=changed since last issue

r committing to custom silicon. Further-re, this development route allowed betasions of the system to be shipped with FPGA solution before production vol-es of the ASIC were available, furtherelerating time-to-market.Three XC4010 FPGAs hold the majoritythe logic in the video processing mod- in the main codec design. Two of theGAs share a common design and act aseo routers, passing CCIR601 digitaleo data from various input sources to desired outputs. Each device is de-ned to route data in the form of an 8-bita bus, requiring two to be used for thebit data in the CCIR601 format. Thus, device handles the routing and control

the luminance data, and the otherndles the chrominance data.These two devices also perform thek of overlaying the graphical user inter-e directly onto the video outputs. Thisludes a patented function that produces

i-transparent video, allowing on-screent to be displayed in an easily-readablemat while not obscuring the live videoeath. The design makes specific use of

XC4000 architecture’s on-chip RAMability to implement fast look-up tables.The third XC4010 FPGA in the videocessing module is a timing generator,viding all the timing functions for theious video field store read and writerations. This FPGA also contains the

te machines that control the reading andting of captured video images to andm the graphics frame stores.The XC4010 designs were entered usingombination of schematic capture andEL hardware descriptions and verifiedh the ViewSim simulator, using a-based Viewlogic environment. Allee FPGAs are about 80% full and runa system clock speed of 13.5 MHz, a

MANUFACTURER MODEL 7318 7336 7336Q 7354 7372 73108 73144ADVANTECH PC-UPROG

LABTOOL-48 V1.31A V1.31A V1.31A V1.31A V1.31A V1.31AADVIN SYSTEMS PILOT-U40 10.84B 10.84B 10.84B 10.84B

PILOT-U84 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84BB&C MICROSYSTEMS, INC. PROTEUS Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96BP MICROSYSTEMS BP-1200 V3.15 V3.18 V3.15 V3.15 V3.15 V3.15

BP-2100 V3.15 V3.18 V3.15 V3.15 V3.15 V3.15DATAMAN DATAMAN-48 V1.30 V1.30 V1.30 V1.30 V1.30 V1.30DATA I/O 2900 Aug-96 Aug-96 Aug-96 Aug-96

3900/AUTOSITE Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96UNISITE Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96

DEUS EX MACHINAENGINEERING XPGM V1.40 V1.40 V1.40 V1.40 V1.40 V1.40E E TOOLS ALLMAX/ALLMAX+ V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U

MEGAMAX V1.1E V1.1E V1.1E V1.1E V1.1E V1.1EELAN 6000 APS 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96HI-LO SYSTEMS RESEARCH ALL-03A V3.09 V3.09 V3.09 V3.09 V3.09 V3.09

ALL-07 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09ICE TECHNOLOGY LTD Micromaster 1000/E V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V1.1

Speedmaster 1000/E V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V1.1Micromaster Lv V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V1.1Speedmaster Lv V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V1.1

LEAP ELECTRONICS LEAPER-10 V2.0 V2.0 V2.0 V2.0 V2.0 V2.0 V2.0LP U4 V2.0 V2.0 V2.0 V2.0 V2.0 V2.0 V2.0

LOGICAL DEVICES ALLPRO-88ALLPRO-88XRALLPRO-96 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26Chipmaster 2000 V2.4U V2.4U V2.4U V2.4U V2.4U V2.4UChipmaster 6000 V1.31A V1.31A V1.31A V1.31A V1.31A V1.31AXPRO-1 73108.304

MICROPROSS ROM9000 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96MQP ELECTRONICS SYSTEM 2000 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96

PINMASTER 48 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96NEEDHAM’S ELECTRONICS EMP20 V3.10 V3.10 V3.10 V3.10 V3.10 V3.10SMS EXPERT 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96

OPTIMA 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96STAG ECLIPSE 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26SUNRISE T-10 UDP Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96

T-10 ULC Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96SUNSHINE ELECTRONICS POWER-100 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96

EXPRO-60/80 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96SYSTEM GENERAL TURPRO-1/FX Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96

MULTI-APRO Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96TRIBAL MICROSYSTEMS Flex-700 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09

TUP-300 V3.09 V3.09 V3.09 V3.09 V3.09TUP-400 V3.09 V3.09 V3.09 V3.09 V3.09

XELTEK SUPERPROSUPERPRO II 2.4B 2.4B 2.4B 2.4BSUPERPRO II/P 2.4B 2.4B 2.4B 2.4B

XILINX HW-130 1.15 1.15 1.06 1.16 1.07 1.07 1.02

0 FPGAs

42

7

PROGRAMMER SUPPORT FOR XILINX XC7200 CPLDS — AUGUST 1996

WHITE=changed since last issueNote: The XC7236 and XC7272 columns have been eliminated

MANUFACTURER MODEL XC7236A XC7272AADVANTECH PC-UPROG

LabTool-48 V1.31A V1.31AADVIN SYSTEMS Pilot-U40 10.84B 10.84B

Pilot-U84 10.84B 10.84BB&C MICROSYSTEMS INC. Proteus Aug-96 Aug-96BP MICROSYSTEMS BP-1200 3.15 3.15

BP-2100 3.15 3.15DATAMAN DATAMAN-48 V1.30 V1.30DATA I/O UniSite Aug-96 Aug-96

2900 Aug-96 Aug-963900 Aug-96 Aug-96AutoSite Aug-96 Aug-96

DEUS EX MACHINA ENGINEERING XPGM V1.40 V1.40E E TOOLS ALLMAX/ALLMAX+ V2.4U V2.4U

MEGAMAX V1.1E V1.1EELAN DIGITAL SYSTEMS 6000 APS 3Q96 3Q96HI-LO SYSTEMS RESEARCH All-03A V3.09 V3.09

All-07 V3.09 V3.09ICE TECHNOLOGY LTD Micromaster 1000/E V1.1 V1.1

Speedmaster 1000/E V1.1 V1.1Micromaster LV V1.1 V1.1Speedmaster LV V1.1 V1.1

LEAP ELECTRONICS LEAPER-10 V2.0 V2.0LP U4 V2.0 V2.0

LOGICAL DEVICES ALLPRO-88ALLPRO-88XRALLPROF-96 6.4.26 6.4.26Chipmaster 2000 V2.4U V2.4UChipmaster 6000 V1.31A V1.31AXPRO-1

MICROPROSS ROM9000 3Q96 3Q96MQP ELECTRONICS SYSTEM 2000 Aug-96 Aug-96

PIN-MASTER 48 Aug-96 Aug-96NEEDHAM’S ELECTRONICS EMP20 V3.10 V3.10SMS Expert 3Q96 3Q96

Optima 3Q96 3Q96Multisyte 3Q96 3Q96

STAG Eclipse 6.4.26 6.4.26SUNRISE ELECTRONICS T-10 UDP Aug-96 Aug-96

T-10 ULC Aug-96 Aug-96SUNSHINE ELECTRONICS POWER-100 Aug-96 Aug-96

EXPRO-60/80 Aug-96 Aug-96SYSTEM GENERAL TURPRO-1/FX Aug-96 Aug-96

MULTI-APRO Aug-96 Aug-96TRIBAL MICROSYSTEMS TUP-300 V3.09 V3.09

TUP-400 V3.09 V3.09FLEX-700 V3.09 V3.09

XELTEK SUPERPROSUPERPRO II 2.4B 2.4BSUPERPRO II/P 2.4B 2.4B

XILINX HW-130 1.14 1.04

performance level that was easily reachedusing timing constraints and automaticplacement and routing tools.

To further reduce hardware costs duringvolume production of the codecs, the XC4010FPGA designs were frozen and converted intoHardWireTM XC4310 devices. Since the Hard-Wire devices are pin and function compatiblewith the FPGAs that they replace, systemflexibility is maintained; the HardWire devicescan be replaced with newly-designed FPGAsif the design evolves at a later date. Accordingto Richard McCandless, Project Leader at GPT

Video Systems, “The HardWire conversionwent extremely well, with very little engi-neering effort required at all, and theycame in on time! In fact, it surprised ushow little engineering effort was needed.”

As noted by McCandless, “These videointerface designs were fairly complex, butthe FPGAs proved to be very flexible andeasy to work with. The high level of inte-gration provided by the FPGA devices hashelped to create the most user-friendlygraphical user interface in the video-conferencing industry.”◆

Video Processing With XC7300 CPLDsBICOM, Inc., (Monroe, CT) is a provider of hard-

ware and software “building blocks” for developing awide range of voice processing applications.BICOM’s products are used in the develop-ment of systems for voice mail, interactivevoice response, audiotex, dictation and callcenter management.

The recent design of their new Geminiseries of high-density computer telephonyplatforms required a high-performance CPLD to integratea variety of logic functions. With cost and ease-of-useconsiderations in mind, the XilinxXC7300TM CPLD family was chosen.

The voice processing boardcontains 14 XC7336 devices.The XC7336-5 CPLDs are usedto hold a variety of logic functions, in-cluding address decoders, state machines, I/O func-tions and glue logic, with XC7336-15 CPLDs for the com-

plicated timing associated withthe telecommunications channel.If BICOM had used traditionalPALs for these logic functions,the design would have encom-

passed two boards rather than one.The design was entered and implemented on a PC

using OrCAD schematic entry tools. The com-plexity of the design (which included a mix ofanalog and digital technologies) and tight devel-opment schedules dictated the use of program-mable devices with predictable performance andgood pin-locking capabilities. The XC7336 CPLDfulfilled both these needs. Pinouts were pre-

assigned and maintained throughout multiple designiterations. This allowed the designers to concentrate onthe more difficult architectural aspects of the design.

As first-time Xilinx users, BICOM engineers wereimpressed with the level of technical support

provided by the Xilinx team.In summary, by

using theXC7300 CPLD

family, BICOMengineers were

able to meet theirperformance needs, reduce design compand save valuable board space as well.◆

GPT

lexity and cost,

41

8

Xilinx Helps Fund New Seiko-Epson Foundryour competitive position and allow us todesign products with ever higher densitiesand faster performance, “ stated XilinxChief Executive Officer Willem Roelandts.“Just as important, it will help us meetgrowing customer demand worldwide forour products into the next century.”

This investment agreement furtherstrengthens the close relationship betweenXilinx and Seiko-Epson; Seiko-Epson hasbeen a supplier to Xilinx for more than adecade. Xilinx also will maintain its exist-ing foundry partnerships with Yamaha,Taiwan Semiconductor ManufacturingCompany (TSMC), United MicroelectronicsCorporation (UMC) and IC Works. Asreported in XCell #20, Xilinx owns a 25%equity stake in a new foundry being con-structed by UMC in Taiwan and scheduledto come on-line in the first half of 1997.◆

New Data Book Now Availablefiles) and its installer are included on theCD-ROM. The main table of contents,chapter tables of contents and the index allinclude hypertext links to immediatelyjump to the appropriate pages in the book.

At 900 pages, the data book includesdata sheets for the XC7300, XC9500,XC3000A/L, XC3100A/L, XC4000E,XC4000EX/XL, XC5200, XC6200, andXC1700D device families. Product specifi-cations for the older XC2000, XC3000,XC3100, and XC4000/A/H/D/L families arenot included, but are still available onWebLINX. The military/high-reliability andHardWireTM product lines are overviewed,but detailed product specifications are stillfound in separate, dedicated documents.

To obtain a copy, contact your localXilinx sales representative.◆

WHI

TE=c

hang

ed si

nce l

ast is

sue;

1736

A, 17

65 an

d 171

28 co

lumns

elim

inate

d sinc

e las

t issu

e

PR

OG

RA

MM

ER

SU

PP

OR

T FO

R X

ILIN

X X

C17

00 S

ER

IAL

PR

OM

S-A

UG

US

T 19

96XC

1718

DXC

1736

DXC

1718

LXC

1712

8DXC

1712

8LM

ANUF

ACTU

RER

MO

DEL

XC17

65D

XC17

65L

XC17

256D

XC17

256L

LINK

CO

MPU

TER

GRA

PHIC

SCL

K-31

00V5

.61

V5.6

1LO

GIC

AL D

EVIC

ESAL

LPRO

-40

ALLP

RO-8

8V2

.7V2

.7AL

LPRO

-88X

RV2

.7V2

.7AL

LPRO

-96

6.5.

106.

5.10

6.5.

106.

5.10

CHIP

MAS

TER

2000

V2.4

UV2

.4U

CHIP

MAS

TER

6000

V1.3

1AAu

g-96

V1.3

1AAu

g-96

XPRO

-1SP

ROM

.310

SPRO

M.31

0SP

ROM

.310

SPRO

M.31

0M

QP

ELEC

TRO

NICS

MO

DEL

200

6.46

6.46

6.46

SYST

EM 20

002.

252.

252.

25PI

N-M

ASTE

R 48

Aug-

96Au

g-96

Aug-

96M

ICRO

PRO

SSR

OM

500

0 B

3Q96

3Q96

RO

M 3

000

U3Q

963Q

96R

OM

9000

3Q96

NEED

HAM

’S E

LECT

RONI

CSEM

P20

V3.1

0V3

.10

RED

SQUA

REIQ

-180

IQ-2

80U

niw

riter

40

Chi

pmas

ter 5

000

SMS

Expe

rt3Q

963Q

96O

ptim

a3Q

963Q

96M

ultis

yte

3Q96

3Q96

Sprin

t Plu

s48

3Q96

STAG

Eclip

se6.

5.10

6.5.

106.

5.10

6.5.

10Q

uasa

rSU

NRIS

ET-

10 U

DP

Aug-

96Au

g-96

T-10

ULC

Aug-

96Au

g-96

SUNS

HINE

POW

ER-1

00Au

g-96

Aug-

96EX

PRO

-60/

80Au

g-96

Aug-

96SY

STEM

GEN

ERAL

TURP

RO-1

V2.2

6HV2

.26H

V2.2

6HTU

RPRO

-1 F/

XV2

.26H

V2.2

6HV2

.26H

TURP

RO-1

T/X

APRO

V1.2

4M

ULTI

-APR

OV1

.16

V1.1

6V1

.16

V1.1

6TR

IBAL

MIC

ROSY

STEM

STU

P-30

0Au

g-96

Aug-

96Au

g-96

Aug-

96TU

P-40

0Au

g-96

Aug-

96Au

g-96

Aug-

96FL

EX-7

00Au

g-96

Aug-

96Au

g-96

Aug-

96XE

LTEK

Supe

rPRO

Supe

rPRO

II2.

4B2.

4B2.

4B2.

4BSu

perP

RO II/

P2.

4B2.

4B2.

4B2.

4BXI

LINX

HW

-112

5.00

5.00

5.00

HW

-130

2.01

2.01

2.01

1.00

Xilinx has announced its funding ofup to $300 million for the construction of anew semiconductor manufacturing facility.The facility will be built and operated bySeiko-Epson Corp. in Sakata, Japan (about200 miles north of Tokyo). Xilinx willmake incremental advance payments overthe next two and one-half years to helpfinance construction of the facility. Inreturn, Xilinx will receive a specified num-ber of wafers from the new line throughthe year 2002.

The new operation will manufacture 8"wafers using advanced 0.35 to 0.25 micronCMOS technology. In time, these advancedprocesses will enable the development ofprogrammable logic devices with capacitiesreaching 500,000 gates. Production at thefacility is expected to begin in early 1998.

“We’re confident that our continuingpartnership with Seiko-Epson will enhance

Both CD-ROM and printed versions ofthe new “Xilinx Programmable Logic DataBook” are now available. The material in

the new data book also is available onWebLINXTM, the Xilinx World

Wide Web site(www.xilinx.com), in theform of individual prod-uct specifications.

The CD-ROM, a firstwith this edition, works

with PCs, Sun worksta-tions, and HP worksta-

tions. Detailed tables ofcontents and the ability to search for

keywords makes the CD-ROM a valuabletool. The entire data book resides in asingle “.pdf” file. The Acrobat™ Readerprogram (that allows users to view .pdf

XC17

18D

XC17

36D

XC17

18L

XC17

128D

XC17

128L

MAN

UFAC

TURE

RM

OD

ELXC

1765

DXC

1765

LXC

1725

6DXC

1725

6LAD

VANT

ECH

PC-U

PRO

GLA

BTO

OL-

48Au

g-96

Aug-

96Au

g-96

Aug-

96AD

VIN

PILO

T-U2

410

.84B

10.8

4BPI

LOT-

U28

10.8

4B10

.84B

PILO

T-U3

210

.84B

10.8

4BPI

LOT-

U40

10.8

4B10

.84B

PILO

T-U8

410

.84B

10.8

4BPI

LOT-

142

10.8

4B10

.84B

PILO

T-14

310

.84B

10.8

4BPI

LOT-

144

10.8

4B10

.84B

PILO

T-14

510

.84B

10.8

4BB&

C M

ICRO

SYST

EMS

INC.

Prot

eus-

UP40

3.7Q

3.7Q

BP M

ICRO

SYST

EMS

CP-1

128

EP-1

140

BP-1

200

V3.1

5V3

.15

V3.1

5BP

-210

0V3

.15

V3.1

5V3

.15

BYTE

K13

5H-F

T/U

MTK

-100

0M

TK-2

000

MTK

-400

0

DAT

AMAN

DAT

AMAN

-48

V1.3

0V1

.30

V1.3

0DA

TA I/

OUn

iSite

Aug-

96Au

g-96

Aug-

96Au

g-96

2900

Aug-

96Au

g-96

Aug-

96Au

g-96

3900

Aug-

96Au

g-96

Aug-

96Au

g-96

Auto

Site

Aug-

96Au

g-96

Aug-

96Au

g-96

Chip

Lab

Aug-

96Au

g-96

Aug-

96Au

g-96

2700

Aug-

96Au

g-96

Aug-

96Au

g-96

DEUS

EX

MAC

HINA

XPG

MV1

.40

V1.4

0V1

.40

V1.4

0E

E TO

OLS

ALLM

AX/A

LLM

AX+

V2.4

UV2

.4U

V2.4

UM

EGAM

AXV1

.1E

V1.1

EV1

.1E

ELAN

DIG

ITAL

SYS

TEM

S30

00-1

4550

00-1

4560

00 A

PS3Q

963Q

963Q

96HI

-LO

SYST

EMS R

ESEA

RCH

All-0

3AAu

g-96

Aug-

96Au

g-96

Aug-

96Al

l-07

Aug-

96Au

g-96

Aug-

96Au

g-96

ICE

TECH

NOLO

GY

LTD

Micr

omas

ter 1

000/

EV3

.17

V3.1

7V3

.17

V3.1

7Sp

eedm

aste

r 100

0/E

V3.1

7V3

.17

V3.1

7V3

.17

Mic

rom

aste

r LV

V3.1

7V3

.17

V3.1

7V3

.17

LV40

Por

tabl

eV3

.17

V3.1

7V3

.17

V3.1

7Sp

eedm

aste

r LV

V3.1

7V3

.17

V3.1

7V3

.17

LEAP

ELEC

TRON

ICS

LEAP

ER-1

0V2

.0V2

.0LP

U4

V2.0

V2.0

40

9

TECHNICAL TRAINING UPDATE

Both Schematic- and Synthesis-Based Classes Offered

What’s New onWebLINX TM

Xilinx Home Page • www.xilinx.com

WebLINX was recently namedan Infoworld HotSite! Here are a few ofthe reasons why:

◆ SmartSearchTM Agents ReleasedCome visit the industry-wide search en-gine made specifically for topics involv-ing programmable logic. You can createyour own agents to notify you by e-mailas material you want becomes availablein any of multiple sites on the web.

◆ Xilinx Guided TourCheck out this on-line company andproduct overview covering topics such asXilinx corporate and product strategies,device selection, XACTstepTM softwaresolutions, quality assurance and Xilinxtechnical support services.

◆ Product SpotlightsExamine a showcase of our latest prod-ucts, currently featuring the XC4000EXand XC9500 device families and theFoundation Series software, with itseasy-to-use, low-cost VHDL synthesissolution.

◆ On-Line Net SeminarsIn cooperation with Marshall Industries,Xilinx holds live seminars on theInternet, complete with an on-line slideand audio presentation and a live chat-response forum for asking questions.Recorded seminars on the XC5200 andXC9500 device families also are avail-able to review at your convenience.◆

Two basic classes are available fromXilinx, a schematic-based and a synthe-sis-based class.

Actually, both classes focus more onoverall design methodologies for usingXilinx devices, rather than the specificfront-end tools. (The tutorials shipped withthe development systems provide thespecific tool training for the new user.)The schematic-based class has traditionallyutilized ViewLogic tools in the examplesand labs. However, with the introductionof XACTstep version 6.0.1, the class hasbeen updated to use the FoundationTM

Development System and its front-endtools from Aldec.

The synthesis-based class uses theSynopsys tools. The course goes beyond

explaining and demonstrating the basicconcepts behind HDL-based design byexamining many of the specific languageconstructs that should be used when de-signing with these tools.

All designers can benefit from takingone of these classes. Even designers al-ready familiar with Xilinx technology canlearn some new methods to reduce designtime and increase device performance.

Remember, either class (and even cus-tomized classes) can be presented right atyour own facility. Please contact your localSales office or our training registrar withyour needs. The latest schedule of classesand contact information is always availableon WebLINX, our World Wide Web site(www.xilinx.com). ◆

XILINX INDIVIDUAL PRODUCTS XILINX PACKAGES

XIL

INX

RE

LEA

SE

D S

OFT

WA

RE

STA

TUS

-AU

GU

ST

1996

XIL

INX P

AR

TC

UR

RE

NT V

ER

SIO

N BY

PLA

TFO

RM

LAST

PR

EV

IOU

SP

RO

DU

CT

PR

OD

UC

TP

RO

DU

CT

REF

EREN

CE

PC

1S

N2

HP

7U

PD

TV

ER

SIO

NN

OT

ES/

KEY

CA

TEG

OR

YD

ES

CR

IPTI

ON

FU

NC

TIO

NN

UM

BE

R6.

24.

1.X

9.01

CO

MP

REL

EASE

FEAT

UR

ES

CO

RE

XE

PLD

XC7K

Sup

port

Cor

e Im

plem

enta

tion

DS

-550

-xxx

6.01

5.2.

15.

2.1

7/9

65.

2/6.

0P

C u

pdat

e by

requ

est o

nly

XA

BE

L-C

PLD

XC7K

, XC

9500

Sup

port

Ent

ry/S

imul

atio

n/C

ore

DS

-571

-PC

16.

117

/96

6.10

New

ver

sion

w/X

C95

00; F

irst

shi

p 4/

29/9

6X

AC

T-C

PLD

XC7K

, XC

9500

Sup

port

Cor

e +

Inte

rfac

eD

S-5

60-x

xx6.

0.1

6.0.

16.

0.1

7/9

66.

0M

ento

r8.

4=A

.4In

terf

ace

and

Libr

arie

sD

S-3

44-x

xx5.

2.1

5.2.

17

/96

5.20

OrC

AD

Inte

rfac

e an

d Li

brar

ies

DS

-35-

PC

16.

0.1

7/9

66.

0S

uppo

rt fo

r SD

T+

, VS

T+

v1.

2S

ynop

sys

Inte

rfac

e an

d Li

brar

ies

DS

-401

-xxx

5.2.

15.

2.1

7/9

65.

20In

clud

es X

C52

00 X

-BLO

X S

uppo

rtV

iew

logi

cP

RO

capt

ure

Inte

rfac

e an

d Li

brar

ies

DS

-390

-PC

16.

0.1

7/9

65.

2/6.

0In

clud

es P

RO

Ser

ies

6.1

Vie

wlo

gic

PR

Osi

mIn

terf

ace

and

Libr

arie

sD

S-2

90-P

C1

6.0.

17

/96

6.0

Incl

udes

PR

O S

erie

s 6.

1V

iew

logi

cIn

terf

ace

and

Libr

arie

sD

S-3

91-x

xx6.

0.1

5.2.

15.

2.1

7/9

66.

0XA

BEL

Ent

ry,S

imul

atio

n,Li

b, O

ptim

izer

DS

-371

-xxx

6.0.

15.

2.1

5.2.

17

/96

5.2/

6.0

Now

ava

ilabl

e on

HP

7X

BLO

XM

odul

e G

ener

ator

& O

ptim

izer

DS

-380

-xxx

6.0.

15.

2.1

5.2.

17

/96

5.2/

6.0

EV

erilo

g2K

,3K

,4K

,7K

Lib

rarie

sM

odel

s &

XN

F T

rans

lato

rE

S-V

ER

ILO

G-x

xx1.

001.

00na

naS

un a

nd H

P

SIL

ICO

N SU

PP

OR

T

2K3K

4K5K

7K9K

Cad

ence

XX

XX

XX

DS

-CD

N-S

TD-x

xx5.

2.1

5.2.

17

/96

5.20

Men

tor

XX

XX

XX

DS

-MN

8-S

TD-x

xx5.

2.1

5.2.

17

/96

5.20

Men

tor

XX

XX

XX

DS

-MN

8-A

DV

-xxx

7.00

7.00

nana

UO

rCA

DX

XX

XX

XD

S-O

R-B

AS

-PC

16.

0.1

7/9

66.

0C

usto

mer

w/v

6.0

will

rece

ive

v6.0

.1 u

pdat

eO

rCA

DX

XX

XX

XD

S-O

R-S

TD-P

C1

6.0.

17

/96

6.0

Syn

opsy

sX

XX

XX

DS

-SY

-STD

-xxx

5.2.

15.

2.1

7/9

65.

20In

clud

es D

S-4

01 v

5.2

Syn

opsy

sX

XX

XX

DS

-SY

-AD

V-x

xx7.

007.

00na

naIn

clud

es D

S-4

01 v

5.2

UV

iew

logi

cX

XX

XX

XD

S-V

L-B

AS

-PC

16.

0.1

7/9

66.

0C

usto

mer

w/v

6.0

will

rece

ive

v6.0

.1 u

pdat

eV

iew

logi

cX

XX

XX

XD

S-V

L-S

TD-x

xx6.

006.

0.1

7/9

66.

0V

iew

logi

cX

XX

XX

XD

S-V

L-A

DV

-xxx

7.00

7.00

7.00

nana

Vie

wlo

gic/

SX

XX

XX

XD

S-V

LS-B

AS

-PC

16.

0.1

7/9

66.

0In

clud

es P

RO

Ser

ies

6.1

Vie

wlo

gic/

SX

XX

XX

XD

S-V

LS-S

TD-P

C1

6.0.

17

/96

6.0

Incl

udes

PR

OS

erie

s 6.

1V

iew

logi

c/S

XX

XX

XX

DS

-VLS

-EX

T-P

C1

6.0.

17

/96

6.0

Incl

PR

OS

erie

s 6.

1/P

RO

synt

h 5.

02X

Vie

wllo

gic/

SX

XX

XX

XD

S-V

LS-A

DV

-PC

17.

00na

naU

3rd

Par

ty A

llian

ceX

XX

XX

XD

S-3

PA

-BA

S-x

xx6.

0.1

7/9

66.

03r

d P

arty

Alli

ance

XX

XX

XX

DS

-3P

A-S

TD-x

xx6.

0.1

5.2.

15.

2.1

7/9

65.

2/6.

0In

clud

es 5

02/5

50/3

803r

d P

arty

Alli

ance

XX

XX

XX

DS

-3P

A-A

DV

-xxx

7.00

7.00

7.00

nana

Incl

udes

502

/550

/380

& F

ound

ryF

ound

atio

n S

erie

sX

XX

XX

XD

S-F

ND

-BA

S-P

C1

6.0.

17

/96

6.0

Incl

udes

sup

port

for X

C40

00E

and

XC

9500

Fou

ndat

ion

Ser

ies

XX

XX

XX

DS

-FN

D-B

SV

-PC

16.

0.1

7/9

66.

0In

clud

es s

uppo

rt fo

r XC

4000

E a

nd X

C95

00F

ound

atio

n S

erie

sX

XX

XX

XD

S-F

ND

-STD

-PC

16.

0.1

7/9

66.

0In

clud

es s

uppo

rt fo

r XC

4000

E a

nd X

C95

00F

ound

atio

n S

erie

sX

XX

XX

XD

S-F

ND

-STV

-PC

16.

0.1

7/9

66.

0In

clud

es s

uppo

rt fo

r XC

4000

E a

nd X

C95

00Lo

giC

ore-

PC

I Sla

veX

LC-D

I-PC

IS-C

1.10

1.10

1.10

nana

Tar

get o

nly;

Req

sig

ned

lic a

gree

men

tLo

giC

ore-

PC

I Mas

ter

XLC

-DI-P

CIM

-C1.

101.

101.

108

/96

1.0

Initi

ator

and

targ

et; R

eq s

igne

d lic

agr

eem

ent

Eva

luat

ion

XX

XX

XX

DS

-EV

AL-

XX

X-C

2.00

2.00

2.00

nana

PC

, Sun

, HP

kits

now

ava

ilabl

ew

ith v

5.2.

1 an

d v6

.0.1

KEY:

N=N

ew P

rodu

ct,

E= E

ngin

eerin

g so

ftwar

e fo

r in

-war

rant

y us

ers

by r

eque

st o

nly,

U=

Upd

ate

by r

eque

st o

nly,

PR =

Pre

-rele

ase

requ

iring

in-

war

rant

y st

atus

or

Prod

uct

Mar

ketin

g ap

porv

al

10

39

Learn about the newest Xilinx products and services through our extensive library ofproduct literature. The most recent pieces are listed below. To order or to obtain a com-plete list of all available literature, please contact your local Xilinx sales representative.◆

New ProductLiterature

1996 Programmable Logic Data Book Technical Data 00103031996 Programmable Logic Data Book on CD-ROM Technical Data 500360Product Overview Brochure Features & Benefits 0010130-05Software Selector Guide Features & Benefits 0010304FPGA Brochure Features & Benefits 0010305

TITLE DESCRIPTION NUMBER

EuroDAC & EuroVHDLSept. 16-20Geneva, Switzerland

International Workshopon Field ProgrammableLogic and ApplicationsSept. 23-25Darmstadt, Germany

PCI EuropeOct. 1-2Paris, France

DSP GermanyOct. 1-2Munich, Germany

Look for Xilinx technical papers and/or product exhibits at these upcoming industry fo-rums. For further information about any of these conferences, please contact KathleenPizzo (Tel: 408-879-5377 FAX: 408-879-4676).◆

UPCOMING EVENTS

ElectronicaNov. 12-15Munich, Germany

Photonics EastNov. 18-22Boston, Massachusetts

BIAS & DSP ItalyNov. 26-29Milan, Italy

DSP UKDec. 3-4London, United Kingdom

DSP World/ICSPATOct. 8-10Boston, MA

Silicon DesignConferenceOct. 9-10Birmingham,United Kingdom

WESCONOct. 22-24Anaheim, California

DSP FranceOct. 22-24Paris, France

PIN

S

TYPE

CO

DE

XC

4005

LX

C40

10L

XC

4013

LX

C52

02X

C52

04X

C52

06X

C52

10X

C52

15X

C72

36A

XC

7272

AX

C73

18X

C73

36X

C73

36Q

XC

7354

XC

7372

XC

7310

8X

C73

144

XC

9536

XC

9510

8X

C95

216

AUGUST 1996

PLASTIC LCC PC44PLASTIC QFP PQ44PLASTIC VQFP VQ44CERAMIC LCC WC44PLASTIC DIP PD48PLASTIC VQFP VQ64PLASTIC LCC PC68CERAMIC LCC WC68CERAMIC PGA PG68PLASTIC LCC PC84CERAMIC LCC WC84CERAMIC PGA PG84CERAMIC QFP CQ100PLASTIC PQFP PQ100PLASTIC TQFP TQ100PLASTIC VQFP VQ100TOP BRZ. CQFP CB100CERAMIC PGA PG120PLASTIC PGA PP132CERAMIC PGA PG132PLASTIC TQFP TQ144CERAMIC PGA PG144CERAMIC PGA PG156PLASTIC PQFP PQ160CERAMIC QFP CQ164TOP BRZ. CQFP CB164PLASTIC PGA PP175CERAMIC PGA PG175PLASTIC TQFP TQ176CERAMIC PGA PG184CERAMIC PGA PG191TOP BRZ. CQFP CB196PLASTIC PQFP PQ208METAL MQFP MQ208HI-PERF QFP HQ208CERAMIC PGA PG223PLASTIC BGA BG225WINDOWED BGA WB225TOP BRZ. CQFP CB228PLASTIC PQFP PQ240METAL MQFP MQ240HI-PERF QFP HQ240CERAMIC PGA PG299HI-PERF. QFP HQ304PLASTIC BGA BG352CERAMIC PGA PG411PLASTIC BGA BG432CERAMIC PGA PG499PLASTIC BGA BG596

44

4864

68

84

100

120

132

144

156160

164

175

176184191196

208

223

225

228

240

299304352411432499596

◆ ◆ ◆ ◆ ◆ ◆◆ ◆ ◆

◆ ◆◆ ◆ ◆ ◆

◆ ◆ ◆

◆ ◆ ◆

◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆◆ ◆ ◆◆

◆ ◆ ◆ ◆ ◆ ◆◆

◆ ◆ ◆ ◆◆

◆ ◆◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆

◆ ◆ ◆

◆

◆ ◆ ◆ ◆ ◆

◆◆ ◆ ◆ ◆ ◆

◆◆

◆

◆ ◆

◆ ◆

◆

◆ ◆ ◆

QuarterlyRevenue

Tops$150M

Please note that the XC8100 familyhas been discontinued.

See page 13.

◆ = Product currently shipping or planned❖ = New since last issue of XCELL

(none appear in this issue)

FINANCIAL RESULTS

Sales revenues rose to $150.2 million inthe first fiscal quarter of 1977 (ending June30, 1996), a 19% increase over the samequarter one year ago and a 0.3% increasefrom the immediately preceding quarter.

“The June quarter was a difficult quarterfor the semiconductor industry,” notedXilinx Chief Executive Officer WillemRoelandts. “Although Xilinx was notimmune to this widespread slowdown, wedid experience minor sequential revenue

growth. The bright spot was the NorthAmerican distribution channel, whichgrew 10% over the prior quarter.”

The XC5000 FPGA family continuedits torrid growth rate, with sales up 30%over the previous quarter. Recently an-nounced price cuts (see page 11) shouldeven further expand the market for thiscost-optimized FPGA family.

Xilinx stock is traded on the NASDAQexchange under stock symbol XLNX.◆

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○

38

11

Xilinx recently announced significantprice reductions and performance improve-ments for the XC5200 FPGA family, further

R

PRODUCT INFORMATION-COMPONENTS

XC5200 Family:Lower Prices & Higher Performance

advancing its position as the industry’smost cost-effective FPGA family.

Performance Improved by 30%In addition to price reductions, a

patented charge-pump transistor design hasbeen added to the XC5200 family. Whencombined with a semiconductor processshrink from 0.6µm to 0.5µm triple-layermetal technology, the result is a new-3 speed-grade that offers up to a 30%performance improvement over the-5 speed grade (see table).

The XC5200 family delivers 2,000 to23,000 usable gates and robust features,such as the VersaRingTM I/O interface thatmaximizes overall utilization and pin as-signment flexibility, dedicated JTAG bound-ary scan logic for increased testability, and

fast carry logic for high speed arithmeticfunctions. The XC5200 FPGA family contin-ues to lead the industry as the lowest cost/gate programmable logic solution.◆

Prices Reduced by up to 50%XC5200 sales have risen at a record

pace. The rapid increase in shipments anda shift to a 0.5 µ process have resulted insignificant cost advantages; these savingsare being passed on directly to our users.With its segmented interconnect structureand an architecture optimized for its sub-micron, triple-layer metal (TLM) process,the XC5200 FPGA family has a significanttechnological advantage over other archi-tectures. The family’s small die sizes — insome cases even approaching today’s gatearray die sizes — lead to correspondinglylow component costs.

The chart below shows current high-volume pricing and projected pricing oneyear from now.

XC5200 Family Volume Pricing*MAXIMUM

DEVICE LOGIC GATES END OF 1996 2H97XC5202 3K $5.00 $4.50XC5204 6K $10.00 $8.00XC5206 10K $17.00 $12.00XC5210 16K $27.00 $18.00XC5215 23K $47.00 $33.00

* Plastic package, -6 speed grade, 25,000 unit quantity, U.S. direct pricing only

XC5200 Performance Benchmarks

XC5210-5 XC5210-3 % Improvement16-Bit Decoder 8 ns 6 ns 25%24-Bit Accumulator 39 MHz 50 MHz 28%16-to-1 Multiplexer 13 ns 9 ns 31%16-Bit Adder 20 ns 15 ns 25%16-Bit Up/Down Counter 50 MHz 65 MHz 30%

PIN

S

TYPE

CO

DE

XC

3020

AX

C30

30A

XC

3042

AX

C30

64A

XC

3090

AX

C30

20L

XC

3030

LX

C30

42L

XC

3064

LX

C30

90L

XC

3142

LX

C31

90L

XC

3120

AX

C31

30A

XC

3142

AX

C31

64A

XC

3190

AX

C31

95A

XC

4003

EX

C40

05E

XC

4006

EX

C40

08E

XC

4010

EX

C40

13E

XC

4020

EX

C40

25E

XC

4028

EX

XC

4036

EX

XC

4044

EX

XC

4052

XL

XC

4062

XL


COMPONENT AVAILABILITY CHART

44

4864

68

84

100

120

132

144

156160

164

175

176184191196

208

223

225

228

240

299304352411432499596

◆ ◆

◆

◆ ◆

◆ ◆ ◆ ◆ ◆

◆ ◆ ◆ ◆ ◆

◆

◆ ◆

◆ ◆

◆ ◆ ◆ ◆ ◆

◆ ◆ ◆◆ ◆

◆

◆ ◆◆ ◆ ◆

◆ ◆ ◆

◆ ◆ ◆ ◆

◆◆ ◆ ◆◆ ◆ ◆

◆◆ ◆

◆ ◆

◆ ◆ ◆◆ ◆ ◆ ◆

◆ ◆ ◆ ◆ ◆ ◆

◆ ◆ ◆ ◆ ◆ ◆◆ ◆

◆ ◆ ◆ ◆ ◆ ◆ ◆◆ ◆ ◆ ◆

◆ ◆ ◆ ◆◆ ◆ ◆ ◆

◆ ◆ ◆ ◆ ◆

◆ ◆ ◆◆ ◆ ◆◆ ◆ ◆◆ ◆ ◆ ◆

◆ ◆ ◆

◆

◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆

◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆

12

The combination of ultra-low-cost44-pin XC7300 CPLDs and easy-to-useXABEL-CPLD development software pro-vides users with the best value in program-mable logic. Three XC7300 family membersare now available in 44-pin PLCC, PQFP orVQFP packages — the XC7336, XC7336Qand XC7354 devices.

Xilinx 44-pin XC7300 CPLDs provide agreater range of performance and signifi-cantly lower costs than PALs and GALs. Infact, the logic from several PAL /GAL de-vices can be integrated into a singleXC7300 CPLD at a lower device cost thanthe replaced PALs/GALs (and sometimes ata component cost equivalent to a singlehigh-speed PAL). The XC7300 CPLDs alsocan replace TTL bus drivers, further reduc-ing component count and cost. Advancedsystem features such as 3.3V or 5V I/O

signaling lprovide suhigh-perfo

44-pin Ctremely adASIC userCPLD soluor repair Afixed-functi“unusable”cess variaor design ing board pin CPLD “system into implemesensitive tflexibility toin to the d

XC7300 CPLDs & XABEL-CPL

XC7336 XC7336Q XC7354 BENEFITS22V10 equiv. 3 3 5 lower inventory & pr16V8 equiv. 4 4 6macrocells 36 36 54usable gates 800 800 1500tPD 5.0 ns 10 ns 7.5 ns XC7336-world’s faste

ICC

(typ.) 126 mA 50 mA 140 mA Significant power sav3.3V/5V I/O Y Y Y Interface with high pe24 mA high drive I/O Y Y Y PCI Bus compliancepackages PC44, PC44, PC44 VQ44 53% smaller th

PQ44 PQ44, VQ44

Push-Button Software Gets the JoLow-cost XABEL-CPLD software obso-

letes all PAL/GAL and low-end CPLD toolsand provides push-button ease of use.Based on ABEL 6.0, XABEL-CPLD offersinstant productivity enhancement to allPAL/GAL users and makes the migration tohigher-density, cost-effective CPLD tech-nology quick and easy.

The colow-cost s44-pin CPLworld wheules and shrinking a

epr

es

o t

s

s

i

o

mi

s

37

vels and 100% PCI complianceport for the newest CPUs and

mance memories.PLDs also have proven ex-pt at fixing “ broken” ASICs. are discovering that 44-pintions can be used to safeguardSIC functionality. Sometimesn ASICs can be renderedby specification changes, pro-

ions that disrupt system timingerrors. Planning ahead by reserv-pace for a small form factor, 44-

can provide ASIC designers withurance.” The CPLD can be usednt control circuitry or correctming paths. In this way, the fix unwanted surprises is built-esign.

QAfter running Fncsim -o(use original schematic) on adesign that contains X-BLOX

components, I see no-connectsymbols on certain pins in thesimulation schematic. What’shappening?

These no-connects will appear in thesimulation schematic any place where twopin vertices are laying on top of eachother. In the original schematic, the pinswould be connected by a zero-length net.In the simulation schematic, however, thecoincident pins will not be connected(hence, the no-connect symbol).

The best fix for this problem is to goback to the original schematic and moveany coincident vertices apart, so that thenet between them may be seen.

D: The Industry’s

duction costs

st CPLDings over multiple PALs/GALsrformance memories and MPUs

an PC44

b Donebination of highly-capable,

licon and software makes XilinxD solutions the best choice in a

re product development sched-ystem component budgets aret an ever-accelerating pace.

continued

Synopsys

QHow can I prevent FPGACompiler from writing mytiming constraints into the

.sxnf file?

During its optimization process,Synopsys’ FPGA Compiler attempts tomeet the timing constraints issued by you;and subsequently writes out the timingconstraints into the netlist (.sxnf) file forthe Xilinx tools to use. You may want toissue these constraints to the Xilinx toolsin a separate constraints file, where youhave the ablility to be more specific aboutparticular paths that you want to constrain.

To do this, issue the followingcommand just prior to writing out the.sxnf file:

xnfout_constraints_per_endpoint = 0

This will result in a netlist (.sxnf) thatdoes not contain any timing constraints.You may then issue XACT Performanceconstraints in a .cst which will be used bythe Xilinx tools. For more information onXACT Performance, see the DevelopmentSystems Reference Guide.◆

13

36 XC8100 FPGA Product Family is Discontinued

Mentor Graphics

QWhile compiling my Autologicdesign through Timsim8,PLD_DVE_BA returns the

following warning, that may repeatseveral times:

# WARNING: Unknown designobject: /JE/I1101S$37$5

What does this mean and howcan I fix it?

Autologic may write out percent signs(%) in its instance names. Although this islegal in Mentor schematics, it is not legal inXilinx netlists. To remedy this, EDIF2XNFchanges each “%” in a netlist to “$37$” (soused because 37 is the ASCII code for thepercent sign). Unfortunately, the Mentorback-annotation file is written with thischange, so that I1101S$37$5 in the MBAfile does not match up with the trueI1101S%5 in the schematic.

The problem may be fixed by modify-ing the mbapp.nawk script, which pro-cesses the MBA file for use inPLD_DVE_BA, to change the $37$’s backto %’s. For more information, send E-mailto [email protected] with send 618 inthe subject line. Once this modification ismade, Timsim8 should run smoothly.

QI have an Autologic design that,during Men2XNF8, gives me thefollowing error in EDIF2XNF:

Error: 5 No direction/pintypefor port:PINBALL/WIZARD

What’s happening and howcan I fix this?

The pin in question does not have aPINTYPE property associated with it. ThePINTYPE property indicates a pin’s direction-ality, and is required in XACT 5.x byEDIF2XNF and XNFMerge. Autologic mayomit PINTYPE properties when synthesizinghierarchical symbols, following the rules ofpre-XACT 5.0 software.

If the offending symbol was created byAutologic II, a patch is available on MentorGraphics’ FTP site at supportnet.mentorg.com(137.202.128.4).

Autologic II version A.x requires Patch244, located in the directory:

/pub/patches/release_A/autologic2

with the filenames:README_P244

(patch information)INSTALL_P244

(installation instructions)sg_p244.sss.tar.Z

(SunOS 4. x)sg_p244.ss5.tar.Z

(Solaris 2. x)sg_p244.hpu.tar.Z

(HP-UX)

Autologic II version B.x requires Patch320, located in the directory:

/pub/patches/release_B/autologic2






(HP-UX)

Best 44-Pin PLD Value

Citing the strong market succcess ofSRAM and FLASH technologies, Xilinxannounced on Aug. 31, 1996, that it willdiscontinue the XC8100TM family of one-time programmable antifuse FPGA devices.The XC8100 family, first introduced lastautumn, was just entering production.

No layoffs or reductions in R&D spend-ing are associated with this decision. Xilinxemployees involved with antifuse develop-ment are taking on new duties in otherareas of the company. Resources andresearch and development spending arebeing redirected to focus more effectivelyon SRAM-based FPGAs, CPLDs and newopportunities more closely aligned withthose products, such as LogiCore modules.

“The XC8100 team successfully developeda number of patented, industry-first innova-tions in antifuse architecture, design, pro-gramming and processes — accomplishmentsno one else in the entire semiconductorindustry has been able to achieve so far with

this difficult technology,” stated Xilinx CEOWim Roelandts.

“But, compared to SRAM development,there are very few people working inantifuse. As a result, antifuse will lag be-hind SRAM, entail dispro-portionately large develop-ment costs, and berelegated to limited mar-kets. For these reasons webelieve further investmentin antifuse product devel-opment are too large to bejustified.”

A number of options areavailable to support currentXC8100 users, includingassistance in moving de-signs to other pin-compat-ible Xilinx devices, softwareupgrades to support otherprogrammable logic products and refundsfor XACTstepTM 8000 software.◆

❝compared to

SRAM development, there are

very few people working in

antifuse. As a result, antifuse

will lag behind SRAM, entail

disproportionately large

development costs, and be

relegated to

ANNOUNCEMENT

FEATURES BENEFITSFamiliar Data I/O ABEL, Windows-based environ- Push button design flow improves productivityment for design entry, simulation and fittingIndustry-standard-ABEL- HDL supports state ABEL-HDL familiar to PAL users, optimizedmachines, high level logic descriptions, truth for PAL and CPLD developmenttables and equation entryHierarchical design entry and JEDEC file Enables reuse of existing PAL codes,conversion for integration of existing PAL designs simplifying design effortinto Xilinx CPLDsFunctional simulation with graphical Waveform Facilitate rapid design verificationViewer and Static Timing ReportsAdvanced XACTstep v6 XC7K & XC9K fitter with auto- Fitter’s architecture-specific knowledge freesomatic device selection, multiple pass optimization, the user to focus on design functionalitypartitioning and mapping, and timing driven fittingAnimated tutorial and on-line help Reduces learning curve:

• tutorial leads users through entiredesign process in minutes

- extensive on-line help places alldocumentation a mouse-click away

◆

TECHNICAL QUESTIONS & ANSWERS

limited markets.❞

35

14

XC4000EX Family FPGAs Entering Production

Faster XC4000E FPGAs Now Available HOTLINE SUPPORT, U.S.

Customer Support Hotline:800-255-7778

Hrs: 8:00 a.m.-5:00 p.m. Pacific time

Customer Support Fax Number:408-879-4442

Avail: 24 hrs/day-7 days/week

E-mail Address:[email protected]

Customer Service*:408-559-7778, ask for customer service

* Call for software updates, authorizationcodes, documentation updates, etc.

HOTLINE SUPPORT, EUROPE

UK, London Officetelephone: (44) 1932 820821fax: (44) 1932 828522Bulletin Board Service: (44) 1932 333540e-mail: [email protected]

France, Paris Officetelephone: (33) 1 3463 0100fax: (33) 1 3463 0959e-mail: [email protected]

Germany, Munich Officetelephone: (49) 89 991 54930fax: (49) 89 904 4748e-mail: [email protected]

Japan, Tokyo Officetelephone: (81) 3 3297 9163fax: (81) 3 3297 0067e-mail: [email protected]

Xilinx has started sample shipments ofthe first two members of the high-densityXC4000EX family. The XC4036EX, with atypical gate range of 22,000 to 65,000gates, and the XC4028EX, with a typicalgate range of 18,000 to 50,000 gates, willenter volume production in the fourthquarter of this year.

The next member of the family to beintroduced is the XC4062XL, featuring atypical gate range of 40,000 to 130,000gates. The XC4062XL will begin samplingin December.◆

The XC4000EX family elevates theXC4000 series to new heights in densityand performance, with up to 125,000 logic

gates and 66 MHz system speeds.Designed “from the ground up”for speed and density using adeep-submicron, triple-layer-metal process, the XC4000EXfamily has abundant routingresources for high utilization andbuffered interconnect to providemaximum performance. (SeeXCell #20, page 21.)

mum chip-to-chip system speeds of theXC4000 and XC4000E devices for theiravailable speed grades.

The XC4000 series (i.e., the XC4000,XC4000E and XC4000EX families) incorpo-rates the world’s most widely used FPGAarchitecture with advanced features such asSelect-RAMTM memory, wide edge decod-ers, internal three-state buffers and multipleglobal clock distribution networks. Thehigh performance levels offered from the-2 speed grade, when combined with theseleading-edge architectural features, furtherextends the range of possible applicationsfor these popular devices.

For example, the capabilities of theXC4000E-2 device enable the delivery ofthe LogiCoreTM PCI Initiator module —an implementation that requires extremelyhigh performance levels, especially forFIFO buffer and registered I/O operations(see page 17).

For further technical information,please refer to the product specifica-tions and application notes onWebLINX, the Xilinx web site(www.xilinx.com). For pricing andavailability, contact your local Xilinxsales representative.◆

Continuing process improvements haveled to the release of a new, faster speedgrade for XC4000ETM FPGAs, available nowfor every member of the device family.

The new -2 speed grade achieves a15-20 percent performance improvementover the -3 speed grade as a result of alogic block propagation time (TILO) of 1.6ns, clock-to-output delays (TOKPOF) of under5 ns and global-clock-to-out, pin-to-pindelays (TICKOF) ranging from 8.7 ns for theXC4003E to 10.7 ns for the XC4025E . SeeFigure 1 for a comparison of the maxi-

Figure 1: Speed Grade Comparisons for XC4000 and XC4000E

70 MHz

60 MHz

50 MHz

40 MHz

30 MHz

20 MHz

10 MHz

0 MHz

Syst

em S

peed

*

XC4000 Family XC4000E Family(3,000-25,000 gates) 3,000-25,000 gates)

-6 -5 -4 -4 -3 -2

3832 MHz

27 MHzMHz

65MHz

56MHz

40MHz

*Maximum chip-to-chip system speed

TECHNICAL SUPPORT RESOURCES

Increased On-Line Technical InformationThe Xilinx BBS mirrored on the World Wide Web.

Xilinx Bulletin Board Service files and resources can now be accessed through theXilinx Internet FTP site.

Xilinx offers increased on-line support resources and choices.In the coming months, keep an eye on the Xilinx Technical Support resources on

WebLINX, the Xilinx web site (www.xilinx.com). In addition to the above mentioned BBSresources, you will see increased access to applications materials, product support materi-als, and commonly asked questions and solutions.

X-TALK: The Xilinx Network of Electronic Services• Xilinx home page on the World Wide Web.........................................www.xilinx.com.• Electronic Technical Bulletin Board (U.S.)................................................. 408-559-9327• XDOCS E-mail document server-

send an E-mail to [email protected] with ‘help’ as the only item in the subject header.You will automatically receive full instructions via E-mail.

• XFACTS fax document server..................................... available by calling 408-879-4400.

E-mail addresses for questions related to specific applications:Digital Signal Processing applications.................................................................dsp@xilinx.comPCI-bus applications............................................................................................. [email protected] and Play ISA applications ............................................................................ [email protected] card applications ............................................................................. [email protected] Transfer Mode applications........................................................ [email protected] Computing applications.................................................... [email protected]

FPGA Express

34

15

Xilinx Alliance member Synopsysunveiled its first entry into the Win95/Windows NT market at the Design Automa-tion Conference in Las Vegas on June 3.“FPGA Express” is a PC-based FPGA

synthesis tool for leading FPGA architec-tures. The first version has Xilinx XC3000family, XC4000 series and XC5200 familysupport. It is scheduled for productionshipment in September. Later versions willsupport the XC9500 CPLD family, as well asother programmable logic vendors.

FPGA Express is unique in its knowl-edge of Xilinx architectures and tools,allowing designers who are new to HDL toget high-quality results. The expert userwill find the sophisticated controls neededto work with very challenging designs.

Compiler). FPGA Express was designed“from the ground up” with PC usersspecifically in mind.

The Xilinx/Synopsys relationship waskey in the development of this product.“This is an excellent example of Xilinx andone of its Alliance partners working to-gether to meet user requirements with aquality product,” noted Wallace Westfeldt,manager of the Xilinx Alliance program.

Xilinx supplied architectural informationand assisted in the market research, defini-tion and development of FPGA Express.As a result, FPGA Express makes optimumuse of Xilinx device features to maximizedensity and performance. For example, itincludes an automatic module generatorthat can infer various operations within theHDL source, such as adders, comparatorsand multipliers, aswell as automati-cally build thecircuits using thededicated carrylogic in theXC4000 series andXC5200 familyarchitectures.

FPGA Expressalso makes fulluse of complexI/O structures present in the Xilinxdevices, including the clock enable feature

IOB registers. Global clockgned bahat allon clock

We are continuously investing in state-of-the-art customer support systems toprovide customers with choices, efficientaccess to support resources and reliableconnections.

When contacting the Technical andApplications Support Hotline in San Jose,you will be prompted to input the purposeof your inquiry to ensure that you reach themost appropriate person as soon as pos-sible. In addition, you will be asked toprovide your “personal ID number” or your“case ID number.”

Anytime during the process, you canbypass the automated inquiries to speakdirectly with a live support representativeor leave a voicemail message for a supportengineer.

What is mypersonal IDnumber?

The first timeyou contact theXilinx hotline,your personal IDnumber will beassigned by ourcustomer casemanagement sys-tem. On subse-quent calls, youmay use this num-ber to speed up

the support process. Once the telecommu-nications system receives your ID number,you will skip directly to a menu of topicsto choose from so that your call can berouted to the most helpful resource orqualified support engineer available.

Cases opened under your ID numberare tracked under your name. If your col-leagues wish to contact Xilinx, advise themthat they can receive their own personal IDnumbers by calling the hotline directly.

What is my case ID number?Each time you call with a new support

need, a case ID number will be assignedand communicated to you by a supportprofessional. If you have further need tocontact the hotline regarding an open case,you can speed your access to your caseworker by inputting the case number di-rectly into the telecommunications system.

What is the fastest way to reach anengineer with a new question?

On a typical day, the fastest path toreach a support engineer is through thetelecommunications system using yourpersonal ID number:

• Select your situation: New Case orExisting Open Case.

• Enter your Personal ID or the OpenCase ID

• For a new case, you will be promptedto select a product topic area.

• Your call is directed to the most appro-priate available resource.

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○

PRODUCT INFORMATION-DEVELOPMENT SYSTEMS

Synopsys Introduces

New Logic Synthesis Tool Targets Xilinx FPGA Families

❝FPGA Express isunique in its knowledge of Xilinx

architectures and tools, allowing

designers who are new to HDL to

get high-quality results.❞

Contin

New Technical Support ChoicesCallers to the Technical Support Hotline

at the Xilinx headquarters in San Jose nowencounter a friendly, ease-to-use telecom-

munications system that allows better accessto the resources and solutions needed toensure design progress and success.

Efficient and Speedy Access to Engineers on theHotline Thr ough Increased Choices

PHO

TO F

OR

ILLU

STR

ATIO

N P

UR

POSE

S O

NLY

sed on an intelli-cates the availablesignal fanout while

○○

○○

○○

○○

R

ued on the next page

FPGA Express is not a rewrite ofFPGA Compiler, although for compatibilityit uses the same VHDL and Verilog com-piler technology as Synopsys’ workstationtools (Design Compiler and FPGA

of the XC4000Ebuffers are assigent algorithm tbuffers based o

16

FPGAExpress

Continued from the previous page

filtering out gated clocks. If desired, userscan specify specific input pins that need tobe connected to a global buffer.

Synopsys revised the mapping andoptimization algorithms to provide all HDLusers with the best possible synthesisresults for area, performance and predict-ability. Testing has shown that FPGA Ex-press can improve area and performanceby up to 25% over existing PC-based syn-thesis tools. Run times are excellent — a3,000-gate design compiled in under aminute and a 20,000-gate design requiredapproximately 10 minutes using a Pentium-class computer.

Xilinx also collaborated with Synopsysto integrate FPGA Express into theXACTstepTM system. FPGA Express uses asophisticated constraint-entry GUI, with an“XACT step-like” from/to syntax for timing

FPGA Express providesa smooth interface to

other Xilinx FPGAdevelopment tools

constraints that directly translates to theXACTstep TIMESPEC format. All netlist andconstraint translation is done by FPGAExpress, eliminating the need for externaltranslators. The tool outputs Unified LibraryXNF with group TIMESPECS. The result isa “plug & play” interface between FPGAExpress and the XACTstep tools (v6.0.xand beyond).

Pricing and AvailabilitySold by Synopsys, FPGA Express starts

at $12,000 (one HDL language and supportfor one FPGA vendor). It will be availablein full production in September, runningon Windows 95 and Windows NT-basedpersonal computers.

For more information about FPGAExpress contact Bruce Jorgens, Prod-uct Line Manager for FPGA Productsat Synopsys 415-528-4955.◆

33

signing with a range of Xilinx parts and isup-to-date on Xilinx products.

XUMA is completely independent fromXilinx, Inc. Many engineers want an inde-pendent technical forum for openly dis-cuss key concerns and issues, both at thesystem- and device-level, and get objectiveanswers from others in their professionalcommunity.◆

Alain Arnaud of ECLA, Inc. (Newton,Massachusetts), a design consultant andexperienced FPGA and ASIC designer, waspondering how to best field his customers’questions — a mix that included bothsystem-level and FPGA-level issues. Toassist in this task, Alain started an e-mailaddress list of colleagues and industrycontacts. This effort has grown into XUMA— the Xilinx User MAiling List — a new,independent forum for the communicationof technical subjects across the Xilinx usercommunity. XUMA, initiated in May,1996,currently has over 250 subscribers and isgrowing rapidly.

XUMA mailings are e-mails of technicalquestions and answers sent to Alain byanybody and forwarded to everyone onthe XUMA mailing list.

Xilinx users can subscribe to the list,unsubscribe from the list or submit achange of address by sending mail to:

[email protected]

To send a technical question, answer orrelated information to the list, mail it to:

[email protected]

Mention in your mail if you would liketo remain anonymous. Alain sends outdigests of messages sent to him abouttwice each week.

XUMA is more focused than the“comp.arch.fpga” news group (see XCell#21, page 41). Comp.arch.fpga is a generalFPGA forum that typically deals withbroad-based questions and issues, whileXUMA is dedicated to trading technicalinformation regarding Xilinx devices andsoftware. As a result, it takes less time toreview XUMA digests for pertinent infor-mation. Furthermore, Alain is actively de-

New, Independent E-Mail User GroupDedicated to Xilinx Technology

XUMA: Xilinx User MA iling list

TO: [email protected]

CC:

TOPIC: Xilinx mailing list

MESSAGE: Alain -- please add my name to the XUMAlist for Xilinx technical issues.


CC:

TOPIC: XC4000 Series tip

MESSAGE: Alain -- I think I have discovered away to use an XC4025E as a barrier toprotect my desk from the harmfuleffects of excess moisture building upon the bottom of my coffee mug.

Remember, Xilinx userscan contact the Xilinx

Technical Support Hotline(see page 35) with

technical questions onXilinx products.

32

17

in XC4013-2 FPGAs. These devices operateat 33 MHz and include high-speed burstsynchronous FIFOs. The modules can becustomized to fit individual design require-ments, resulting in a cost-effective, single-chip solution.

The LogiCore PCI Master module (LC-DI-PCIM-C) for Xilinx FPGA and HardWiredevices, complete with a data sheet, com-prehensive user guide and PCI SystemsArchitecture textbook, is available fordesigning with Viewlogic schematics,VHDL and Verilog for $8,995. The PCISlave module (LC-DI-PCIS-C) is availablefor $4,995.

For further information about theLogiCore PCI Interface or other mod-ules in the program, please contactyour local Xilinx representative orvisit the LogiCore section of theWebLINX World Wide Web site.◆

LogiCoreTM PCI Intitiator DebutsXilinx recently announced the delivery

of its second, 100% compliant PCI core,the LogiCoreTM PCI “Master” (Initiator/Target) module. Previously, the LogiCorePCI “Slave” (Target only) module couldonly perform slave functions. With the newmodule, a user can now complete a masterinterface design in which the Master mod-ule acts as a controller for the PCI bus.The implementation of critical paths in thecore are pre-defined to ensure PCI compli-ance. As a result, designers can reducedesign risk and cut development time by atleast nine months.

The new -2 speed grade for theXC4013E FPGA enables the delivery of thePCI Master module, which requires a highlevel of design complexity and perfor-mance (see article about -2 speed grade onpage 14). The LogiCore PCI modules wereclosely developed with beta users whohave successfully implemented the design

Foundation Series Enjoys Successful IntroductionThe number of Foundation

SeriesTM users has been growing rapidlysince the inaugural release of this fullyintegrated PLD design software pack-age in 2Q96. User feedback has beenextremely positive, especially regardingthe ease-of-use resulting from the tightintegration of all the design tools.There also has been high praise for theHDL Wizard, including the HDL Editor,with color coding, and the LanguageAssistant, with templates for easy andquick coding of VHDL and ABEL-HDL.

The Foundation Series developmenttools for FPGA and CPLD design in-clude a highly integrated set of Win-dows-based design tools. Along with

the Xilinx XACTstepTM implementa-tion tools, it includes an HDL editor,synthesis compiler, schematic editorand simulator.

Xilinx has added more featuresto the Foundation packages in thev6.0.1 release, which is now ship-ping. Features in this release includesupport for the latest Xilinx devicefamilies: the XC9500 CPLDs andXC4000E FPGAs. Both device fami-lies are integrated into the easy-to-use, shrink-wrapped solution, mak-ing it simple to access and convert designsfor these new families. All users who pur-chased Foundation v6.0 will automaticallyreceive this new update.◆

❝Xilinx has

added more features

to the Foundation

packages in the

v6.0.1 release, which

is now shipping.❞

tion of RAINPORT.EXE , available in theSWHLP\XACTFPGA directory of the Bulle-tin Board Service (BBS). This program fixesparallel port access problems that occurwhen the security key is checked.

XACT step and AlternateOperating Systems

The Xilinx XACTstepTM developmentsystem software is available for both work-station and PC platforms. The PC-basedversion is designed for Windows 3.1, and

the Sun-based version for the Sun OS. How-ever, with some exceptions as detailedbelow, XACTstep software can run on somevariants of these popular operating systems.

Running XACT step v6.0.1 in Windows 95The majority of the XACTstep 6.0.1

software will run in Windows 95. However,there are some known compatibility issues:

• The Design Manager will cause aGeneral Protection fault when it isclosed. This causes no system problemsand can be ignored.

• The Hardware Debugger does not run.There is no known workaround.

• The ProSeries software does not rununder Windows 95. WorkView Office isavailable on an as-needed basis. Contactthe Xilinx Technical Hotline for moreinformation.

Running XACTstep v5.2.1 in Windows NTThe XACTstep v6.0.1 GUI tools (DM,

Floorplanner, Prom File Formatter, Hard-ware Debugger) will not run in WindowsNT, but the v5.2.1 executables can bemade to run in a DOS box with the addi-

Install problem, a script called cdi.csh hasbeen developed that will install the soft-ware in a non-graphical mode. This scriptcan be found on the Xilinx BBS (408-559-9327) and on the Xilinx FPT site(xilinx.com). Unfortunately, the Xilinx-Mentor Graphics interface (DS-344) doesnot work under Solaris, so Mentor Graph-ics’ users should stay with SunOS 4.1.X.◆

Solaris Support for XACTstep v5.2.1

Although not officially supported andtested by Xilinx, most of the XACTsteptools work with Solaris 2.5. The XCheckerprogram, which did not work with Solarisversion 2.4, will run under 2.5 when theSunOS 4.1.3 backwards-compatibility op-

tion is used. However, the Installprogram still does not work inSolaris. As a workaround to the

18

The Xilinx XC9500 CPLD family pro-vides the most-advanced, most-reliable pin-locking capability in the industry. Thisimportant feature allows designers to main-tain pinouts after making design changes,eliminating costly, time-consuming PCboard re-work. CPLDs that do not haveadequate pin-locking capability often re-quire pinout changes even after minordesign changes, leaving no room for errorand no possibility for field upgrades orfield customization.

Pin-Locking IssuesIn most CPLDs, each I/O pin is driven

directly by a macrocell through an I/Oblock, as shown in Figure 1. When the

design is pinlocked, the fitter is forced tomap logic into specific macrocells to main-tain the pinout. If the device architecture islimited, with inadequate routing in thecentral switch matrix, the fitter may not beable to place and route the design whenthe pins are locked.

Some CPLDs use an output routing poolto compensate for their primary routingdeficiencies. However, output routing poolsintroduce additional delays and do notprevent the fitter from having to consumelogic resources as routing feedthroughs,

impacting resource u

Logic reof the fittewhen the designs wirequiring fuct terms than high and produ

The KeysTo add

Xilinx XC95routing resin and flexXC9500 fitplacement locking ca

Pin-lockto place droutability of a CPLDlogic blockterms and modate delocked in aCPLD, burregards totion block by the logi

The XCrouting resfamily. All 100% routblock resowill route.

Wide fuimportant Since CPLspeed, sigwide functfor implem

DESIGN HINTS AND ISSUES

R

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

Benchmarks Confir

Figure 1: SimplifiedXC9500 I/O Architecture

both design performantilization.quirements also affect

r to place and route thpinout is locked. Slowth simple, narrow logiew inputs, feedbacks are inherently easier tspeed designs with wct term intensive logic

to Reliable Pin-Locress these pin-locking 00 CPLDs feature abuources, wide function ible product term allocter also optimizes the ito maximize the desig

pability.ing restricts the fitter’sesign resources; thereis crucial. The routing determine how much resources (inputs, prregisters) can be usesign changes after the design. In a fully rou

ied logic can be move routing restrictions, frresources that may bc that drives the I/O p9500 family provides tources of any availabldevices in the XC9500 able; if there are enouurces to implement th

nction block fan-in is requirement for pin-locDs typically are used fnal-intensive logic funion block fan-in is a renting functions in a s

m XC9

31

ce and

the abilitye design

speedc functionsand prod-o pinlockide fan-in functions.

kingissues,ndantblock fan-ation. Thenitialn’s pin-

capabilityfore, goodresourcesof theoductd to accom- pins are

tabled withouteeing func-e neededins.

he moste CPLDfamily aregh functione design, it

anotherking.

or high-ctions,equirementingle logic

XC4005E-3 and the XC3142A-09; and, forcomparison purposes, two older-technol-ogy devices, the XC4005-6 and the XC3042-70. In each device, two different implemen-tations test the IOB and CLB flip-flops. TheXC5200-5 CLB flip-flop was also tested.(There is no IOB flip-flop in XC5200 archi-tecture.)

The XC4000E amd XC4000 devicesshowed little difference between IOB andCLB behavior, but in the XC3000-seriesdevices, the IOB flip-flops showed dramati-cally better metastable performance thanthe CLB flip-flops. This difference can betraced to subtle differences in circuit designand layout and will guide us to furtherimprovements in metastable performanceof future designs.

Metastable measurement results arelisted in the table and plotted in the figure.The results for XC4000E-3 IOB and CLBflip-flops, XC5200-5 CLB flip-flops andXC3100A-09 IOB flip-flops are outstanding,far superior to most metastability datapublished anywhere else. When granted 2or 3 ns of extra settling delay, these devicescome close to eliminating the problemscaused by metastability, since their mean-time-between-failure exceeds millions ofyears. The older-technology devices areslightly less impressive, but still show veryacceptable performance, especially the IOBinput flip-flops that are normally used tosynchronize asynchronous input signals.

Metastability CalculationsThe Mean Time Between Failures

(MTBF) can only be defined statistically. Itis inversely proportional to the product ofthe two frequencies involved, the clockfrequency and the average frequency of theasynchronous data changes, provided thatthese two frequencies are independent andhave no correlation. The generally acceptedequation for MTBF is

MTBF = eK2 ××××× t

F1 ××××× F2 ××××× K1

500 CPLD

K2 is an exponent that describes the speedwith which the metastable condition isbeing resolved.

K1 represents the metastability-catchingsetup time window that describes thelikelihood of going metastable

F1 is the frequency of the asynchronous datainput

F2 is the flip-flop clock frequency

t is the settling time

K2 is an indication of the gain-bandwidthproduct in the feedback path of themaster latch in the flip-flop. A smalldecrease in the time constant 1/K2 resultsin an enormous improvement in MTBF.

With F1 = 1 MHz, F2 = 10 MHz andK1 = 0.1 ns,

MTBF (in seconds) = 10-3 ××××× eK2 ×××××t

The values of K2 under these condi-tions — expressed as 1/K2 in the table —were experimentally derived (as describedin the “1996 Programmable Logic DataBook,” page 14-41).

The MTBF under other operating condi-tions can be estimated using the data inthe diagram. Simply divide the appropriateMTBF from the diagram by the product ofthe two relative frequencies. For example,for a 10 MHz asynchronous input synchro-nized by a 40 MHz clock, the MTBF is 40times shorter than plotted, and for a 50KHz signal and a 1 MHz clock, the MTBFis 200 times longer than plotted here.◆

Metastability Measurement Results

TESTED FLIP-FLOP VALUE OF 1/K2 IN PICOSECONDS

XC4005E-3 CLB 52IOB 62

XC4005-6 CLB 127IOB 118

XC3142A-09 CLB 208IOB 79

XC3042-70 CLB 385IOB 238

XC5200-5 CLB 73

30 19

level. The number of available functionblock inputs affects the fitter’s ability to addmore signals to any logic that must remainin that function block (because it drivesI/O pins). Wide fan-in capability also helpsthe fitter implement that logic in a singlepass though the device.

Each XC9500 function block has 36inputs from the switch matrix. Competingin-system programmable CPLDs have asfew as 16 inputs.

Product term allocation is important topin-locking because it allows designchanges that increase the product termrequirement. All XC9500 devices allocateindividual product terms from anywhere inthe function block to the macrocell thatneeds them, accommodating logic changeswhen the design is pinlocked.

In the XC9500 family, up to 90 productterms can be allocated to any macrocell inthe function block. This is in contrast tocompeting CPLDs that restrict the productterm availability (from 5 to 32 pterms) onthe basis of macrocell location in thefunction block.

Fitter software is a key component ofany successful CPLD pin-locking solution.The fitter must work in conjunction withthe device architecture, spreading the out-puts to accommodate design changes whenthe design is pinlocked.

The XC9500 fitter is optimized to takefull advantage of the hardware resources ofthe XC9500 family. The Xilinx fitter is ca-pable of intelligently utilizing all availabledevice resources to retain pinouts and still

Whenever a clocked flip-flop syn-chronizes an asynchronous input, there isa small probability that the flip-flop outputwill exhibit an unpredictable delay. Thishappens when the input transition not onlyviolates the setup and hold-time specifica-tions, but actually occurs within the tinytiming window where the flip-flop acceptsthe new input. Under these circumstances,the flip-flop can enter a symmetrically-balanced transitory state, called a meta-stable state.

While the slightest deviation from per-fect balance will cause the output to revertto one of its two stable states, the delay indoing so depends not only on the gain-bandwidth product of the circuit, but also

on how perfect the balance was and on thenoise level within the circuit; the delay can,therefore, only be described in statisticalterms. The problem for the system designeris not the illegal logic level in the balancedstate (it’s easy enough to translate thatarbitrarily to either a 0 or a 1), but theunpredictable timing of the final change toa valid logic state. If the metastable flip-flopdrives two destinations with differing pathdelays, one destination might clock in thefinal data state while the other does not.

Metastability MeasurementsRecently, the metastable delays of four

different Xilinx FPGA devices were mea-sured: two cutting-edge devices using 0.5micron, 3-layer-metal technology, the

Pin-Locking Capabilitiesmance of the XC9500 CPLDs and twocompetitor’s ISP CPLD families. Thesebenchmarks are based on typical applica-tions such as address decoders, datapathdesigns and address counters. They illus-trate the CPLD device’s capability to ac-commodate design changes while main-taining an acceptable level of designperformance; not only must the iterateddesign reroute when the pinout is main-tained, it must do so with minimal impacton design performance. Therefore, all ofthe benchmark data is normalized to thedesign performance that is achieved whenthe fitters are free to choose the pinoutswithout restrictions.

Address DecoderBenchmark

This benchmarkdesign contains two16-, 32- or 36-bit bus-ses which are decodedto generate two chipselect outputs and isintended to measurethe effect of routingresources and function

Metastability Recovery in Xilinx FPGAs

Figure: Mean TimeBetween Failure forvarious IOB and CLBflip-flop outputs whensynchronizing a 1 MHzasynchronous input witha 10 MHz clock.

❝The benchmark results confirm

the superior pin-locking performance of the

Xilinx XC9500 family. This performance is

consistent across all devices and package types.❞

fan-in on thes pin-lockinglity. A typical design change in- the correction of an error in whichtputs are decoded incorrectly.

Continued onthe next page

maintain the required performance, evenafter significant design changes.

The Pin-locking BenchmarksThe following three sets of benchmark

data show the relative pin-locking perfor-

block CPLD’capabivolvesthe ou

The benchmark results demonstrate that both the family and the Vendor A dto accommodate the desigout any impact on design Vendor L devices maintainpinout, but with a significanperformance penalty. Sincedevices have 16 input logiperformance degradation oaddress decoder can be arouting resources while thethe 32 and 36-bit decodesboth poor routing and narrfan-in.

Datapath BenchmarkThis benchmark design

affect of routing resources pin-locking capability. This a single 16-, 32- or 36-bit A typical design change indering of data bits.

The benchmark results Figure 3 show that both thefamily and Vendor A devicaccommodate the design any impact on design perVendor L devices sacrifice(up to 80%) to reroute thepinlocked. Since only one input was required for eacperformance degradation cto poor routing resources, mance, or both, but cannoto logic block fan-in.

Address Counter BenchThis benchmark design

16-, 24- or 32-bit loadableloaded from separate busemon clock and hold signalsdesign change alters the ivalue. This benchmark meof routing resources and ffan-in on the CPLDs pin-lo

20Figure 2: Address Decoder-Normalized Benchmark Results

Figure 3: Data Path-Normalized Benchmark Results

XC9500 BenchmContinued from the previous pa

in Figure 2Xilinx XC9500evices were ablen changes with-performance.

ed the samet (up to 60%) the Vendor Lc blocks, thef the 16-bitttributed to poor performance of

is degraded byow logic block

measures theon the CPLD’sdesign contains

wide data bus.volves the reor-

shown in Xilinx XC9500

es were able tochanges withoutformance.d performance design whenlogic blockh output, thisan be attributedor fitter perfor-t be attributed

mark contains two address counterss but with com-. A typical

nitial count loadasures the effectunction blockcking capability

29

arksge Figure 1:

Maximum acceptable power consump-tion as a function of ambient tempera-ture and package thermal resistance,assuming full performance (i.e. 85° Cjunction temperature).

Figure 2:Maximum acceptable powerconsumption as a function of ambi-ent temperature and package thermalresistance, at reduced performance(14% longer delay, 12% lower speedat 125° C junction temperature).

28 21

There are well-defined relationshipsbetween chip power consumption, pack-age thermal characteristics, ambient andjunction temperature, and device perfor-mance.

In many cases, the user has no controlover the maximum ambient temperature,but can choose the device and package,and then strive for an acceptable powerconsumption.In other cases,chip, package,power con-sumption andambient tem-perature aregiven, and theresultingachievableperformancelevel must becalculated. If performance cannot be sacri-ficed, thermal management techniques (e.g,airflow and heat sinks) can be used tolower the thermal resistance.

ΘJ-A is expressed in degrees C of junc-tion temperature rise over the ambienttemperature for every Watt dissipated in thedevice. ΘJ-A is primarily a function of thepackage and the airflow, with die size asecondary factor. (Larger die have a lowerΘJ-A value). See Table 1.

When the junction is hotter than 85°C,where Xilinx tests and guarantees perfor-

mance param-eters, delaysincrease 0.35%for every addi-tional degree C.At 125°C, themaximum al-lowed junctiontemperature in aplastic package,delays are 14%longer, and

speed is thus 12% lower than the guaran-teed values in the data book and the soft-ware. In ceramic packages, the maximumallowed junction temperature is 150°C.◆

Figure 4: Address Counter-Normalized Benchmark Results

stressed, performance didn’t just degrade,the devices completely failed to route.Vendor L devices used several layers oflogic in the initial design, with corre-spondingly low fMAX. This enabled thefitter to reroute the design using alternaterouting paths, with less performancedegradation (20%) than designs initiallyrequiring only one logic level.

when macrocell feedbacks and otherhigh fan-out signals are involved.

The benchmark results shown inFigure 4 demonstrate the superiority ofthe XC9500 CPLD architecture. AllXC9500 devices were able to accommo-date the design changes without anyimpact on design performance. WhenVendor A’s routing resources were

ConclusionsThe benchmark results confirm the superior pin-locking performance of the

Xilinx XC9500 family. This performance is consistent across all devices and pack-age types. The wide function block fan-in enables pin-locking of wide, high-speedlogic functions. Furthermore, because feedthroughs are not needed for routing,there is no performance degradation due to routing congestion. This timing consis-tency is as important as routing ability for maintaining pin-locked designs.

ho e not

e use

Power, Package & PerformanceTrading OffAmong the

Three Ps

The governing equation is

TJ = TA + P ××××× ΘΘΘΘΘJ-A

where TJ = junction temperature

TA = ambient temperature

ΘJ-A (Theta J-A) = Thermal resistanceof the package-die combination

P = power dissipation

Typical thermal resistance for various packageswith and without airflow

250 FT/MIN 500 FT/MIN 750 FT/MINPACKAGE STILL AIR (1.3 M/S) (2.5 M/S) (3.8 M/S)

HQ304 11 7 6 5 °C/WHQ240 12 9 7 6 °C/WHQ208 14 10 8 7 °C/WMQ240 17 12 11 10 °C/WMQ208 18 14 13 12 °C/WPQ240 23 17 15 14 °C/WPQ208 32 23 21 19 °C/WPQ160 32 24 21 20 °C/WPQ100 33 29 28 27 °C/WPC84 33 25 21 17 °C/WTQ100 31 26 24 23 °C/WVQ100 38 32 30 29 °C/W

e industry’s best pin-locking capability,ns due to design changes. This featurses design costs but also facilitates th or modify systems in the field.◆

The XC9500 CPLD devices feature teliminating the need for PCB modificationly shortens design cycles and decreaof in-system programmability to upgrade

Designers need options for managingthe many signal switching conditions thatoccur in their systems. One simple buteffective option is the output slew ratecontrol provided in the XC9500 familyCPLDs. This feature permits the simpleselection between a slew-rate-limited outputdrive and a high-speed output drive. Theresult is easy, convenient control of switch-ing characteristics on a pin-by-pin basis.

Currently, the default condition of thedesign software provides a slew-rate-limitedconfiguration on all output pins. This isconsistent with the default condition pro-

vided by the Xilinx FPGA developmenttools. To obtain faster switching speeds,the designer must configure the appropri-ate output buffers for the fast slew rate.

Since the slower slew rate is the default,reported timing for an implemented designmay be slower than expected for a givenspeed grade. This is simply due to the factthat a slower slew rate output crosses theswitching threshold at a later time than afaster slewing signal (see Figure 1). TheXilinx timing report simply adds a smalltime delay to the output signal, accountingfor the added delay.

22 27

Shorter Design CyclesThe ease-of-use associated with edge-

triggered memory design results in shorterdesign cycles as compared to using level-sensitive RAM. The design, simulation andtesting steps are all simplified.

PerformanceAs mentioned above, level-sensitive RAM

designs may require both a 2X clock andsignificant signal manipulation to meet thestringent timing requirements on the WriteEnable signal. The Address and Data inputsmust be set-up at the RAM input pins bythe time the Write Enable signal arrives,typically halfway through the write cycle.

When the same design is implementedusing edge-triggered RAM, Address andData may change in response to (for ex-ample) the rising edge of the input clock.The Write can occur on the next risingedge of the same clock. Therefore, theAddress and Data have the full write cycleto set-up at the RAM input pins. The resultis a memory block that operates at approxi-mately twice the speed of the level-sensi-tive version of the design. When the simul-taneous read/write capability of thedual-port Select-RAM option is taken intoaccount, data throughput can be doubledagain, resulting in a total four-fold increase

in effective data rates. These results aredemonstrated in a simple FIFO design inthe Xilinx application note “ImplementingFIFOs in XC4000 Series RAM.”

Distributed RAM provides an additionalspeed advantage: locating RAM blockscloser to related logic minimizes routingdelays on critical paths.

Uses of Select-RAM MemoryThe edge-triggered RAM capability can

and should be used in all new designsrequiring RAM. These applications includeregister files, FIFO buffers, multipliers, shiftregisters and pseudo-random sequencegenerators.

The dual-port option adds the ability toread and write simultaneously from twodifferent addresses. This ability consider-ably simplifies FIFO designs and is usefulfor constructing dual-port register files.◆

The Application Notesreferenced in this article are

available on the XilinxWebLINX web site at

www.xilinx.com, or bycontacting the Xilinx

Technical Hotline.

Using XC9500 Slew Rate Controls

Figure 1: Effectof slew rate

control on outputswitching times

A number of methods are available for specifying the fast slew rate,dependent on the design style chosen.

• For XABEL-CPLD, include one or more of the following directives:XEPLD Property ‘FAST ON’;

Sets all pins to fast slew rateXEPLD Property ‘FAST ON A B C’;

Pins A,B and C will be fast & all others remain slew rate limited

• For schematic entry, attach a FAST attribute to the appropriate output pad symbol.

• For Synopsys VHDL, use the following DC Shell commands to set all outputsfor the fast slew rate:set_port_is_pad “*”set_pad_type -slewrate NONE all_outputs()insert_pads

Alternatively, the fast slew rate can be specified for individual outputs by replacing thesecond line above with commands of the form:set_pad_type -slewrate NONE port_name

• For Metamor VHDL, add the Metamor library to your VHDL file with the commands:library metamor;use metamor.attributes.all

Then, after your signal declarations, assign the fast attribute to a signal with the command:attribute property of port_name : signal is “Fast”

Figure 1: XC4000 SeriesConceptual Model for Edge-Triggered Memory

26 23

The XC5200 FPGA’s carry logic isdeceptively simple. While this architectureonly provides a series of multiplexers inter-connected by dedicated carry nets, the useof function generators to control thesemultiplexers makes the XC5200 FPGA’scarry logic extremely flexible — moreflexible, in fact, than the XC4000 carrylogic with its multiplicity of modes.

In the XC5200 architecture, one bit of asimple adder uses two function generatorsand a carry chain multiplexer, as shown inFigure 1. However, not all of the functiongenerator’s capability is utilized in the basicadder. In the input function generator, theadder input, bi, can be any function of thethree inputs that are available. For example,one of these inputs could be used as anadd/subtract control, inverting bi in an XORgate when necessary.

Similarly, the adder output can be com-bined in any way with the two remainingfunction generator inputs. In a typicalcounter application, these might be usedfor a multiplexer to load the counter or,alternatively, for an AND gate to provide asynchronous clear.

A more complex example uses thisadditional capability in a carry-select adderthat trades additional logic for higher per-formance (Figure 2). The adder is dividedinto two sections. The lower half operatesnormally, but in the upper half two carrychains are used in parallel, one initializedwith a ‘0’ and the other with a ‘1.’ The carryoutput of the lower half is used to selectwhich carry chain is used to complete thesum. The carry propagates simultaneouslyin the upper and lower halves of the adder;thus, the settling time is reduced.

Since a single function generator canboth select the carry and complete thesum, the incremental cost over the basicadder is only 25%. The direct access to thecarry chain minimizes the timing overheadassociated with this technique, which iseffective even for relatively short adders.

The XC4000 Series of FPGA devices(i.e., the XC4000E and XC4000EX families,and their low-voltage counterparts, theXC4000L and XC4000XL families) includesseveral architectural improvements over thehighly-successful XC4000 FPGA family. Oneof the most important new features is Se-lect-RAMTM memory. Select-RAM memorycan be defined as the capability of pro-gramming the look-up tables inConfigurable Logic Blocks (CLBs) as ROMor as single- or dual-port RAM, with edge-triggered (synchronous) or level-sensitive(asynchronous) timing. Select-RAM memoryalso can be initialized to a known value inall RAM and ROM modes.

Select-RAM memory is unique in itsrange of options and ability to deliver high-speed dual-port memory. The advantagesof the Select-RAM capability include flex-ibility, increased ease-of-use, shorter designcycles and increased performance.

FlexibilityClearly, the options of edge-triggered or

level-sensitive and single-port or dual-portRAM provide a wide selection of choicesfor the designer. The distributed nature ofthe RAM, which is implemented in indi-vidual CLBs, also contributes to the flexibil-ity of Select-RAM memory. Only sufficientCLBs to implement a given memory blockneed be allocated as RAM: the memoryblock size can be scaled to exactly matchthe requirements of the application. EachRAM block can be placed close to relatedlogic. There is no need to consume a largeblock of dedicated memory to implement asmall RAM function, nor to route controland data lines across the device to reachsuch dedicated blocks. Each CLB can beindividually configured, so the designer can

“mix and match” RAM modes. Select-RAMis the most flexible memory implementa-tion available in an FPGA today.

Ease of UseTraditional RAM capability, now referred

to as the level-sensitive or asynchronousoption to Select-RAM memory, has neverbeen simple to use. Meeting the requiredtiming relationships often involved carefullayout and detailed timing analysis. Toguarantee correct behavior, a 2X clock istypically required, in order to generate theWrite Enable during the third quadrant ofthe write clock cycle. This type of RAM isthe only available option in the originalXC4000 family devices.

None of these delicate timing relation-ships need be maintained when using oneof the edge-triggered Select-RAM modesavailable in XC4000-Series devices. Instead,writing to a memory block is just like writ-ing to a data register: set up the addressand data, enable the RAM and apply theeffective clock edge. A conceptual modelfor a Select-RAM block in edge-triggeredmode is shown in the Figure 1.

The ability to initialize RAM, as well asROM, as part of device configuration elimi-nates the need for logic to perform thatinitialization. Reduced logic results insmaller, simpler and more reliable designs.

All of the Select-RAM options are di-rectly and easily implemented using any ofthe schematic entry, MemGen memoryblock generator tool, X-BLOXTM schematic-based synthesis, or HDL synthesis designenvironments. Detailed information on howto use these tools to implement Select-RAMis available in the new Xilinx applicationnote “Using Select-RAM Memory in XC4000Series FPGAs.”

Designing With XC5200 Carry LogicSimple design makes XC5200carry logic even more flexiblethan that of XC4000 Series

Figure 1:XC5200 Carry Structure

The corresponding acceleration tech-nique for long adders in the XC4000 archi-tecture is the conditional-sum technique.In the upper half of a conditional-sumadder, two complete adders are imple-mented with ‘0’ and ‘1’ carry inputs, and


XC4000 Series Select-RAM Memory:

Advantages and Uses

Figure 2:XC5200 Carry-Select Adders

24 25

additional CLBs are required to selectbetween the outputs of these adders ac-cording to the carry output from the lowerhalf. The technique is only effective forrelatively long adders; the incremental costis 100%.

It is interesting to note that, in theXC5200 architecture, the carry-select andconditional-sum techniques cannot always

Figure 3:4-Bit Cascade Multiplier

XC5200Carry Logic


be distinguished. Both sums of the condi-tional-sum adder can be completed in thesame function generator. This functiongenerator can be further used to selectbetween them. If this is done, all the func-tion-generator truth tables and all the inter-connections become identical to the carry-select adder. This should not be surprising,however, since both techniques implementthe same uniquely defined adder function.

Figure 4:Bit-Slice of FirstTwo Adders

In a simple multiplier, the product iscomputed using a cascade of gated adderstogether with appropriate shifts (Figure 3).A more detailed view of a single bit slicethrough the first two adders of this multi-plier is shown in Figure 4. One of the twoAND gates that precedes the first adder iscombined into the function generator thatcontrols the carry multiplexer. The other

AND gate, however, must use a separatefunction generator because there is a fan-out point at the second input to the adder.

In the second and subsequent adders,the AND gates again use separate functiongenerators. This permits the XOR gates thatcomplete the previous sums to be mergedadder inputs, thus saving both logic re-sources and critical-path delay. If, instead,the AND gates had been merged into the

inputs, the XOR gates would have requiredfunction generators. In this case, the re-source utilization would have been thesame, but the delay longer. Only in thefinal adder is a separate function generatorneeded for the XOR gate.

The speed of the multiplier can beincreased by rearranging the cascade ofadders into a tree, as in Figure 5. After thefirst set of adders, the input of each addercan absorb the output XOR gate of one ofthe two preceding adders, as described inthe cascade multiplier. The other precedingadder, however, must use a separate func-tion generator for its XOR gate.

In the first set of adders, the objective isto multiply the X input by bit pairs of Y,creating products that are 0X, 1X, 2X or 3X.This is usually achieved by gating X and 2Xinto an adder, as is shown in Figure 5.

However, a different, more directapproach may be used in XC5200 FPGA.

Figure 5:Adder-Tree Multiplier

Figure 6:First Stage of a Tree-AdderMultiplier

A bit slice of this more efficient approach isshown in Figure 6. The carry chain is onlyused to add X and 2X when the 3X outputis required. Otherwise, 0, X or 2X is se-lected in the first function generator androuted to the second function generatorwhere it passes through unaltered. Whilethe carry chain continues to operate in ameaningless way, it cannot damage itself,and its outputs are not required. When 3Xis required, the first function generatorXORs X and 2X to control the carry chainin a normal addition. The sum is completedin the XOR gate that precedes the multi-plexer in the second function generator.◆

24 25

additional CLBs are required to selectbetween the outputs of these adders ac-cording to the carry output from the lowerhalf. The technique is only effective forrelatively long adders; the incremental costis 100%.

It is interesting to note that, in theXC5200 architecture, the carry-select andconditional-sum techniques cannot always

Figure 3:4-Bit Cascade Multiplier

XC5200Carry Logic


be distinguished. Both sums of the condi-tional-sum adder can be completed in thesame function generator. This functiongenerator can be further used to selectbetween them. If this is done, all the func-tion-generator truth tables and all the inter-connections become identical to the carry-select adder. This should not be surprising,however, since both techniques implementthe same uniquely defined adder function.

Figure 4:Bit-Slice of FirstTwo Adders

In a simple multiplier, the product iscomputed using a cascade of gated adderstogether with appropriate shifts (Figure 3).A more detailed view of a single bit slicethrough the first two adders of this multi-plier is shown in Figure 4. One of the twoAND gates that precedes the first adder iscombined into the function generator thatcontrols the carry multiplexer. The other

AND gate, however, must use a separatefunction generator because there is a fan-out point at the second input to the adder.

In the second and subsequent adders,the AND gates again use separate functiongenerators. This permits the XOR gates thatcomplete the previous sums to be mergedadder inputs, thus saving both logic re-sources and critical-path delay. If, instead,the AND gates had been merged into the

inputs, the XOR gates would have requiredfunction generators. In this case, the re-source utilization would have been thesame, but the delay longer. Only in thefinal adder is a separate function generatorneeded for the XOR gate.

The speed of the multiplier can beincreased by rearranging the cascade ofadders into a tree, as in Figure 5. After thefirst set of adders, the input of each addercan absorb the output XOR gate of one ofthe two preceding adders, as described inthe cascade multiplier. The other precedingadder, however, must use a separate func-tion generator for its XOR gate.

In the first set of adders, the objective isto multiply the X input by bit pairs of Y,creating products that are 0X, 1X, 2X or 3X.This is usually achieved by gating X and 2Xinto an adder, as is shown in Figure 5.

However, a different, more directapproach may be used in XC5200 FPGA.

Figure 5:Adder-Tree Multiplier

Figure 6:First Stage of a Tree-AdderMultiplier

A bit slice of this more efficient approach isshown in Figure 6. The carry chain is onlyused to add X and 2X when the 3X outputis required. Otherwise, 0, X or 2X is se-lected in the first function generator androuted to the second function generatorwhere it passes through unaltered. Whilethe carry chain continues to operate in ameaningless way, it cannot damage itself,and its outputs are not required. When 3Xis required, the first function generatorXORs X and 2X to control the carry chainin a normal addition. The sum is completedin the XOR gate that precedes the multi-plexer in the second function generator.◆

26 23

The XC5200 FPGA’s carry logic isdeceptively simple. While this architectureonly provides a series of multiplexers inter-connected by dedicated carry nets, the useof function generators to control thesemultiplexers makes the XC5200 FPGA’scarry logic extremely flexible — moreflexible, in fact, than the XC4000 carrylogic with its multiplicity of modes.

In the XC5200 architecture, one bit of asimple adder uses two function generatorsand a carry chain multiplexer, as shown inFigure 1. However, not all of the functiongenerator’s capability is utilized in the basicadder. In the input function generator, theadder input, bi, can be any function of thethree inputs that are available. For example,one of these inputs could be used as anadd/subtract control, inverting bi in an XORgate when necessary.

Similarly, the adder output can be com-bined in any way with the two remainingfunction generator inputs. In a typicalcounter application, these might be usedfor a multiplexer to load the counter or,alternatively, for an AND gate to provide asynchronous clear.

A more complex example uses thisadditional capability in a carry-select adderthat trades additional logic for higher per-formance (Figure 2). The adder is dividedinto two sections. The lower half operatesnormally, but in the upper half two carrychains are used in parallel, one initializedwith a ‘0’ and the other with a ‘1.’ The carryoutput of the lower half is used to selectwhich carry chain is used to complete thesum. The carry propagates simultaneouslyin the upper and lower halves of the adder;thus, the settling time is reduced.

Since a single function generator canboth select the carry and complete thesum, the incremental cost over the basicadder is only 25%. The direct access to thecarry chain minimizes the timing overheadassociated with this technique, which iseffective even for relatively short adders.

The XC4000 Series of FPGA devices(i.e., the XC4000E and XC4000EX families,and their low-voltage counterparts, theXC4000L and XC4000XL families) includesseveral architectural improvements over thehighly-successful XC4000 FPGA family. Oneof the most important new features is Se-lect-RAMTM memory. Select-RAM memorycan be defined as the capability of pro-gramming the look-up tables inConfigurable Logic Blocks (CLBs) as ROMor as single- or dual-port RAM, with edge-triggered (synchronous) or level-sensitive(asynchronous) timing. Select-RAM memoryalso can be initialized to a known value inall RAM and ROM modes.

Select-RAM memory is unique in itsrange of options and ability to deliver high-speed dual-port memory. The advantagesof the Select-RAM capability include flex-ibility, increased ease-of-use, shorter designcycles and increased performance.

FlexibilityClearly, the options of edge-triggered or

level-sensitive and single-port or dual-portRAM provide a wide selection of choicesfor the designer. The distributed nature ofthe RAM, which is implemented in indi-vidual CLBs, also contributes to the flexibil-ity of Select-RAM memory. Only sufficientCLBs to implement a given memory blockneed be allocated as RAM: the memoryblock size can be scaled to exactly matchthe requirements of the application. EachRAM block can be placed close to relatedlogic. There is no need to consume a largeblock of dedicated memory to implement asmall RAM function, nor to route controland data lines across the device to reachsuch dedicated blocks. Each CLB can beindividually configured, so the designer can

“mix and match” RAM modes. Select-RAMis the most flexible memory implementa-tion available in an FPGA today.

Ease of UseTraditional RAM capability, now referred

to as the level-sensitive or asynchronousoption to Select-RAM memory, has neverbeen simple to use. Meeting the requiredtiming relationships often involved carefullayout and detailed timing analysis. Toguarantee correct behavior, a 2X clock istypically required, in order to generate theWrite Enable during the third quadrant ofthe write clock cycle. This type of RAM isthe only available option in the originalXC4000 family devices.

None of these delicate timing relation-ships need be maintained when using oneof the edge-triggered Select-RAM modesavailable in XC4000-Series devices. Instead,writing to a memory block is just like writ-ing to a data register: set up the addressand data, enable the RAM and apply theeffective clock edge. A conceptual modelfor a Select-RAM block in edge-triggeredmode is shown in the Figure 1.

The ability to initialize RAM, as well asROM, as part of device configuration elimi-nates the need for logic to perform thatinitialization. Reduced logic results insmaller, simpler and more reliable designs.

All of the Select-RAM options are di-rectly and easily implemented using any ofthe schematic entry, MemGen memoryblock generator tool, X-BLOXTM schematic-based synthesis, or HDL synthesis designenvironments. Detailed information on howto use these tools to implement Select-RAMis available in the new Xilinx applicationnote “Using Select-RAM Memory in XC4000Series FPGAs.”

Designing With XC5200 Carry LogicSimple design makes XC5200carry logic even more flexiblethan that of XC4000 Series

Figure 1:XC5200 Carry Structure

The corresponding acceleration tech-nique for long adders in the XC4000 archi-tecture is the conditional-sum technique.In the upper half of a conditional-sumadder, two complete adders are imple-mented with ‘0’ and ‘1’ carry inputs, and


XC4000 Series Select-RAM Memory:

Advantages and Uses

Figure 2:XC5200 Carry-Select Adders

Designers need options for managingthe many signal switching conditions thatoccur in their systems. One simple buteffective option is the output slew ratecontrol provided in the XC9500 familyCPLDs. This feature permits the simpleselection between a slew-rate-limited outputdrive and a high-speed output drive. Theresult is easy, convenient control of switch-ing characteristics on a pin-by-pin basis.

Currently, the default condition of thedesign software provides a slew-rate-limitedconfiguration on all output pins. This isconsistent with the default condition pro-

vided by the Xilinx FPGA developmenttools. To obtain faster switching speeds,the designer must configure the appropri-ate output buffers for the fast slew rate.

Since the slower slew rate is the default,reported timing for an implemented designmay be slower than expected for a givenspeed grade. This is simply due to the factthat a slower slew rate output crosses theswitching threshold at a later time than afaster slewing signal (see Figure 1). TheXilinx timing report simply adds a smalltime delay to the output signal, accountingfor the added delay.

22 27

Shorter Design CyclesThe ease-of-use associated with edge-

triggered memory design results in shorterdesign cycles as compared to using level-sensitive RAM. The design, simulation andtesting steps are all simplified.

PerformanceAs mentioned above, level-sensitive RAM

designs may require both a 2X clock andsignificant signal manipulation to meet thestringent timing requirements on the WriteEnable signal. The Address and Data inputsmust be set-up at the RAM input pins bythe time the Write Enable signal arrives,typically halfway through the write cycle.

When the same design is implementedusing edge-triggered RAM, Address andData may change in response to (for ex-ample) the rising edge of the input clock.The Write can occur on the next risingedge of the same clock. Therefore, theAddress and Data have the full write cycleto set-up at the RAM input pins. The resultis a memory block that operates at approxi-mately twice the speed of the level-sensi-tive version of the design. When the simul-taneous read/write capability of thedual-port Select-RAM option is taken intoaccount, data throughput can be doubledagain, resulting in a total four-fold increase

in effective data rates. These results aredemonstrated in a simple FIFO design inthe Xilinx application note “ImplementingFIFOs in XC4000 Series RAM.”

Distributed RAM provides an additionalspeed advantage: locating RAM blockscloser to related logic minimizes routingdelays on critical paths.

Uses of Select-RAM MemoryThe edge-triggered RAM capability can

and should be used in all new designsrequiring RAM. These applications includeregister files, FIFO buffers, multipliers, shiftregisters and pseudo-random sequencegenerators.

The dual-port option adds the ability toread and write simultaneously from twodifferent addresses. This ability consider-ably simplifies FIFO designs and is usefulfor constructing dual-port register files.◆

The Application Notesreferenced in this article are

available on the XilinxWebLINX web site at

www.xilinx.com, or bycontacting the Xilinx

Technical Hotline.

Using XC9500 Slew Rate Controls

Figure 1: Effectof slew rate

control on outputswitching times

A number of methods are available for specifying the fast slew rate,dependent on the design style chosen.

• For XABEL-CPLD, include one or more of the following directives:XEPLD Property ‘FAST ON’;

Sets all pins to fast slew rateXEPLD Property ‘FAST ON A B C’;

Pins A,B and C will be fast & all others remain slew rate limited

• For schematic entry, attach a FAST attribute to the appropriate output pad symbol.

• For Synopsys VHDL, use the following DC Shell commands to set all outputsfor the fast slew rate:set_port_is_pad “*”set_pad_type -slewrate NONE all_outputs()insert_pads

Alternatively, the fast slew rate can be specified for individual outputs by replacing thesecond line above with commands of the form:set_pad_type -slewrate NONE port_name

• For Metamor VHDL, add the Metamor library to your VHDL file with the commands:library metamor;use metamor.attributes.all

Then, after your signal declarations, assign the fast attribute to a signal with the command:attribute property of port_name : signal is “Fast”

Figure 1: XC4000 SeriesConceptual Model for Edge-Triggered Memory

28 21

There are well-defined relationshipsbetween chip power consumption, pack-age thermal characteristics, ambient andjunction temperature, and device perfor-mance.

In many cases, the user has no controlover the maximum ambient temperature,but can choose the device and package,and then strive for an acceptable powerconsumption.In other cases,chip, package,power con-sumption andambient tem-perature aregiven, and theresultingachievableperformancelevel must becalculated. If performance cannot be sacri-ficed, thermal management techniques (e.g,airflow and heat sinks) can be used tolower the thermal resistance.

ΘJ-A is expressed in degrees C of junc-tion temperature rise over the ambienttemperature for every Watt dissipated in thedevice. ΘJ-A is primarily a function of thepackage and the airflow, with die size asecondary factor. (Larger die have a lowerΘJ-A value). See Table 1.

When the junction is hotter than 85°C,where Xilinx tests and guarantees perfor-

mance param-eters, delaysincrease 0.35%for every addi-tional degree C.At 125°C, themaximum al-lowed junctiontemperature in aplastic package,delays are 14%longer, and

speed is thus 12% lower than the guaran-teed values in the data book and the soft-ware. In ceramic packages, the maximumallowed junction temperature is 150°C.◆

Figure 4: Address Counter-Normalized Benchmark Results

stressed, performance didn’t just degrade,the devices completely failed to route.Vendor L devices used several layers oflogic in the initial design, with corre-spondingly low fMAX. This enabled thefitter to reroute the design using alternaterouting paths, with less performancedegradation (20%) than designs initiallyrequiring only one logic level.

when macrocell feedbacks and otherhigh fan-out signals are involved.

The benchmark results shown inFigure 4 demonstrate the superiority ofthe XC9500 CPLD architecture. AllXC9500 devices were able to accommo-date the design changes without anyimpact on design performance. WhenVendor A’s routing resources were

ConclusionsThe benchmark results confirm the superior pin-locking performance of the

Xilinx XC9500 family. This performance is consistent across all devices and pack-age types. The wide function block fan-in enables pin-locking of wide, high-speedlogic functions. Furthermore, because feedthroughs are not needed for routing,there is no performance degradation due to routing congestion. This timing consis-tency is as important as routing ability for maintaining pin-locked designs.

The XC9500 CPLD devices feature the industry’s best pin-locking capability,eliminating the need for PCB modifications due to design changes. This feature notonly shortens design cycles and decreases design costs but also facilitates the useof in-system programmability to upgrade or modify systems in the field.◆

Power, Package & PerformanceTrading OffAmong the

Three Ps

The governing equation is

TJ = TA + P ××××× ΘΘΘΘΘJ-A

where TJ = junction temperature

TA = ambient temperature

ΘJ-A (Theta J-A) = Thermal resistanceof the package-die combination

P = power dissipation

Typical thermal resistance for various packageswith and without airflow

250 FT/MIN 500 FT/MIN 750 FT/MINPACKAGE STILL AIR (1.3 M/S) (2.5 M/S) (3.8 M/S)

HQ304 11 7 6 5 °C/WHQ240 12 9 7 6 °C/WHQ208 14 10 8 7 °C/WMQ240 17 12 11 10 °C/WMQ208 18 14 13 12 °C/WPQ240 23 17 15 14 °C/WPQ208 32 23 21 19 °C/WPQ160 32 24 21 20 °C/WPQ100 33 29 28 27 °C/WPC84 33 25 21 17 °C/WTQ100 31 26 24 23 °C/WVQ100 38 32 30 29 °C/W

The benchmark results in Figure 2demonstrate that both the Xilinx XC9500family and the Vendor A devices were ableto accommodate the design changes with-out any impact on design performance.Vendor L devices maintained the samepinout, but with a significant (up to 60%)performance penalty. Since the Vendor Ldevices have 16 input logic blocks, theperformance degradation of the 16-bitaddress decoder can be attributed to poorrouting resources while the performance ofthe 32 and 36-bit decodes is degraded byboth poor routing and narrow logic blockfan-in.

Datapath BenchmarkThis benchmark design measures the

affect of routing resources on the CPLD’spin-locking capability. This design containsa single 16-, 32- or 36-bit wide data bus.A typical design change involves the reor-dering of data bits.

The benchmark results shown inFigure 3 show that both the Xilinx XC9500family and Vendor A devices were able toaccommodate the design changes withoutany impact on design performance.Vendor L devices sacrificed performance(up to 80%) to reroute the design whenpinlocked. Since only one logic blockinput was required for each output, thisperformance degradation can be attributedto poor routing resources, or fitter perfor-mance, or both, but cannot be attributedto logic block fan-in.

Address Counter BenchmarkThis benchmark design contains two

16-, 24- or 32-bit loadable address countersloaded from separate buses but with com-mon clock and hold signals. A typicaldesign change alters the initial count loadvalue. This benchmark measures the effectof routing resources and function blockfan-in on the CPLDs pin-locking capability

20 29Figure 2: Address Decoder-Normalized Benchmark Results

Figure 3: Data Path-Normalized Benchmark Results

XC9500 BenchmarksContinued from the previous page Figure 1:

Maximum acceptable power consump-tion as a function of ambient tempera-ture and package thermal resistance,assuming full performance (i.e. 85° Cjunction temperature).

Figure 2:Maximum acceptable powerconsumption as a function of ambi-ent temperature and package thermalresistance, at reduced performance(14% longer delay, 12% lower speedat 125° C junction temperature).

30 19

level. The number of available functionblock inputs affects the fitter’s ability to addmore signals to any logic that must remainin that function block (because it drivesI/O pins). Wide fan-in capability also helpsthe fitter implement that logic in a singlepass though the device.

Each XC9500 function block has 36inputs from the switch matrix. Competingin-system programmable CPLDs have asfew as 16 inputs.

Product term allocation is important topin-locking because it allows designchanges that increase the product termrequirement. All XC9500 devices allocateindividual product terms from anywhere inthe function block to the macrocell thatneeds them, accommodating logic changeswhen the design is pinlocked.

In the XC9500 family, up to 90 productterms can be allocated to any macrocell inthe function block. This is in contrast tocompeting CPLDs that restrict the productterm availability (from 5 to 32 pterms) onthe basis of macrocell location in thefunction block.

Fitter software is a key component ofany successful CPLD pin-locking solution.The fitter must work in conjunction withthe device architecture, spreading the out-puts to accommodate design changes whenthe design is pinlocked.

The XC9500 fitter is optimized to takefull advantage of the hardware resources ofthe XC9500 family. The Xilinx fitter is ca-pable of intelligently utilizing all availabledevice resources to retain pinouts and stillmaintain the required performance, evenafter significant design changes.

The Pin-locking BenchmarksThe following three sets of benchmark

data show the relative pin-locking perfor-

Whenever a clocked flip-flop syn-chronizes an asynchronous input, there isa small probability that the flip-flop outputwill exhibit an unpredictable delay. Thishappens when the input transition not onlyviolates the setup and hold-time specifica-tions, but actually occurs within the tinytiming window where the flip-flop acceptsthe new input. Under these circumstances,the flip-flop can enter a symmetrically-balanced transitory state, called a meta-stable state.

While the slightest deviation from per-fect balance will cause the output to revertto one of its two stable states, the delay indoing so depends not only on the gain-bandwidth product of the circuit, but also

on how perfect the balance was and on thenoise level within the circuit; the delay can,therefore, only be described in statisticalterms. The problem for the system designeris not the illegal logic level in the balancedstate (it’s easy enough to translate thatarbitrarily to either a 0 or a 1), but theunpredictable timing of the final change toa valid logic state. If the metastable flip-flopdrives two destinations with differing pathdelays, one destination might clock in thefinal data state while the other does not.

Metastability MeasurementsRecently, the metastable delays of four

different Xilinx FPGA devices were mea-sured: two cutting-edge devices using 0.5micron, 3-layer-metal technology, the

Pin-Locking Capabilitiesmance of the XC9500 CPLDs and twocompetitor’s ISP CPLD families. Thesebenchmarks are based on typical applica-tions such as address decoders, datapathdesigns and address counters. They illus-trate the CPLD device’s capability to ac-commodate design changes while main-taining an acceptable level of designperformance; not only must the iterateddesign reroute when the pinout is main-tained, it must do so with minimal impacton design performance. Therefore, all ofthe benchmark data is normalized to thedesign performance that is achieved whenthe fitters are free to choose the pinoutswithout restrictions.

Address DecoderBenchmark

This benchmarkdesign contains two16-, 32- or 36-bit bus-ses which are decodedto generate two chipselect outputs and isintended to measurethe effect of routingresources and functionblock fan-in on theCPLD’s pin-lockingcapability. A typical design change in-volves the correction of an error in whichthe outputs are decoded incorrectly.


Metastability Recovery in Xilinx FPGAs

Figure: Mean TimeBetween Failure forvarious IOB and CLBflip-flop outputs whensynchronizing a 1 MHzasynchronous input witha 10 MHz clock.

❝The benchmark results confirm

the superior pin-locking performance of the

Xilinx XC9500 family. This performance is

consistent across all devices and package types.❞

18 31

The Xilinx XC9500 CPLD family pro-vides the most-advanced, most-reliable pin-locking capability in the industry. Thisimportant feature allows designers to main-tain pinouts after making design changes,eliminating costly, time-consuming PCboard re-work. CPLDs that do not haveadequate pin-locking capability often re-quire pinout changes even after minordesign changes, leaving no room for errorand no possibility for field upgrades orfield customization.

Pin-Locking IssuesIn most CPLDs, each I/O pin is driven

directly by a macrocell through an I/Oblock, as shown in Figure 1. When the

design is pinlocked, the fitter is forced tomap logic into specific macrocells to main-tain the pinout. If the device architecture islimited, with inadequate routing in thecentral switch matrix, the fitter may not beable to place and route the design whenthe pins are locked.

Some CPLDs use an output routing poolto compensate for their primary routingdeficiencies. However, output routing poolsintroduce additional delays and do notprevent the fitter from having to consumelogic resources as routing feedthroughs,

impacting both design performance andresource utilization.

Logic requirements also affect the abilityof the fitter to place and route the designwhen the pinout is locked. Slow speeddesigns with simple, narrow logic functionsrequiring few inputs, feedbacks and prod-uct terms are inherently easier to pinlockthan high speed designs with wide fan-inand product term intensive logic functions.

The Keys to Reliable Pin-LockingTo address these pin-locking issues,

Xilinx XC9500 CPLDs feature abundantrouting resources, wide function block fan-in and flexible product term allocation. TheXC9500 fitter also optimizes the initialplacement to maximize the design’s pin-locking capability.

Pin-locking restricts the fitter’s capabilityto place design resources; therefore, goodroutability is crucial. The routing resourcesof a CPLD determine how much of thelogic block resources (inputs, productterms and registers) can be used to accom-modate design changes after the pins arelocked in a design. In a fully routableCPLD, buried logic can be moved withoutregards to routing restrictions, freeing func-tion block resources that may be neededby the logic that drives the I/O pins.

The XC9500 family provides the mostrouting resources of any available CPLDfamily. All devices in the XC9500 family are100% routable; if there are enough functionblock resources to implement the design, itwill route.

Wide function block fan-in is anotherimportant requirement for pin-locking.Since CPLDs typically are used for high-speed, signal-intensive logic functions,wide function block fan-in is a requirementfor implementing functions in a single logic

DESIGN HINTS AND ISSUES

R

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

XC4005E-3 and the XC3142A-09; and, forcomparison purposes, two older-technol-ogy devices, the XC4005-6 and the XC3042-70. In each device, two different implemen-tations test the IOB and CLB flip-flops. TheXC5200-5 CLB flip-flop was also tested.(There is no IOB flip-flop in XC5200 archi-tecture.)

The XC4000E amd XC4000 devicesshowed little difference between IOB andCLB behavior, but in the XC3000-seriesdevices, the IOB flip-flops showed dramati-cally better metastable performance thanthe CLB flip-flops. This difference can betraced to subtle differences in circuit designand layout and will guide us to furtherimprovements in metastable performanceof future designs.

Metastable measurement results arelisted in the table and plotted in the figure.The results for XC4000E-3 IOB and CLBflip-flops, XC5200-5 CLB flip-flops andXC3100A-09 IOB flip-flops are outstanding,far superior to most metastability datapublished anywhere else. When granted 2or 3 ns of extra settling delay, these devicescome close to eliminating the problemscaused by metastability, since their mean-time-between-failure exceeds millions ofyears. The older-technology devices areslightly less impressive, but still show veryacceptable performance, especially the IOBinput flip-flops that are normally used tosynchronize asynchronous input signals.

Metastability CalculationsThe Mean Time Between Failures

(MTBF) can only be defined statistically. Itis inversely proportional to the product ofthe two frequencies involved, the clockfrequency and the average frequency of theasynchronous data changes, provided thatthese two frequencies are independent andhave no correlation. The generally acceptedequation for MTBF is

MTBF = eK2 ××××× t

F1 ××××× F2 ××××× K1

Benchmarks Confirm XC9500 CPLD

Figure 1: SimplifiedXC9500 I/O Architecture

K2 is an exponent that describes the speedwith which the metastable condition isbeing resolved.

K1 represents the metastability-catchingsetup time window that describes thelikelihood of going metastable

F1 is the frequency of the asynchronous datainput

F2 is the flip-flop clock frequency

t is the settling time

K2 is an indication of the gain-bandwidthproduct in the feedback path of themaster latch in the flip-flop. A smalldecrease in the time constant 1/K2 resultsin an enormous improvement in MTBF.

With F1 = 1 MHz, F2 = 10 MHz andK1 = 0.1 ns,

MTBF (in seconds) = 10-3 ××××× eK2 ×××××t

The values of K2 under these condi-tions — expressed as 1/K2 in the table —were experimentally derived (as describedin the “1996 Programmable Logic DataBook,” page 14-41).

The MTBF under other operating condi-tions can be estimated using the data inthe diagram. Simply divide the appropriateMTBF from the diagram by the product ofthe two relative frequencies. For example,for a 10 MHz asynchronous input synchro-nized by a 40 MHz clock, the MTBF is 40times shorter than plotted, and for a 50KHz signal and a 1 MHz clock, the MTBFis 200 times longer than plotted here.◆

Metastability Measurement Results

TESTED FLIP-FLOP VALUE OF 1/K2 IN PICOSECONDS

XC4005E-3 CLB 52IOB 62

XC4005-6 CLB 127IOB 118

XC3142A-09 CLB 208IOB 79

XC3042-70 CLB 385IOB 238

XC5200-5 CLB 73

32

17

in XC4013-2 FPGAs. These devices operateat 33 MHz and include high-speed burstsynchronous FIFOs. The modules can becustomized to fit individual design require-ments, resulting in a cost-effective, single-chip solution.

The LogiCore PCI Master module (LC-DI-PCIM-C) for Xilinx FPGA and HardWiredevices, complete with a data sheet, com-prehensive user guide and PCI SystemsArchitecture textbook, is available fordesigning with Viewlogic schematics,VHDL and Verilog for $8,995. The PCISlave module (LC-DI-PCIS-C) is availablefor $4,995.

For further information about theLogiCore PCI Interface or other mod-ules in the program, please contactyour local Xilinx representative orvisit the LogiCore section of theWebLINX World Wide Web site.◆

LogiCoreTM PCI Intitiator DebutsXilinx recently announced the delivery

of its second, 100% compliant PCI core,the LogiCoreTM PCI “Master” (Initiator/Target) module. Previously, the LogiCorePCI “Slave” (Target only) module couldonly perform slave functions. With the newmodule, a user can now complete a masterinterface design in which the Master mod-ule acts as a controller for the PCI bus.The implementation of critical paths in thecore are pre-defined to ensure PCI compli-ance. As a result, designers can reducedesign risk and cut development time by atleast nine months.

The new -2 speed grade for theXC4013E FPGA enables the delivery of thePCI Master module, which requires a highlevel of design complexity and perfor-mance (see article about -2 speed grade onpage 14). The LogiCore PCI modules wereclosely developed with beta users whohave successfully implemented the design

Foundation Series Enjoys Successful IntroductionThe number of Foundation

SeriesTM users has been growing rapidlysince the inaugural release of this fullyintegrated PLD design software pack-age in 2Q96. User feedback has beenextremely positive, especially regardingthe ease-of-use resulting from the tightintegration of all the design tools.There also has been high praise for theHDL Wizard, including the HDL Editor,with color coding, and the LanguageAssistant, with templates for easy andquick coding of VHDL and ABEL-HDL.

The Foundation Series developmenttools for FPGA and CPLD design in-clude a highly integrated set of Win-dows-based design tools. Along with

the Xilinx XACTstepTM implementa-tion tools, it includes an HDL editor,synthesis compiler, schematic editorand simulator.

Xilinx has added more featuresto the Foundation packages in thev6.0.1 release, which is now ship-ping. Features in this release includesupport for the latest Xilinx devicefamilies: the XC9500 CPLDs andXC4000E FPGAs. Both device fami-lies are integrated into the easy-to-use, shrink-wrapped solution, mak-ing it simple to access and convert designsfor these new families. All users who pur-chased Foundation v6.0 will automaticallyreceive this new update.◆

❝Xilinx has

added more features

to the Foundation

packages in the

v6.0.1 release, which

is now shipping.❞

tion of RAINPORT.EXE , available in theSWHLP\XACTFPGA directory of the Bulle-tin Board Service (BBS). This program fixesparallel port access problems that occurwhen the security key is checked.

XACT step and AlternateOperating Systems

The Xilinx XACTstepTM developmentsystem software is available for both work-station and PC platforms. The PC-basedversion is designed for Windows 3.1, and

the Sun-based version for the Sun OS. How-ever, with some exceptions as detailedbelow, XACTstep software can run on somevariants of these popular operating systems.

Running XACT step v6.0.1 in Windows 95The majority of the XACTstep 6.0.1

software will run in Windows 95. However,there are some known compatibility issues:

• The Design Manager will cause aGeneral Protection fault when it isclosed. This causes no system problemsand can be ignored.

• The Hardware Debugger does not run.There is no known workaround.

• The ProSeries software does not rununder Windows 95. WorkView Office isavailable on an as-needed basis. Contactthe Xilinx Technical Hotline for moreinformation.

Running XACTstep v5.2.1 in Windows NTThe XACTstep v6.0.1 GUI tools (DM,

Floorplanner, Prom File Formatter, Hard-ware Debugger) will not run in WindowsNT, but the v5.2.1 executables can bemade to run in a DOS box with the addi-

Install problem, a script called cdi.csh hasbeen developed that will install the soft-ware in a non-graphical mode. This scriptcan be found on the Xilinx BBS (408-559-9327) and on the Xilinx FPT site(xilinx.com). Unfortunately, the Xilinx-Mentor Graphics interface (DS-344) doesnot work under Solaris, so Mentor Graph-ics’ users should stay with SunOS 4.1.X.◆

Solaris Support for XACTstep v5.2.1

Although not officially supported andtested by Xilinx, most of the XACTsteptools work with Solaris 2.5. The XCheckerprogram, which did not work with Solarisversion 2.4, will run under 2.5 when theSunOS 4.1.3 backwards-compatibility op-

tion is used. However, the Installprogram still does not work inSolaris. As a workaround to the

16

33

FPGAExpress


filtering out gated clocks. If desired, userscan specify specific input pins that need tobe connected to a global buffer.

Synopsys revised the mapping andoptimization algorithms to provide all HDLusers with the best possible synthesisresults for area, performance and predict-ability. Testing has shown that FPGA Ex-press can improve area and performanceby up to 25% over existing PC-based syn-thesis tools. Run times are excellent — a3,000-gate design compiled in under aminute and a 20,000-gate design requiredapproximately 10 minutes using a Pentium-class computer.

Xilinx also collaborated with Synopsysto integrate FPGA Express into theXACTstepTM system. FPGA Express uses asophisticated constraint-entry GUI, with an“XACT step-like” from/to syntax for timing

FPGA Express providesa smooth interface to

other Xilinx FPGAdevelopment tools

constraints that directly translates to theXACTstep TIMESPEC format. All netlist andconstraint translation is done by FPGAExpress, eliminating the need for externaltranslators. The tool outputs Unified LibraryXNF with group TIMESPECS. The result isa “plug & play” interface between FPGAExpress and the XACTstep tools (v6.0.xand beyond).

Pricing and AvailabilitySold by Synopsys, FPGA Express starts

at $12,000 (one HDL language and supportfor one FPGA vendor). It will be availablein full production in September, runningon Windows 95 and Windows NT-basedpersonal computers.

For more information about FPGAExpress contact Bruce Jorgens, Prod-uct Line Manager for FPGA Productsat Synopsys 415-528-4955.◆

signing with a range of Xilinx parts and isup-to-date on Xilinx products.

XUMA is completely independent fromXilinx, Inc. Many engineers want an inde-pendent technical forum for openly dis-cuss key concerns and issues, both at thesystem- and device-level, and get objectiveanswers from others in their professionalcommunity.◆

Alain Arnaud of ECLA, Inc. (Newton,Massachusetts), a design consultant andexperienced FPGA and ASIC designer, waspondering how to best field his customers’questions — a mix that included bothsystem-level and FPGA-level issues. Toassist in this task, Alain started an e-mailaddress list of colleagues and industrycontacts. This effort has grown into XUMA— the Xilinx User MAiling List — a new,independent forum for the communicationof technical subjects across the Xilinx usercommunity. XUMA, initiated in May,1996,currently has over 250 subscribers and isgrowing rapidly.

XUMA mailings are e-mails of technicalquestions and answers sent to Alain byanybody and forwarded to everyone onthe XUMA mailing list.

Xilinx users can subscribe to the list,unsubscribe from the list or submit achange of address by sending mail to:

[email protected]

To send a technical question, answer orrelated information to the list, mail it to:

[email protected]

Mention in your mail if you would liketo remain anonymous. Alain sends outdigests of messages sent to him abouttwice each week.

XUMA is more focused than the“comp.arch.fpga” news group (see XCell#21, page 41). Comp.arch.fpga is a generalFPGA forum that typically deals withbroad-based questions and issues, whileXUMA is dedicated to trading technicalinformation regarding Xilinx devices andsoftware. As a result, it takes less time toreview XUMA digests for pertinent infor-mation. Furthermore, Alain is actively de-

New, Independent E-Mail User GroupDedicated to Xilinx Technology

XUMA: Xilinx User MA iling list


CC:

TOPIC: Xilinx mailing list

MESSAGE: Alain -- please add my name to the XUMAlist for Xilinx technical issues.


CC:

TOPIC: XC4000 Series tip

MESSAGE: Alain -- I think I have discovered away to use an XC4025E as a barrier toprotect my desk from the harmfuleffects of excess moisture building upon the bottom of my coffee mug.

Remember, Xilinx userscan contact the Xilinx

Technical Support Hotline(see page 35) with

technical questions onXilinx products.

FPGA Express

34

15

Xilinx Alliance member Synopsysunveiled its first entry into the Win95/Windows NT market at the Design Automa-tion Conference in Las Vegas on June 3.“FPGA Express” is a PC-based FPGA

synthesis tool for leading FPGA architec-tures. The first version has Xilinx XC3000family, XC4000 series and XC5200 familysupport. It is scheduled for productionshipment in September. Later versions willsupport the XC9500 CPLD family, as well asother programmable logic vendors.

FPGA Express is unique in its knowl-edge of Xilinx architectures and tools,allowing designers who are new to HDL toget high-quality results. The expert userwill find the sophisticated controls neededto work with very challenging designs.

FPGA Express is not a rewrite ofFPGA Compiler, although for compatibilityit uses the same VHDL and Verilog com-piler technology as Synopsys’ workstationtools (Design Compiler and FPGA

Compiler). FPGA Express was designed“from the ground up” with PC usersspecifically in mind.

The Xilinx/Synopsys relationship waskey in the development of this product.“This is an excellent example of Xilinx andone of its Alliance partners working to-gether to meet user requirements with aquality product,” noted Wallace Westfeldt,manager of the Xilinx Alliance program.

Xilinx supplied architectural informationand assisted in the market research, defini-tion and development of FPGA Express.As a result, FPGA Express makes optimumuse of Xilinx device features to maximizedensity and performance. For example, itincludes an automatic module generatorthat can infer various operations within theHDL source, such as adders, comparatorsand multipliers, aswell as automati-cally build thecircuits using thededicated carrylogic in theXC4000 series andXC5200 familyarchitectures.

FPGA Expressalso makes fulluse of complexI/O structures present in the Xilinxdevices, including the clock enable featureof the XC4000E IOB registers. Global clockbuffers are assigned based on an intelli-gent algorithm that allocates the availablebuffers based on clock signal fanout while

We are continuously investing in state-of-the-art customer support systems toprovide customers with choices, efficientaccess to support resources and reliableconnections.

When contacting the Technical andApplications Support Hotline in San Jose,you will be prompted to input the purposeof your inquiry to ensure that you reach themost appropriate person as soon as pos-sible. In addition, you will be asked toprovide your “personal ID number” or your“case ID number.”

Anytime during the process, you canbypass the automated inquiries to speakdirectly with a live support representativeor leave a voicemail message for a supportengineer.

What is mypersonal IDnumber?

The first timeyou contact theXilinx hotline,your personal IDnumber will beassigned by ourcustomer casemanagement sys-tem. On subse-quent calls, youmay use this num-ber to speed up

the support process. Once the telecommu-nications system receives your ID number,you will skip directly to a menu of topicsto choose from so that your call can berouted to the most helpful resource orqualified support engineer available.

Cases opened under your ID numberare tracked under your name. If your col-leagues wish to contact Xilinx, advise themthat they can receive their own personal IDnumbers by calling the hotline directly.

What is my case ID number?Each time you call with a new support

need, a case ID number will be assignedand communicated to you by a supportprofessional. If you have further need tocontact the hotline regarding an open case,you can speed your access to your caseworker by inputting the case number di-rectly into the telecommunications system.

What is the fastest way to reach anengineer with a new question?

On a typical day, the fastest path toreach a support engineer is through thetelecommunications system using yourpersonal ID number:

• Select your situation: New Case orExisting Open Case.

• Enter your Personal ID or the OpenCase ID

• For a new case, you will be promptedto select a product topic area.

• Your call is directed to the most appro-priate available resource.

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○

R

PRODUCT INFORMATION-DEVELOPMENT SYSTEMS

Synopsys Introduces

New Logic Synthesis Tool Targets Xilinx FPGA Families

❝FPGA Express isunique in its knowledge of Xilinx

architectures and tools, allowing

designers who are new to HDL to

get high-quality results.❞

Continued on the next page

New Technical Support ChoicesCallers to the Technical Support Hotline

at the Xilinx headquarters in San Jose nowencounter a friendly, ease-to-use telecom-

munications system that allows better accessto the resources and solutions needed toensure design progress and success.

Efficient and Speedy Access to Engineers on theHotline Thr ough Increased Choices

PHO

TO F

OR

ILLU

STR

ATIO

N P

UR

POSE

S O

NLY

35

14

XC4000EX Family FPGAs Entering Production

Faster XC4000E FPGAs Now Available HOTLINE SUPPORT, U.S.

Customer Support Hotline:800-255-7778

Hrs: 8:00 a.m.-5:00 p.m. Pacific time

Customer Support Fax Number:408-879-4442

Avail: 24 hrs/day-7 days/week

E-mail Address:[email protected]

Customer Service*:408-559-7778, ask for customer service

* Call for software updates, authorizationcodes, documentation updates, etc.

HOTLINE SUPPORT, EUROPE

UK, London Officetelephone: (44) 1932 820821fax: (44) 1932 828522Bulletin Board Service: (44) 1932 333540e-mail: [email protected]

France, Paris Officetelephone: (33) 1 3463 0100fax: (33) 1 3463 0959e-mail: [email protected]

Germany, Munich Officetelephone: (49) 89 991 54930fax: (49) 89 904 4748e-mail: [email protected]

Japan, Tokyo Officetelephone: (81) 3 3297 9163fax: (81) 3 3297 0067e-mail: [email protected]

Xilinx has started sample shipments ofthe first two members of the high-densityXC4000EX family. The XC4036EX, with atypical gate range of 22,000 to 65,000gates, and the XC4028EX, with a typicalgate range of 18,000 to 50,000 gates, willenter volume production in the fourthquarter of this year.

The next member of the family to beintroduced is the XC4062XL, featuring atypical gate range of 40,000 to 130,000gates. The XC4062XL will begin samplingin December.◆

The XC4000EX family elevates theXC4000 series to new heights in densityand performance, with up to 125,000 logic

gates and 66 MHz system speeds.Designed “from the ground up”for speed and density using adeep-submicron, triple-layer-metal process, the XC4000EXfamily has abundant routingresources for high utilization andbuffered interconnect to providemaximum performance. (SeeXCell #20, page 21.)

mum chip-to-chip system speeds of theXC4000 and XC4000E devices for theiravailable speed grades.

The XC4000 series (i.e., the XC4000,XC4000E and XC4000EX families) incorpo-rates the world’s most widely used FPGAarchitecture with advanced features such asSelect-RAMTM memory, wide edge decod-ers, internal three-state buffers and multipleglobal clock distribution networks. Thehigh performance levels offered from the-2 speed grade, when combined with theseleading-edge architectural features, furtherextends the range of possible applicationsfor these popular devices.

For example, the capabilities of theXC4000E-2 device enable the delivery ofthe LogiCoreTM PCI Initiator module —an implementation that requires extremelyhigh performance levels, especially forFIFO buffer and registered I/O operations(see page 17).

For further technical information,please refer to the product specifica-tions and application notes onWebLINX, the Xilinx web site(www.xilinx.com). For pricing andavailability, contact your local Xilinxsales representative.◆

Continuing process improvements haveled to the release of a new, faster speedgrade for XC4000ETM FPGAs, available nowfor every member of the device family.

The new -2 speed grade achieves a15-20 percent performance improvementover the -3 speed grade as a result of alogic block propagation time (TILO) of 1.6ns, clock-to-output delays (TOKPOF) of under5 ns and global-clock-to-out, pin-to-pindelays (TICKOF) ranging from 8.7 ns for theXC4003E to 10.7 ns for the XC4025E . SeeFigure 1 for a comparison of the maxi-

Figure 1: Speed Grade Comparisons for XC4000 and XC4000E

70 MHz

60 MHz

50 MHz

40 MHz

30 MHz

20 MHz

10 MHz

0 MHz

Syst

em S

peed

*

XC4000 Family XC4000E Family(3,000-25,000 gates) 3,000-25,000 gates)

-6 -5 -4 -4 -3 -2

3832 MHz

27 MHzMHz

65MHz

56MHz

40MHz

*Maximum chip-to-chip system speed

TECHNICAL SUPPORT RESOURCES

Increased On-Line Technical InformationThe Xilinx BBS mirrored on the World Wide Web.

Xilinx Bulletin Board Service files and resources can now be accessed through theXilinx Internet FTP site.

Xilinx offers increased on-line support resources and choices.In the coming months, keep an eye on the Xilinx Technical Support resources on

WebLINX, the Xilinx web site (www.xilinx.com). In addition to the above mentioned BBSresources, you will see increased access to applications materials, product support materi-als, and commonly asked questions and solutions.

X-TALK: The Xilinx Network of Electronic Services• Xilinx home page on the World Wide Web.........................................www.xilinx.com.• Electronic Technical Bulletin Board (U.S.)................................................. 408-559-9327• XDOCS E-mail document server-

send an E-mail to [email protected] with ‘help’ as the only item in the subject header.You will automatically receive full instructions via E-mail.

• XFACTS fax document server..................................... available by calling 408-879-4400.

E-mail addresses for questions related to specific applications:Digital Signal Processing applications.................................................................dsp@xilinx.comPCI-bus applications............................................................................................. [email protected] and Play ISA applications ............................................................................ [email protected] card applications ............................................................................. [email protected] Transfer Mode applications........................................................ [email protected] Computing applications.................................................... [email protected]

13

36 XC8100 FPGA Product Family is Discontinued

Mentor Graphics

QWhile compiling my Autologicdesign through Timsim8,PLD_DVE_BA returns the

following warning, that may repeatseveral times:

# WARNING: Unknown designobject: /JE/I1101S$37$5

What does this mean and howcan I fix it?

Autologic may write out percent signs(%) in its instance names. Although this islegal in Mentor schematics, it is not legal inXilinx netlists. To remedy this, EDIF2XNFchanges each “%” in a netlist to “$37$” (soused because 37 is the ASCII code for thepercent sign). Unfortunately, the Mentorback-annotation file is written with thischange, so that I1101S$37$5 in the MBAfile does not match up with the trueI1101S%5 in the schematic.

The problem may be fixed by modify-ing the mbapp.nawk script, which pro-cesses the MBA file for use inPLD_DVE_BA, to change the $37$’s backto %’s. For more information, send E-mailto [email protected] with send 618 inthe subject line. Once this modification ismade, Timsim8 should run smoothly.

QI have an Autologic design that,during Men2XNF8, gives me thefollowing error in EDIF2XNF:

Error: 5 No direction/pintypefor port:PINBALL/WIZARD

What’s happening and howcan I fix this?

The pin in question does not have aPINTYPE property associated with it. ThePINTYPE property indicates a pin’s direction-ality, and is required in XACT 5.x byEDIF2XNF and XNFMerge. Autologic mayomit PINTYPE properties when synthesizinghierarchical symbols, following the rules ofpre-XACT 5.0 software.

If the offending symbol was created byAutologic II, a patch is available on MentorGraphics’ FTP site at supportnet.mentorg.com(137.202.128.4).

Autologic II version A.x requires Patch244, located in the directory:

/pub/patches/release_A/autologic2






(HP-UX)

Autologic II version B.x requires Patch320, located in the directory:

/pub/patches/release_B/autologic2






(HP-UX)

Best 44-Pin PLD Value

Citing the strong market succcess ofSRAM and FLASH technologies, Xilinxannounced on Aug. 31, 1996, that it willdiscontinue the XC8100TM family of one-time programmable antifuse FPGA devices.The XC8100 family, first introduced lastautumn, was just entering production.

No layoffs or reductions in R&D spend-ing are associated with this decision. Xilinxemployees involved with antifuse develop-ment are taking on new duties in otherareas of the company. Resources andresearch and development spending arebeing redirected to focus more effectivelyon SRAM-based FPGAs, CPLDs and newopportunities more closely aligned withthose products, such as LogiCore modules.

“The XC8100 team successfully developeda number of patented, industry-first innova-tions in antifuse architecture, design, pro-gramming and processes — accomplishmentsno one else in the entire semiconductorindustry has been able to achieve so far with

this difficult technology,” stated Xilinx CEOWim Roelandts.

“But, compared to SRAM development,there are very few people working inantifuse. As a result, antifuse will lag be-hind SRAM, entail dispro-portionately large develop-ment costs, and berelegated to limited mar-kets. For these reasons webelieve further investmentin antifuse product devel-opment are too large to bejustified.”

A number of options areavailable to support currentXC8100 users, includingassistance in moving de-signs to other pin-compat-ible Xilinx devices, softwareupgrades to support otherprogrammable logic products and refundsfor XACTstepTM 8000 software.◆

❝compared to

SRAM development, there are

very few people working in

antifuse. As a result, antifuse

will lag behind SRAM, entail

disproportionately large

development costs, and be

relegated to limited markets.❞

ANNOUNCEMENT

FEATURES BENEFITSFamiliar Data I/O ABEL, Windows-based environ- Push button design flow improves productivityment for design entry, simulation and fittingIndustry-standard-ABEL- HDL supports state ABEL-HDL familiar to PAL users, optimizedmachines, high level logic descriptions, truth for PAL and CPLD developmenttables and equation entryHierarchical design entry and JEDEC file Enables reuse of existing PAL codes,conversion for integration of existing PAL designs simplifying design effortinto Xilinx CPLDsFunctional simulation with graphical Waveform Facilitate rapid design verificationViewer and Static Timing ReportsAdvanced XACTstep v6 XC7K & XC9K fitter with auto- Fitter’s architecture-specific knowledge freesomatic device selection, multiple pass optimization, the user to focus on design functionalitypartitioning and mapping, and timing driven fittingAnimated tutorial and on-line help Reduces learning curve:

• tutorial leads users through entiredesign process in minutes

- extensive on-line help places alldocumentation a mouse-click away

◆

TECHNICAL QUESTIONS & ANSWERS

37

12

The combination of ultra-low-cost44-pin XC7300 CPLDs and easy-to-useXABEL-CPLD development software pro-vides users with the best value in program-mable logic. Three XC7300 family membersare now available in 44-pin PLCC, PQFP orVQFP packages — the XC7336, XC7336Qand XC7354 devices.

Xilinx 44-pin XC7300 CPLDs provide agreater range of performance and signifi-cantly lower costs than PALs and GALs. Infact, the logic from several PAL /GAL de-vices can be integrated into a singleXC7300 CPLD at a lower device cost thanthe replaced PALs/GALs (and sometimes ata component cost equivalent to a singlehigh-speed PAL). The XC7300 CPLDs alsocan replace TTL bus drivers, further reduc-ing component count and cost. Advancedsystem features such as 3.3V or 5V I/O

signaling levels and 100% PCI complianceprovide support for the newest CPUs andhigh-performance memories.

44-pin CPLDs also have proven ex-tremely adept at fixing “ broken” ASICs.ASIC users are discovering that 44-pinCPLD solutions can be used to safeguardor repair ASIC functionality. Sometimesfixed-function ASICs can be rendered“unusable” by specification changes, pro-cess variations that disrupt system timingor design errors. Planning ahead by reserv-ing board space for a small form factor, 44-pin CPLD can provide ASIC designers with“system insurance.” The CPLD can be usedto implement control circuitry or correctsensitive timing paths. In this way, theflexibility to fix unwanted surprises is built-in to the design.

QAfter running Fncsim -o(use original schematic) on adesign that contains X-BLOX

components, I see no-connectsymbols on certain pins in thesimulation schematic. What’shappening?

These no-connects will appear in thesimulation schematic any place where twopin vertices are laying on top of eachother. In the original schematic, the pinswould be connected by a zero-length net.In the simulation schematic, however, thecoincident pins will not be connected(hence, the no-connect symbol).

The best fix for this problem is to goback to the original schematic and moveany coincident vertices apart, so that thenet between them may be seen.

XC7300 CPLDs & XABEL-CPLD: The Industry’s

XC7336 XC7336Q XC7354 BENEFITS22V10 equiv. 3 3 5 lower inventory & production costs16V8 equiv. 4 4 6macrocells 36 36 54usable gates 800 800 1500tPD 5.0 ns 10 ns 7.5 ns XC7336-world’s fastest CPLD

ICC

(typ.) 126 mA 50 mA 140 mA Significant power savings over multiple PALs/GALs3.3V/5V I/O Y Y Y Interface with high performance memories and MPUs24 mA high drive I/O Y Y Y PCI Bus compliancepackages PC44, PC44, PC44 VQ44 53% smaller than PC44

PQ44 PQ44, VQ44

Push-Button Software Gets the Job DoneLow-cost XABEL-CPLD software obso-

letes all PAL/GAL and low-end CPLD toolsand provides push-button ease of use.Based on ABEL 6.0, XABEL-CPLD offersinstant productivity enhancement to allPAL/GAL users and makes the migration tohigher-density, cost-effective CPLD tech-nology quick and easy.

The combination of highly-capable,low-cost silicon and software makes Xilinx44-pin CPLD solutions the best choice in aworld where product development sched-ules and system component budgets areshrinking at an ever-accelerating pace.

continued

Synopsys

QHow can I prevent FPGACompiler from writing mytiming constraints into the

.sxnf file?

During its optimization process,Synopsys’ FPGA Compiler attempts tomeet the timing constraints issued by you;and subsequently writes out the timingconstraints into the netlist (.sxnf) file forthe Xilinx tools to use. You may want toissue these constraints to the Xilinx toolsin a separate constraints file, where youhave the ablility to be more specific aboutparticular paths that you want to constrain.

To do this, issue the followingcommand just prior to writing out the.sxnf file:

xnfout_constraints_per_endpoint = 0

This will result in a netlist (.sxnf) thatdoes not contain any timing constraints.You may then issue XACT Performanceconstraints in a .cst which will be used bythe Xilinx tools. For more information onXACT Performance, see the DevelopmentSystems Reference Guide.◆

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○

38

11

Xilinx recently announced significantprice reductions and performance improve-ments for the XC5200 FPGA family, further

R

PRODUCT INFORMATION-COMPONENTS

XC5200 Family:Lower Prices & Higher Performance

advancing its position as the industry’smost cost-effective FPGA family.

Performance Improved by 30%In addition to price reductions, a

patented charge-pump transistor design hasbeen added to the XC5200 family. Whencombined with a semiconductor processshrink from 0.6µm to 0.5µm triple-layermetal technology, the result is a new-3 speed-grade that offers up to a 30%performance improvement over the-5 speed grade (see table).

The XC5200 family delivers 2,000 to23,000 usable gates and robust features,such as the VersaRingTM I/O interface thatmaximizes overall utilization and pin as-signment flexibility, dedicated JTAG bound-ary scan logic for increased testability, and

fast carry logic for high speed arithmeticfunctions. The XC5200 FPGA family contin-ues to lead the industry as the lowest cost/gate programmable logic solution.◆

Prices Reduced by up to 50%XC5200 sales have risen at a record

pace. The rapid increase in shipments anda shift to a 0.5 µ process have resulted insignificant cost advantages; these savingsare being passed on directly to our users.With its segmented interconnect structureand an architecture optimized for its sub-micron, triple-layer metal (TLM) process,the XC5200 FPGA family has a significanttechnological advantage over other archi-tectures. The family’s small die sizes — insome cases even approaching today’s gatearray die sizes — lead to correspondinglylow component costs.

The chart below shows current high-volume pricing and projected pricing oneyear from now.

XC5200 Family Volume Pricing*MAXIMUM

DEVICE LOGIC GATES END OF 1996 2H97XC5202 3K $5.00 $4.50XC5204 6K $10.00 $8.00XC5206 10K $17.00 $12.00XC5210 16K $27.00 $18.00XC5215 23K $47.00 $33.00

* Plastic package, -6 speed grade, 25,000 unit quantity, U.S. direct pricing only

XC5200 Performance Benchmarks

XC5210-5 XC5210-3 % Improvement16-Bit Decoder 8 ns 6 ns 25%24-Bit Accumulator 39 MHz 50 MHz 28%16-to-1 Multiplexer 13 ns 9 ns 31%16-Bit Adder 20 ns 15 ns 25%16-Bit Up/Down Counter 50 MHz 65 MHz 30%

PIN

S

TYPE

CO

DE

XC

3020

AX

C30

30A

XC

3042

AX

C30

64A

XC

3090

AX

C30

20L

XC

3030

LX

C30

42L

XC

3064

LX

C30

90L

XC

3142

LX

C31

90L

XC

3120

AX

C31

30A

XC

3142

AX

C31

64A

XC

3190

AX

C31

95A

XC

4003

EX

C40

05E

XC

4006

EX

C40

08E

XC

4010

EX

C40

13E

XC

4020

EX

C40

25E

XC

4028

EX

XC

4036

EX

XC

4044

EX

XC

4052

XL

XC

4062

XL


COMPONENT AVAILABILITY CHART

44

4864

68

84

100

120

132

144

156160

164

175

176184191196

208

223

225

228

240

299304352411432499596

◆ ◆

◆

◆ ◆

◆ ◆ ◆ ◆ ◆

◆ ◆ ◆ ◆ ◆

◆

◆ ◆

◆ ◆

◆ ◆ ◆ ◆ ◆

◆ ◆ ◆◆ ◆

◆

◆ ◆◆ ◆ ◆

◆ ◆ ◆

◆ ◆ ◆ ◆

◆◆ ◆ ◆◆ ◆ ◆

◆◆ ◆

◆ ◆

◆ ◆ ◆◆ ◆ ◆ ◆

◆ ◆ ◆ ◆ ◆ ◆

◆ ◆ ◆ ◆ ◆ ◆◆ ◆

◆ ◆ ◆ ◆ ◆ ◆ ◆◆ ◆ ◆ ◆

◆ ◆ ◆ ◆◆ ◆ ◆ ◆

◆ ◆ ◆ ◆ ◆

◆ ◆ ◆◆ ◆ ◆◆ ◆ ◆◆ ◆ ◆ ◆

◆ ◆ ◆

◆

◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆

◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆

10

39

Learn about the newest Xilinx products and services through our extensive library ofproduct literature. The most recent pieces are listed below. To order or to obtain a com-plete list of all available literature, please contact your local Xilinx sales representative.◆

New ProductLiterature

1996 Programmable Logic Data Book Technical Data 00103031996 Programmable Logic Data Book on CD-ROM Technical Data 500360Product Overview Brochure Features & Benefits 0010130-05Software Selector Guide Features & Benefits 0010304FPGA Brochure Features & Benefits 0010305

TITLE DESCRIPTION NUMBER

EuroDAC & EuroVHDLSept. 16-20Geneva, Switzerland

International Workshopon Field ProgrammableLogic and ApplicationsSept. 23-25Darmstadt, Germany

PCI EuropeOct. 1-2Paris, France

DSP GermanyOct. 1-2Munich, Germany

Look for Xilinx technical papers and/or product exhibits at these upcoming industry fo-rums. For further information about any of these conferences, please contact KathleenPizzo (Tel: 408-879-5377 FAX: 408-879-4676).◆

UPCOMING EVENTS

ElectronicaNov. 12-15Munich, Germany

Photonics EastNov. 18-22Boston, Massachusetts

BIAS & DSP ItalyNov. 26-29Milan, Italy

DSP UKDec. 3-4London, United Kingdom

DSP World/ICSPATOct. 8-10Boston, MA

Silicon DesignConferenceOct. 9-10Birmingham,United Kingdom

WESCONOct. 22-24Anaheim, California

DSP FranceOct. 22-24Paris, France

PIN

S

TYPE

CO

DE

XC

4005

LX

C40

10L

XC

4013

LX

C52

02X

C52

04X

C52

06X

C52

10X

C52

15X

C72

36A

XC

7272

AX

C73

18X

C73

36X

C73

36Q

XC

7354

XC

7372

XC

7310

8X

C73

144

XC

9536

XC

9510

8X

C95

216

AUGUST 1996


44

4864

68

84

100

120

132

144

156160

164

175

176184191196

208

223

225

228

240

299304352411432499596

◆ ◆ ◆ ◆ ◆ ◆◆ ◆ ◆

◆ ◆◆ ◆ ◆ ◆

◆ ◆ ◆

◆ ◆ ◆

◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆◆ ◆ ◆◆

◆ ◆ ◆ ◆ ◆ ◆◆

◆ ◆ ◆ ◆◆

◆ ◆◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆

◆ ◆ ◆

◆

◆ ◆ ◆ ◆ ◆

◆◆ ◆ ◆ ◆ ◆

◆◆

◆

◆ ◆

◆ ◆

◆

◆ ◆ ◆

QuarterlyRevenue

Tops$150M

Please note that the XC8100 familyhas been discontinued.

See page 13.

◆ = Product currently shipping or planned❖ = New since last issue of XCELL

(none appear in this issue)

FINANCIAL RESULTS

Sales revenues rose to $150.2 million inthe first fiscal quarter of 1977 (ending June30, 1996), a 19% increase over the samequarter one year ago and a 0.3% increasefrom the immediately preceding quarter.

“The June quarter was a difficult quarterfor the semiconductor industry,” notedXilinx Chief Executive Officer WillemRoelandts. “Although Xilinx was notimmune to this widespread slowdown, wedid experience minor sequential revenue

growth. The bright spot was the NorthAmerican distribution channel, whichgrew 10% over the prior quarter.”

The XC5000 FPGA family continuedits torrid growth rate, with sales up 30%over the previous quarter. Recently an-nounced price cuts (see page 11) shouldeven further expand the market for thiscost-optimized FPGA family.

Xilinx stock is traded on the NASDAQexchange under stock symbol XLNX.◆

40

9

TE

CH

NIC

AL T

RA

ININ

G U

PD

AT

E

Both Schematic- and Synthesis-Based C

lasses Offered

What’s New on

WebLINX

TM

Xilinx H

ome P

age•

ww

w.xilinx.com

WebLIN

X was recently nam

edan Infoworld HotSite!

Here are a few

ofthe reasons w

hy:

◆Sm

artSearch TM Agents Released

Com

e visit the industry-wide search en-

gine made specifically for topics involv-

ing programm

able logic. You can createyour ow

n agents to notify you by e-mail

as material you w

ant becomes available

in any of multiple sites on the w

eb.

◆Xilinx G

uided TourC

heck out this on-line company and

product overview covering topics such as

Xilinx corporate and product strategies,device selection, XAC

Tstep TM software

solutions, quality assurance and Xilinxtechnical support services.

◆Product SpotlightsExam

ine a showcase of our latest prod-

ucts, currently featuring the XC4000EX

and XC9500 device fam

ilies and theFoundation Series softw

are, with its

easy-to-use, low-cost VH

DL synthesis

solution.

◆O

n-Line Net Sem

inarsIn cooperation w

ith Marshall Industries,

Xilinx holds live seminars on the

Internet, complete w

ith an on-line slideand audio presentation and a live chat-response forum

for asking questions.R

ecorded seminars on the XC

5200 andXC

9500 device families also are avail-

able to review at your convenience.

◆

Tw

o basic classes are available fromXilinx, a

schematic-based and a synthe-

sis-based class.Actually, both classes focus m

ore onoverall design m

ethodologies for usingXilinx devices, rather than the specificfront-end tools. (The tutorials shipped w

iththe developm

ent systems provide the

specific tool training for the new user.)

The schematic-based class has traditionally

utilized ViewLogic tools in the exam

plesand labs. H

owever, w

ith the introductionof XAC

Tstep version 6.0.1, the class hasbeen updated to use the Foundation

TM

Developm

ent System and its front-end

tools from Aldec.

The synthesis-based class uses theSynopsys tools. The course goes beyond

explaining and demonstrating the basic

concepts behind HD

L-based design byexam

ining many of the specific language

constructs that should be used when de-

signing with these tools.

All designers can benefit from taking

one of these classes. Even designers al-ready fam

iliar with Xilinx technology can

learn some new

methods to reduce design

time and increase device perform

ance.R

emem

ber, either class (and even cus-tom

ized classes) can be presented right atyour ow

n facility. Please contact your localSales office or our training registrar w

ithyour needs. The latest schedule of classesand contact inform

ation is always available

on WebLIN

X, our World W

ide Web site

(ww

w.xilinx.com

). ◆

XILI

NX IN

DIVI

DUAL

PRO

DUCT

SXI

LINX

PAC

KAG

ESXILINX RELEASED SOFTWARE STATUS-AUGUST 1996

XILINX PART CURRENT VERSION BY PLATFORM LAST PREVIOUSPRODUCT PRODUCT PRODUCT REFERENCE PC1 SN2 HP7 UPDT VERSION NOTES/

KEY CATEGORY DESCRIPTION FUNCTION NUMBER 6.2 4.1.X 9.01 COMP RELEASE FEATURES

CORE XEPLD XC7K Support Core Implementation DS-550-xxx 6.01 5.2.1 5.2.1 7/96 5.2/6.0 PC update by request onlyXABEL-CPLD XC7K, XC9500 Support Entry/Simulation/Core DS-571-PC1 6.11 7/96 6.10 New version w/XC9500; First ship 4/29/96XACT-CPLD XC7K, XC9500 Support Core + Interface DS-560-xxx 6.0.1 6.0.1 6.0.1 7/96 6.0Mentor 8.4=A.4 Interface and Libraries DS-344-xxx 5.2.1 5.2.1 7/96 5.20OrCAD Interface and Libraries DS-35-PC1 6.0.1 7/96 6.0 Support for SDT+, VST+ v1.2Synopsys Interface and Libraries DS-401-xxx 5.2.1 5.2.1 7/96 5.20 Includes XC5200 X-BLOX SupportViewlogic PROcapture Interface and Libraries DS-390-PC1 6.0.1 7/96 5.2/6.0 Includes PRO Series 6.1Viewlogic PROsim Interface and Libraries DS-290-PC1 6.0.1 7/96 6.0 Includes PRO Series 6.1Viewlogic Interface and Libraries DS-391-xxx 6.0.1 5.2.1 5.2.1 7/96 6.0XABEL Entry,Simulation,Lib, Optimizer DS-371-xxx 6.0.1 5.2.1 5.2.1 7/96 5.2/6.0 Now available on HP7XBLOX Module Generator & Optimizer DS-380-xxx 6.0.1 5.2.1 5.2.1 7/96 5.2/6.0

E Verilog 2K,3K,4K,7K Libraries Models & XNF Translator ES-VERILOG-xxx 1.00 1.00 na na Sun and HP

SILICON SUPPORT

2K 3K 4K 5K 7K 9KCadence X X X X X X DS-CDN-STD-xxx 5.2.1 5.2.1 7/96 5.20Mentor X X X X X X DS-MN8-STD-xxx 5.2.1 5.2.1 7/96 5.20Mentor X X X X X X DS-MN8-ADV-xxx 7.00 7.00 na na

U OrCAD X X X X X X DS-OR-BAS-PC1 6.0.1 7/96 6.0 Customer w/v6.0 will receive v6.0.1 updateOrCAD X X X X X X DS-OR-STD-PC1 6.0.1 7/96 6.0Synopsys X X X X X DS-SY-STD-xxx 5.2.1 5.2.1 7/96 5.20 Includes DS-401 v5.2Synopsys X X X X X DS-SY-ADV-xxx 7.00 7.00 na na Includes DS-401 v5.2

U Viewlogic X X X X X X DS-VL-BAS-PC1 6.0.1 7/96 6.0 Customer w/v6.0 will receive v6.0.1 updateViewlogic X X X X X X DS-VL-STD-xxx 6.00 6.0.1 7/96 6.0Viewlogic X X X X X X DS-VL-ADV-xxx 7.00 7.00 7.00 na naViewlogic/S X X X X X X DS-VLS-BAS-PC1 6.0.1 7/96 6.0 Includes PROSeries 6.1Viewlogic/S X X X X X X DS-VLS-STD-PC1 6.0.1 7/96 6.0 Includes PROSeries 6.1Viewlogic/S X X X X X X DS-VLS-EXT-PC1 6.0.1 7/96 6.0 Incl PROSeries 6.1/PROsynth 5.02XViewllogic/S X X X X X X DS-VLS-ADV-PC1 7.00 na na

U 3rd Party Alliance X X X X X X DS-3PA-BAS-xxx 6.0.1 7/96 6.03rd Party Alliance X X X X X X DS-3PA-STD-xxx 6.0.1 5.2.1 5.2.1 7/96 5.2/6.0 Includes 502/550/3803rd Party Alliance X X X X X X DS-3PA-ADV-xxx 7.00 7.00 7.00 na na Includes 502/550/380 & FoundryFoundation Series X X X X X X DS-FND-BAS-PC1 6.0.1 7/96 6.0 Includes support for XC4000E and XC9500Foundation Series X X X X X X DS-FND-BSV-PC1 6.0.1 7/96 6.0 Includes support for XC4000E and XC9500Foundation Series X X X X X X DS-FND-STD-PC1 6.0.1 7/96 6.0 Includes support for XC4000E and XC9500Foundation Series X X X X X X DS-FND-STV-PC1 6.0.1 7/96 6.0 Includes support for XC4000E and XC9500LogiCore-PCI Slave X LC-DI-PCIS-C 1.10 1.10 1.10 na na Target only; Req signed lic agreementLogiCore-PCI Master X LC-DI-PCIM-C 1.10 1.10 1.10 8/96 1.0 Initiator and target; Req signed lic agreementEvaluation X X X X X X DS-EVAL-XXX-C 2.00 2.00 2.00 na na PC, Sun, HP kits now available

with v5.2.1 and v6.0.1

KEY: N=New Product, E= Engineering software for in-warranty users by request only, U= Update by request only,PR = Pre-release requiring in-warranty status or Product Marketing apporval

41

8

Xilinx Helps Fund New Seiko-Epson Foundryour com

petitive position and allow us to

design products with ever higher densities

and faster performance, “ stated Xilinx

Chief Executive O

fficer Willem

Roelandts.

“Just as important, it w

ill help us meet

growing custom

er demand w

orldwide for

our products into the next century.”This investm

ent agreement further

strengthens the close relationship between

Xilinx and Seiko-Epson; Seiko-Epson hasbeen a supplier to Xilinx for m

ore than adecade. Xilinx also w

ill maintain its exist-

ing foundry partnerships with Yam

aha,Taiw

an Semiconductor M

anufacturingC

ompany (TSM

C), U

nited Microelectronics

Corporation (U

MC

) and IC W

orks. Asreported in XC

ell #20, Xilinx owns a 25%

equity stake in a new foundry being con-

structed by UM

C in Taiw

an and scheduledto com

e on-line in the first half of 1997. ◆

New Data Book Now Availablefiles) and its installer are included on theC

D-R

OM

. The main table of contents,

chapter tables of contents and the index allinclude hypertext links to im

mediately

jump to the appropriate pages in the book.At 900 pages, the data book includes

data sheets for the XC7300, XC

9500,XC

3000A/L, XC3100A/L, XC

4000E,XC

4000EX/XL, XC5200, XC

6200, andXC

1700D device fam

ilies. Product specifi-cations for the older XC

2000, XC3000,

XC3100, and XC

4000/A/H/D

/L families are

not included, but are still available onW

ebLINX. The m

ilitary/high-reliability andH

ardWire TM

product lines are overviewed,

but detailed product specifications are stillfound in separate, dedicated docum

ents.To obtain a copy, contact your local

Xilinx sales representative. ◆

WHITE=changed since last issue; 1736A, 1765 and 17128 columns eliminated since last issue

PROGRAMMER SUPPORT FOR XILINX XC1700 SERIAL PROMS-AUGUST 1996XC1718DXC1736D XC1718L XC17128D XC17128L

MANUFACTURER MODEL XC1765D XC1765L XC17256D XC17256LLINK COMPUTER GRAPHICS CLK-3100 V5.61 V5.61LOGICAL DEVICES ALLPRO-40

ALLPRO-88 V2.7 V2.7ALLPRO-88XR V2.7 V2.7ALLPRO-96 6.5.10 6.5.10 6.5.10 6.5.10CHIPMASTER 2000 V2.4U V2.4UCHIPMASTER 6000 V1.31A Aug-96 V1.31A Aug-96XPRO-1 SPROM.310 SPROM.310 SPROM.310 SPROM.310

MQP ELECTRONICS MODEL 200 6.46 6.46 6.46SYSTEM 2000 2.25 2.25 2.25PIN-MASTER 48 Aug-96 Aug-96 Aug-96

MICRO PROSS ROM 5000 B 3Q96 3Q96ROM 3000 U 3Q96 3Q96ROM9000 3Q96

NEEDHAM’S ELECTRONICS EMP20 V3.10 V3.10RED SQUARE IQ-180

IQ-280Uniwriter 40Chipmaster 5000

SMS Expert 3Q96 3Q96Optima 3Q96 3Q96Multisyte 3Q96 3Q96Sprint Plus48 3Q96

STAG Eclipse 6.5.10 6.5.10 6.5.10 6.5.10Quasar

SUNRISE T-10 UDP Aug-96 Aug-96T-10 ULC Aug-96 Aug-96

SUNSHINE POWER-100 Aug-96 Aug-96EXPRO-60/80 Aug-96 Aug-96

SYSTEM GENERAL TURPRO-1 V2.26H V2.26H V2.26HTURPRO-1 F/X V2.26H V2.26H V2.26HTURPRO-1 T/XAPRO V1.24MULTI-APRO V1.16 V1.16 V1.16 V1.16

TRIBAL MICROSYSTEMS TUP-300 Aug-96 Aug-96 Aug-96 Aug-96TUP-400 Aug-96 Aug-96 Aug-96 Aug-96FLEX-700 Aug-96 Aug-96 Aug-96 Aug-96

XELTEK SuperPROSuperPRO II 2.4B 2.4B 2.4B 2.4BSuperPRO II/P 2.4B 2.4B 2.4B 2.4B

XILINX HW-112 5.00 5.00 5.00HW-130 2.01 2.01 2.01 1.00

Xilinx has announced its funding of

up to $300 million for the construction of a

new sem

iconductor manufacturing facility.

The facility will be built and operated by

Seiko-Epson Corp. in Sakata, Japan (about

200 miles north of Tokyo). Xilinx w

illm

ake incremental advance paym

ents overthe next tw

o and one-half years to helpfinance construction of the facility. Inreturn, Xilinx w

ill receive a specified num-

ber of wafers from

the new line through

the year 2002.The new

operation will m

anufacture 8"w

afers using advanced 0.35 to 0.25 micron

CM

OS technology. In tim

e, these advancedprocesses w

ill enable the development of

programm

able logic devices with capacities

reaching 500,000 gates. Production at thefacility is expected to begin in early 1998.

“We’re confident that our continuing

partnership with Seiko-Epson w

ill enhance

Both C

D-R

OM

and printed versions ofthe new

“Xilinx Programm

able Logic Data

Book” are now available. The m

aterial inthe new

data book also is available onW

ebLINX

TM, the Xilinx World

Wide W

eb site(w

ww

.xilinx.com), in the

form of individual prod-

uct specifications.The C

D-R

OM

, a firstw

ith this edition, works

with PC

s, Sun worksta-

tions, and HP w

orksta-tions. D

etailed tables ofcontents and the ability to search for

keywords m

akes the CD

-RO

M a valuable

tool. The entire data book resides in asingle “.pdf” file. The Acrobat™

Reader

program (that allow

s users to view .pdf

XC1718DXC1736D XC1718L XC17128D XC17128L

MANUFACTURER MODEL XC1765D XC1765L XC17256D XC17256LADVANTECH PC-UPROG

LABTOOL-48 Aug-96 Aug-96 Aug-96 Aug-96ADVIN PILOT-U24 10.84B 10.84B

PILOT-U28 10.84B 10.84BPILOT-U32 10.84B 10.84BPILOT-U40 10.84B 10.84BPILOT-U84 10.84B 10.84BPILOT-142 10.84B 10.84BPILOT-143 10.84B 10.84BPILOT-144 10.84B 10.84BPILOT-145 10.84B 10.84B

B&C MICROSYSTEMS INC. Proteus-UP40 3.7Q 3.7QBP MICROSYSTEMS CP-1128

EP-1140BP-1200 V3.15 V3.15 V3.15BP-2100 V3.15 V3.15 V3.15

BYTEK 135H-FT/UMTK-1000MTK-2000MTK-4000

DATAMAN DATAMAN-48 V1.30 V1.30 V1.30DATA I/O UniSite Aug-96 Aug-96 Aug-96 Aug-96

2900 Aug-96 Aug-96 Aug-96 Aug-963900 Aug-96 Aug-96 Aug-96 Aug-96AutoSite Aug-96 Aug-96 Aug-96 Aug-96ChipLab Aug-96 Aug-96 Aug-96 Aug-962700 Aug-96 Aug-96 Aug-96 Aug-96

DEUS EX MACHINA XPGM V1.40 V1.40 V1.40 V1.40E E TOOLS ALLMAX/ALLMAX+ V2.4U V2.4U V2.4U

MEGAMAX V1.1E V1.1E V1.1EELAN DIGITAL SYSTEMS 3000-145

5000-1456000 APS 3Q96 3Q96 3Q96

HI-LO SYSTEMS RESEARCH All-03A Aug-96 Aug-96 Aug-96 Aug-96All-07 Aug-96 Aug-96 Aug-96 Aug-96

ICE TECHNOLOGY LTD Micromaster 1000/E V3.17 V3.17 V3.17 V3.17Speedmaster 1000/E V3.17 V3.17 V3.17 V3.17Micromaster LV V3.17 V3.17 V3.17 V3.17LV40 Portable V3.17 V3.17 V3.17 V3.17Speedmaster LV V3.17 V3.17 V3.17 V3.17


42

7

PROGRAMMER SUPPORT FOR XILINX XC7200 CPLDS — AUGUST 1996

WHITE=changed since last issueNote: The XC7236 and XC7272 columns have been eliminated

MANUFACTURER MODEL XC7236A XC7272AADVANTECH PC-UPROG

LabTool-48 V1.31A V1.31AADVIN SYSTEMS Pilot-U40 10.84B 10.84B

Pilot-U84 10.84B 10.84BB&C MICROSYSTEMS INC. Proteus Aug-96 Aug-96BP MICROSYSTEMS BP-1200 3.15 3.15

BP-2100 3.15 3.15DATAMAN DATAMAN-48 V1.30 V1.30DATA I/O UniSite Aug-96 Aug-96

2900 Aug-96 Aug-963900 Aug-96 Aug-96AutoSite Aug-96 Aug-96

DEUS EX MACHINA ENGINEERING XPGM V1.40 V1.40E E TOOLS ALLMAX/ALLMAX+ V2.4U V2.4U

MEGAMAX V1.1E V1.1EELAN DIGITAL SYSTEMS 6000 APS 3Q96 3Q96HI-LO SYSTEMS RESEARCH All-03A V3.09 V3.09

All-07 V3.09 V3.09ICE TECHNOLOGY LTD Micromaster 1000/E V1.1 V1.1

Speedmaster 1000/E V1.1 V1.1Micromaster LV V1.1 V1.1Speedmaster LV V1.1 V1.1


LOGICAL DEVICES ALLPRO-88ALLPRO-88XRALLPROF-96 6.4.26 6.4.26Chipmaster 2000 V2.4U V2.4UChipmaster 6000 V1.31A V1.31AXPRO-1

MICROPROSS ROM9000 3Q96 3Q96MQP ELECTRONICS SYSTEM 2000 Aug-96 Aug-96

PIN-MASTER 48 Aug-96 Aug-96NEEDHAM’S ELECTRONICS EMP20 V3.10 V3.10SMS Expert 3Q96 3Q96

Optima 3Q96 3Q96Multisyte 3Q96 3Q96

STAG Eclipse 6.4.26 6.4.26SUNRISE ELECTRONICS T-10 UDP Aug-96 Aug-96

T-10 ULC Aug-96 Aug-96SUNSHINE ELECTRONICS POWER-100 Aug-96 Aug-96

EXPRO-60/80 Aug-96 Aug-96SYSTEM GENERAL TURPRO-1/FX Aug-96 Aug-96

MULTI-APRO Aug-96 Aug-96TRIBAL MICROSYSTEMS TUP-300 V3.09 V3.09

TUP-400 V3.09 V3.09FLEX-700 V3.09 V3.09

XELTEK SUPERPROSUPERPRO II 2.4B 2.4BSUPERPRO II/P 2.4B 2.4B

XILINX HW-130 1.14 1.04

performance level that was easily reachedusing timing constraints and automaticplacement and routing tools.

To further reduce hardware costs duringvolume production of the codecs, the XC4010FPGA designs were frozen and converted intoHardWireTM XC4310 devices. Since the Hard-Wire devices are pin and function compatiblewith the FPGAs that they replace, systemflexibility is maintained; the HardWire devicescan be replaced with newly-designed FPGAsif the design evolves at a later date. Accordingto Richard McCandless, Project Leader at GPT

Video Systems, “The HardWire conversionwent extremely well, with very little engi-neering effort required at all, and theycame in on time! In fact, it surprised ushow little engineering effort was needed.”

As noted by McCandless, “These videointerface designs were fairly complex, butthe FPGAs proved to be very flexible andeasy to work with. The high level of inte-gration provided by the FPGA devices hashelped to create the most user-friendlygraphical user interface in the video-conferencing industry.”◆

Video Processing With XC7300 CPLDsBICOM, Inc., (Monroe, CT) is a provider of hard-

ware and software “building blocks” for developing awide range of voice processing applications.BICOM’s products are used in the develop-ment of systems for voice mail, interactivevoice response, audiotex, dictation and callcenter management.

The recent design of their new Geminiseries of high-density computer telephonyplatforms required a high-performance CPLD to integratea variety of logic functions. With cost and ease-of-useconsiderations in mind, the XilinxXC7300TM CPLD family was chosen.

The voice processing boardcontains 14 XC7336 devices.The XC7336-5 CPLDs are usedto hold a variety of logic functions, in-cluding address decoders, state machines, I/O func-tions and glue logic, with XC7336-15 CPLDs for the com-

plicated timing associated withthe telecommunications channel.If BICOM had used traditionalPALs for these logic functions,the design would have encom-

passed two boards rather than one.The design was entered and implemented on a PC

using OrCAD schematic entry tools. The com-plexity of the design (which included a mix ofanalog and digital technologies) and tight devel-opment schedules dictated the use of program-mable devices with predictable performance andgood pin-locking capabilities. The XC7336 CPLDfulfilled both these needs. Pinouts were pre-

assigned and maintained throughout multiple designiterations. This allowed the designers to concentrate onthe more difficult architectural aspects of the design.

As first-time Xilinx users, BICOM engineers wereimpressed with the level of technical support

provided by the Xilinx team.In summary, by

using theXC7300 CPLD

family, BICOMengineers were

able to meet theirperformance needs, reduce design complexity and cost,and save valuable board space as well.◆

GPT

43

6

CUSTOMER SUCCESS STORIES PROGRAMMER SUPPORT FOR XILINX XC7300 CPLDS-AUGUST 1996

WHITE=changed since last issue

GPT Video Systems (Maidenhead,Berks, U.K.) designs and manufactureshigh-quality videoconferencing solutionsunder the brand name FOCUS. GPT VideoSystems is a long time user of Xilinx prod-ucts; its designers use FPGA technology tomaintain the flexibility and rapid time-to-market required in the fast moving multi-media market.

The flexibility of FPGA technologywas evident in the design of the latestFOCUS videoconferencing systems, whereXC4000TM series FPGAs were used for bothprototyping and production applications.

During system proto-typing, three

XC4013devices

wereused to

develop andtest the function-

ality required for alarge ASIC device. Mean-

while, XC4010 FPGAs wereused to implement key data rout-

ing and timing generation functions inthe production version of the video pro-cessing module.

An audio, video and data multiplexerdesign targeted for a semi-custom gatearray implementation was prototyped withthree XC4013 devices. The developmentwas carried out using Cadence Verilogsoftware running on a Sun SparcStation.The FPGAs provided a fast and flexibledevelopment route, culminating in a fully-functional ASIC on the first try. The ASICdevice holds about 30,000 gates of logic,with a 20 MHz system clock rate. Verifyingthe design with the FPGAs saved signifi-cant additional NRE costs and developmenttime that would have been incurred ifchanges to the design had been required

after committing to custom silicon. Further-more, this development route allowed betaversions of the system to be shipped withthe FPGA solution before production vol-umes of the ASIC were available, furtheraccelerating time-to-market.

Three XC4010 FPGAs hold the majorityof the logic in the video processing mod-ule in the main codec design. Two of theFPGAs share a common design and act asvideo routers, passing CCIR601 digitalvideo data from various input sources tothe desired outputs. Each device is de-signed to route data in the form of an 8-bitdata bus, requiring two to be used for the16-bit data in the CCIR601 format. Thus,one device handles the routing and controlof the luminance data, and the otherhandles the chrominance data.

These two devices also perform thetask of overlaying the graphical user inter-face directly onto the video outputs. Thisincludes a patented function that producessemi-transparent video, allowing on-screentext to be displayed in an easily-readableformat while not obscuring the live videobeneath. The design makes specific use ofthe XC4000 architecture’s on-chip RAMcapability to implement fast look-up tables.

The third XC4010 FPGA in the videoprocessing module is a timing generator,providing all the timing functions for thevarious video field store read and writeoperations. This FPGA also contains thestate machines that control the reading andwriting of captured video images to andfrom the graphics frame stores.

The XC4010 designs were entered usinga combination of schematic capture andABEL hardware descriptions and verifiedwith the ViewSim simulator, using aPC-based Viewlogic environment. Allthree FPGAs are about 80% full and runat a system clock speed of 13.5 MHz, a

MANUFACTURER MODEL 7318 7336 7336Q 7354 7372 73108 73144ADVANTECH PC-UPROG

LABTOOL-48 V1.31A V1.31A V1.31A V1.31A V1.31A V1.31AADVIN SYSTEMS PILOT-U40 10.84B 10.84B 10.84B 10.84B

PILOT-U84 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84BB&C MICROSYSTEMS, INC. PROTEUS Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96BP MICROSYSTEMS BP-1200 V3.15 V3.18 V3.15 V3.15 V3.15 V3.15

BP-2100 V3.15 V3.18 V3.15 V3.15 V3.15 V3.15DATAMAN DATAMAN-48 V1.30 V1.30 V1.30 V1.30 V1.30 V1.30DATA I/O 2900 Aug-96 Aug-96 Aug-96 Aug-96

3900/AUTOSITE Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96UNISITE Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96

DEUS EX MACHINAENGINEERING XPGM V1.40 V1.40 V1.40 V1.40 V1.40 V1.40E E TOOLS ALLMAX/ALLMAX+ V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U

MEGAMAX V1.1E V1.1E V1.1E V1.1E V1.1E V1.1EELAN 6000 APS 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96HI-LO SYSTEMS RESEARCH ALL-03A V3.09 V3.09 V3.09 V3.09 V3.09 V3.09

ALL-07 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09ICE TECHNOLOGY LTD Micromaster 1000/E V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V1.1

Speedmaster 1000/E V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V1.1Micromaster Lv V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V1.1Speedmaster Lv V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V1.1

LEAP ELECTRONICS LEAPER-10 V2.0 V2.0 V2.0 V2.0 V2.0 V2.0 V2.0LP U4 V2.0 V2.0 V2.0 V2.0 V2.0 V2.0 V2.0

LOGICAL DEVICES ALLPRO-88ALLPRO-88XRALLPRO-96 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26Chipmaster 2000 V2.4U V2.4U V2.4U V2.4U V2.4U V2.4UChipmaster 6000 V1.31A V1.31A V1.31A V1.31A V1.31A V1.31AXPRO-1 73108.304

MICROPROSS ROM9000 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96MQP ELECTRONICS SYSTEM 2000 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96

PINMASTER 48 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96NEEDHAM’S ELECTRONICS EMP20 V3.10 V3.10 V3.10 V3.10 V3.10 V3.10SMS EXPERT 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96

OPTIMA 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96STAG ECLIPSE 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26SUNRISE T-10 UDP Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96

T-10 ULC Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96SUNSHINE ELECTRONICS POWER-100 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96

EXPRO-60/80 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96SYSTEM GENERAL TURPRO-1/FX Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96

MULTI-APRO Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96TRIBAL MICROSYSTEMS Flex-700 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09

TUP-300 V3.09 V3.09 V3.09 V3.09 V3.09TUP-400 V3.09 V3.09 V3.09 V3.09 V3.09

XELTEK SUPERPROSUPERPRO II 2.4B 2.4B 2.4B 2.4BSUPERPRO II/P 2.4B 2.4B 2.4B 2.4B

XILINX HW-130 1.15 1.15 1.06 1.16 1.07 1.07 1.02

Videoconferencing with XC4000 FPGAs

44

5

Continued from

theprevious page

❝this conference was their first

chance to talk with the early adopters of

reconfigurable computing technology; it is

certain not inconceivable that some cooperative

product development efforts w

ill eventuallyresult from

this meeting. ❞

compliant w

ith Texas Instrument

Modules (TIM

) specifications and aresupported by a library of com

mon D

SPfunctions. M

iroTech has signed an OEM

agreement w

ith a major m

anufacturer ofD

SP boards.

The remaining com

panies at the confer-ence preview

ed products in development.

enVia Inc. (Menlo Park, C

A) is developingconsum

er telecomm

unications equipment

that uses reconfigurable FPGAs to address

the growing problem

of incompatible

wireless telecom

munications standards.

Octree C

orp. (Cupertino, C

A) has imple-

mented 3D

volume rendering system

s onAnnapolis M

icro Systems and G

iga Opera-

tions platforms, and is developing products

for both medical equipm

ent and videogam

e manufacturers. Start-up Adaptive

CAD

Technologies (Sunnyvale, CA) and

consulting firm M

emec D

esign Services(G

arden Valley, CA) also attended, and

are applying RC

technology in some new

application areas (but it’s too early toreveal them

).Another encouraging sign w

as thepresence of representatives from

several ofthe C

AE companies in the Xilinx Alliance

Program. The enorm

ous potential ofreconfigurable com

puting is beginning

to attract the attention of the CAE tool

vendors. For many of these vendors, this

conference was their first chance to talk

with the early adopters of reconfigurable

computing technology; it is certainly not

inconceivable that some cooperative prod-

uct development efforts w

ill eventuallyresult from

this meeting.

In summ

ary, reconfigurable computing

technology is continuing to ‘come of age,’

with several com

panies already garneringrevenue from

a wide variety of R

C-based

products, penetration of RC

technologyinto large, w

ell-known electronic equip-

ment m

anufacturers, and the attentionof leading design tool vendors. I’malready looking forw

ard to nextyear’s conference. ◆

Sharp-eyed readers may notice a slight change to the format of

XCell inthis issue. The tables listing com

ponent availability, Xilinx software status, Alliance

partner information, and device program

mer status have been m

oved from the

“General Inform

ation” section to the last few pages of the new

sletter. As a fewreaders have suggested, this w

ill make the tables easier to find as w

ell as providingfor better continuity for those w

ho read the whole journal front-to-back.

We are alw

ays interested in reader feedback. This issue includes a short readersurvey on page 47. W

e would greatly appreciate if you w

ould take a few m

inutes tofill out this questionnaire and m

ail or FAX it back to us. Alternatively, you can sendyour com

ments directly to m

e via E-mail at brad.faw

[email protected]

. We’re looking

forward to hearing from

you. ◆

2K/3K/ XC CPLD UNI PLATFORMSCOMPANY NAME PRODUCT NAME VERSION FUNCTION DESIGNKIT 4K 5200 7K9K LIB PC SUN RS6000 HP7

Aldec Active-CAD 2.0 Schematic Entry & Simulation & HDL Editor Included ✓ ✓ ✓ ✓ ✓

Cadence Verilog 2.4 Simulation Xilinx Front End ✓ ✓ 7k ✓ ✓ ✓ ✓Concept 2.1 Schematic Entry Xilinx Front End ✓ 7k ✓ ✓ ✓ ✓FPGA Designer 9504 Topdown FPGA Synthesis Call Xilinx ✓ ✓ 7k ✓ ✓ ✓ ✓Synergy 2.3 FPGA Synthesis Call Xilinx ✓ ✓ 7k ✓ ✓ ✓ ✓Composer 4.4 Schematic Entry Xilinx Front End ✓ 7k ✓ ✓ ✓ ✓

Mentor Graphics Autologic B.x Synthesis Xilinx Synthesis Lib. ✓ ✓ 7k ✓ ✓ ✓ ✓Design Architect B.x Schematic Entry Call Xilinx ✓ ✓ 7k ✓ ✓ ✓ ✓QuickSim II B.x Simulation Call Xilinx ✓ ✓ 7k ✓ ✓ ✓ ✓QuickHDL B.x Simulation Call Xilinx ✓ ✓ 7k ✓ ✓ ✓ ✓

OrCAD Simulate (Win) 6.10 Simulation Call Xilinx ✓ ✓ 7k ✓VST 386+ (DOS) 1.2 Simulation Call Xilinx ✓ 7k ✓ ✓Capture (Win) 7.0 Schematic Entry Call Xilinx ✓ ✓ 7k ✓ ✓SDT 386+ (DOS) 1.2 Schematic Entry Call Xilinx ✓ 7k ✓ ✓PLD 386+ (DOS) 2.0 Synthesis Call OrCAD ✓ 7k ✓

Synario Design Automation ABEL 6.2 Synthesis, Simulation XEPLD Fitter ✓ ✓ ✓Synario 2.2 Schematic Entry, Synthesis & Simulation SYN-LCA ✓ ✓ ✓ ✓ ✓

Synopsys FPGA Compiler 3.4b Synthesis Call Xilinx ✓ ✓ ✓ ✓ ✓ ✓ ✓VSS 3.4b Simulation Call Xilinx ✓ ✓ ✓ ✓ ✓ ✓ ✓Design Compiler 3.4b Synthesis Call Xilinx ✓ ✓ ✓ ✓ ✓ ✓ ✓FPGA Express 1.0 Synthesis Call Xilinx ✓ ✓ ✓

Viewlogic WorkView Office 7.1.2/7.2 Schem/Sim/Synth Call Xilinx ✓ XACT6 ✓ ✓ ✓ ✓ ✓ ✓ProSynthesis 5.02 Synthesis Call Xilinx ✓ XACT6 7k ✓ ✓ ✓ ✓ ✓ProSim 6.1 Simulation, Timing Analysis Call Xilinx ✓ XACT6 7k ✓ ✓ ✓ ✓ ✓ProCapture 6.1 Schematic Entry Call Xilinx ✓ XACT6 7k ✓ ✓ ✓ ✓ ✓PowerView 6.0 Schem/Sim/Synth/Timing Anal Call Xilinx ✓ ✓ ✓ ✓ ✓ ✓ ✓

Capilano Computing Design Works 3.1 Schematic Entry/Sim XD-1 ✓ ✓ ✓

Compass Design ASIC Navigator Schematic Entry Xilinx Design Kit ✓ ✓ 7k ✓ ✓Automation X-Syn Synthesis ✓ ✓ ✓

QSim Simulation ✓ ✓ 7k ✓ ✓

Escalade DesignBook 2.0 Design Entry ✓ ✓ ✓ ✓

Exemplar Logic Galileo 3.2 Synthesis/Timing Analysis Simulation Included ✓ ✓ ✓ ✓ ✓ ✓ ✓

IK Technology Co. ISHIZUE PROFESSIONALS 1.05.02 Schematic Entry/Simulation Xilinx Design Kit ✓ ✓ ✓ ✓

IKOS Systems Voyager 2.11 Simulation Xilinx Tool Kit ✓ ✓ ✓

INCASES Engineering GmbH Theda 4.0 Schematic Entry Xilinx Kit ✓ ✓

ISDATA LOG/iC Classic 4.2 Synthesis LCA-PP ✓ 7k ✓ ✓ ✓ ✓LOG/iC2 4.2 Synthesis Simulation Xilinx Mapper ✓ ✓ 7k ✓ ✓ ✓ ✓

Logic Modeling Corp. Smart Model Simulation Models In Smart Model Lib. ✓ ✓ 7k,9k ✓ ✓ ✓ ✓(Synopsis Division) LM1200 Hardware Modeler Xilinx Logic Module ✓ 7k,9k ✓ ✓ ✓

Model Technology V-System/VHDL 4.4j (PC) Simulation ✓ ✓ ✓ ✓ ✓ ✓4.6a (WS)

Protel Technology Advanced Schematic 3.1 Schematic Entry/Client Server Xilinx Interface ✓ 7k ✓

Quad Design Technology Motive 4.3 Timing Analysis XNF2MTV ✓ ✓ ✓ ✓ ✓

SimuCad Silos III 95.100 Simulation Included ✓ ✓ ✓

Sophia Sys & Tech Vanguard 5.31 Schematic Entry Xilinx I/F Kit ✓ ✓ ✓ ✓ ✓

Summit Design Corp. Visual HDL 3.0 Graphical Design Entry/Simulation/Debug EDIF Interface ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓

Synplicity, Inc. Synplify-Lite 2.6a Synthesis Xilinx Mapper ✓ ✓ 9k ✓ ✓ ✓ ✓Synplify 2.6a Synthesis included ✓ ✓ 9k ✓ ✓ ✓ ✓

TopDown Design Solutions V-BAK 1.1 XNF to VHDL translator XNF interface ✓ ✓ ✓ ✓ ✓ ✓

DIA

MO

ND

RU

BY

XILINX ALLIANCE-EDA COMPANIES & PRODUCTS-AUGUST 1996-1 OF 2

4

GU

ES

T ED

ITOR

IAL

Continued from

the previous pageB. The system

-level issues related to ISP(i.e., safe pin states during ISPoperations, describing how

parts cansafely initialize after ISP is com

pleted,etc.) m

ust be addressed.The XC

9500 ISPEN and ISPEX instruc-

tions provide a framew

ork for protectingthe user’s system

during ISP operations.This type of functionality is absolutelycritical for developing a truly w

orkableISP-based system

— Xilinx has it now

.

C. The interchange of inform

ationshould be included as part of the

Products that have already reached them

arketplace include Digital Wings for

Audio from M

etalithic Systems (Sausalito,

CA), satellite ground station com

munica-

tions systems from

TSI Telsys (Colum

bia,M

D), the D

eCypher II ‘G

e-netics Supercom

puting PC’

from Tim

e Logic (InclineVillage, N

V), and the X-CIM

line of DSP acceleration

modules from

MiroTech

Microsystem

s (Saint Laurent,Q

uebec, Canada).

•Available soon in retail

music equipm

ent stores,D

igital Wings is a 128-track

audio authoring system that operates in

the Window

s environment on a PC

(see

XCell #20, page 42). M

etalithic Systems

overall standard. Serial vector format

(SVF), suitably modified, m

ight bestserve as that vehicle.The EZTag softw

are generates SVF filesto describe all XC

9500 ISP operations.

D. The R

UN

-TEST/IDLE state is the

“action” state in which program

ming

or erase latency times are spent.

This is exactly the way XC

9500 partsfunction.

A final report will be m

ade to the 1149.1w

orking group at the International TestC

onference in October. At that tim

e, it will

be decided whether to pursue this as a

separate standard within the 1149 fram

e-w

ork or as an application of the 1149.1standard.

Either way, Xilinx has already equipped

the new XC

9500 family w

ith the industry’sbest JTAG

/ISP capabilities and is spearhead-ing the next generation of program

ming and

testing standards. ◆

THE

FAW

CE

TT

Continued from

page 2

is targeting the ‘music enthusiasts’

market w

ith this product, and isdeveloping a low

er-cost version forthe consum

er market.

•TSI Telsys recently sold several of itssatellite ‘gatew

ay’ systems to N

ASA’sM

arshall Space Flight Center, w

here itw

ill support programs such as the Space

Station project.

•Tim

e Logic’s DeC

ypher II system,

designed for screening DN

A sequencedata, is proving popular w

ith both phar-m

aceutical companies and m

edicalresearch facilities, w

here it outperforms

multi-m

illion-dollar supercomputers.

•M

iroTech Microsystem

s is addressingthe FPG

A-based DSP m

arket. Its DSP

acceleration modules are fully

❝Either way, Xilinx has

already equipped the new XC

9500 family w

iththe industry’s best JTAG

/ISP capabilities and isspearheading the next generation of

programm

ing and testing standards.❞

❝The enormous

potential of reconfigurable

computing is beginning to

attract the attention of the

CAE tool vendors.❞

2K/3K/ XC CPLD UNI PLATFORMSCOMPANY NAME PRODUCT NAME VERSION FUNCTION DESIGNKIT 4K 5200 7K9K LIB PC SUN RS6000 HP7

VEDA DESIGN AUTOMATION INC Vulcan 4.5 Simulation XILINX Tool Kit ✓ ✓ ✓

Veribest Veribest VHDL 14.0 Schematic Entry Xilinx FPGA Design Kit 3k,4k ✓ ✓ ✓ ✓Veribest Verilog 14.0 Simulation Xilinx FPGA Design Kit 3k,4k ✓ ✓ ✓ ✓VeriBest Simulator 14.0 Simulation Xilinx FPGA Design Kit 3k,4k ✓ ✓ ✓ ✓ ✓DMM 14.x Design Management Xilinx FPGA Design Kit 3k,4k ✓ ✓ ✓ ✓ ✓VeriBest Synthesis 14.0 Synthesis Xilinx FPGA Design Kit 3k,4k ✓ ✓ ✓ ✓ ✓Synovation 12.2 Synthesis Xilinx FPGA Design Kit 3k,4k ✓ ✓ ✓ ✓PLDSyn 12.0 Design Entry Synthesis ✓ 7k ✓ ✓ ✓VerBest Design Capture 14.x Design Capture Xilinx FPGA Design Kit 3k,4k ✓ ✓ ✓ ✓ ✓

Accolade Design Automation Peak FPGA Plus 2.2 HDL, Synthesis, Simulation Included ✓ ✓ ✓ ✓ ✓

ACEO Technology, Inc. Asyn 3.3 Synthesis Included ✓ ✓ ✓ ✓ ✓ ✓ ✓Softwire 3.3 Multi-FPGA Partitioning Included ✓ ✓ ✓ ✓ ✓ ✓ ✓Gatran 3.3 ASIC to FPGA Netlist Mapping Included ✓ ✓ ✓ ✓ ✓ ✓ ✓

Acugen Software, Inc. Sharpeye 2.60 Testability Analysis AALCA interface ✓ ✓ 7k ✓ ✓ ✓ATGEN 2.60 Automatic Test Generation AALCA interface ✓ ✓ 7k ✓ ✓ ✓

ALPS LSI Technologies, Inc. Edway Design Systems Synthesis/Simlulation ✓ ✓ ✓

Aptix Corporation System Explorer 2.1 System Emulation Axess 2.Yes ✓

Aptix Corporation ASIC Explorer 2.3 ASIC Emulation Axess 2.3 4K ✓ ✓

Aster Ingenierie S.A. XILLAS 4.1 LASAR model generation Worst Case Simulation ✓ 7k ✓ ✓ ✓

Chronology Corporation TimingDesigner 3.0 Timing Specification and Analysis Included ✓ ✓ 7k,9k ✓ ✓ ✓ ✓QuickBench 1.0 Visual Test Bench Generator Included ✓ ✓ 7k,9k ✓ ✓ ✓ ✓

CINA-Computer SmartViewer 1.0c Schematic XNF Interface ✓ 7k ✓Integrated Network Analysis

Epsilon Design Systems Logic Compressor Synthesis optimization ✓ ✓ ✓ ✓ ✓ ✓

Flynn Systems Probe 3.0 Testability Analysis Xilinx Kit ✓ ✓ 7k ✓FS-ATG 3.0 Test Vector Generation Xilinx Kit ✓ ✓ 7k ✓CKTSIM 3.0 Logic Analysis Xilinx Kit ✓ ✓ 7k ✓FS-SIM 3.0 Simulation Xilinx Kit ✓ ✓ 7k ✓

Fujitsu LSI PROVERD Top-Down Design System Included 3k,4k ✓

Harmonix Corporation PARTHENON 2.3 Synthesis 4k 7k ✓ ✓

MINC PLDesigner-XL 3.3 Synthesis Xilinx Design Module ✓ ✓ ✓ ✓

Teradyne Lasar 6 Simulation Xilinx I/F Kit ✓ ✓ ✓

The Rockland Group One-Hot State Machine Lib. Graphic Design for One-Hot State Machines Xilinx Kit ✓ ✓ ✓ ✓ ✓ ✓ ✓

Tokyo Electron Limited ViewCAD 1.2 FLDL to XNF translator XNFGEN ✓

Trans EDA Limited TransPRO 1.2 Synthesis Xilinx Library ✓ ✓ ✓

Zuken Tsutsuji Synthesis/Simulation XNF Interface 3k,4k ✓ ✓ ✓

Zycad Paradigm RP Rapid Prototyping ✓ ✓ ✓Paradigm XP Gate-level Sim ✓ ✓ ✓

EM

ER

ALD

RU

BY

Alliance Program Categories:Diamond: These partners have strong strategic relationships with Xilinx and havea direct impact on our releases. Typically, Xilinx is directly involved in the devel-opment and testing of the interface to XACTstep software for these products.

Ruby: These partners have a high degree of compatibility andhave repeatedly shown themselves to be significant contribu-tors to our users’ development solutions.Emerald: Proven Xilinx compatibility

XILINX ALLIANCE-EDA COMPANIES & PRODUCTS-AUGUST 1996-2 OF 2

45

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

R

GUEST EDITORIAL

3

46

Xilinx Takes the Lead in ISPStandardization EffortBy NEIL G. JACOBSON ◆ Manager, JTAG Research & Development

In-system programming (ISP) allows users to program and re-program partsthat are already soldered on a system board to facilitate prototyping, streamlinemanufacturing flows and enable remote system updating.

As ISP proliferates, end-users are strained by the difficulty of finding thirdparty applications solutions that address the system-level issues for the widevariety of ISP parts available. In addition, their own test and diagnostic softwaredevelopment costs escalate as new devices come on-line, requiring extensiveprogramming algorithm re-work.

At the last IEEE 1149.1 (JTAG) working group meeting, it was recognizedthat the use of the 4-pin 1149.1 test access port (TAP) as the platform for ISPdevelopment is becoming a de facto standard among most PLD manufacturers.(For example, XC9500 family CPLDs are always programmed through the TAP, andXC4000 series FPGAs optionally can be programmed through the TAP). The workinggroup chose to take a active role in bringing an ISP extension to 1149.1 under itspurview, with Xilinx taking the lead in this effort.

Xilinx and Hewlett Packard organized a meeting of more than 30 participantsfrom about 20 companies. This first ‘study group’ meeting was held on April 19 atHewlett Packard’s Manufacturing Test Division in Loveland, CO.The attendees included PLD manufacturers such as Xilinx, Altera,Lattice, AMD, Cypress and IBM; third-party tool manufacturerssuch as Asset Intertech, Corelis, Intellitech and APG Test Con-sultants; automatic test equipment manufacturers such as HP,GenRad and Teradyne; and ISP end-users such as Cisco Systemsand HP.

There was broad agreement that the value of standardizationwas great. Immediate applications could be envisioned in fieldsas diverse as emulation technologies and remote field test anddiagnostics. The vendor approaches to ISP were close enough toone another for the development of a standard approach to bemeaningful. General consensus seems to be forming in thefollowing areas:

A. The IDCODE and USERCODE registers are a vital part of any ISP device andwill probably be made mandatory.The XC9500 CPLD architecture already includes these optional 1149.1 functions.Indeed, not supporting these part, program content and version identificationinstructions makes ISP impractical since the revision level and contents of a sys-tem would be otherwise unobtainable.

Continued on the next page

❝As ISP proliferates, end-

users are strained by the difficulty

of finding third party applications

solutions that addresss the system-

level issues for the wide variety

of ISP parts available.❞

XILINX ALLIANCE-EDA CONTACTS-AUGUST 1996COMPANY NAME CONTACT NAME PHONE NUMBER E-MAIL ADDRESS

Accolade Design Automation Dave Pellerin (800) 470-2686 [email protected]

ACEO Technology, Inc. Ray Wei (510) 656-2189 [email protected]

Acugen Software, Inc. Nancy Hudson (603) 881-8821

Aldec David Rinehart (702) 456-1222 x12 [email protected]

ALPS LSI Technologies, Inc. David Blagden 441489571562

Alta Group Baruch Deutsch (408) 523-4137 [email protected]

Aptix Corporation Henry Verheyen (408) 428-6209 [email protected]

Aster Ingenierie S.A. Christopher Lotz +33-99537171

Cadence Ann Heilmann (408) 944-7016 [email protected]

Capilano Computing Chris Dewhurst (604) 522-6200 [email protected]

Chronology Corporation MikeMcClure (206) 869-4227 x116 [email protected]

CINA-Computer Integrated Network Analysis Brad Ashmore (415) 940-1723 [email protected]

Compass Design Automation Marcia Murray (408) 474-5002

Epsilon Design Systems, Inc. Cuong Do (408) 934-1536 [email protected]

Escalade Rod Dudzinski (408) 654-1651

Exemplar Logic Shubha Shukla (510) 337-3741 [email protected]

Flynn Systems Matt Van Wagner (603) 598-4444 [email protected]

Fujitsu LSI Masato Tsuru +81-4-4812-8043

Harmonix Corporation Shigeaki Hakusui (617) 935-8335

IK Technology Co. Tsutomu Someya +81-3-3839-0606 [email protected]

IKOS Systems Brad Roberts (408) 366-8509 [email protected]

INCASES Engineering GmbH Christian Kerscher +49-89-839910 [email protected]

ISDATA Ralph Remme +49-72-1751087 [email protected]

ITS Frank Meunier (508) 897-0028

Logic Modeling Corp. (Synopsis Division) Marnie McCollow (503) 531-2412 [email protected]

Logical Devices David Mot (303) 279-6868 x209

Mentor Graphics Sam Picken (503) 685-1298 [email protected]

MINC Kevin Bush (719) 590-1155

Minelec Marketing Department +32-02-4603175

Model Technology Greg Seltzer (503) 526-5465 [email protected]

OrCAD Mike Jingozian (503) 671-9500 [email protected]

Protel Technology Luise Markham (408) 243-8143

Quad Design Technology, Inc. Britta Sullivan (805) 988-8250

SimuCad Richard Jones (510) 487-9700 [email protected]

Sophia Sys & Tech Tom Tilbon (408) 232-4764

Summit Design Corporation Ed Sinclair (503) 643-9281

Synario Design Automation Jacquelin Taylor (206) 867-6257 [email protected]

Synopsys Lynn Fiance (415) 694-4289 [email protected]

Synplicity, Inc. Alisa Yaffa (415) 961-4962 [email protected]

Teradyne Mike Jew (617) 422-3753 [email protected]

The Rockland Group Rocky Awalt (916) 622-7935 [email protected]

Tokyo Electron Limited Shige Ohtani +81-3-334-08198 [email protected]

TopDown Design Solutions Art Pisani (603) 888-8811

Trans EDA Limited James Douglas +44-703-255118

VEDA DESIGN AUTOMATION INC Kathie O’Toole (408) 496-4515

Veribest Loren Lacy (303) 581-2330 [email protected]

Viewlogic John Dube (508) 480-0881 [email protected]

Visual Software Solutions, Inc. Andy Bloom (305) 423-8448

Zuken Makato Ikeda +81-4-594-27787

Zycad Mike Hannig (201) 989-2900

Inquiries about the Xilinx Alliance Program can be e-mailed to [email protected].

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

○○

FROM THE FAWCETT

Reconfigurable Computing:

Coming of AgeBy BRADLY FAWCETT ◆◆◆◆◆ Editor

R

XCELLPlease direct all inquiries,comments and submissions to:

Editor: Bradly Fawcett

Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124Phone: 408-879-5097FAX: 408-879-4676E-Mail: [email protected]

©1996 Xilinx Inc.All rights reserved.

XCELL is published quarterly forcustomers of Xilinx, Inc. Xilinx, theXilinx logo and XACT are registeredtrademarks; all XC-designatedproducts, HardWire, FoundationSeries, and XACTstep are trademarks;and “The Programmable LogicCompany” is a service mark of Xilinx,Inc. All other trademarks are theproperty of their respective owners.

2

47

Continued on page 4

This past June, Xilinx held its firstReconfigurable Computing Developer’s

Program Conference at ahotel in Santa Clara, notfar from company head-quarters. Planned to bean annual event, theconference broughttogether representativesfrom 11 of the more than20 companies that areparticipants in theDeveloper’s Program.

The Reconfigurable Computing (RC)Developer’s Program was founded inmid-1995 to proactively spur commercialdevelopment of reconfigurable computingapplications and products (see XCell #19,page 35). The program is designed to aidcommercial companies through technical,marketing and, insome cases, finan-cial assistance.In this context,reconfigurablecomputing isloosely defined asthe practice ofusing in-system-configurableFPGAs as computing elements to acceler-ate operations in general-purpose comput-ers. In these systems, FPGAs are reconfig-ured during system operation to perform avariety of operations directly in hardware,off-loading the host processor and dramati-cally increasing system performance.

Each company attending the meetinggave a short presentation about the prod-ucts it has developed or is developing.Several companies brought demonstration

systems to the meeting. The conferencewas an ideal forum for letting representa-tives of the member companies interactwith Xilinx R&D personnel and each other.

The conference provided some valuableinsights into the nature of the nascent butgrowing market for RC-based products.Among this small sampling, there weretwo main business models. Some compa-nies specialize in providing hardwareand software tools to OEM accounts thatdevelop their own products, while othermember companies are focused on theirown specific end applications.

The first category includes AnnapolisMicro Systems (Annapolis, MD), VirtualComputer Corp. (Reseda, CA), and GigaOperations (Berkeley, CA). All are makingsignificant strides in the development ofRC-based hardware platforms and soft-

ware tools. Oneof the mostinteresting as-pects of theirpresentationswas the mentionof the types oflarge corporateOEM accountsthat are using or

evaluating those products — names likeBoeing, Ericsson, Loral, NTT, Delco,E-Systems and TRW.

Other companies are using RC-basedsystems in their end products to tackle awide variety of high-performance comput-ing tasks, ranging from satellite communi-cations to automated searches of DNAsequences to 3-D graphic rendering forvideo games.

❝The conferenceprovided some valuable insightsinto the nature of the nascentbut growing market for RC-

based products.❞

Dear Reader,XCell is intended to provide you, our users, with the latestinformation about Xilinx products and their applications. Inthis issue, we’d like to get your feedback on the effective-ness of this publication. By answering the following ques-tions, you’ll help us determine which articles are the mostuseful to you. In addition, we’d like your suggestions on howto improve the distribution of the XCell newsletter. Our goalis to make XCell a source of information to help you get themost out of Xilinx products and services.

After marking your choices, please tearoff or copy the page and send it to:

6. How would you rank the usefulness of the categories ofinformation in XCell listed below?(circle one; 1=not useful at all; 5=extremely useful)

Not VeryGENERAL FEATURES useful useful

From The Fawcett: 1 2 3 4 5Editorial comments on issues of significancein the programmable logic industry.

Guest editorial: 1 2 3 4 5Xilinx senior staff members highlightthe companies strategies and directions.

Customer success story: 1 2 3 4 5Applications that currently use Xilinx products.

General interest features: 1 2 3 4 5Updates on new product literature,technical conferences, financial status

Not VeryPRODUCT INFORMATION useful useful

Components: 1 2 3 4 5New product introductions, new speed grades, etc.

Development systems: 1 2 3 4 5Additions to our development system product line.

Design hints and issues 1 2 3 4 5

Recurring, informational charts 1 2 3 4 5Current availability of components, development systemsand third-party programmers and software.

XCell 3Q96 Reader Survey

Jan HoutsXilinx Inc.2100 Logic DriveSan Jose, CA 95124Fax: 408-879-4676

Of course, any additional comments are welcome.

To: Jan Houts, XilinxFax: 408-879-4676From: _________________________

(optional)

Company: _______________________________

1. Do you read every issue of XCell? ❏ Yes ❏ No

2. How many people read your copy of XCell? __________

2. What amount of time do you generally spend readingan issue of the XCell newsletter?❏ 5-15 min. ❏ 15-30 min. ❏ 30-60 min ❏ Over 1 hour

3. XCell is mainly distributed quarterly as a hard copymagazine. Do you receive it consistently?❏ Yes ❏ No

4. Technology makes other XCell formats possible. Pleaserank these five options according to your preference.(rank most preferred format as 1, second most as 2, etc.)

_______Access via the Xilinx Website_______E-mailed to you_______CD-ROM mailed to you_______Faxed to you_______Hard copy (as it is now)

5. Do you have access to the Xilinx website?❏ Yes ❏ No

✁✁

CU

T HER

E AND

MAIL O

R FAX

✁✁

COMMENTS: _________________________________________________________________________________________________

____________________________________________________________________________________________________________

____________________________________________________________________________________________________________

____________________________________________________________________________________________________________

Issue 22Third Quarter 1996

GENERALFawcett: Reconfigurable Computing ...... 2Guest Editorial ........................................ 3Customer Success Stories

GPT Video Systems ........................ 6-7BICOM .............................................. 7

Xilinx Funds Seiko-Epson Foundry ............ 8New Data Book Now Available ...............8What’s New on WebLINX ........................ 9Training Update .......................................9Financial Results .................................... 10New Product Literature ......................... 10Upcoming Events .................................. 10

PRODUCTSXC5200 Prices Down, Value Up ........... 11XC7300 Best 44-Pin PLD ................... 12-13XC8100 Family Discontinued ................ 13Production Begins for XC4000EX .......... 14Faster -2 Speed Grade for XC4000E ...... 14

DEVELOPMENT SYSTEMSSynopsys’ FPGA Express .................. 15-16LogiCore PCI Initiator Debuts ............... 17Foundation Introduction Successful ...... 17

HINTS & ISSUESXC9500 CPLD Pin-Locking .............. 18-21XC9500 Slew Rate Controls ................. 22Using XC5200 Carry Logic ................ 23-25Advantages of Select-RAM ................26-27Power, Package & Performance ........ 28-29Metastability Recovery in FPGAs ...... 30-31XACTstep on Alternate Systems ............ 32E-Mail Group Monitors Xilinx Products . 33New Technical Support Choices ....... 34-35Questions & Answers ........................ 36-37Component Availability Chart ........... 38-39Development Systems Chart ................. 40Programming Support Charts ............ 41-43Alliance Program Charts .................... 44-46Reader Survey ....................................... 47Fax Response Form ............................... 48

The ProgrammableLogic CompanySM

Inside This Issue:

T H E Q U A R T E R L Y J O U R N A L F O R X I L I N X P R O G R A M M A B L E L O G I C U S E R S

R

40

FAX in Your Comments and SuggestionsTo: Brad Fawcett, XCELL Editor Xilinx Inc. FAX : 408-879-4676

From: ________________________________________ Date: ____________

❏❏❏❏❏ Please add my name to the XCELL mailing list.

NAME

COMPANY

ADDRESS

CITY/STATE/ZIP

PHONE

❏❏❏❏❏ I’m interested in having my company’s design featured in a future edition ofXCELL as a Customer Feature.

Comments and Suggestions:_______________________________________________________

_______________________________________________________________________________

_______________________________________________________________________________

_______________________________________________________________________________

_______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Please use this form to FAX in your comments and suggestions, or to request an addition to theXCELL mailing list. Please feel free to make copies of this form for your colleagues.

U.S. PostagePAID

First ClassPermit No. 2196

San Jose, CA2100 Logic DriveSan Jose, CA 95124-3450

FAX RESPONSE FORM-XCELL 22 3Q96 XCELLCorporateHeadquartersXilinx, Inc.2100 Logic DriveSan Jose, CA 95124Tel: 408-559-7778Fax: 408-559-7114

EuropeXilinx, Ltd.Suite 1B, Cobb HouseOyster LaneByfleetSurrey KT147DUUnited KingdomTel: 44-1-932-349401Fax: 44-1-932-349499

JapanXilinx, KKDaini-Nagaoka Bldg. 2F2-8-5, Hatchobori,Chuo-ku, Tokyo 104JapanTel: 81-3-3297-9191Fax: 81-3-3297-9189

Asia PacificXilinx Asia PacificUnit 4312, Tower IIMetroplazaHing Fong RoadKwai Fong, N.T.Hong KongTel: 852-2424-5200Fax: 852-2494-7159

R

PRODUCT INFORMATION

XC5200 FPGAs:Prices Go Down andPerformance Goes Up

Pinlocking & XC9500 CPLDsIn further proof that designers must consider morethan just the expected specifications, XC9500TM CPLDshave proven themselves to be the best choice formaintaining pinouts during design iterations...

See Page 18

Using XC5200 FPGA Carry LogicTips for using this simple, but flexible, feature...

See Page 23

Process improvements and record saleshave helped to knock as much as 50% offthe price on XC5200TM family FPGAs, whileboosting performance by as much as 30%...

See Page 11

DESIGN TIPS & HINTS

Synopsys IntroducesFPGA ExpressAlliance partner Synopsys has built on thestrengths of its FPGA Compiler to create aWindows 95 and NT product that includes allof the hottest new Xilinx products...

See Page 15

NAME Europe THE QUARTERLY JOURNAL FOR XILINX …china.xilinx.com/publications/archives/xcell/Xcell22.pdf · 2. How many people read your copy of XCell? _____ 2. What amount of time

Text of NAME Europe THE QUARTERLY JOURNAL FOR XILINX...

SOLUTIONS FOR A PROGRAMMABLE WORLDjapan.xilinx.com/publications/archives/xcell/Xcell...E640-based embedded system with a Xilinx® Spartan®-6 FPGA PCI Express (PCIe) daughter card

china.xilinx.com · Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Overall

Xcell Journal: Issue 7 - china.xilinx.com · State Machines Using Xilinx ABEL X-BLOX: High-level Schematic Entry 7 AD/ Version 3.20 Now Shipping Integrated Cadence Design Environment

Xcell - Xilinx...ISSUE 58, THIRD QUARTER 2006 XCELL JOURNAL XILINX, INC. R Issue 58 Third Quarter 2006 THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS Xcell …

Xilinx UG130 Spartan-3 FPGA Starter Kit Board User …china.xilinx.com/support/documentation/boards_and_kits/... Spartan-3 FPGA Starter Kit Board User Guide UG130 (v1.2) June 20, 2008

KC705 Si5324 Design - china.xilinx.com

Xcell Journal: Issue 3 - Xilinx · LCA design flow. The Xilinx Design Manager (XDM) is a menu-based interface that "looks and feels" much like the XACT design editor. All programs

ISSUE 43, SUMMER 2002 XCELL JOURNAL XILINX, INC. Cover Story

Xilinx XAPP1127 XPS LL Tri-Mode Ethernet MAC Performance ...china.xilinx.com/support/documentation/application... · Note: MontaVista Linux must be installed and properly configured

Powertool catalogue xcell

Xcell - Xilinx

Xcell Journal Issue 74: Wireless MIMO Sphere Detector ...china.xilinx.com/.../xcell/issue74/wireless-mimo-sphere-detector.pdf · VHDL and Verilog. Recently, new high ... Figure 1

Vivado Design Suite User Guide - china.xilinx.com · Vivado Design Suite 2018.2 Release Notes 8 UG973 (v2018.2) July 23, 2018 Chapter 1: Release Notes 2018.2 Xilinx Embedded Software

Xcell Journal: Issue 3 - University of California, Berkeleyinst.eecs.berkeley.edu/~cs294-59/fa10/resources/Xilinx-history/... · new Design Manager, XDM, will ship in October. Both

FOCUS ON PRODUCT DIFFERENTIATION WITH XILINX …china.xilinx.com/publications/prod_mktg/consumer_prodbrief.pdfSpartan® FPGAs are a low risk solution that offer an optimal balance

Vivado Design Suite Tutorial - china.xilinx.com · This Xilinx® Vivado™ Design Suite tutorial provides designers with an in-depth introduction to the Vivado simulator. The Vivado

Xcell Journal

Xilinx ISE Design Suite 14: Release Notes, Installation, and Licensing (UG631)china.xilinx.com/support/documentation/sw_manuals/xilinx... · 2018-08-03 · ISE Design Suite 14 Release

Demonstration of XCell ATF 2 and XCell ATF 6 Single-use ... · Demonstration of XCell™ ATF 2 and XCell™ ATF 6 Single-use Performance ... on XCell™ ATF SU Units . Test. ... @

Announcing the New Xcell Software Journal · XCELL SOFTWARE JOURNAL MEDIA KIT. 2015-16 Xilinx Partner Rates Full Page – 8.5" x 11" 1X – $2800 2X – $2600 3X – $2400 4X –

PROGRAMMABLE SYSTEMS EDITION Xcell - Xilinx · Avnet Electronics Marketing introduces the EXP speciﬁcation – a versatile expansion interface for FPGA development boards that allows

Xcell - Xilinx · ADVERTISING SALES Dan Teie 1-800-493-5551 TECHNICAL COORDINATOR Larry Caputo INTERNATIONAL Piera Or, Asia Pacific [email protected] Christelle Moraga, Europe

Leveraging Power Leadership at 28 nm with Xilinx 7 …china.xilinx.com/.../white_papers/wp436-Power-Leadership-28nm.pdf · low-power solutions, and best-in-class power tools. The

Xcell - Xilinx · 2019. 10. 14. · Sr. Director, Software Marketing Xilinx, Inc. [email protected] FPGA business dynamics have been rather consistent over the past decade. Price

Xcell Journal Issue 49 - Xilinx · PDF file · 2018-01-10Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx is a ... HDL Bencher, IRL, J Drive, Jbits,

XCell - ZIV

Xcell - Xilinx...Xcell journal TABLE OF CONTENTS 2005, ISSUE 54 VIEWPOINT ハードウェアがソフトウェアに出会うとき SYSTEM PERFORMANCE より高速・よりフレキシブルなエンベデッドシステム

Xcell Journal: Issue 68 - Xilinx · Xcell journal Third Quarter 2009 SOLUTIONS FOR A PROGRAMMABLE WORLD INSIDE Novel PC Architecture Ditches Microprocessor for an FPGA ... a formulation

Video Starter Kit - china.xilinx.com

PROGRAMMABLE SYSTEMS EDITION Xcell - Xilinx · networks, flat-panel displays, mobile phones, global positioning systems, and the Internet, and we arrive at today’s automobile –

Documents

NAME Europe THE QUARTERLY JOURNAL FOR XILINX …china.xilinx.com/publications/archives/xcell/Xcell22.pdf · 2. How many people read your copy of XCell? _____ 2. What amount of time

Text of NAME Europe THE QUARTERLY JOURNAL FOR XILINX...