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Issue 68 Third Quarter 2009 Xcell journal Xcell journal SOLUTIONS FOR A PROGRAMMABLE WORLD SOLUTIONS FOR A PROGRAMMABLE WORLD INSIDE Novel PC Architecture Ditches Microprocessor for an FPGA European Ultrawideband Project Taps Virtex-5 FPGAs Choosing the Right FPGA Gigabit Transceiver is a Matter of Protocol Interpolated Lookup Tables Offer Easy Path to DSP Functions INSIDE Novel PC Architecture Ditches Microprocessor for an FPGA European Ultrawideband Project Taps Virtex-5 FPGAs Choosing the Right FPGA Gigabit Transceiver is a Matter of Protocol Interpolated Lookup Tables Offer Easy Path to DSP Functions www.xilinx.com/xcell/ Accelerate Innovation with Targeted Design Platforms Accelerate Innovation with Targeted Design Platforms

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  • Issue 68Third Quarter 2009

    Xcell journalXcell journalS O L U T I O N S F O R A P R O G R A M M A B L E W O R L DS O L U T I O N S F O R A P R O G R A M M A B L E W O R L D


    Novel PC Architecture DitchesMicroprocessor for an FPGA

    European UltrawidebandProject Taps Virtex-5 FPGAs

    Choosing the Right FPGAGigabit Transceiver is a Matter of Protocol

    Interpolated Lookup TablesOffer Easy Path to DSP Functions


    Novel PC Architecture DitchesMicroprocessor for an FPGA

    European UltrawidebandProject Taps Virtex-5 FPGAs

    Choosing the Right FPGAGigabit Transceiver is a Matter of Protocol

    Interpolated Lookup TablesOffer Easy Path to DSP Functions


    Accelerate Innovation withTargeted Design Platforms

    Accelerate Innovation withTargeted Design Platforms

  • 1 . 8 0 0 . 3 3 2 . 8 6 3 8www.em.avnet.com

    Copyright 2008, Avnet, Inc. All rights reserved. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other brands are the property of their respective owners.Prices and kit configurations shown are subject to change.

    Xilinx Spartan-3A Evaluation Kit

    The Xilinx Spartan-3A Evaluation Kit provides an easy-to-use, low-cost platform for experimenting and prototyping applications based on the Xilinx Spartan-3A FPGA family. Designed as an entry-level kit, first-time FPGA designers will find the boards functionality to be straightforward and practical, while advanced users will appreciate the boards unique features.

    Get Behind the Wheel of the Xilinx Spartan-3A Evaluation Kit and takea quick video tour to see the kit in action (Run time: 7 minutes).

    Ordering InformationPart Number Hardware Resale

    AES-SP3A-EVAL400-G Xilinx Spartan-3A Evaluation Kit $39.00* USD (*Limit 5 per customer)

    Take the quick video tour or purchase this kit at: www.em.avnet.com/spartan3a-evl

    Target ApplicationsGeneral FPGA prototypingMicroBlaze systems Configuration developmentUSB-powered controller Cypress PSoC evaluation

    Key FeaturesXilinx XC3S400A-4FTG256C Spartan-3A FPGA

    Four LEDs Four CapSense switches I 2C temperature sensor Two 6-pin expansion headers 20 x 2, 0.1-inch user I/O header 32 Mb Spansion MirrorBitNOR GL Parallel Flash

    128 Mb Spansion MirrorBit SPI FL Serial Flash

    USB-UART bridge I 2C port SPI and BPI configuration Xilinx JTAG interface FPGA configuration via PSoC

    Kit IncludesXilinx Spartan-3A evaluation board ISE WebPACK 10.1 DVDUSB cableWindows programming application Cypress MiniProg Programming UnitDownloadable documentation and reference designs

  • FASTER THAN THEThe path to true innovation is never a straight line. Only Xilinx programmable silicon,software, IP and 3rd party support gives you the agility to stay ahead of the competition and adapt

    to changing market requirements, without slowing down. So you have the freedom to innovate

    without risk. Find out more about Xilinx Targeted Design Platforms at www.xilinx.com.


    Copyright 2009 Xilinx, Inc. All rights reserved. Xilinx and the Xilinx logo are registered trademarks of Xilinx in the United States and other countries. All other trademarks are property of their respective holders.

  • L E T T E R F R O M T H E P U B L I S H E R

    Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124-3400Phone: 408-559-7778FAX: 408-879-4780www.xilinx.com/xcell/

    2009 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands includedherein are trademarks of Xilinx, Inc. All other trade-marks are the property of their respective owners.

    The articles, information, and other materials includedin this issue are provided solely for the convenience ofour readers. Xilinx makes no warranties, express,implied, statutory, or otherwise, and accepts no liabilitywith respect to any such articles, information, or othermaterials or their use, and any use thereof is solely atthe risk of the user. Any person or entity using suchinformation in any way releases and waives any claim itmight have against Xilinx for any loss, damage, orexpense caused thereby.

    PUBLISHER Mike [email protected]

    EDITOR Jacqueline Damian

    ART DIRECTOR Scott Blair

    DESIGN/PRODUCTION Teie, Gelwicks & Associates1-800-493-5551

    ADVERTISING SALES Dan [email protected]

    INTERNATIONAL Melissa Zhang, Asia [email protected]

    Christelle Moraga, Europe/Middle East/[email protected]

    Yumi Homura, [email protected]

    SUBSCRIPTIONS All Inquirieswww.xcellpublications.com

    REPRINT ORDERS 1-800-493-5551

    Xcell journal


    Golden Age of SemiconductorsPoints to Platinum Era Ahead

    any years ago, one of my former colleagues over at EDN magazine mailed me a copyof Gordon Moores landmark article Cramming More Components onto IntegratedCircuits. It was a reprint of a piece that first appeared in the now-defunct magazineElectronics on April 19, 1965, and Ive kept it at my desk ever since. If youve never

    read the article, do so. Moore opens with the sentence, The future of integrated electronics isthe future of electronics itself, and then goes on to make a slew of brilliant predictions, fore-seeing the inventions of the personal computer, the Internet and the handheld marketfruits ofthe ever-progressing IC.

    Of course, the article is considered a landmark chiefly because Moore goes on to write that thenumber of transistors on an IC will double roughly every year (later amended to every two years),a formulation that Cal Tech professor Carver Mead famously dubbed Moores Law. The semi-conductor and, in turn, electronics industries have soared for the last 44 years paced indisputablyby Moores Law.

    Back in 2005, I had the pleasure of covering a Computer History Museum event for EDNwhere Carver Mead actually interviewed Moore about his law. (You can view the video of their chat at http://www.youtube.com/watch?v=MH6jUSjpr-Q&feature=PlayList&p=6B12A0FACFA35D1F&index=7.) More recently, I witnessed another event of historic importancefor the industry: the induction ceremony of 15 semiconductor giants into the National InventorsHall of Fame (read my pldesignline.com blog coverage at http://www.dspdesignline.com/news/217400639).

    Moore and Mead were among the 15 inductees, but I was really there to honor Xilinx co-founderRoss Freeman, who was also inducted (posthumously) into the Hall of Fame, and to learn more

    about him from his colleagues and family. For those of you who may notbe familiar with the name, Freeman invented the FPGA in 1984 (PatentNo. 4,870,302), only five years before he died prematurely at the age of45. At this fascinating event, I learned that the FPGA probably would nothave been commercialized or grown as successful as it has had Freeman,his co-founders and, ultimately, Xilinxs early investors not wholeheart-edly embraced Moores Law.

    Essentially, Freemans early FPGA circuit wasnt considered the mostefficient use of transistors, but it was inventive and unique. In thosedays, transistors were very expensive to produce. Freemans inventiontraded off transistor minimization and utilization for flexibility, fastturnaround and the convenience of outsourced manufacturing. Back in

    MOnly the beginning of a great new wave of invention built on the IC.

    Xilinx co-founder Ross Freeman

  • Mike SantariniPublisher

    1984, Freeman predicted that as time and Moores Law pro-gressed, FPGAs would keep pace, at least doubling in logic-cellcounts, and that the cost per transistor would decline dramatical-ly, making programmable devices more attractive to a growingnumber of users.

    Just as Moore identified a trend in the cycle of IC manufactur-ing, Freemanalong with fellow co-founders Bernie Vonderschmittand Jim Barnettpinpointed a related economic trend. Namely, ifmanufacturing kept pace with Moores Law by introducing a newprocess technology every two years, the associated costs of build-ing a fab and outfitting it with the latest process equipment would,over time, make owning a fab less feasible for a growing numberof chip companies.

    So, for Xilinxs first production FPGA, the XC2064,Vonderschmitt masterminded a revolutionary deal to have Seikomanufacture the parts. That marked the birth of the fabless model.Today, the vast majority of semiconductor and system companiesno longer manufacture their own ICs, but contract with foundries because, as Ross and Berniepredicted, manufacturing costs have spiraled with each new process introduction.

    The exorbitant cost, which foundries pass on to customers, has now made even fablessproduction of ASICs and ASSPs economically out of reach for an ever-growing number ofdesigners. These engineers are increasingly turning to FPGAs.

    Today, Freemans predictions about the increasing value of FPGAs resonate more stronglythan ever, thanks in part to Xilinxs employees and customers, who have collaborated over theselast two decades to advance FPGA technology in extraordinary ways, helping Xilinx innovateusing the worlds most advanced process technologies. As a result of this ongoing innovation,todays FPGAs contain hundreds of thousand of logic cells and include microprocessorcores, DSP slices and high-speed I/O. FPGAs are gaining broader use every day as designersincreasingly choose them as the means to quickly turn their inventions into reality.

    The spirit of innovation honored at the 2009 Inventors Hall of Fame ceremony wasnt just acelebration of the golden age of semiconductors. It was also a celebration of myriad inventions youdesigners will continue to enable in the future. The last 50 years may have been golden, but thenext 50 could surely be platinum. As Cal Techs Mead graciously put it in his brief acceptancespeech, this is only the beginning

    Ross Freemans mother, Ethel, holds

    the Xilinx co-founders award at

    National Inventors Hall of Fame

    ceremony. Ross brother Fred

    Freeman (right) accepted the

    award on the familys behalf.


    N C



  • C O N T E N T S



    Letter from the Publisher Golden Age of SemiconductorsPoints to Platinum Era Ahead4

    Xpectations Targeted Design Platforms Take FPGA Innovation to New Heights66


    Xcellence in Wired CommunicationsBlade Management Controller Rides FPGA Processor14

    Xcellence in Wireless CommunicationsVirtex-5 Propels Ultrawideband Comms and Ranging22

    Xcellence in Industrial Control FPGA-Powered Platform Controls IndustrialMotors for Maximum Efficiency26

    Xcellence in New ApplicationsEVE Taps Xilinx for Multiple Generations of Emulators32


    Cover StoryTargeted Design Platforms Put Innovation on Fast Track

  • T H I R D Q U A R T E R 2 0 0 9 , I S S U E 6 8

    Xperts Corner Understanding Timing Parametersin Xilinx System Generator36

    Xplanation: FPGA 101 The Right FPGA GigabitTransceiver Makes All the Difference41

    Xperiment: FPGA Anchors Innovative General-Purpose PC48

    Ask FAE-X Interpolated Lookup Tables: SimpleWay to Implement a DSP Function54

    Profiles of Xcellence Dick Corey Has theEngineering Bug64






    Are You Xperienced? Sign up today for X-fest60

    Xamples A mix of new and popular application notes62

  • by Mike SantariniPublisher, Xcell JournalXilinx, [email protected]

    When Moshe Gavrielov joined Xilinx in 2008as the companys new president and CEO, hebrought with him decades of knowledge as asemiconductor executive and designer of ICs,and the aggregate perspective that many eco-nomic realities are converging to make pro-grammability an imperative for a greaternumber of electronic end products.

    Prior to joining Xilinx, Gavrielov managedLSI Logics ASIC group for many years beforemoving on to serve as the CEO for EDA firmVerisity. During his years in the business, he haswitnessed firsthand the rise in both IC designcomplexity and cost of manufacturing, in tan-dem with ever-tighter development budgets ascompanies strive to rapidly address new mar-kets and evolving standards.

    8 Xcell Journal Third Quarter 2009

    Targeted Design Platforms Put Innovation on Fast TrackTargeted Design Platforms Put Innovation on Fast TrackXilinx pioneers cutting-edge infrastructure for its latest FPGAs, the Spartan-6 and Virtex-6.Xilinx pioneers cutting-edge infrastructure for its latest FPGAs, the Spartan-6 and Virtex-6.


  • Gavrielov concluded that these converg-ing factors would present Xilinx with amajor opportunity for growth. Thatsbecause FPGAs dont burden the users withmanufacturing costs. Also, the devices arereprogrammable and, thus, inherently flex-ible and forgiving of design errors.

    However, to really seize the opportunity,Xilinx not only has to provide customerswith the best FPGAs in the industry, butmust complement that silicon with world-class tools, intellectual property (IP) thats

    easy to integrate, evaluation kits, services,helpful documentation and targeted refer-ence designs. Each part of the puzzle is nec-essary to facilitate customers getting theirinnovations to market quickly.

    To turn Gavrielovs vision into a reality,the hard-working employees of Xilinx andits partners put their heads together toengineer the Xilinx Targeted DesignPlatform approach, which streamlines theFPGA design process for all users, fromnovice to expert.

    leverage to create innovations for an ever-growing number of applications, saidGavrielov. All told, the opportunity is ripefor Xilinx to more rapidly take marketshare away from ASICs and ASSPs andassume a more central role at the heart ofnext-generation electronic innovations.Targeted Design Platforms will facilitatethe FPGA development process for ourgrowing user base, so designers can get themost out of our FPGAs and can get theirinnovations to market faster.

    At the foundation layer of the pyramidis the Base Targeted Design Platform,which Xilinx made available in June of thisyear, following the February 2009 launchof the Virtex-6 (http://www.xilinx.com/products/virtex6/index.htm) and Spartan-6(http://www.xilinx.com/products/spartan6/index.htm) FPGA families. In April, thecompany released its ISE Design SuiteEdition 11 in support of the Targeted DesignPlatforms (http://www.xilinx.com/support/documentation/white_papers/wp307.pdf).

    The Xilinx Targeted Design PlatformTo communicate this approach, Xilinxrepresents the strategy as a pyramid con-sisting of four layers: the Base TargetedDesign Platform, the Domain-SpecificPlatform and the Market-SpecificPlatform, topped off with the capstone ofuser differentiation (Figure 1). Users canautomate a greater percentage of themore-basic parts of their designs byadding, at their discretion, upcomingXilinx domain-specific and market-spe-

    cific platform offerings to the BaseTargeted Design Platform. The approachwill enable them to get products to mar-ket fast, and focus the majority of theirdesign cycles on the elements that willreally differentiate those products.

    Today, our high-performance Virtex-6 and high-volume Spartan-6 FPGAsboast several hundreds of thousands of pro-grammable logic cells, up to 11.2-Gbit/sec-ond transceivers, 38 Mbits of block RAMand 2,000 DSP slices that designers can

    Third Quarter 2009 Xcell Journal 9

    Targeted Design Platforms will facilitate the FPGA development process for ourgrowing user base, says Xilinx CEO Moshe Gavrielov, so designers can get the

    most out of our FPGAs and can get their innovations to market faster.


    Base Platform








    Communication Video AVBMarket-Specific IP, Custom Tools, Custom Boards

    Focus on Differentiation

    Embedded DSP ConnectivityDomain IP, Domain Tools, FMC Daughter Cards

    Virtex SpartanBase IP, ISE Program, Base Boards

    Figure 1 The Xilinx Targeted Design Platform squarely aims at increased user productivity.

  • The June launch announced first deliveryof the of the Base Targeted Design Platformfor Virtex-6 and Spartan-6 FPGAs in theform of evaluation kits that combine all theelements customers need to realize the ben-efits this new platform approach promises.These evaluation kits combine the latest ISEDesign Suite 11.2 with Virtex-6 LX240Tand Spartan-6 LX16 FPGA evaluationboards, preverified base IP, base platformreference designs and a complete set of doc-umentation that guides customers throughthe entire process, from setting up the hard-ware to installing software and beginningtheir design. (See www.xilinx.com/products/targeted_design_platforms.htm.)

    The release of the Base TargetedDesign Platform means that Virtex-6 andSpartan-6 are now open for business, saidBrent Przybus, director of product market-ing. Customers can now download ISEDesign Suite 11.2, order base evaluationkits for Spartan-6 and Virtex-6 FPGAs,and access comprehensive documentationto begin developing designs.

    The Targeted Design Platform MethodologyWith the Targeted Design Platformmethodology, Xilinx users will start theirprojects with the Base Targeted DesignPlatform, gaining access to basic functionscommon in almost all applications. Then,depending on the design domain in whichthey typically worklogic designer, DSP,embedded-software programmer or sys-

    tems engineerthey can add XilinxDomain-Specific kits of their choice to theBase Targeted Design Platform.

    These kits will provide domain-specifictools (available in ISE Design Suite 11Editions), along with libraries of preverifieddomain-specific IP from Xilinx and key IPpartners as well as domain-specific daughtercards. Designers can plug the cards intotheir Base Targeted Design platform evalua-tion boards by means of an FPGAMezzanine Connector (FMC) on the baseplatform evaluation boards to more quicklyimplement their designs (see sidebar, page12). Each Domain-Specific kit will alsoinclude targeted reference designs to helpusers quickly implement a greater numberof functions in their designs.

    In addition to these Domain-Specifickits, Xilinx and its partners are also develop-ing Market-Specific Platforms, which willallow users to attach daughter cards gearedfor specific market segments to the base plat-form via the FMC connection, or to accessmarket-specific boards. Each of the individ-ual market-specific kits will likewise includepreverified IP and reference designs to helpusers quickly add functions to their designs.

    Przybus said that the more elements ofthe Targeted Design Platform users add, thefaster they will complete their designs. Bysimply leveraging all thats available in thebase platform, he said, users could conceiv-ably implement up to 25 percent of theiroverall project, saving valuable time in

    which to develop the rest of their design.And if they leverage the domain-specific kitstoo, they should be able to quickly imple-ment as much as 50 percent of their design.Going a step further and using the market-specific kits, designers could quickly imple-ment up to 75 percent of their designs,Przybus said, freeing them to focus on the 25percent of the design that will bring thegreatest differentiation to the end products.

    Przybus notes that some users may wantto design their entire FPGA implementationfrom scratch, and they still can do so if theywish. But he believes a vast majority will wel-come the great benefits of leveraging all theelements of the Targeted Design Platform.

    Targeting Your Needs Przybus explains that Xilinx created TargetedDesign Platforms to help every category ofcustomer, from FPGA design experts whohave used programmable devices religiouslyfor many years; to ramping designers whomay have traditionally focused on ASIC andASSP designs but have started to transitionthe bulk of their efforts to FPGAs; all theway to novices who have never used FPGAsbefore but have traditionally targeted ASICs,or perhaps only have experience program-ming standalone processors.

    With Targeted Design Platforms,Przybus said, Xilinx is giving the novices notonly the FPGAs, IP and tools they will needto quickly start designing, but also referencedesigns to help them build their products.

    10 Xcell Journal Third Quarter 2009





    Board Power

    USB Download



    1 9




    12 11


    # Feature

    1 DDR2

    2 SPI x4, x1, Ext. x4 Configuration

    3 SPI Header

    4 Parallel Flash

    5 10/100/1000 Ethernet

    6 USB UART

    7 IIC

    8 Clock, Socket, SMA

    9 FMC LPC connector

    10 LED

    11 DIP Switch

    12 Pushbutton

    13 USB JTAG

    14 12-pin (8 I/O) Header

    15 VCCint Voltage Selection Header


    Figure 2 The Spartan-6 SP601 Evaluation Kits board features a rich set of system functions.

  • Third Quarter 2009 Xcell Journal 11

    They can take these reference designs andadd their own content to create differentiat-ed products, said Przybus. Targeted DesignPlatforms will help novices quickly becomefamiliar with FPGA design, and as theygrow more experienced they can add evengreater amounts of their own differentiation.

    For those already knowledgeable aboutFPGA design and who are escalating theirFPGA design efforts, Przybus said theTargeted Design Platforms will help acceler-ate their development time and get to marketfaster. These groups are typically familiarwith FPGA design, but one of the biggestissues they have is migrating a design, orcomponents of a design, to a new FPGA, hesaid. The Targeted Design Platforms willmake that migration very simple, with refer-ence designs that show how the new featuresare used, as well as useful migration tech-niques. They will be able to see how Xilinxdid it, learn from that example and thenaccelerate their own design efforts.

    Expert FPGA designers are also con-cerned with migrating their designs, but theyare typically more focused on getting maxi-mum performance out of their FPGAs ormaximizing power efficiency, Przybus said.The Targeted Design Platforms will providethese users with examples to help them getthe greatest efficiencies out of their FPGAdesigns, leveraging the new FPGA and toolcapabilities, he said. We are providingthem with a design environment that willallow them to closely monitor power con-sumption to optimize their designs for power

    efficiency, and also implement and analyzemultigigabit transceivers and DSP slices run-ning at their fastest rates. And for the firsttime, we are giving them a whole system-centric design to evaluate those elements.

    The combination, Przybus said, willaccelerate their development time.

    Spartan-6 and Virtex-6 Evaluation KitsA central element of the Base TargetedDesign platform is the evaluation kitspecifically, the Spartan-6 SP601Evaluation Kit and the Virtex-6 ML605Evaluation Kit. Customers can order bothof these new products today.

    Przybus described the Spartan-6 FPGASP601 Evaluation Kit (Figure 2) as a low-cost, entry-level environment for developingconsumer, infotainment, video and othercost- and power-sensitive applications usingthe Spartan-6 LX16 FPGA. The kits sys-tem-level capabilities include DDR2 memo-ry control, flash, Ethernet, general-purposeI/O and UART. The kit include ISE DesignSuite 11.2 WebPACK, reference designs, agetting started demo, board design files,documentation, cables and a power supply.

    Meanwhile, the Virtex-6 FPGA ML605Evaluation Kit (Figure 3) is a scalable envi-ronment for developing system designswith the Virtex-6 LX240T FPGA. Amongother system-level capabilities, the kitincludes high-speed serial transceivers,PCIe Gen2 blocks, a soft DDR3 memo-ry controller, Gigabit Ethernet and DVI. Italso includes the ISE Design Suite 11.2

    Logic Edition, reference designs, a gettingstarted demo, board design files, docu-mentation, cables and a power supply.

    Three Easy Steps to Kick-Start Your DesignPrzybus said that Xilinx designed these kitsto get users up and running right out ofthe box in a three-step process.

    In step 1, users connect cables from theboard to their PC, power up the board,load the reference design interface softwareon their computer, view the referencedesign demo and begin working.

    In step 2, users will evaluate the refer-ence design, which includes alternativedesign implementations using hard andsoft IP to implement common functions.Customers can evaluate features directlyfrom the base reference design and see theresults visually as well as view key per-formance statistics.

    In step 3, users will open the ISEDesign Suite design tools, customize thereference design and generate a new designin the software. Next, they will downloadit to the evaluation board and then run thedesign on the FPGA. Its really that sim-ple, said Przybus. In a matter of minutes,you can be up and running.

    With the release of ISE Design Suite11.2, the Xilinx tool suite now supports theVirtex-6 and Spartan-6 FPGA families,delivering a 2x overall run-time improve-ment, speeding synthesis runs by betterthan 2x using XST and offering place-and-route optimizations that lower overall





    14 114






    1612 12



    # Feature1 DDR 32 GPIO Dip Switch3 SFP4 Flash5 10/100/1000 Ethernet6 USB UART & USB JTAG7 MGT Clock8 User Clocks9 FMC Connectors10 Pushbuttons11 MGT 12 USB 2.013 Card Reader for System ACE14 DVI Output15 PCI Express16 12V Wall Adapter Power17 12V ATX Power18 Power Regulator Control


    Board Power

    16 x 2 Display

    Figure 3 The Virtex-6 ML605 Evaluation Kit offers world-class functionality.

  • dynamic power consumption by 10 per-cent. In addition, the tools have a 28 per-cent smaller workstation memory footprintthan the prior version of ISE.

    ISE 11.2 supports the SecureIP simula-tion model, facilitating compatibility withthird-party simulators from Cadence,Mentor Graphics and Synopsys. Also,Mentor Graphics Precision RTL andPrecision RTL Plus products support theBase Targeted Design Platform, as do theSynplify Pro and Synplify Premier toolsfrom Synopsys (Synplicity).

    Certainly, another key component ofthe Base Targeted Design Platform and theoverall Targeted Design Platform strategyis IP support. In conjunction with therelease of the Base Targeted DesignPlatform, Xilinx and its IP partners arerolling out numerous soft cores supportingthe Spartan-6 and Virtex-6 FPGA families.

    The upcoming domain-specific andmarket-specific offerings will feature some

    of these pieces of IP. One, for example, is aPCI Express DMA Engine fromNorthwest Logic. Xilinx and Northwestwill package the DMA Engine with ademonstration application and drivers toform a complete Connectivity TargetedReference Design built to support the newSpartan-6 and Virtex-6 devices with theXilinx base platform.

    Xilinx is selling the Spartan-6 FPGASP601 Evaluation Kit for $295 and theVirtex-6 FPGA ML605 Evaluation Kit for$1,995. The Spartan-6 FPGA SP601Evaluation Kit is available now. TheVirtex-6 FPGA ML605 Evaluation Kitwill be available in late July.

    In the third quarter, Xilinx and resellerAvnet will begin rolling out domain-specifickits for the connectivity, embedded andDSP spaces, followed by market-specific kitsfor communications, video and broadcast.

    For more information, contact yourlocal Xilinx sales office or distributor.

    12 Xcell Journal Third Quarter 2009


    The FPGA Mezzanine Card (FMC) connection will facilitate rapid IP and kit development.

    Spartan-6/Virtex-6 FPGA Base Board

    FMC Modules

    FMC Card Expedites Design DevelopmentOne of the key enablers of the Targeted Design Platform approach is the mutual adop-tion by Xilinx and its network of resellers and IP partners of the FPGA Mezzanine Cardfrom the VITA standards body. The FMC will serve as a standard interface to attachDomain-Specific and Market-Specific Kits from Xilinx and its partners to the BaseEvaluation Kits (see figure).

    This standards-based approach allows Xilinx and its network of third-party compo-nent and board suppliers, including Avnet Electronics, Curtiss-Wright ControlsEmbedded Computing, Linear Technology and Northwest Logic, to deliver to mutualcustomers their latest and greatest offerings.

    The ANSI-approved VITA 57.1 standard incorporates predefined and fixed locationsof parallel and serial I/Os, clocks, JTAG, control signals and power. It uses the well-defined high-performance Samtec SeaRay, supporting Low Pin Count (LPC) 4x40-rowand High Pin Count (HPC) 10x40-row connection. For compatibility with older XilinxFPGA boards, it also includes a voltage-compatible FMC HPC/LPC module.

    Mike Santarini

  • Toggle among banks of internal signals for incremental real-time internal measurements without:

    See how you can save time by downloading our free application note.


    Quickly see inside your FPGA

    u.s. 1-800-829-4444 canada 1-877-894-4414 Agilent Technologies, Inc. 2009

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  • by Andy NortonDistinguished Engineer, Office of the CTOCloudShield Technologies, [email protected]

    Jeff MullinsPrincipal Engineer, Embedded Systems LeadCloudShield Technologies, [email protected]

    Dick MincherEmbedded Systems SpecialistCloudShield Technologies, [email protected]

    The trend toward converged networks forboth telecom and enterprise simplifies net-work infrastructure and dramatically low-ers costs while providing scalable, openplatforms. Blade platforms are achievingnetwork convergence using Ethernet, scal-ing from 1G/10G to 40G/100G, withblade-management controllers keepingpace by using standards-based IntelligentPlatform Management Interfaces (IPMI).

    To help drive network convergence intothe mainstream market, our design teamhere at CloudShield Technologies architect-ed a flexible blade-management controllerby integrating the PowerPC 440 found inthe Virtex-5 with standard and customperipheral cores, creating multiple embed-ded-system configurations with a commonhardware design. This FPGA-based designtook advantage of a unique and flexible fea-ture set that included system reconfigura-tion, powerful embedded processors,intellectual-property (IP) cores and embed-ded Linux firmware for chassis manage-ment services unique to the resident blade.

    14 Xcell Journal Third Quarter 2009

    Blade Management Controller RidesFPGA Embedded ProcessorCloudShield builds powerful, flexible solution around Xilinx PowerPC 440 running embedded Linux.


  • Xilinx Platform Studio cores allowed usto quickly instantiate UARTs, I2C buses,memory interfaces, Ethernet MAC/PHYcombinations and a system monitor for volt-age and temperature oversight. We easilycreated custom cores to provide novel sys-tem acceleration, offloading real-time tasks.Our application implemented standards-based IPMI and chassis managementfirmware running over embedded Linux, fora robust and open software infrastructure.

    Deep-Packet Processing Our next-generation content-processingplatform is a highly programmable, modu-lar, high-speed hardware system capable ofhandling a wide range of network applica-tions and multiple simultaneous func-tions, as shown in Figure 1. The chassisintegrates deep-packet processor blades,application-services processor blades,redundant chassis management modulesand an array of interface modules that canbe deployed with different network inter-face options and configurations.

    Chassis and blade management are underthe control of redundant chassis manage-ment modules using a variant of theIntelligent Chassis Management Bus(ICMB) that extends IPMI intelligent plat-form management to meet highly securerequirements. Each blade or module of thisbusexcept for the power supply modulecontains an IPMI management controller toshare environmental monitoring and statuswith the chassis management module.

    Sharing common requirements, ourfamily of management controllers consistsof chassis management controllers(CMCs), processor management con-trollers (PMCs) on processor blades andinterface management controllers (IMCs)on interface modules, as shown in Figure 2.

    The chassis extensive networking fea-tures support four control-plane GigabitEthernet links to each blade. The dataplane has 16 high-speed lanes to each bladethat provide four 10-Gbit Ethernet linksusing XAUI (4 x 3.125 Gbits/second).Future bandwidth scalability exists, witheach lane capable of 10GBASE-KR (singlelane, 10.3125 Gbps). We used XilinxVirtex-5 FPGAs to implement control-

    available power supplies, the active CMCregulates power demand for the entirechassis by allowing the IMCs and PMCsto power on only when capacity remains.The fan tray and power supply modulesuse a chassis I2C bus where the activeCMC ensures sufficient power and cool-ing for the entire chassis.

    Once the CMC detects a new blade inthe chassis, it uses a discovery protocol tolocate and identify each blade. The discov-ery protocol exchanges IPMI messages toretrieve serial number, model number andinventory for the blade or module, andthen sends a command with power permis-sions if the blade can be correctly identifiedand power is available. The CMC monitorsevents from each IMC or PMC to detectwarning and critical conditions, collectingand storing them in an event log.

    To provide a rich user feature set, ourprimary user interface to the chassis man-agement system is through a window man-agement or command line interface (WMIor CLI) running on an application proces-sor blade. The application processor bladeeither occupies a chassis slot or remotelycommunicates through a control-planenetwork connection to the chassis manage-ment controller. The CMC autonomouslyprovides chassis oversight for health and

    plane Gigabit Ethernet functions with hardtrimode Ethernet media-access controllers(TEMACs) as well as data plane 10-GbitEthernet using the Xilinx 10GEMAC IPcore with integrated XAUI (usingRocketIO serial transceivers).

    Blade Management ServicesOur chassis management solution is a hier-archical structure, with the IMC and PMCentities operating in much the same way asa standard IPMI baseboard managementcontroller (BMC) for their respective mod-ule or blade. For each blade, the controllersuse IPMI commands to monitor voltageand temperature, provide a power controlinterface, enable blade network interfaceconfiguration and allow interrogation ofmanufacturing data.

    As the center of chassis management,the CMC shares common IPMI BMCboard-level features with the IMC andPMC, along with additional higher-levelchassis management functionality. Thedual redundant CMCs operate in anactive/standby capacity with automatichealth monitoring and failover. This chas-sis management capability allows theCMC to discover, inventory and providepower permissions for all blades and mod-ules. To prevent oversubscription of the

    Third Quarter 2009 Xcell Journal 15

    Service Control Traffic Prioritization Bandwidth Usage Control Network Flow Analysis L2-L7 Access Analysis P2P Control & Cache Tiered Services & QoS

    Transport IPv4 & IPv6 Migration (Transition, Stacks) Multicasting & Acceleration (IPTV, VoIP, P2P) Content-Based Routing (User Services)

    Security DDoS Mitigation DNS Protection BGP Protection Botnet Protection Content Filtering Native IPv6 Security

    Service Control



    CloudShield Deep Packet Inspection

    Figure 1 Next-generation deep-packet inspection processing system enables convergence of service control, security and transport functions into integrated services and capabilities.


  • environmental monitoring, presenting thisinformation through front-panel LEDs,while application-specific user controlcomes from the application processorblade. This same blade interrogates allblades and modules, including the CMC,to provide the user with environmental aswell as operational health and status. TheCMC contains an RS485 IPMI proxy serv-ice to pass application processor bladecommands on the control plane through tothe RS485 IPMI path to the target blade.

    Each CMC has five independent point-to-point RS485 links to each blade. Unlikea bus topology, this architecture providesincreased security from eavesdropping,minimizes contention and increases reliabil-ity, in that a failing blade cannot disruptcommunication to other blades. Ourredundancy implementation requires thestandby CMC to constantly monitor thehealth of the active CMC. Upon detection

    of a failure, the standby CMC can take over,with its independent set of radial RS485links, to keep the chassis operational.

    Management Controller Hardware ArchitectureSharing common hardware functionality,our controllers include FPGA multibootand fallback capability, PowerPC440processor, SDRAM and NOR flash memo-ry configuration, interrupt controller, serialconsole UART, ICMB RS485 custom core,Gigabit Ethernet links, system monitorsensors and local I2C buses.

    Our controller family is uniquely archi-tected to share a common hardware plat-form using a single microprocessorhardware specification file that defines theembedded-processor core instantiations,connectivity and parameterization. Ourmini boot loader resides in internal blockrandom-access memory (BRAM), whichcopies the U-Boot boot loader from flash

    to DDR memory and then jumps to the U-Boot entry point.

    Taking advantage of the features of theVirtex-5 FX30T FPGA, CloudShieldsteam easily assembled an advanced embed-ded system, integrating the PowerPC 440,DDR2 memory controller, multiportmemory controller for flash, EthernetMAC/PHYs, system monitor and otherstandard cores with our custom core.

    By leveraging the Virtex-5s multibootreconfiguration, the system achieves truein-system FPGA upgradability without aprocessor to manage bitstream loading.Our external flash supports both goldenand upgrade bit files located at addressesthe revision select pins determine. TheFPGAs ability to fall back and reconfigureusing the golden image in the event of anupgrade image failure was essential to ourdesign objective of a configurable high-availability system.

    16 Xcell Journal Third Quarter 2009

    Chassis Management Module (Active)


    Chassis Management Module (Standby)





    Redundant Radial RS 485


    Interface Switch Modules

    Deep Packet Processor Blades

    Application Processor Blade

    Power SuppliesFan Tray

    Figure 2 Secure ICMB chassis management system


  • Third Quarter 2009 Xcell Journal 17

    Post-configuration, the PowerPC 440core operates at 400 MHz, the crossbarand MPLB bus at 133 MHz, TEMACs at125 MHz and DDR2 at 266 MHz. Ourconstructed hardware system covered thesuperset of functionality needed amongthe CMC, IMC and PMC variants asshown in Figure 3. The flash containsenough space for multiple application pro-grams, including the CMC, IMC andPMC configurations.

    We were able to rapidly craft the base sys-tem thanks to the wide variety of standardperipheral cores available in the IP library.We selected cores as complex as GigabitEthernet (with choices of 1000BASEX,SGMII and GMII PHY interfaces) and assimple as traditional 16550 UARTs to meetour system requirements.

    Key requirements for a blade controllerinvolved chip- and board-level monitor-ing and alarms for voltages and tempera-tures. We took advantage of an integratedsystem monitor, simply instantiating theSYSMON_ADC pcore from the standardIP library. The system monitor is a hardmacro on Virtex-5 devices that contains a10-bit, 200-kilosample/s analog-to-digitalconverter, supporting both on-chip andoff-chip monitoring of supply voltagesand temperatures.

    Off-the-shelf IP and the availability ofan Avnet Virtex-5 FXT evaluation kit thatused the XC5VFX30T FPGA allowed us torapidly prototype our design and kick-startthe software development effort right outof the box.

    With the software effort under way, wethen created custom IP cores to satisfy anumber of needs. While off-the-shelfpcores might meet functional require-ments, multiple instances of simple pcoressuch as GPIO can result in excessiveProcessor Local Bus (PLB) loading as wellas higher slice utilization. Rather thanincur the expense of multiple IP interfaces,we built a single super-GPIO module withthe help of the Create Import Peripheral(CIP) wizard integrated into XPS.Amortizing a single IP interface over mul-tiple GPIO registers, we collapsed largenumbers of internal and external registersinto a single custom pcore including revi-

    sion, scratch, and internal and externalGPIO registers.

    We also used the CIP wizard to buildour special-purpose custom IP. The wizardcreated the necessary files (MPD, PAO,HDL templates) and directory structure,

    and offered easy selection of IP interfaceservices and user logic interfaces. It alsogenerated the bus functional model neededfor simulation. Our novel PicoBlaze-based coprocessor pcore is described laterin greater detail.





    User UART


    Console UART

    PPC440 CPU














    Console UART

    PPC440 CPU












    Console UART

    PPC440 CPU








    customCMB Pblaze

    customCMB Pblaze

    customCMB Pblaze

    Figure 3 Common hardware architecture for CMC (top), IMC (center) and PMC versions.


  • IPMI Messaging Our chassis management controller withits corresponding system interfaces isshown in Figure 4. We use the customICMB coprocessor pcore for IPMI mes-saging to the processor-management andinterface-management blade controllers.GPIOs monitor and control the frontpanel, backplane, redundancy and inter-locks, as well as internal registers, whileTEMACs are used for control-planeEthernet switch management. Our I2Csread the local module EEPROM, andhandle remote monitoring of chassis fansand power supplies. UARTs take care of

    front-panel user connectivity, debug con-soles and proxy UARTs to CPUs onprocessor blades.

    The real-time protocol requirements ofthe Intelligent Chassis Management Buspresented us with a problem in that theembedded Linux operating system couldnot natively guarantee interrupt latency.

    Our solution uses a custom ICMB pcorewith the PicoBlaze 8-bit sequencer as anICMB data-link and physical-layercoprocessor offloading the PowerPC. Thisunderappreciated resource (see Xcell Journal,issue 67, page 53, A Hidden Gem:PicoBlaze IP) is shown in Figure 5, coupled

    with BRAM instruction store, registers,communication FIFOs, UARTs and timers.After initialization, the PowerPC holds thePicoBlaze in reset, loads code into thePicoBlaze program BRAM and thenremoves reset, activating the coprocessor.

    We wrote our PicoBlaze code in theform of a state machine to monitor thetransmit FIFO and control registers, imple-ment the collision-avoidance and back-offalgorithms, and manage five UARTs.

    The TX FIFO passes 8-bit data from thePowerPC to the PicoBlaze for transmissionon the ICMB bus. To transmit a packet, thePowerPC writes the packet into the TX

    18 Xcell Journal Third Quarter 2009

    PMC Slot 3

    IMC Slot 4

    IMC Slot 5

    I2C Control/Monitoringfor fans, power supplies

    Front panel buttons /LEDsBackplane monitor



    FLASHConfigSW app


    IPMI Control Messages


    Gigabit Ethernetswitch





    User UART


    customCMB Pblaze


    PPC440 V5 CPU









    PMC Slot 2

    PMC Slot 1



    Front PanelRJ-45



    Figure 4 CMC system interfaces

    The embedded Linux operat ing system could not nat ively guarantee interrupt la tency. Our solut ion leveraged the

    capabi l i t ies of the PicoBlaze 8-bi t sequencer.


  • Third Quarter 2009 Xcell Journal 19

    FIFO, followed by a write to the controlregister with a start bit and channel num-ber. Using a common transmit UART andindividual transmit enables, the PicoBlazeenables a single RS-485 transceiver for datatransmission. Upon completion, thePicoBlaze indicates success or failure bywriting to the status register and generatingan interrupt to the PowerPC.

    Packets come in on multiple UARTssimultaneously. The PicoBlaze maintainsindividual state information for each chan-nel. Indications of start/end of packet anddata bytes are placed in the RX FIFO alongwith the channel number, and thePowerPC gets an interrupt when data isavailable. The RX FIFO passes 8-bit data,

    5-bit status (start/end of packet, error indi-cations, debug information) and 3-bitchannel number information from thePicoBlaze to the PowerPC. The PowerPCthen demultiplexes packet data and, whenvalid, sends it up to the servicing agent. Weincluded additional trace and state transi-tion capability in the receive channel inorder for the PowerPC to print debug mes-sages to the console.

    We used the CIP wizard to create a busfunctional model, enabling us to generatebus stimulus and verify the operation ofthe peripheral core without needing to cre-ate an extensive test bench or full-systemsimulation. The wizard made it easy togenerate, respond to and analyze bus trans-

    actions. As a result, we created and modi-fied our simulation for the custom pcoreand got it running in a matter of hours.

    We used the output of the PicoBlazeassembler to initialize the program BRAM.Next, using the Bus Functional Languageto describe PLB bus transactions, we gener-ated a PicoBlaze reset, sent data to the TXFIFO and wrote to the control register totransmit data on a channel. Looping backtransmit and receive ports was a simple wayto verify the operation of the receive chan-nels and RX FIFO.

    Firmware Architecture There are many embedded-OS choicesavailable for the PowerPC 440 and, specif-ically, the Xilinx hard PPC440 core. All ofthe management controllers required real-time performance, a robust network stackand extensibility for our custom peripher-als. Our choice of embedded Linuxallowed us to take advantage of existingopen-source resources, utilities, optimiza-tions and support.

    After reset, the PowerPC bootsequence begins from reset vector spacewithin a small internal BRAM. Mappedinto this area is a small mini boot loader(12 kbytes), which looks for a valid U-Boot image at an upgrade or goldenlocation within the NOR flash. Since thegolden image is programmed only at thefactory during the manufacturing process,this choice eliminates the possibility of afailure during flash programming of a newU-Boot version. Once it detects and vali-dates the proper U-Boot image, thePowerPC loads it into SDRAM and exe-cutes it. U-Boot then loads the properLinux image files and passes control forthe final time. At this point, a fully con-figured Linux kernel loads and begins ourapplication-specific processes.

    We considered several options for theboot sequence during the design process.For example, the mini boot loader couldhave mapped the NOR flash into thereset vector area and eliminated theBRAM. This would have saved someBRAM, but the processor would then bedependent on a valid NOR flash part andimage, which could be corrupted during a

    IP InterConnect (IPIC)

    TX FIFORX FIFOCtl RegStatus Reg


    laze Reset


    Kcpsm3 (PicoBlaze)


    Uart Clock


    Gap Timer

    TransmitEnable Control

    BackOff Timer

    PLB v46



    Register I/F Address Range Decode













    Receive FIFOs /UARTs


    Receive Timer

    StartUp Timer



    Figure 5 Custom ICMB PicoBlaze pcore


  • failed flash attempt. Similarly, a casecould be made for eliminating U-Boot byloading and executing Linux directly.While this could be a much more directboot sequence, we found the features ofU-Boot during the development phase tobe extremely valuable for prototype bring-up and debugging.

    Our initial design challenge was tolocate and choose the correct open-sourcetrees. DENX Software Engineering(www.denx.de) has extensively developedthe Das U-Boot boot loader for a varietyof embedded-processor boards. But whileit directly supports the MicroBlaze,PowerPC 405 and PowerPC 440 proces-sor cores, the DENX version does notinclude the latest patches, board supportor drivers for some of the XPS IP coresthat come with the EDK.

    Therefore, we chose to use the Xilinxdevelopment branch of the U-Boot tree(xilinx.wikidot.com), which contains thelatest changes and the drivers for the I2C,ENET and LLTEMAC, providing addi-tional functionality without starting fromscratch. Xilinx frequently updates its devel-opment branch from the original DENXmaster tree, submitting changes upstreamfor acceptance into the DENX tree.

    Having selected the Xilinx U-Boottree, we looked at the main Linux tree(www.kernel.org) and its support for theXilinx drivers. We similarly concludedthat we obtained more working function-ality when choosing the Xilinx-main-tained Linux development branch (also atxilinx.wikidot.com), which included thelatest changes that may not necessarily bein the main Linux tree.

    A potential drawback of using theXilinx-maintained trees is that there is lagtime in terms of synchronization with themain trees, and they are officially devel-opment-quality branches. Nevertheless,we selected the Xilinx trees to support theLLTEMAC cores and newer features inour design.

    In order to build U-Boot and Linux,we needed a Linux distribution andmachine to run the scripts and tools thatcross-compile, link and build thePowerPC executable. While this could be

    a barrier if only Windows-based machineswere available, there are now a fewWindows virtual machines that runLinux within the Windows environment.The added benefit is that once we set upa build machine, we could back up thevirtual-machine disk image or replicate itfor use on other development machines.We selected Sun xVM VirtualBox as alightweight, reliable and easy-to-use vir-tual machine that will run many differentOS types, including Linux.

    While the Linux kernel provided anexcellent foundation, the actual drivers andapplications handled the entire workloadspecific to our application. The Xilinx I2C

    and LLTEMAC drivers connect the LinuxIP stack to the hardware, and theCloudShield ICMB driver hooks the cus-tom PicoBlaze IP core into the Linux driv-er subsystem. We used Busybox as astandard Linux application, and addedthree new CloudShield applications forchassis management by the CMC, asshown in Figure 6.

    Our RS485 proxy application connectsto a standard IP port and communicatesover the control-plane Ethernet, decodingeach packet. Packets received from ourWMI/CLI on the application processorblade may be addressed to three differenttargets in the system: BMC functions onthe chassis management module board,CMM blade management for the chassisor other blades within the chassis. Allbaseboard management controller func-tionality runs over the I2C buses, handling

    CMC and chassis health requests. TheRS485 proxy application translates pack-ets destined for other blades in the chassisinto ICMB packets and sends them overthe RS485 link to the appropriate destina-tion. Blade management packets allow theuser to obtain chassis status, such as powersubscription, as viewed by the CMC.Some additional minor applications forredundancy and front-panel serial consoleinteraction complete the CMC.

    Our IMC and PMC were very similar tothe CMC firmware, except that we replacedthe blade-management application with aswitch- or processor-management applica-tion appropriate for that blade.

    Architect, Build, Verify, Deliver The key to rapidly architecting, develop-ing and delivering complex embedded-system solutions is right-sizing thechoices, efforts and methodology. Thecombination of powerful embeddedprocessors in FPGAs, off-the-shelf IP andaccelerated design and verification ofcustom IP enabled us to create multipleembedded-system configurations with acommon hardware design. The benefitsof using Linux and an integrated devel-opment environment freed us to focus onthe target application while utilizing theavailable open-source services, driversand libraries.

    Indeed, the ability to rapidly alter inter-nal FPGA embedded architecture, easilydeploy in-system upgrades and exploit newhardware-software trade-off boundaries istransforming embedded-system design.

    20 Xcell Journal Third Quarter 2009

    Linux kernel

    LLTEMAC driver Linux drivers

    BusyboxBMC functions

    IP stack

    Blade mgmtRS485 Proxy

    ICMB driverI2C driver


    Environmental Control PlaneEthernet


    Figure 6 CMC firmware architecture


  • More gates, more speed, more versatility, and ofcourse, less cost its what you expect from The Dini Group. This new

    board features 16 Xilinx Virtex-5 LX 330s (-1 or -2 speed grades). With over 32 Million ASICgates (not counting memories or multipliers) the DN9000K10 is the biggest, fastest, ASICprototyping platform in production.

    User-friendly features include:

    9 clock networks, balanced and distributed to all FPGAs

    6 DDR2 SODIMM modules with options for FLASH, SSRAM, QDR SSRAM, Mictor(s),DDR3, RLDRAM, and other memories

    USB and multiple RS 232 ports for user interface

    1500 I/O pins for the most demanding expansion requirements

    Software for board operation includes reference designs to get you up and running quickly. Theboard is available off-the-shelf with lead times of 2-3 weeks. For more gates and more speed,call The Dini Group and get your product to market faster.

    www.dinigroup.com 1010 Pearl Street, Suite 6 La Jolla, CA 92037 (858) 454-3419 e-mail: [email protected]

  • by Guy EschemannResearch Engineer Sennheiser electronic GmbH & Co. [email protected]

    Heinz LdigerProject ManagerIMST [email protected]

    Birgit KullSenior ScientistIMST [email protected]

    Since the Federal CommunicationsCommission authorized the unlicenseduse of the ultrawideband (UWB) radiotechnique in 2002, most of the technolo-gys commercial applications, such aswireless USB, have been based on fre-quency-domain modulation techniques(such as OFDM) for high-data-rate trans-missions. Alongside this establishedapproach, UWB offers the potential foranother kind of data transmission basedon ultrashort pulses with durations onthe order of nanoseconds. So-called

    22 Xcell Journal Third Quarter 2009

    Virtex-5 Propels UltrawidebandComms and Ranging Europes PULSERS project

    uses Xilinx FPGA with MicroBlaze processor in impulse-radio UWB system.


  • impulse-radio (IR) systems transmitinformation by modulating one or moreof the pulse parameters, such as positionor amplitude. At the same time, by meas-uring the pulses time-of-flight, they canimplement centimeter-accurate rangingcapabilities.[1] This opens up the field toa new range of location-aware applica-tions in such diverse areas as logistics(package tracking), manufacturing,search and rescue (communication withand localization of firefighters, for exam-ple) or smart tour guides.

    The European PULSERS Phase IIProject, an industry-led collaboration intoUWB radio technology by 30 key industri-al and academic organizations, has set outto design and implement an IR-UWB com-munication and ranging system [2] featur-ing data transmission capabilities in themegabit/second vicinity and a ranging reso-lution of 4 cm. Our system consists of a setof identical autonomous nodes, each ofwhich can communicate with and deter-mine the range to every other node in thenetwork. A node consists of a custom UWBdaughterboard connected to an off-the-

    measuring the time delay between sending aranging request and receiving the answerfrom the remote node (see sidebar). Rangingrequests are always sent in beacon slot 1,while ranging answers are expected to comeback in slot 3. This gives the remote node theduration of a full beacon slot (slot 2, approx-imately 33 microseconds) for processing thereceived ranging request and scheduling theoutgoing ranging answer.

    shelf Xilinx ML506 development board(see Figure 1). The high performance of theVirtex-5 SXT architecture combined withthe flexibility of a MicroBlaze softprocessor allowed us to implement theentire baseband signal chain as well as allthe higher system layers in a single FPGA.

    IR-UWB Communication and RangingTo transmit information, our system uses asimple pulse-position modulation with fourpossible time shifts (4-PPM), where eachpulse encodes two data bits. Pulses aregrouped into frames and transmitted in apredefined raster of beacon frames andtime-hopping frames, as illustrated inFigure 2. Each beacon frame consists ofthree identical beacon slots that customerscan use for ranging or communication pur-poses. We initially intended the time-hop-ping frame to carry high-data-ratetransmissions based on time-hopping code,but well use that technique in a later prod-uct. At this time, all the data transmissionsoccur in the beacon frames.

    We performed ranging using a methodknown as two-way ranging, which consists of

    Third Quarter 2009 Xcell Journal 23







    CPLD Exp


    on H





    on H


    r MicroBlaze










    RF Front End ML506

    SMAconn. Antenna switch

    Comparator trigger


    240 MHzClock






    60 MHz clock


    Diff.clock input


    Beacon frame Beacon frameTime-hopping frame Time-hopping frame

    ...slot #1 slot #2 slot #3 slot #1 slot #2 slot #3

    Typ. 100 s

    Typ. 1 ms

    Center frequency 7.68 GHz

    Baseband bandwidth 750 MHz

    Expected range 25 - 30 meters

    Actual range 3 m (due to local-oscillator crosstalk)

    Ranging resolution 3.9 cm

    Communication data rate > 1 Mbit/s

    Figure 2 Periodic beacon frames consisting of three beacon slots are interspersed with time-hopping frames.

    Figure 1 The system consists of an off-the-shelf Xilinx ML506 board connected to a custom UWB daughterboard.

    Table 1 UWB communication and ranging system characteristics


  • System ArchitectureThe ultrawideband daughterboard carriesboth the impulsive-transmitter and incoher-ent-receiver ASICs, which we designedspecifically for this project using IHPs 0.25-micron SiGe:C BiCMOS technology. [3, 4]

    The transmitter ASIC, which generatesUWB pulses as shown in Figure 3, is capa-ble of modulating both the amplitude andthe position of the generated pulses. Itincludes a 3.84-GHz counter for preciselyscheduling the time of transmit of the out-going pulses and measuring the time ofarrival of the received pulses.

    The reception path splits into twobranches inside the receiver ASIC. The firstbranch, which has a relatively narrowbandwidth (120 MHz), serves communi-cation and coarse pulse-timing purposes.Precise pulse timing occurs on a secondreception branch that utilizes the fullimpulse bandwidth (750 MHz). On thisbranch, a high-speed comparator detectsincoming pulses. Its output triggers thereadout of the 3.84-GHz counter runninginside the transmitter ASIC. Thus, thetime of arrival of each received pulse ismeasured with a resolution of 260 ps,which translates into a spatial resolution ofapproximately 8 cm.

    The daughterboard feeds the basebandmodule in the Virtex-5 FPGA with twodata buses running at 120 MHz. The com-munication (COMM) bus carries the ADCsamples while the time-of-arrival bus con-veys the high-resolution time stamps asso-

    ciated with the received pulses. Both busesgo through an XC95144XV CPLD which,while not strictly required, was a greatdebugging aid. We can set the CPLD tooutput a sequence of pseudo-random num-bers [5] on the buses to the FPGA. Wethen use the CPLD output to both adjustthe FPGAs input timing and to verify theintegrity of the bus linestasks that wouldhave been difficult without a priori knowl-edge of the transmitted data sequence.

    Inside the FPGA, the baseband module(see Figure 4) takes care of both the encod-ing of the outgoing pulses and the decod-ing of the received pulses. The transmissionpart of the baseband module is relativelystraightforward, consisting mostly of outer(CRC) and inner (convolutional) coding.The implementation of the reception

    counterpart involves, among other things, achannel estimator and a custom Viterbidecoder, and is thus much more resource-intensive. We connected the basebandmodule to the processor system via aProcessor Local Bus (PLB) interface.

    While programmable logic is notori-ously more difficult to debug than soft-ware, the ChipScope Pro tool, withboth an integrated logic analyzer and abus analyzer configuration, was of greathelp during debugging sessions. The logicanalyzer proved useful for simultaneouslycapturing a burst of COMM and time-of-arrival samples, providing real-world datato our MATLAB simulator. The busanalyzer helped us debug a few issuesrelated to the PLB interface of our base-band module.

    24 Xcell Journal Third Quarter 2009




    Channel Estimator

    AGC & Sync. Header InsertionSymbol



    Convolutional EncoderIncluding Tail Bits






    RX pulseshape


    LLVs ofPPM


    LLVs ofcoded bits

    RX signal(ADC samples)

    OutputPPM symbols

    Decodeddata bits

    Outputdata bits

    Figure 4 The baseband modules reception (top) and transmission chains.

    Figure 3 A UWB pulse consists of a 7.68-GHz carrier wave with a Gaussian envelope.


  • Third Quarter 2009 Xcell Journal 25

    Processor SystemWe generated the processor system using theBase System Builder wizard within the XilinxPlatform Studio (XPS) design tool, which gaveus a perfectly working system to start with.After that, we incrementally modified the basesystem to obtain the system shown in theFPGA section of Figure 1. These modificationsinvolved, among other things, switching to adifferential clock input and connecting thebaseband module to the PLB.

    The software application runs on anembedded MicroBlaze processor on top ofXilkernel, which is a minimal real-time oper-ating system perfectly suited for small appli-cations. The application is divided into threethreads that run concurrently:

    The UWB thread manages the configura-tion and operation of the baseband module.

    The application thread is responsiblefor the audio acquisition and playbackactivities when the system is used indata transmission mode.

    The RS232 thread communicates withan external PC running the demonstra-tion graphical user interface.

    Since the GNU development chain,which XPS uses, is available on a numberof other platforms, we could easily com-pile and test the hardware-independentmodules of code on a host PC (for exam-ple, using the Cygwin environment)rather than on the embedded target. Thatmade debugging a lot easier. Only thefinal testing had to be done on the embed-ded target, and having a source-leveldebugger like GDB was a real blessing.Xilinx application note XAPP1037 [6]

    showed us many useful tricks for debug-ging our software.

    A few hardware issues, located in theUWB ASICs, currently limit the nominalrange of our system to 3 meters instead ofthe initially expected 25 to 30 meters.Still, we have been able to demonstrateboth the communication and rangingcapabilities of the system, which makesthe project a great success.

    Future work may include redesigningthe UWB ASICs to increase the systemsoperating range, as well as implementingmultilateration capabilities to move from aranging system to an actual indoor posi-tioning system.

    For more information, visit http://www.imst.de/de/forschung_pul.php or [email protected]


    We wish to acknowledge Erwin Stenzel and DanielKotzor from EADS; Gunter Fischer from IHP; ThorstenKohl, Jac Romme and Norbert Schmidt from IMST;Maria Dolores Prez-Guirao from the Leibniz Universityof Hannover; Axel Schmidt from Sennheiser, andDajana Cassioli from RadioLabs for their contributionsto this project. Thanks to Steven Backer from Sennheiserfor reviewing drafts of this article.

    This work was co-funded by the European Commissionunder the Information Society Technologies integratedproject PULSERS Phase II.


    [1] S. Gezici, Z. Tian, G. B. Giannakis, H. Kobayashi,A. F. Molisch, H. V. Poor and Z. Sahinoglu,Localization via Ultra-Wideband Radios, IEEESignal Processing Magazine, July 2005.

    [2] H. Ldiger, B. Kull, M. D. Perez-Guirao, An Ultra-Wideband Approach towards Autonomous RadioControl and Positioning Systems in Manufacturing &Logistics Processes, Proceedings of the 4th Workshopon Positioning, Navigation and Communication,Hannover, Germany, March 2007.

    [3] G. Fischer, O. Klymenko, D. Martynenko, Time-of-Arrival Measurement Extension to a Non-CoherentImpulse Radio UWB Transceiver, Proceedings of the5th Workshop on Positioning, Navigation andCommunication, Hannover, Germany, March 2008.

    [4] O. Klymenko, G. Fischer, D. Martynenko, A HighBand Non-Coherent Impulse Radio UWB Receiver,Proceedings of the IEEE International Conference onUltra-Wideband, ICUWB 2008, Hannover, Germany,September 2008.

    [5] P. Alfke, Efficient Shift Registers, LFSR Counters,and Long Pseudo-Random Sequence Generators,XAPP052 application note.

    [6] B. Hill, Introduction to Software Debugging onXilinx MicroBlaze Embedded Platforms, XAPP1037.

    Two-way ranging demystifiedIn two-way ranging, the technology we employed in our impulse-radio UWB system,the distance between node A and node B is determined using the following tech-nique (see figure):

    1. Node A sends a ranging request

    to node B and starts its high-

    resolution clock (3.84 GHz).

    2. Node B receives the ranging

    request after the signal propaga-

    tion delay , which is

    proportional to the distance

    between nodes A and B.

    3. Node B sends back a ranging answer to node A after a known

    processing delay .

    4. Upon receipt of the ranging answer, node A stops its clock at time . It can

    then compute the one-way signal propagation delay , which,

    multiplied by the speed of light, gives the range between A and B.

    The 3.84-GHz clocks time resolution of 260 picoseconds yields a spatial resolu-tion of approximately 8 cm. Since, however, the radio signal traverses the distancebetween the two nodes twice, the range can be determined with a resolution of 4 cm.

    Knowing the range between itself and three non-co-linear anchor nodes, amobile node can compute its 2-D position. Using four non-co-planar anchornodes, it can even find its 3-D position.

    Guy Eschemann, Heinz Ldiger and Birgit Kull

    Node A Node B

    Node A Node B

    Node A Node B

    Node A Node B





    The two-way ranging process


  • by Greg CrouchEmbedded Systems Business DirectorNational [email protected]

    Facing increased regulation and the need toreduce factory operating costs, machinebuilders are looking for solutions to boostproduct power efficiencies. Along withHVAC systems, the top consumers of elec-tricity in a factory are water heating, light-ing, office equipment and, especially,machinery. More specifically, the motorswithin these factory machines are responsi-ble for approximately two-thirds of thetotal electrical-energy consumption in atypical industrial facility. Motors are every-wherein blowers, pumps, compressors,conveyors, machine tools, mixers, shred-ders and more.

    One way to get the maximum efficiencyfrom the motors that control machinery isto employ more efficient and sophisticatedfield-oriented control to optimize their effi-ciency (see sidebar, Motor Efficiency Leadsto Greener Bottom Line). To this end, ourteam at National Instruments (NI) usedXilinx FPGAs as the basis for a commonhardware architecture called reconfigurableI/O (RIO) to create a flexible embeddedcontroller with high computing perform-ance. Our machine-builder customers useRIO as a platform from which to drawfield-oriented control (FOC) techniquesthat improve motor efficiency.

    26 Xcell Journal Third Quarter 2009

    FPGA-Powered PlatformControls Industrial Motorsfor Maximum EfficiencyNational Instruments uses Xilinx devices inCompactRIO design for industrial-equipmentbuilders requiring optimal motor control.


  • This RIO architecture is now deployedin many systems, such as those fromEUROelectronics, Srl. The architecturehelped EUROelectronics advance from theprototyping phase to the final machinesetup in only three months (Figure 1).

    Reduced Machine Design Time U.S. Department of Energy data informsmachine builders that switching to amotor with a 4 to 6 percent higher effi-ciency rating can pay for itself in just twoyears if that motor is in operation formore than 4,000 hours a year.Unfortunately, many machines hostmotors that are very large and too costlyto replace. So in these cases, the key toreaping savings lies in updated drive-con-trol algorithms and controller hardware.

    A second challenge is the integratedcontrol complexities required for brush-less DC and permanent-magnet synchro-nous AC motors (PMSM), bothcommonly grouped together as brushlessDC motors (BLDC). Many machinebuilders lack the software or hardwaredesign expertise required to build anembedded controller that can executereal-time closed-loop control on a widevariety of analog and digital sensor types.

    backplanes, combined with PowerPC

    603e-based processors in various perform-ance frequencies (Figure 2).

    We built into our RIO framework con-figuration software utilities and dynamicI/O reconfiguration capabilities that savetime in setup and reuse for both the end-

    To reduce time to final design forembedded-machine builders, we incorpo-rated one form of our RIO-based architec-ture into a product called CompactRIO.These FPGA-based configurations includesystems built from Xilinx Virtex-5 LX85to Spartan-3 and Virtex-II 1M-gate-based

    Third Quarter 2009 Xcell Journal 27



    Disk on Chip




    UART Ethernet Phy

    Power SupplyInterface






    us UART Ethernet MAC







    GPIO 12C


    Configuration Flash

    Onboard ADC,DAC, 24V DIO

    5V TolerantDIO

    110 DIO



    NI C Series I/O

    Custom I/O

    Custom I/O

    Processor FPGA

    Figure 1 Embedded-machine builder EUROelectronics reduced power use with FPGA-based field-oriented control.

    Figure 2 Modular RIO architecture-based framework for NIs single-board RIO and CompactRIO configurations

  • application programmer and the digitaldesign engineer. Our configuration soft-ware automatically detects custom hard-ware installed in the system. Integrateddiagnostic tests of I/O peripherals ensurethat I/O devices function properly. Thedesigner connects the custom circuitrydirectly to the Xilinx FPGA, and can

    design logic with the Xilinx tools or the NILabVIEW FPGA Module.

    Planning for dynamic configurationhelps the machine builder design for hard-ware reuse. At the same time, it providesthe ability to begin high-level applicationcoding before the final new I/O circuitrydesign is complete.

    It can be problematic if driver softwareand the associated APIs do not executeproperly or return device-specific errorswithout the I/O circuitry installed. To getaround this problem, software developersoften create simulation subroutines thattemporarily replace the I/O circuit codewithin the application. This method makesit difficult to get a start on the applicationdevelopment and virtually impossible to

    debug the code. Our RIO middlewaredriver architecture includes functionality tointegrate simulation code directly into thefunctional driver, thus simplifying codereuse and debugging.

    For example, Figure 3 describes theembedded middleware software designhierarchy. These middleware drivers and

    system services have proven their mettlein thousands of deployed machine-builder applications. Parallel and multi-thread-safe embedded-middleware driversare an integral part of RIO. The machinebuilder can call both multithread-safe andreentrant functions from multiple threadsat the same time, and still operate cor-rectly without blockingan importantfeature for writing parallel code and opti-mizing performance. Drivers that lackreentrant execution can erode perform-ance or, worse, cause a crash. Your codehas to wait until the other threads aredone using each function before it canaccess them. Reentrancy is an importantconsideration to eliminate any unneces-sary dependencies in your code.

    Help from FPGA Control Algorithms Although brushless DC motors and perma-nent-magnet synchronous AC motors areboth considered brushless DC motors, theydiffer in the way their stator is wound.When rotated, the stator of the BLDC iswound in such a way as to produce a trape-zoidally shaped back-EMF voltage, while

    the PMSMs voltage is sinusoidally shaped. Brushless DC motors are more costly

    than AC induction motors but provide bet-ter energy efficiency and performance whencontrolled using advanced algorithms.Moreover, they can scale up to serve veryhigh-power and high-speed applications.While AC induction motors still dominatethe market, brushless DC motor sales havequadrupled over the last five years to morethan $1.2 billion, according to the ARCAdvisory Group.

    BLDC motors are a type of synchronousmotor. This means the magnetic field thestator generates and the magnetic field offthe rotor rotate at the same frequency.Usually BLDCs are equipped with threephases. The stator of a BLDC motor con-

    28 Xcell Journal Third Quarter 2009


    Figure 3 With processor middleware drivers, machine builders can focus on custom circuitry design. They can link to the programmable Xilinx FPGAs through standard header connectors.

    The machine builder can call both multi thread-safe and reentrant functions from multiple threads at the same t ime. Drivers that lack reentrant execution

    can erode performance or, worse, cause a crash.

  • Third Quarter 2009 Xcell Journal 29

    sists of stacked steel laminations withwindings placed in slots that are axially cutalong the inner periphery. Most BLDCmotors have three stator windings connect-ed in a star fashion. The internal structureis like that of an induction motor contain-ing pairs of permanent magnets on therotor rather than windings.

    As the name implies, the brushless DCmotor is designed to operate without brush-es. This means that the commutation thebrushes provide must now be handled elec-tronically. To rotate the BLDC motor, thestator windings are energized in a sequence.

    To calculate which winding to energize at atime, it is necessary to know the rotor posi-tion, typically measured by three Hall-effectsensors embedded into the stator. Based onthe triple combination of these sensor sig-nals, the control electronics can determinethe exact sequence of commutation.

    Because brushless motors use perma-nent magnets in their rotors rather thanpassive windings, they natively providehigher power than induction motors fortheir size and weight. The key to high-effi-ciency operation, however, lies in theFPGA-based controller.

    FPGA-based algorithm control deliversbetter efficiency than microprocessors canachieve. A wide range of control-systemalgorithms are available, including trape-zoidal, sinusoidal and field-oriented.

    Trapezoidal, or six-step, control is thesimplest but lowest-performance method.For each of the six commutation steps,the motor drive provides a current pathbetween two windings while leaving thethird motor phase disconnected. However,torque ripple causes vibration, noise,mechanical wear and greatly reducedservo performance.


    On todays factory floor, the motor-driven equipment is estimatedto be responsible for two-thirds of the total electricity-energy con-sumption. This is creating a challenge for equipment manufactur-ers to develop more energy-efficient systems. The effort can bemanifested in many ways, such as selecting a more efficient motor,properly sizing a motor for its designed load or improving motorperformance through better and faster feedback and control.

    Check the Efficiency RatingSimply replacing an existing motor with a more energy-efficientmodel justifies the slight premium of its initial cost. For a 500-horsepower motor that runs 8,000 hours a year, switching to amodel with a 5 percent higher efficiency rating could save morethan $12,000 and 170 kilowatt-hours of electricity annually. Tooffset the upfront costs, some utility companies and public agen-cies provide incentives to encourage customers to upgrade toNEMA Premium Motors, certified by the national trade organi-zation for the electrical manufacturing industry.

    Size Matters; So Does LoadIn general, motor efficiencies also vary based on the amount ofload on the motor, and can range from 85 percent to 97 percent atfull load, with a peak on average at 70 percent to 80 percent load.Counterintuitively, slightly oversizing a motor (up to 25 percent)can actually increase efficiency. Also, a seemingly minor increase ina motors full-load rotational speed of 40 RPM can result in a 3 to6 percent increase in the load placed upon the motor, increasingenergy consumption by 7 percent and offsetting the energy anddollar savings expected from a NEMA Premium Motor.

    Field-Oriented Control Squeezes More SavingsThe load to the motor is never constant; therefore, feedback fromthe motor will help to track incremental load changes. While the

    Motor Efficiency Leads to Greener Bottom LineBy Wil Florentino Product Marketing Manager, ISM Vertical Market, Xilinx

    traditional, scalar control techniques for variable-speed opera-tion of three-phase electric motors offer simple implementa-tion, they limit the performance. Field-oriented control(FOC), also called vector control, is a better method, since itprovides for faster feedback and tighter control of the torqueby controlling the current with every PWM cycle. In this way,FOC ensures that current is inherently limited. An additionalbenefit is the ability to use a smaller motor without sacrificingtorque or speed, while running at higher efficiencies, provid-ing better dynamic response.

    Apart from enabling the use of a smaller motor, FOC canlower a motors energy consumption while providing betterefficiency. For example, FOC implemented within an ACinduction motor can improve motor efficiencies up to 25 per-cent beyond whats attainable in a non-field-oriented approach.The U.S. Department of Energy estimated that implementingenergy-saving techniques, such as FOC, can shave operatingmargins by 1 to 5 percent, significant when compared with thetypical plant operating margins of 16 percent.

    Science and ArtThere is a definite science and a little bit of art involved indesigning-in the most efficient motor and drive system for yourequipment. Choices can range from selecting the right sizemotor for the expected load to pushing the performance limitsusing a more-complex motor-control algorithm such as FOC.

    The benefits of increasing the efficiency of motor-controlledsystems start with lower manufacturing costs. Indeed, no mat-ter whether you are moving fluids, using a drill or controlling arobot arm, motor selection and control techniques will affectyour bottom line. Also, the environmental impact of reducingenergy consumption provides for more efficient use of the lim-ited natural resources available to us today.

  • Sinusoidal control, also known as volt-age-over-frequency commutation, addressesmany of these issues. A sinusoidal controllerdrives the three motor windings with cur-rents that vary smoothly. This eliminatestorque ripple issues and offers smooth rota-tion. The fundamental weakness of sinu-soidal commutation is that it attempts tocontrol time-varying motor currents using abasic proportional-integral (PI) controlalgorithm, and doesnt account for interac-tions between the phases. As a result, per-formance suffers at high speeds.

    Field-oriented control, also known asvector control, improves upon sinusoidalcontrol by providing high efficiency atfaster motor speeds. It delivers the highesttorque per watt of power input comparedwith the other control techniques, andallows precise and responsive speed controlwhen the load changes. FOC also guaran-

    tees optimized efficiency, even during tran-sient operation, by perfectly maintainingthe stator and rotor fluxes.

    A Deeper Look at FOC One way to understand how FOC works is toform a mental image of the coordinate refer-ence transformation process. If you picture anAC motor operation from the perspective ofthe stator, you see a sinusoidal input currentapplied to the stator. This time-variant signalgenerates a rotating magnetic flux. The speedof the rotor is a function of the rotating fluxvector. From a stationary perspective, the sta-tor currents and the rotating flux vector looklike AC quantities.

    Now, imagine being inside the motor andrunning alongside the spinning rotor at thesame speed as the rotating flux vector that thestator currents generate. Observing the motorfrom this perspective during steady-state con-

    ditions, the stator currents look like constantvalues and the rotating flux vector is station-ary. Ultimately, you want to control the sta-tor currents to obtain the desired rotorcurrents. With coordinate reference transfor-mation, you can control stator currents suchas DC values using simple PI-control loops.

    Under the hood, the FOC algorithmworks by removing time and speeddependencies and enabling the direct andindependent control of both magnetic fluxand torque. It accomplishes this by math-ematically transforming the electrical stateof the motor into a two-coordinate time-invariant rotating frame using mathemati-cal formulas known as the Clarke and Parktransformations.

    An efficient method to control thepower electronics, called space-vector pulse-width modulation (PWM), maximizes theusage of the motor supply voltage and min-

    30 Xcell Journal Third Quarter 2009


    Encoder Hall Effect Sensors Analog Sensors

    Velocity Measurement Digital Input SPI ADC Interface

    Lowpass Filters










    er R



    Field-Oriented Controller

    LCD Controller


    16x2 Character LCD

    PWMIGBT Pair

    PWMIGBT Pair

    PWMIGBT Pair S


    y In
















    LabVIEW FPGA IP Modules

    External Interfaces

    Figure 4 System diagram for FOC implementation using a Xilinx FPGA-based RIO hardware platform

    Field-oriented control, also known as vector control, improves upon sinusoidal controlby providing high efficiency at faster motor speeds. It allows precise and responsive

    speed control when the load changes and also guarantees optimized efficiency.

  • Third Quarter 2009 Xcell Journal 31

    imizes harmonic losses. Harmonics can sig-nificantly erode motor efficiency by induc-ing energy-sucking eddy currents in theiron core of the motor.

    Best of all, designers can utilize field-oriented control for both AC inductionand brushless DC machines to improveefficiency and performance. They can alsoapply FOC to existing motors by upgrad-ing the control system. In fact, they canemploy vector-control techniques likeFOC with AC induction motors to enableservo-motor-like performance.

    FPGAs Tackle FOC ChallengeIt takes powerful computation devices toimplement FOC, and this requirementmakes FPGAs a natural fit for motor con-trol. An FOC system must continuouslyrecompute the vector-control algorithm ata rate of 10 to 100 kHz. In parallel to thecontrol algorithm, additional intellectual-property (IP) blocks such as the high-speedPWM outputs need to execute withoutaffecting the timing of the control algo-rithm. With their inherent parallel execu-tion and hardware reliability, FPGAs areable to perform control algorithms withloop rates up to hundreds of kilohertz, withroom left over to handle communication

    and provide the data for user-interfaceapplications on the host microprocessor.Moreover, the reconfigurability of FPGAsallows the customer to adjust the controlalgorithm whenever necessary.

    Figure 4 illustrates a system for FOCimplementation using a Xilinx FPGA onthe National Instruments RIO platform.Besides the actual control algorithm, theFPGA executes IP blocks to read the threeHall-effect sensors, an encoder and threeadditional analog sensors as it generatesPWM signals that drive external electronicsto power the motor. For communication toa host processor and a simple user interface,IP blocks execute in parallel.

    Figure 5 shows the LabVIEW FPGAimplementation of the FPGA-based FOCalgorithm. The Clarke transformation con-verts the three-axis coordinates shifted by120 (Ia, Ib, Ic) into orthogonal two-axisones (Ia, Ib). In a second step, the Parktransformation converts the fixed (Ia, Ib)coordinates into decoupled two-axis rotat-ing coordinates (Id and Iq), which a simplePI controller can then control. The FOCsystem uses inverse Park and Clarke trans-formation to bring them back into thefixed AC three-phase frame of the statorwindings. NI provides the complete source

    IP at our IPNet Web site at ni.com/ipnet. One of our customers, electronic-sys-

    tem designer and manufacturer BAESystems Avionics, used our RIO platformwith Xilinx FPGAs to squeeze 15 percentextra performance from its existing motorswhile saving weight in avionics products byreducing motor mass. Thanks to the effi-ciency and tight power control of FOC, theBAE Servo Systems Technology Group inEdinburgh, Scotland, now specifies smallermotors than previously possible.

    Ultimately, machine-builder designrequirements insist