of 68/68
R Issue 63 First Quarter 2008 Xcell journal Xcell journal SOLUTIONS FOR A PROGRAMMABLE WORLD SOLUTIONS FOR A PROGRAMMABLE WORLD INSIDE At the Heart of Consumer and Automotive Innovation Marriage Made in Heaven? Scalable and Flexible In-Vehicle Networking Designing Portable Handsets Using CoolRunner-II CPLDs A High-Speed Broadcast Video Connectivity Solution INSIDE At the Heart of Consumer and Automotive Innovation Marriage Made in Heaven? Scalable and Flexible In-Vehicle Networking Designing Portable Handsets Using CoolRunner-II CPLDs A High-Speed Broadcast Video Connectivity Solution www.xilinx.com/xcell/ At the Heart of Innovation At the Heart of Innovation At the Heart of Innovation PROGRAMMABLE SYSTEMS EDITION

PROGRAMMABLE SYSTEMS EDITION Xcell - Xilinx · networks, flat-panel displays, mobile phones, global positioning systems, and the Internet, and we arrive at today’s automobile –

  • View
    2

  • Download
    1

Embed Size (px)

Text of PROGRAMMABLE SYSTEMS EDITION Xcell - Xilinx · networks, flat-panel displays, mobile phones, global...

  • R

    Issue 63First Quarter 2008

    Xcell journalXcell journalS O L U T I O N S F O R A P R O G R A M M A B L E W O R L DS O L U T I O N S F O R A P R O G R A M M A B L E W O R L D

    INSIDE

    At the Heart of Consumer and Automotive Innovation

    Marriage Made in Heaven?

    Scalable and Flexible In-Vehicle Networking

    Designing Portable HandsetsUsing CoolRunner-II CPLDs

    A High-Speed Broadcast Video Connectivity Solution

    INSIDE

    At the Heart of Consumer and Automotive Innovation

    Marriage Made in Heaven?

    Scalable and Flexible In-Vehicle Networking

    Designing Portable HandsetsUsing CoolRunner-II CPLDs

    A High-Speed Broadcast Video Connectivity Solution

    www.xilinx.com/xcell/

    At the Heart of InnovationAt the Heart

    of InnovationAt the Heart

    of Innovation

    P R O G R A M M A B L E S Y S T E M S E D I T I O N

  • Support Across The Board.™

    Add Functionality to Your Prototype Platform

    Available EXP Modules

    • EXP to P160 Adapter

    • EXP Prototype

    • Analog Devices EXP Adapter Module

    • Video EXP Module

    • High-Speed ADC EXP Module

    • High-Speed DAC EXP Module

    • Interface EXP Module

    EXP Baseboards

    • Xilinx Spartan-3A DSP Starter Kit

    • Xilinx Spartan-3 PCI Express Starter Kit

    • Xilinx Virtex-4 FX60 PCI Express Board

    • Xilinx Virtex-5 LX Development Kit

    • Xilinx Virtex-5 LXT PCI Express Board

    • Xilinx Virtex-5 SXT PCI Express Board

    Avnet Electronics Marketing introduces the EXP specification –

    a versatile expansion interface for FPGA development boards

    that allows designers to add application specific daughter

    cards and easily connect to FPGA I/Os.

    Key EXP Features

    • Royalty free, public domain specification

    • Full and half card options

    • 168 (full module) and 84 (half module) user I/O

    • Single-ended and differential pair signaling

    • High-performance: > 100 MHz single-ended and

    > 300 MHz differential

    Learn more about EXP at www.em.avnet.com/exp

    Enabling success from the center of technology™

    800-332-8638www.em.avnet.com

    © Avnet, Inc. 2007. Al l r ights reserved. AVNET is a registered trademark of Avnet, Inc.Al l other brand or product names are trademarks of their respect ive owners.

  • EmbeddedUnlock your future

    Enter the New Era of ConfigurableEmbedded Processing

    Adapt to changing algorithms, protocols and interfaces, by creatingyour next embedded design on the world’s most flexible systemplatform. With the latest processing breakthroughs at your fingertips,you can readily meet the demands of applications in automotive,industrial, medical, communications, or defense markets.

    Architect your embedded vision• Choose MicroBlaze™, the only 32-bit soft processor with a configurable

    MMU, or the industry-standard 32-bit PowerPC® architecture• Select the exact mix of peripherals that meet your I/O needs, and stitch

    them together with the new optimized CoreConnect™ PLB bus

    Build, program, debug . . . your way• Port the OS of your choice including Linux 2.6 for PowerPC or MicroBlaze• Reduce hardware/software debug time using Eclipse-based IDEs

    together with integrated ChipScope™ analyzer

    Eliminate risk & reduce cost• No worry of processor obsolescence with Xilinx Embedded Processing

    technology and a range of programmable devices• Reconfigure your design even after deployment, reducing support cost

    and increasing product life

    Order your complete development kit today, and unlock the futureof embedded design.

    ©2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

    www.xilinx.com/processor

    At the Heart of Innovation

    Get the Complete Embedded Solution

    Linux 2.6

    www.xilinx.com/processor

  • O

    L E T T E R F R O M T H E P U B L I S H E R

    Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124-3400Phone: 408-559-7778FAX: 408-879-4780www.xilinx.com/xcell/

    © 2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands includedherein are trademarks of Xilinx, Inc. All other trade-marks are the property of their respective owners.

    The articles, information, and other materials includedin this issue are provided solely for the convenience ofour readers. Xilinx makes no warranties, express,implied, statutory, or otherwise, and accepts no liabilitywith respect to any such articles, information, or othermaterials or their use, and any use thereof is solely atthe risk of the user. Any person or entity using suchinformation in any way releases and waives any claim itmight have against Xilinx for any loss, damage, orexpense caused thereby.

    Forrest CouchPublisher

    PUBLISHER Forrest [email protected]

    EDITOR Charmaine Cooper Hussain

    ART DIRECTOR Scott Blair

    DESIGN/PRODUCTION Teie, Gelwicks & Associates1-800-493-5551

    ADVERTISING SALES Dan [email protected]

    TECHNICAL COORDINATORS Kevin KitagawaKevin TanakaTamara SnowdenSilvia Gianelli

    INTERNATIONAL Piera Or, Asia [email protected]

    Christelle Moraga, Europe/Middle East/[email protected]

    Yumi Homura, [email protected]

    SUBSCRIPTIONS All Inquirieswww.xcellpublications.com

    REPRINT ORDERS 1-800-493-5551

    Xcell journal

    www.xilinx.com/xcell/

    Behind the WheelOne of the benefits of growing older is that you gain perspective. You have a longer time span fromwhich to observe change and gauge its relative positive and negative consequences.

    For example, I can remember that myparents’ new car came luxuriouslyequipped with an AM radio that hadchrome metal push-button tuning,electric windows, a driver’s-side powerseat that went forward and back, and areally cool telescoping radio antennathat magically raised and lowered intothe fender like some kind of futuristicspace vehicle.

    Cars back then were basically heavy electro-mechanical devices with a lot of chrome.

    Now fast-forward through a myriad of technologies ranging from personal computers, wirelessnetworks, flat-panel displays, mobile phones, global positioning systems, and the Internet, andwe arrive at today’s automobile – a highly sophisticated, computerized transportation system.

    What a trip!

    The Xilinx® Automotive (XA) product family is ideal for many advanced automotive electronicsmodules and systems, ranging from the latest driver assistance and infotainment systems toreconfigurable instrument clusters and electronic control unit gateways. Essentially, we helpmake the automobile environment more entertaining, informative, and productive.

    Xilinx is also responding to rapidly changing consumer product requirements in the low-cost,high-volume markets with domain-optimized PLDs, custom IP, and development boards, creatingsolutions for two key consumer product segments: displays and handsets.

    Today we are witnessing a convergence of high technologies that are changing forever the waywe communicate and do business with each other. Limited only by our imagination, there seemsno end in sight.

  • O N T H E C O V E R

    2525

    A U T O M O T I V E

    4040

    P O R T A B L E H A N D S E T S

    1515

    A U T O M O T I V E

    Marriage Made in Heaven?Creating standard automotive platforms with maximum differentiation.

    5353A U D I O / V I D E O

    A High-Speed Broadcast Video Connectivity SolutionXilinx Spartan-3E and Spartan-3A FPGAs, National Semiconductor PHY,and the Xilinx protocol stack provide a cost-effective and flexibleapproach to the challenges of multi-rate broadcast.

    Scalable and Flexible In-Vehicle NetworkingFPGAs and full IP solutions give automotive engineers options in optimizing their electrical architectures.

    Designing Portable HandsetsUsing CoolRunner-II CPLDs CPLDs can improve processor-based handsets.

    At the Heart of Consumer and Automotive Innovation Xilinx offers silicon, development tools, IP, middleware, and design services for the automotive electronics market while meeting the industry’s temperature, quality, and reliability requirements.

    1212 Cover

  • F I R S T Q U A R T E R 2 0 0 8 , I S S U E 6 3 Xcell journalXcell journalVIEWPOINTSLetter from the Publisher: Behind the Wheel ........................................................................5

    Wim Roelandts: Looking Ahead in 2008.............................................................................8

    Kevin Morris: Short Stack with Syrup................................................................................10

    Ivo Bolsens: Enabling Efficient Packet Processing................................................................66

    FEATURES

    CoverAt the Heart of Consumer and Automotive Innovation .........................................................12

    AutomotiveMarriage Made in Heaven?.............................................................................................15

    Block Matching for Automotive Applications on Spartan-3A DSP Devices ................................16

    A Compact Multimedia Display Development Platform for Automotive and Industrial Markets .........20

    Scalable and Flexible In-Vehicle Networking.......................................................................25

    Portable HandsetsDesigning GPS Systems Using CoolRunner-II CPLDs .............................................................29

    Decrease Processor Power Consumption Using a CPLD.........................................................32

    Supporting Multiple SD Devices with CPLDs .......................................................................37

    Designing Portable Handsets Using CoolRunner-II CPLDs ......................................................40

    Easing Design Challenges with CoolRunner-II CPLDs ............................................................43

    Audio / VideoDesigning Digital Displays with Spartan-3 Generation FPGAs ................................................46

    Taking Device DNA Technology to the Next Level ................................................................49

    A High-Speed Broadcast Video Connectivity Solution ...........................................................53

    RESOURCESTechnical Papers and Literature ........................................................................................58

    Automotive ECU Development Kit .....................................................................................59

    Spartan-3AN FPGA Starter Kit ..........................................................................................60

    CoolRunner-II CPLD Starter Kit..........................................................................................61

    Protect Your Brand with Spartan-3 Generation FPGAs ..........................................................62

    Titanium Dedicated Engineering .......................................................................................63

    WEB XCLUSIVESThese articles are available at: www.xilinx.com/publications/xcellonline/xcell_63/

    Implementing Industrial Ethernet....................................................................................Web

    Designing Efficient, Synchronized, and Reliable Motion Networks .......................................Web

    Speeding Up Control Automation with EtherCAT................................................................Web

  • by Wim RoelandtsCEO and Chairman of the BoardXilinx, Inc.

    Last year was yet another successful year forXilinx, with record sales of our 90-nm and65-nm devices in consumer and communi-cations applications. Nowhere was thisgrowth more evident than Asia, where rev-enues increased nearly 500 percent.* Ourcustomer base continues to expandthroughout Asia as more and more design-ers adopt Xilinx solutions to meet technicaland time-to-market demands.

    The year 2007 also brought the largestsingle order in our history: 8 millionunits for a single socket. As the million-unit orders continue, we envision a timewhere anyone who does logic design willconsider Xilinx. We are perhaps halfwaythere. Industry analysts project furthergrowth for PLDs as new requirementsthroughout the electronics industry forcethe need for flexible architectures that cancope with not only current applicationsbut future and possibly unknown fea-tures. As systems continue to increase incomplexity, designers will naturally makethe transition to a programmable fabric.

    8 Xcell Journal First Quarter 2008

    Looking Ahead in 2008Looking Ahead in 2008Xilinx is poised for growth in high-volume consumer applications.Xilinx is poised for growth in high-volume consumer applications.

    Viewfrom the top

  • Looking AheadIf economic conditions remain favorable,we anticipate yet another year of growth in2008, particularly in consumer, surveil-lance, automotive, and communicationsapplications. The flat-panel display marketis one of the fastest growing segments inthe electronics industry, thanks to declin-ing prices and government mandates pro-moting digital programming. FPGAs areplaying a key role in enabling many of thekey technologies behind the latest displays.

    In fact, our Spartan™ Generationdevices can be found in many of the lat-est flat-panel displays. This is a highgrowth market for Xilinx as panel makersexpand production capacities to meetconsumer demand. According to iSuppli,worldwide shipments of LCD and PDPTVs are expected to reach nearly 80 mil-lion units in 2009.

    With the ongoing threats to globalsecurity, demand for high-performancesurveillance video products continues togrow. Today’s surveillance video systemsmust not only record – they must analyzedata in real time. This requires higherquality video and DSP processing capabil-ities, something our devices are very goodat. This is a big opportunity for Xilinx anda major reason we’ve focused on constant-ly pushing the DSP performance capabili-ties of our FPGAs.

    In the automotive space, we’re seeingtremendous growth in driver assistanceapplications. Previously only available inhigh-end luxury cars, electronic driverassistance systems are making their wayinto the average vehicle. Market analystsexpect driver assistance system demand togrow by 5x between 2007 and 2012.

    Mobile devices also offer an excellentopportunity for PLDs as portable elec-tronic manufacturers continue to rushnew products to market. Today’s designersare now looking beyond the fixed archi-tecture of ASICs and ASSPs to discoverthe innate design flexibility and time-to-

    ality, and other functions suited to specificapplication requirements.

    Xilinx will continue to expand its effortsin delivering optimized solutions for abroad set of markets and applications. Inaddition to providing just the right amountof features in our silicon, we’re workinghard to provide just the right amount of IP,design tools, and peripherals required todeliver an “out-of-the-box” solution.

    *Source: Xilinx Financials, September quarter FY08 versus September quarter FY06.

    market benefits of programmable logic.Rather than demanding higher perform-ance, consumers now demand ease of use –the iPhone is an excellent example. PLDsallow designers to differentiate their prod-ucts with ease-of-use features while provid-ing faster time to market.

    Finally, in the communications sector, webelieve that growth will accelerate as wirelessservice providers continue their quest toupgrade the infrastructure and triple play con-tinues to be deployed. Next-generation basestation deployments must conquer the chal-lenge of continually reducing cost (as meas-ured by cost per channel) while at the sametime adding increased functionality to sup-port new services, protocols, and changingsubscriber usage patterns. Programmablelogic is the ideal solution for wireless base sta-tions, providing not only a flexible designplatform but allowing service providers tomake future upgrades from a remote location.This can literally save millions in the long run.

    ConclusionXilinx pioneered the industry’s transfor-mation toward a focus on vertical marketsand engaging with customers at a systemarchitecture level. Today, this transforma-tion lets us address our customer’s com-plex design challenges by providing themwith innovative, flexible, and compellingsolutions that help them achieve theirobjectives of cost management, time tomarket, and leadership.

    And while the beauty of programmablelogic is its flexibility – PLDs can be used invirtually any electronic system so there is noimmediate need to develop new products tomeet the demand of any specific “hot”application – providing just the right mix offeatures for a given application is a great wayto reduce system cost. By optimizing ourdevices for a given domain, we offer thebroadest range of solutions in the industry,providing a unique mix of core capabilities,such as logic, memory, parallel and serialI/Os, embedded processors, DSP function-

    First Quarter 2008 Xcell Journal 9

    On November 14, 2007, the board of direc-tors of the Semiconductor IndustryAssociation (SIA) elected Willem ("Wim") P.Roelandts, chairman, president and CEO ofXilinx, as its 2008 board chairman.Roelandts succeeds Richard Templeton, pres-ident and chief executive officer of TexasInstruments. Hector de J. Ruiz, chairman andCEO of AMD, was elected vice chairman.

    "Wim Roelandts and Hector Ruiz bringmany years of leadership in the micro-electronics industry to the positions ofchairman and vice chairman of the SIAboard," said SIA President George Scalise."That experience will be invaluable as thesemiconductor industry continues itsefforts to secure additional funding foruniversity research, immigration, andeducation reform to ensure access to ahighly skilled workforce, and tax reformto level the global playing field.

    "Leadership in innovation is the key toleadership in technology," said Roelandts."The SIA public policy agenda is focused onensuring that the U.S. has a business cli-mate that encourages and supports innova-tion. I welcome the opportunity to be aspokesman for our innovation agenda."

    Xilinx Chief Willem Roelandts

    Elected SIA Chairman

    The beauty of programmable logic is its flexibility to meet the demand of any specific “hot” application.

    V I E W F R O M T H E T O P

  • by Kevin MorrisEditor – FPGA and Structured ASIC Journal [email protected]

    Non-volatile FPGAis one of today’s odd-est market segments.

    Bound by the ill-defined characteristic of“non-volatility,” the field of availabledevices is diverse from the ground up,with strikingly different architectures,approaches, and benefits.

    Actel, long the leader in non-volatileFPGAs, began with antifuse technology(which is one-time programmable) and fol-lowed later with flash-based FPGAs.QuickLogic fielded an antifuse-typeapproach from the beginning, and LatticeSemiconductor joined the fray over a yearago with their LatticeXP hybrid devices,embedding a flash boot PROM on theFPGA for rapid, on-chip configuration.

    With the new, non-volatileSpartan™-3AN family, it is clear thatXilinx approached the non-volatile prob-lem differently. Often, on your board,you’d pair a low-cost SRAM FPGA like aSpartan-3 device with a commodity flashmemory for storing the bitstream and pos-sibly other user data. Xilinx just took thedie for that flash memory and the die forthat FPGA, stacked them using packagingtechniques now common in cell phonesand other space-constrained devices, anddropped them into a single package. Voila!A non-volatile FPGA.

    Hey, wait, that’s totally cheating, isn’t it?Does stacking the two die vertically insteadof horizontally on your board somehowchange a regular-old volatile SRAM FPGAinto a newfangled non-volatile one? Aren’t

    there rules about these things? Somebodybring in a referee. What’s the catch?

    In reality, there is no “catch.” Like anyengineering solution to a problem, there aretrade-offs. To understand the ones involvedin Spartan-3AN FPGAs, we need to exam-ine our possible reasons for wanting a non-volatile FPGA in the first place, and thensee how the various options stack up.

    As long as we don’t pop open the pack-age and start asking too many questions(we’ll discuss opening the package later, sokeep those Dremel tools powered down forthe moment, lil’ hacker dudes), we canassume that a non-volatile FPGA is one thatdoesn’t require an external boot PROM.You apply power to the pins and (after sometime passes) the FPGA is ready to go, inde-pendent of any other devices on the board.

    Why do we care? Well, wemight want the smaller footprintof a single chip. We might wantsimpler board design. We mighthope for lower power consump-tion. We might want additionaldesign security. We might be try-ing to reduce total BOM cost.We might want instant (or near-instant) power on. Comparedwith Spartan-3A devices, howdoes the new Spartan-3AN fam-ily do on these issues? Yes, yes,no, sorta, and probably not.

    Xilinx Spartan-3AN FPGAsare available in a subset of thepackage options of theSpartan-3A family. Probablybecause the stacked-die pack-aging process is more expen-sive, Xilinx isn’t rolling out theentire fleet of packages forSpartan-3AN devices. The

    company says they will probably be addingadditional packaging options based oncustomer demand, so if the package youwant is not on the list – vote early andoften. The good news is that the packageyou choose will be the only FPGA-relatedthing you have to buy, inventory, place,and connect to your board. You won’t needa separate boot PROM as you would withan SRAM-based FPGA. Board real estateand complexity is definitely reduced.

    The FPGA portion of a Spartan-3ANdevice has the same power consumption as acorresponding 90-nm Spartan-3A devicebecause – hey, it’s the same die. As a review– Spartan-3A devices have some nicepower-saving features for an SRAMFPGA. Its 90-nm technology gives it prettygood dynamic power consumption. In addi-

    10 Xcell Journal First Quarter 2008

    Short Stack with SyrupLooking between the layers of the non-volatile Spartan-3AN family.

    First appeared in FPGA and Structured ASIC Journal (www.fpgajournal.com). Copyright Techfocus Media, Inc. Reprinted with permission.

  • tion, Spartan-3A devices (and thus alsoSpartan-3AN devices) have two additionalpower modes called “Suspend” and“Hibernate” that allow you to drop static(standby) power by 40% with a fast wake-up time (suspend mode) or by 99% with a“normal” wake-up time (hibernate mode).This means that the device is still morepower-hungry than other super-low-powernon-volatile FPGAs like QuickLogic’sPolarPro or Actel’s Igloo, but it maintainsother advantages. (Remember what we saidabout trade-offs?)

    The flash portion of the Spartan-3ANFPGA will, of course, have the samepower profile as the commodity flashmemory device that it is. If you droppedone of those on your board next to aSpartan-3A device, your total power char-acteristics should be almost identical. Onecould argue that having the flash separategives you more options on the flash sidethan defaulting to the built-in flash inSpartan-3AN FPGAs. If one argued that,one would be correct.

    Security RisksDesign security is one of the issues mostoften cited for wanting a non-volatileFPGA over a conventional SRAM design.The important thing to remember here isthat security is relative. Every option avail-able on the market provides differingamounts and types of security. Almostnothing can protect against the best-fund-ed security risks such as those funded bygovernments. As you move down the scaleon attackers’ budgets and time constraints,however, security measures start to shakeout at different levels.

    The biggest design security risk withSRAM-based FPGAs is the availability ofthe configuration bitstream going betweenthe boot PROM and the FPGA duringstartup. Since FPGAs are standard parts, ifthe contents of the boot PROM can becloned, the design is stolen. The normal wayto deal with this is to encrypt the bitstreamin the boot PROM, and to have an encryp-tion key stored in the FPGA that will allowthe bitstream to be decrypted upon load.The problem with SRAM (and non-volatiledevices in general) is that any encryption key

    It’s also important to look at Spartan-3AN devices in comparison with othernon-volatile options. After all, from a mar-keting perspective, the Spartan-3ANFPGA is probably most important becauseit gets Xilinx into the non-volatile FPGArace. Before, a list of non-volatile FPGAvendors would have included Actel (fortheir antifuse and flash-based devices),QuickLogic (for their antifuse devices),Lattice (for their LatticeXP hybrid devices)and arguably even Altera for their Max II(which is really an FPGA marketed as aCPLD). Now, that list includes Xilinx withthe Spartan-3AN family.

    With a 90-nm SRAM-based FPGA atits core, Spartan-3AN devices will be fasterand have higher density than the otherentrants. Because it uses commodity flashbonded to the FPGA, it will offer morenon-volatile storage than the otherentrants. On the down-side, it will takelonger to configure (in the range of 100milliseconds because of streaming the con-figuration over a serial flash versusmicroseconds or even near-zero for trulynon-volatile devices like antifuse andActel’s flash). It will likely be less securethan the other options, and although itspower consumption will be very good, itwill consume more power in both activeand standby modes than the other non-SRAM alternatives.

    The Spartan-3AN family offers devicesranging from 50K to 1.4M “system gates”(corresponding with Spartan-3A devicesXC3S50A to XC3S1400A) with flash mem-ory ranging from 1M to 16M. Three of thedevices, the XC3S200AN, XC3S700AN,and XC3S1400AN are available now, withthe remaining devices (XC3S50AN andXC3S400AN) slated for second quarter.

    Xilinx Spartan-3AN FPGAs are likelyto be popular in space-, cost-, and power-constrained high-volume applicationsthat need some of the features of non-volatile FPGAs with the performance anddensity of leading-edge SRAM devices. Inaddition to bringing Xilinx officially intothe non-volatile game, the unique charac-teristics of the Spartan-3AN family givesus another valuable trade-off point in ourFPGA selection.

    stored in SRAM is lost when the device ispowered down. This leaves us with a prob-lem in moving encrypted bitstreams thathas been addressed two ways: 1) by attach-ing an external battery to the device tomaintain the encryption key and 2) byadding permanent fuses to each device forstoring the encryption key.

    The Spartan-3AN device does neitherof these. Not exactly, anyway. There is apermanent serial number stored in eachdevice, and that serial number can beused to implement various securityschemes as you see fit. It is not, however,used to decrypt the incoming bitstream.Bitstream protection is done by obscur-ing the connection between the FPGAand the boot PROM (now stacked ontop of the FPGA inside a single package).While more secure than a separate bootPROM, the scheme is still far fromimpermeable as far as configurationstream protection goes. (OK, you can fireup those Dremel tools now.)

    Because the Spartan-3AN FPGA hasroom for two complete configurations inthe flash, it’s obvious that Xilinx thinksyou’ll be updating the bitstream at somepoint in the product life cycle. TheSpartan-3AN device even has a nice fea-ture that’ll let it boot on the original “gold-en” bitstream if a bad download or othercorruption causes the new, updated one tomalfunction. The problem is, any mecha-nism you have for delivering an updatedbitstream to the device will be snoopableby prying eyes (or prying logic analyzers,really). The bitstream obscuring methoddoesn’t hold up as well when the bitstreamhas to travel from your home base to thedevice in the field. Be sure to design yoursecurity scheme accordingly.

    As far as the lower cost question goes,you’ll probably pay a bit of a premium forSpartan-3AN devices compared with thesame Spartan-3A device with the sameflash memory. When you factor in theother costs of an additional device such asboard area and inventory and such, it maybe a wash. On the positive side, you cer-tainly won’t be taking a big BOM hit forusing the new family. Xilinx projects pricesin the $5 range in volume.

    First Quarter 2008 Xcell Journal 11

  • by Kevin M. KitagawaDirector, Worldwide Marketing, High-Volume ProductsXilinx, [email protected]

    As we move toward an increasingly digitalworld, consumers want to experience con-tent such as audio, video, and data anytimeand anywhere. Better and inexpensive wiredand wireless infrastructure is available todeliver content for a better consumer experi-ence, and product manufacturers are consis-tently challenged to come up with newinnovations to improve that experience.

    As an example, digital music players,HDTV digital displays, automotive elec-tronics, cell phones, and broadband Internetaccess have all changed consumer expecta-tions and behavior on how to access andexperience content at home, in the car, or onthe move. Predicting which innovations willbe successful often requires potentially riskyproduct decisions, and manufacturers aretrying to incorporate feedback directly fromconsumers into product development cyclesearly to ensure success of their products.This often translates to the need for quickproduct development cycles to get innova-tive products to market quickly.

    The initial costs of developing ASICshave been exponentially rising with eachprocess geometry shrink, making this pathless attractive for most applications. Also,

    ASSPs typically cannot meet theneeds of every customer, and siliconmanufacturers must make compro-mises to implement the featurescustomers request the most.

    Xilinx® FPGAs and CPLDs are atthe heart of innovation. These productsprovide flexible yet low-cost solutions tomeet the application-specific requirementsof high-volume products such as digital dis-plays, set-top boxes, automotive rear-seatentertainment systems, smartphones, andvideo equipment.

    Xilinx in Consumer ElectronicsConsumer electronics manufacturers needto differentiate their products from theircompetitors. They are often driven to deliv-er the latest technologies and innovationsas quickly as possible to the consumer tostay ahead in a highly competitive market-

    place. Later in theproduct life cycle, manu-facturers focus on driving productcosts down to deliver more and morevalue at lower prices to the consumer.

    As an example, HDTV digital displaymanufacturers are challenged with the evo-lution of new flat-panel technologies andinterface standards while trying to improveimage quality to address any shortcomings

    12 Xcell Journal First Quarter 2008

    At the Heart of Consumerand Automotive InnovationXilinx offers silicon, developmenttools, IP, middleware, and designservices for the automotive electronics market while meeting the industry’s temperature, quality,and reliability requirements.

    C O V E R S T O R Y

  • Xilinx in Automotive ElectronicsNew and future vehicles are increasinglyreliant on electronics in order to allowOEM automakers to differentiate theirproducts. These electronics systems rangefrom driver information and rear-seat enter-tainment systems to newer driver-assistancetechnologies such as night-view and lane-departure warning systems.

    The Xilinx Automotive (XA) family ofproducts brings the scalability and flexibilityof FPGAs and CPLDs to the automotiveelectronics market, allowing automotivetier-ones to bring out innovative featureswhile also giving them platform develop-ment capabilities (even in a fragmentedapplication sector), thus lowering costs.

    With the increasing use of LCD/TFTdisplays, multiple networking protocols,video, and graphics, Xilinx XA solutionsallow for quick development cycles and flex-ibility of customization through to produc-tion. By using Xilinx XA programmablelogic, automotive tier-ones can quickly addnew features, improve existing features, orchange interfaces simply by making changeswithin the FPGA fabric without needing towait years until the next time the electronicsare redesigned. FPGAs also allow designersto look again at their overall applicationarchitecture and build systems based on theirneeds instead of what is available in semi-conductor hardware today.

    ConclusionWith Xilinx high-volume Spartan,CoolRunner™-II CPLD, and XA productfamilies, manufacturers can afford to delivermore innovative products quickly to market,knowing that they have the flexibility of pro-grammable logic minimizing their risk.

    Decreasing costs from our suppliers,along with leading-edge technology, haveallowed us to extend lower prices to our cus-tomers, accelerating our success in high-vol-ume design wins moving into production.With cost points starting in the low singledigits, Xilinx FPGAs and CPLDs can elimi-nate the need to move to ASICs or ASSPs inproduction in high-volume applicationssuch as consumer or automotive electronics,while still allowing endless customization tomeet your customer requirements.

    in the quest to deliver the perfect TV pic-ture. Variations in panels used in differentmodels often have different specifications oreven different suppliers.

    FPGA programmability enables manufac-turers to easily accommodate these variationsusing image-enhancement algorithms imple-mented in a Spartan™ FPGA and allowingthe same hardware design to be utilized in awhole family of products. Native support formost differential I/O interfaces in SpartanFPGAs makes it easy to directly interface withthe new panel interfaces. These advantagesmake Spartan FPGAs a compelling option inmany consumer electronics products.

    First Quarter 2008 Xcell Journal 13

    C O V E R S T O R Y

  • Xilinx is Driving Automotive Solutions

    Xilinx is Driving Automotive Solutions

    As the automotive electronics market grows inthe areas of infotainment, driver assistance, anddriver information systems, Xilinx® devices areat the heart of each new innovation.

    ■ Image Processing and Recognition –Offering faster development and product dif-ferentiation for driver assistance applications.

    ■ Video and Graphics – Allowing for highly scalable and cost-efficient implementations of infotainment and driver information systems.

    ■ Application Development Platforms –Providing developers a quick start andserving as a comprehensive hardwarebase to satisfy their expectations.

    ■ Xilinx Technology Leadership –Leading the way in programmable logicdevices, one of the fastest growing segments of the semiconductor industry.

    ■ Vehicle Networking – Designingand supporting key automotive-specificnetwork interfaces.

    As the automotive electronics market grows inthe areas of infotainment, driver assistance, anddriver information systems, Xilinx® devices areat the heart of each new innovation.

    ■ Image Processing and Recognition –Offering faster development and product dif-ferentiation for driver assistance applications.

    ■ Video and Graphics – Allowing for highly scalable and cost-efficient implementations of infotainment and driver information systems.

    ■ Application Development Platforms –Providing developers a quick start andserving as a comprehensive hardwarebase to satisfy their expectations.

    ■ Xilinx Technology Leadership –Leading the way in programmable logicdevices, one of the fastest growing segments of the semiconductor industry.

    ■ Vehicle Networking – Designingand supporting key automotive-specificnetwork interfaces.

    For more information on Xilinx automotive products, visit

    www.xilinx.com/automotiveFor more information on Xilinx automotive products, visit

    www.xilinx.com/automotive

  • by Nick DiFioreGeneral Manager, Automotive DivisionXilinx, [email protected]

    Within the Automotive Business Divisionof Xilinx, we are very excited by the changeswe see coming. Programmable logic isdeveloping rapidly, as are the requirementsof the automotive market. These changesare providing some great opportunities tocreate solutions to complex problems cur-rently plaguing automotive design.

    The advantages of programmable logichave always been flexibility, scalability, andfast time to market. Today, these are advan-tages of key value in the automotive elec-tronics market, as consumer products withhighly complex and varying networkingand interface standards are introduced intovehicles at a rate never seen before.

    Vehicle differentiation and high value-add is often provided by the OEMsthrough the electronics, but at the sametime, engineering resource and time con-straints mean that tier ones need to supplycommon platforms and reusable designs.PLDs in automotive electronics make for agreat partnership, but like all partnerships,there are also many challenges.

    As a new technology in this market, thefirst challenge is in providing not just cut-ting-edge silicon, but full solutions todemonstrate and prove the technology outto our customers. To achieve this goal, wehave made a large investment at Xilinx torecruit both highly experienced automotivesystem architecture engineers and veteranautomotive semiconductor personnel towork directly with customers and deter-mine what silicon and solutions would be atrue value-add in this market. We have alsoinvested in engineers to develop IP both

    internally and externally through ourLogiCORE™ IP and automotiveAllianceCORE programs.

    To continue our own learning and alsodrive the market forward, Xilinx has joineda number of consortiums, such asAUTOSAR, JASPAR, the FlexRayConsortium, and the MOST Cooperation.By doing this, we have been able to puttogether an arsenal of fully scalable in-vehi-cle networking and video/graphics solutions.

    These critical investments have resultedin complete solutions for applications,such as video displays (“A CompactMultimedia Display DevelopmentPlatform for Automotive and Industrial

    Markets,” also in this issue of Xcell Journal),driver assistance systems (“Block Matchingfor Automotive Applications on Spartan-3A DSP Devices” in this issue), and a flex-ible Xilinx MOST solution (see ourdemonstration at CES).

    The second challenge is in meeting thevery high-quality and reliability standardsthat the automotive market requires of

    semiconductor suppliers. The advan-tages of working with automotive cus-

    tomers were recognized at the veryhighest levels of management

    within Xilinx. By achievingISO-TS16949 certification,implementing the AEC-Q100 qualification stan-dard, and creating a

    separate XA line of productsin order to control bill-of-mate-

    rials (BOM) and production sites,we can improve the quality and logistic

    processes for all of our customers andensure that we are on the path of continu-ous improvement, which is a key part ofour corporate philosophy.

    The last four years of the automotiveXA program at Xilinx have been both chal-lenging and exciting, but our success inbecoming the number-one programmablelogic supplier (based on Semicast data) inthe automotive electronics market showsthat we are on the right track.

    Our next challenge is to ensure thateven with all of the possible opportunitiesthere are for programmable logic, we con-tinue to work closely with our automotivecustomers to ensure that we focus on theright solutions to meet their future needs inarchitecture and design.

    First Quarter 2008 Xcell Journal 15

    Marriage Made in Heaven?Creating standard automotive platforms with maximum differentiation.

    A U T O M O T I V E

  • by Daniele Bagni DSP SpecialistXilinx, Inc. [email protected]

    Paul ZorattiAutomotive Senior System ArchitectXilinx, [email protected]

    Automotive engineers are adaptingnumerous intelligent technologies toassist humans in operating vehicles safely.Prominent technologies in vehicle systemsinclude radar-, ultrasonic-, and camera/vision-based sensing. Collectively referred toas driver assistance (DA) systems, these tech-nologies are designed to facilitate safe driv-ing during adverse conditions andpotentially dangerous roadway situations.

    The first generation of camera-basedDA systems is now available on a varietyof production vehicle models. The major-ity of such systems provide drivers with avideo image of the environment aroundthe vehicle. The most prevalent systemsare parking/backup aids that use a rear-facing camera to capture the scene behindthe host vehicle and display the image ona radio/navigation system screen, or on asmall display in the instrument cluster.

    A second generation of camera-basedsystems is in development and testing,with some limited deployment. Ratherthan merely providing an image to driv-ers, these second-generation systemsapply image processing and analytics toextract information from the videostream and characterize and evaluate thevehicle environment. If warranted, thedriver receives an appropriate warning.

    As engineers gain real-world experi-ence in characterizing the vehicle envi-ronment, future DA techniques willincrease in complexity, offer greater utili-ty to consumers, and enhance the per-formance of other vehicle subsystems.Figure 1 summarizes the variety of cur-rent and future DA features.

    Advanced Processing RequirementsProcessing requirements for DA systemscan exceed the capabilities of currentautomotive-grade serial DSP processors.In addition, a growing need exists to bun-dle multiple DA features together, basedon a single suite of vision sensors to driveconsumer value.

    For example, a forward-looking visionmodule may need to simultaneously sup-port lane departure warning, intelligentheadlamp control, and sign recognitionfunctionality – all of which require differ-ent processing algorithms. Therefore, theDA market offers a real opportunity forFPGAs to provide system value throughraw processing performance, configurationflexibility, and device scalability.

    Image processing and analytics function-ality for vision-based DA schemes caninclude spatial/temporal filtering, lens-dis-tortion correction, image sharpening, con-trast enhancement, edge detection, patternmatching, object recognition, object track-ing, and, in some cases, graphical overlay. Ofparticular interest is a form of pattern-matching functionality that supports motionestimation or stereo disparity calculations.

    To illustrate the performance value ofFPGA processing, consider the followingvision-based system: a wide-VGA resolu-tion imaging device (752 x 480 pixels) gen-erating video at a 30-Hz frame rate (fps),and the need to estimate the motion (orflow) of objects from one frame to another.One algorithmic approach – also suitablefor stereo ranging disparity calculations –is to partition the image into blocks (say,4 x 4 pixels in size) and evaluate a matchcriteria for each block in the first frame toa location in the second frame over a spec-ified search area (say, 20 x 20 pixels).

    A common match criteria is to findthe minimum absolute error (MAE) ofthe pixel intensities between the 4 x 4

    16 Xcell Journal First Quarter 2008

    Block Matching for AutomotiveApplications on Spartan-3A DSP DevicesThe Spartan-3A DSP FPGA outshines VLIW DSP-CPUs in automotive driver assistance applications.

    A U T O M O T I V E

  • block in the first image and the pixelswithin the search area on the secondimage by using an operator called SAD(sum of absolute differences).

    Our 4 x 4 block matching examplerequires more than 250 MMAE/s (millionsof MAE calculations per second), since(752 pixels) x (480 lines) x (20 x 20 pixelsearch area) x (30 fps) / (4 x 4 pixel blocksize) = 270,720,000 MAE/s. MAE indi-cates the final matching error of a 4 x 4pixel block, whereas SAD refers to the sumof absolute differences calculation on fourindividual pairs of elements. Therefore,every MAE requires four SAD operations.

    Processing OptionsProcessing options at the automotive designengineer’s disposal include very longinstruction word (VLIW) DSP-CPUs andFPGAs. FPGAs offer dramatically higher

    CPU, thus efficiently executingthe equivalent of 11 elemen-tary instructions in only onecycle, as shown in Figure 2.

    For example, the NexperiaPNX1500 media processorequipped with the TriMedia32-bit VLIW-CPU can imple-ment two quadruple SADinstructions on a single clockcycle for 8-bit pixels with twocycles of latency. Associatedwith every long instructionword are as many as five ele-mentary RISC/SIMD instruc-

    tions per clock cycle, of which only twocan be SAD (named “8meii” in theTriMedia databook).

    Therefore, the MAE on a 4 x 4 block sizewould require five clock cycles, as shown inTable 1: two cycles for pipelining twoquadruple SADs (cycle 1 for sad1/sad2,cycle 2 for sad3/sad4) and three cycles foraccumulating the partial results (cycles 3, 4,and 5). Hence, a 300-MHz NexperiaPNX1500 processor could compute a peakof 60 MMAE/s if processing a single block.

    By processing more than one 4 x 4 blockat a time, the peak performance canimprove a little. For example, the MAE oftwo 4 x 4 blocks in parallel could be com-puted in seven cycles, thus achieving 85.71MMAE/s, and three blocks could beprocessed in nine cycles, or 100 MMAE/s.

    The maximum amount of blocks thatcan be processed in parallel is limited firstby the number of SIMD SAD operationsallowable in any long instruction word;second by the number of general-purposeregisters of the VLIW-CPU; and third bythe scheduling algorithms of the optimiz-ing compiler. Overall performance goesinto saturation when adding more blocks,which is why we do not consider more thanthree MAEs processed in parallel.

    The Texas Instruments (TI)TMSD320DM6437 digital media proces-sor has a long instruction of eight elemen-tary RISC operations per cycle throughtwo separated data paths: each one of fourslots per cycle. Its VLIW-CPU can executeas many as two SAD instructions per cycle(named “subabs4” in the TI DM6437

    processing capability than any existingVLIW DSP-CPU. This is because of thearchitecture of the FPGA: the large amountof functional units in parallel (includingprogrammable MACs) allows the FPGA toachieve 10-30 times better performancethan that offered by any DSP, depending onthe application implemented, even if theclock frequency of the FPGA is much lowerthan the clock frequency of the DSP-CPU.Using the block-matching operationexample, we will demonstrate that Xilinx®

    FPGAs have superior performance to anyVLIW DSP-CPU processor.

    SAD and MAE Calculations in VLIW DSP-CPU ProcessorsA SAD operation on four elements of 8-bitpixel video data could be implemented in asingle-instruction-on-multiple-data(SIMD) within a 32-bit architecture DSP-

    First Quarter 2008 Xcell Journal 17

    Awareness Warning Temporary Control

    Panic Brake AssistLane Departure Warning

    Front Collision Warning

    Back-Up Warning Aid

    Pedestrian Detection

    Drowsy Driver

    Blindspot Detection

    Sign Recognition

    Park/Back-Up Assist

    Lane Change Assist

    Night Vision

    Pre-Crash Sensing

    Side Impact Detection

    Pedestrian Protection

    Automatic Braking

    Lane Keeping

    Adaptive Cruise Control

    Automated Parking

    Convenience Oriented

    Safety Oriented

    Performance Enhancement

    Driver Assistance Features

    unsigned unsigned unsigned

    unsigned

    unsigned unsigned unsigned unsigned unsigned

    src1 (32-bit unsigned)

    dst (32-bit unsigned)

    SAD performs 11 RISC operations

    src2 (32-bit unsigned)

    --

    --

    ||||

    +

    ++

    ||||

    Figure 2 – An example of SIMD: SAD operation on a quadruple of 8-bit samples

    Figure 1 – Driver assistance features

    A U T O M O T I V E

  • databook), each with a latency of onecycle. However, to accumulate the partialresults, a three-cycle latency SIMD MACoperation must be performed (named“dotpsu4”), with a constant 0x01010101.

    Therefore, a 600-MHz TI DM6437DSP-CPU could compute an MAE inseven cycles (as shown in Table 2), thusachieving a peak performance of 85.71MMAE/s for 4 x 4 pixel blocks. If twoblocks are processed in parallel, we getnine cycles and 133.33 MMAE/s, whereasfor three blocks we get 11 cycles and163.64 MMAE/s – again lower than our250 MSAD/s requirement.

    De-Rating VLIW DSP-CPU PerformanceThus far, we have assumed 8 bits per pixel,which is very suitable for 32-bit architec-ture DSP-CPU processors. However, newCMOS image sensors have a higher resolu-tion range: 12 to 14 bits per pixel. For thesedata types, the classic quadruple 8-bit sub-words SIMD of 32-bit architectures are lesseffective and must be replaced by dual 16-bit half-words SIMD, in which the sub-

    word parallelism is only two. Therefore,peak performance degrades significantly,because more clock cycles are necessary tocompute an MAE.

    Table 3 shows what could be the pseu-do assembly code of the SAD computa-tion on the TI VLIW DSP-CPU whenusing 16-bit sub-word instructions, con-sidering the correct latency and the func-tional issue slot able to deliver suchinstructions. As a result, eight cycles arenecessary for one 4 x 4 block while 10and 12 cycles are required, respectively,for two and three blocks processed in par-allel. Corresponding peak performance isthen 75 MMAE/s, 120 MMAE/s, and150 MMAE/s. All of these numbers aresmaller than the ones achieved with 8-bitsub-word instructions.

    Spartan-3A DSP FPGA SAD and MAE Performance To fill the processing performance gapbetween Spartan™-3 and Virtex™-4devices, Xilinx introduced the Spartan 3A-DSP 1800A and 3400A FPGAs. These

    devices incorporate a modified version ofthe DSP48 slices found in Virtex-4 devices.In addition, 3A-DSP parts include a largernumber of on-chip memory (block RAMs).Both of these enhancements, along with aprice point suited to high-volume applica-tions, make 3A-DSP devices a good fit forautomotive vision-based DA systems.

    Figure 3 shows the scheme of SAD com-putation for a quadruple of 12-bit pixels onthe Spartan-3A DSP 1800 (XC3SD1800A-4FG676) device. This implementation wasdone with the System Generator for DSPdesign flow (a bit-true, cycle-accurate, syn-thesizable library provided by Xilinx in theSimulink tool). The amount of resourcesrequired is 121 slices (236 LUTs and 140flip-flops). By replicating this structure fourtimes and adding the partial results, we getthe scheme for a whole 4 x 4 block, whichrequires 508 slices (990 flip-flops and 606LUTs) with a throughput of one (whichmeans that at any clock cycle we can startthe computation of a new MAE) and alatency of seven cycles.

    Utilizing a 150-MHz clock frequency(of the maximum 250 MHz the devicecould achieve), we would need only twoparallel structures occupying approxi-mately 6% of the device area to achieve300 MMAE/s and meet the 250 MMAE/srequirement of our example application.This leaves ample resources available toimplement other image processing func-

    18 Xcell Journal First Quarter 2008

    Cycle 1

    Cycle 2

    Cycle 3

    Cycle 4

    Cycle 5

    Slot 3

    sad2=8meii(A2,B2)

    sad4=8meii(A4,B4)

    nop

    nop

    nop

    Slot 2

    nop

    nop

    nop

    nop

    nop

    Slot 4

    nop

    nop

    nop

    nop

    nop

    Slot 5

    nop

    nop

    nop

    nop

    nop

    Slot 1

    sad1=8meii(A1,B1)

    sad3=8meii(A3,B3)

    sad12=sad1+sad2

    sad34=sad3+sad4

    tot=sad12+sad34

    Cycle 1

    Cycle 2

    Cycle 3

    Cycle 4

    Cycle 5

    Cycle 6

    Cycle 7

    Slot 1

    L1

    d1=subabs4(A1,B1)

    d3=subabs4(A3,B3)

    nop

    nop

    nop

    sad13=sad1+sad3

    tot = sad13+sad24

    Slot 2

    S1

    nop

    nop

    nop

    nop

    nop

    nop

    nop

    Slot 3

    M1

    nop

    sad1=dotpsu4(d1, 0x01010101)

    sad3=dotpsu4(d3, 0x01010101)

    nop

    nop

    nop

    nop

    Slot 4

    D1

    nop

    nop

    nop

    nop

    nop

    nop

    nop

    Slot 5

    L2

    d2=subabs4(A2,B2)

    d4=subabs4(A4,B4)

    nop

    nop

    nop

    sad24=sad2+sad4

    nop

    Slot 6

    S2

    nop

    nop

    nop

    nop

    nop

    nop

    nop

    Slot 7

    M2

    nop

    sad2=dotpsu4(d2, 0x01010101)

    sad4=dotpsu4(d4, 0x01010101)

    nop

    nop

    nop

    nop

    Slot 8

    D2

    nop

    nop

    nop

    nop

    nop

    nop

    nop

    Cycle 1

    Cycle 2

    Cycle 3

    Cycle 4

    Cycle 5

    Cycle 6

    Cycle 7

    Cycle 8

    Slot 1

    L1

    d1=sub2(A1,B1)

    ad1=abs2(d1)

    ad3=abs2(d3)

    z13=add2(ad1, ad3)

    nop

    nop

    nop

    tot = s13 + s24

    Slot 2

    S1

    d3=sub2(A3,B3)

    nop

    nop

    nop

    nop

    nop

    nop

    nop

    Slot 3

    M1

    nop

    nop

    nop

    nop

    s13=dotp2(z13, 0x00010001)

    nop

    nop

    nop

    Slot 4

    D1

    nop

    nop

    nop

    nop

    nop

    nop

    nop

    nop

    Slot 5

    L2

    d2=sub2(A2,B2)

    ad2=abs2(d2)

    ad4=abs2(d4)

    z24=add2(ad2, ad4)

    nop

    nop

    nop

    nop

    Slot 6

    S2

    d4=sub2(A4,B4)

    nop

    nop

    nop

    nop

    nop

    nop

    nop

    Slot 7

    M2

    nop

    nop

    nop

    nop

    s24=dotp2(z24, 0x00010001)

    nop

    nop

    nop

    Slot 8

    D2

    nop

    nop

    nop

    nop

    nop

    nop

    nop

    nop

    Table 3 – Pseudo assembly code for the MAE computation on the TI VLIW DSP CPU, with dual 16-bit sub-word parallelism

    Table 2 – Pseudo assembly code for the MAE computation on the TI VLIW DSP-CPU, with quadruple 8-bit sub-word parallelism

    Table 1 – Pseudo assembly code for the MAE computation on the Nexperia/TriMedia VLIW DSP-CPU, with quadruple 8-bit sub-word parallelism

    A U T O M O T I V E

  • First Quarter 2008 Xcell Journal 19

    tions, data routing pipes, memory interfacecontrollers, and a 32-bit MicroBlaze™embedded processor for serial processingand external communications.

    For reference, by utilizing only 70% ofthe whole FPGA device again at 150 MHz,the Spartan 3A-DSP 1800A device couldprocess up to 23 blocks in parallel (70% x16,640 slices/508 slices/block = 23 blocks).This corresponds to a peak performance of3,529 MMAE/s, which is at least 25 timesgreater than the 600-MHz TI DSP-CPU’speak performance.

    ConclusionUsing an automotive vision-based applica-tion example, we’ve shown how to leveragethe programmable parallelism of a medi-um-sized, low-cost Xilinx FPGA to providerequired processing performance overVLIW DSP-CPUs. Table 4 summarizes theresults of our analysis.

    Note that for MAE calculations on 4 x 4blocks of 12-bit pixel data, the Spartan-3ADSP outperforms the TI TMS320DM6437by 2 times at only one-fourth the clockspeed. Furthermore, resource utilization onthe FPGA is only 6%, thus allowing for theimplementation of other image processingfunctions (in parallel if necessary) on thesame device.

    On the other hand, the VLIW DSP-CPU is totally busy during the SAD calcu-lations, leaving little opportunity toconduct other simultaneous functions byconsuming the available slots of the serialprocessor long instructions.

    We were quite conservative about theFPGA estimated clock frequency (150 vs.250 MHz), as well as the motion estimationsearch area (the larger the search area,greater the number of MAEs to be comput-ed). A 30 x 30 search area, for example,would require 609 MMAE/s, far beyondthe VLIW DSP-CPU capability but usingonly 12% of the slices on the 1800A device.

    Finally, in the MAE implementation wedid not use at all of the DSP48 MAC units:we estimate that a 4 x 4 block of 12-bitinput data MAE could take 400 slices (782flip-flops and 400 LUTs) and four DSP48sby replacing the 100-slice adder tree withfour DSP48 units.

    Thus, the Spartan-3A DSP 1800A deviceis well suited for vision-based applicationsrequiring significant processing horsepower,

    flexibility, and scalability such as those foundon future generations of automotive driverassistance applications.

    Device Configuration Clock Freq. Performance

    Example Application Requirement 752 x 480 image N/A > 250 MMAE/s4 x 4 pixel block20 x 20 pixel search area

    Philips Nexperia PNX 1500 8-bit pixel depth 300 MHz 100 MMAE/sVLIW DSP-CPU Parallelism: Three 4 x 4 blocks

    TI TMSD320DM6437 8-bit pixel depth 600 MHz 163.64 MMAE/sVLIW DSP-CPU Parallelism: Three 4 x 4 blocks

    TI TMSD320DM6437 12-bit pixel depth 600 MHz 150 MMAE/sVLIW DSP-CPU Parallelism: Three 4 x 4 blocks

    Xilinx Spartan-3A DSP 1800A FPGA 12-bit pixel depth 150 MHz 300 MMAE/sParallelism: Two 4 x 4 blocks(approximately 6% of deviceresources)

    Xilinx Spartan-3A DSP 1800A FPGA 12-bit pixel depth 150 MHz 3,450 MMAE/sParallelism: 23 4 x 4 blocks(approximately 70% of deviceresources)

    Figure 3 – System Generator for DSP scheme of the SAD computation for a quadruple of four 12-bit samples in the Spartan-3A DSP 1800 device

    • Evaluate the System Generator for DSP design tool.

    • Learn more about and purchase the Spartan-3A DSP 1800A device.

    • Buy the XtremeDSP Development Platform – Spartan-3A DSP 3400A Edition.

    TAKE THE NEXT STEP (Digital Edition: www.xcellpublications.com/subscribe/)

    Table 4 – Summary of results

    A U T O M O T I V E

  • by Davor KovacecCEOXylon [email protected]

    Market leadership in the fast-moving elec-tronics market continuously demandsinnovative and cost-effective products.With an ever-shrinking time-to-marketwindow, design tools and pre-designed IPblocks are important elements of success.

    The right development platform canmake all the difference between success andfailure. It is a balancing act between the con-tradictory requirements of having a standardbut still highly configurable solution.

    Combining Xilinx® FPGAs with theXylon logicBRICKS IP cores library,Xylon’s feature-rich logiCRAFT 3 com-pact multimedia display developmentplatform is an ideal solution, addressingthe time-to-market and flexibility needs ofthe high-volume customer base. You canquickly turn system designs running onthis generic FPGA development platforminto specialized products. Such a designapproach enables a large portion of designreuse through different hardware (IPcores) and software modules. You canreuse these same modules in many systemdesigns for different applications.

    The logiCRAFT PlatformThe logiCRAFT 3 compact multimediadisplay development platform (Figure 1)is an FPGA-based board using hardwaremodules in the form of IP cores to devel-op FPGA functionality. The platform isdesigned to support a wide variety ofaudio and video sources and handle a

    20 Xcell Journal First Quarter 2008

    A Compact Multimedia DisplayDevelopment Platform for Automotive and Industrial Markets Xilinx FPGAs and Xylon IP cores shorten design cycles and lower production costs for multimedia applications.

    A U T O M O T I V E

  • variety of display types. With several stan-dard communication interfaces, you caneasily integrate the logiCRAFT 3 platforminto a larger system. Figure 2 showslogiCRAFT 3’s functional blocks.

    A wide variety of system interfaces such asaudio/video (A/V) I/Os, line drivers, gener-

    through two embedded IR headphone audiooutputs for the RSE is also an opportunity toreduce system cost. The FM modulation isimplemented using the logiAIR IP core,enabling the use of a low-cost field effecttransistor (FET) for IR LED driving. Thereis also the flexibility to enable Bluetooth withthe addition of a Bluetooth module.

    Audio and video streams, as well as con-trol data, are transferred to the RSE head-rest unit by using an embedded high-speedGbps digital link. The low data-rate con-tent, such as push-button status, remotecontroller data, touch-screen data, and oth-ers are transferred using the same link.

    The link itself requires only two twistedpair lines. One line may also be used forpowering the platform, resulting in a sig-nificant reduction in infotainment wiringcosts. You can have the A/V devices con-nected to the logiCRAFT 3 through thecomposite video blanking and sync

    al-purpose I/Os, and COG power suppliesmakes this platform extremely versatile.

    The logiCRAFT 3 platform is primarilyaimed at the automotive market, includingapplications such as navigation, infotain-ment, rear-seat entertainment (RSE), anddriver assistance. Other multimedia appli-cations are equally applicable, such as con-sumer, medical, and measurementinstrumentation or factory automationapplications.

    Figure 3 shows block schematics of anautomotive RSE system. In this particularexample, the logiCRAFT 3 is used in the carheadrests and serves to deliver A/V content.

    The platform’s flexibility can helpreduce overall solution costs as well as timeto market. For example, the platform’scapability to fully support a number of dif-ferent displays enables you to make selec-tions when required for cost or availability.Implementing high-quality wireless audio

    First Quarter 2008 Xcell Journal 21

    FPGALCD

    TV

    logiCRAFT3

    PAL/NTSC/

    SECAM

    CAMERA

    Four CVBS or

    Two S-VIDEO

    Inputs

    Four LVDS Pairs

    One (two) Twisted

    Pair Lines

    IR

    Remote

    Sensor

    Eight 3V3 TTL

    Lines

    CAN

    CAN

    iPod Serial

    Control

    Bluetooth Port

    Four Stereo Audio

    Line Inputs

    Microphone

    Input

    Audio Codec

    TVL320AIC23

    Single Wire CAN

    Interface

    Gbps Pixel Link

    Receiver

    INAP125R24

    IR Remote

    Sensor

    Interface

    8-bit General-

    Purpose I/O

    PAL/NTSC/SECAM

    Decoder 1

    SAA7113A

    PAL/NTSC/SECAM

    Encoder

    SAA7120H

    FLASH

    FLASH

    Headphones

    Output

    Four LVDS Pairs

    Display Data Out

    CVBS/S-VIDEO Out

    Stereo Audio Out

    Channel 1

    Stereo Audio Out

    Channel 2

    Line Out

    SDRAM

    COG Display

    Power Supply

    GAMMA Correction

    CCFL/LED Backlight

    Power and Control

    Touch Screen

    Controller

    PAL/NTSC/SECAM

    Decoder 2

    SAA7113A

    CAN Interface

    User

    Config.

    IR LED

    Drivers

    2 x SI9955DY

    RS232 InterfaceRS232

    XBOX

    PLAYSTATION

    DVD

    User-

    Selectable

    Assembly

    Select

    User-

    Selectable

    Figure 1 – LogiCRAFT 3 compact multimediadisplay development platform

    Figure 2 – LogiCRAFT 3 platform’s functional blocks

    A U T O M O T I V E

  • (CVBS) or S-video inputs (video) andstereo line inputs (audio). An iPod can alsobe connected as required.

    The logiCRAFT 3 platform can also beused in stand-alone human machine inter-face (HMI) applications such as:

    • Instrument cluster applications (Figure 4)

    • Car radio and navigation

    • Industrial and medical instrumentation(Figure 5)

    In these applications, you can use eitherthe CAN network connection for all datatransfer or the standard RS232 channel forcommunication and debugging. For appli-cations requiring HMI control, an embed-ded IR remote control sensor, touch-screeninterfaces, and GPIO for buttons andLEDs are provided.

    You can also add features by usingXilinx LogiCORE™ IP, other third-partyIP cores, or by designing a custom circuit.

    The list of key IP cores that can be utilizedon the logiCRAFT 3 includes:

    • logiCVC-ML – compact multilayervideo controller

    • logi2D – 2-D graphics accelerator

    • logiCAN – CAN 2.0B-compatible net-work controller

    • logiUART – universal asynchronousreceiver/transmitter

    • logiWIN – versatile video input

    • logiMEM – flexibleSDRAM/DDRAM/flash memory controller

    • logiI2S – I2S transceiver

    • logiRC – IR remote controller receiver

    • logiAIR – digital FM modulator for IRheadphones

    Spartan™-3E FPGA hardwareresources, dedicated multipliers, digitalclock managers (DCMs), and block RAMsensure that IP cores operate at higherspeeds and consume less area on the FPGA.In addition, FPGA configuration from anexternal byte-width memory provides fastboard startup time, which is of a greatimportance in automotive applications. AllXylon IP cores are carefully designed for

    22 Xcell Journal First Quarter 2008

    IR Audio

    Gbps High-Speed Digital Link

    +

    Power Supply

    FLASH

    FLASH

    Gbps Receiver

    INAP125R24

    Audio/Video

    Separation

    I2C Controller

    MicroBlaze

    Processor

    logiRC

    logiAIR

    Audio

    Video

    FPGA

    logiCRAFT 3

    Touch-Screen

    Controller

    IR Remote

    Sensor

    Interface

    DISPLAY

    Touch Screen

    IR

    Remote

    Sensor

    IR RemoteControl Sensor

    BluetoothRF Module

    BluetoothRF Module

    Gbps High-Speed LinkAV Content, Control Data,

    Low Data Rate Back-Channel+

    Power Supply

    Gbps High-Speed LinkAV Content, Control Data,

    Low Data Rate Back-Channel+

    Power Supply

    Compact Multimedia FPGAPlatform

    Compact Multimedia FPGAPlatform

    DISPLAY and TOUCHSCREEN

    IR Audio

    DISPLAY and TOUCHSCREEN

    IR Audio

    IR RemoteControl Sensor

    INFOTAINMENTMASTER BOARD

    logiCRAFT 2

    Figure 3 – Rear-seat entertainment system

    Figure 4 – Platform/FPGA structure for rear-seat entertainment application

    A U T O M O T I V E

  • First Quarter 2008 Xcell Journal 23

    the lowest FPGA resource utilization,making them particularly suitable for high-volume applications.

    Platform Features

    • Small form factor 155 mm x 115 mm(4” x 3”)

    • Supports Spartan-3E3S250E/500E/1200E 256-pin FPGAs

    • 8 MB of NOR flash

    • 16 MB/32-bit-wide SDRAM runningup to 133 MHz

    • Up to two simultaneous video inputsselectable from:

    • Four CVBS or two S-videoPAL/NTSC/SECAM inputs

    • One LVDS channel (clock + threedata pairs) directly connected tothe FPGA

    • High-speed LVDS Gbps digital transceiver

    • 8-bit general-purpose I/O

    • Touch-screen controller

    • CAN interface and single-wire CANinterface

    • RS232 interface

    • Interface to external Bluetooth module

    • iPod control interface

    • One stereo audio input selectable fromfour stereo line inputs

    • Microphone input

    • Audio line output

    • Headphone output

    • Two stereo IR headphone audio outputs

    • Video output configurable as:

    • CVBS/S-video PAL/NTSC/SECAM output

    • One LVDS channel (clock + threedata pairs) directly from FPGA

    • Digital RGB interface

    • Power supply for COG displays,including GAMMA correction andVCOM circuits

    • Power and control output for CCFLbacklight inverters and LCD backlights

    RSE ExampleFigure 4 shows the platform/FPGA struc-ture for an RSE application where theFPGA design is based on Xylon’s IP cores.In such applications, A/V and control datais usually transferred between an infotain-ment master board and the electronics,which are embedded into car headreststhrough a number of cables.

    The LogiCRAFT 3 platform, with itssupport for a high-speed Gbps digital link,

    dramatically reduces the complexity andcost of the wiring required. You can trans-fer all digital video, audio, and bi-direc-tional control data using only two twistedpair lines. You can also discard the powercable, because the platform can be poweredthrough one of the two twisted pair lines.

    Besides the reduction in wiring com-plexity, the logiCRAFT 3 platform alsointegrates many functions otherwise sup-ported by dedicated integrated circuits intojust one low-cost Spartan-3 XC3S250EFPGA. You will not need additional elec-tronics for IR audio FM modulation, IRremote protocol decoding, or I2C bus con-trol, among others. The logiCRAFT 3 rep-resents an ideal solution for saving yourbudget without having to sacrifice anythingfrom the set of common RSE features.

    Instrument Cluster ExampleFigure 5 shows the platform/FPGA structurefor an instrument cluster, where the powerfulyet compact logiCVC multilayer displaycontroller will help you create a state-of-the-art instrument panel. With a 60-fps refreshrate, you will be able to animate on-screengauges and give them the motion smooth-ness of their analog counterparts.

    In addition, the logi2D graphic acceler-ator, with its bitmap image rotating capa-bility, offers additional flexibility forinstrument animation. You can easily

    Touch PanelTouch-Screen

    Controller

    FLASH

    logiMEM

    logiMEM

    logiWIN

    logiCAN

    GPIO Bus

    PAL/NTSC/SECAM

    Decoder

    SAA7113A

    IR Remote

    Sensor

    Interface

    IR

    Remote

    Sensor

    Parking

    Assist

    Camera

    Measured

    Values

    Control

    Buttons

    8

    RS232

    CAN

    RS232 Interface

    CAN Interface

    FPGA

    logiCRAFT 3

    logiRC

    logiUART logiBITBLT

    MicroBlaze

    Processor

    I2C Controller

    logiCVC

    SDRAM

    DISPLAY

    Figure 5 – Platform/FPGA structure for instrument cluster application

    A U T O M O T I V E

  • design an instrument panel with GUIbuilder or graphic libraries to efficiently useXylon’s graphics acceleration IP cores.

    Communication between the vehicleengine control unit data and the platformis easy by using the onboard CAN interfacewith our logiCAN IP core. You can alsoconnect a suitable camera using the Gbpsdigital link, thus adding a parking assistcapability to the list of features. You can usea standard PAL/NTSC/SECAM as well.

    With the help of our logiWIN IP core,you can de-interlace scale and positionincoming video to optimize it for your par-ticular display. All FPGA functionalityrequired to support the instrument clusterconfiguration will fit into one Spartan-3XC3S1200E FPGA. This way, you canachieve an outstanding cost-to-perform-ance ratio and provide a very competitivesolution for today’s demanding and fast-changing markets.

    Industrial Application ExampleFigure 6 shows the platform/FPGA struc-ture where a LogiCRAFT 3 compact multi-media display development platform servesas a central unit for monitoring and con-trolling industrial processes, with the FPGAdesign based on Xylon IP cores. As in theprevious example, the logiCVC/logi2D

    combination, supported with dedicatedgraphic software libraries, gives you every-thing you need for making and combiningscreen elements required for successfulprocess monitoring and control. You canalso use an embedded touch-screen con-troller to make human-machine interactionintuitive and logical.

    For handling classical buttons and indi-cators, an I2C-controlled GPIO interface isat your disposal. If your application calls forreal-time environment surveillance or real-time video process monitoring, the plat-form’s PAL/NTSC/SECAM video decodersprovide an excellent solution.

    By introducing the logiWIN IP coreinto your FPGA configuration, you caneasily handle decoded video signals interms of de-interlacing, scaling, and posi-tioning. The platform also provides themeans to create audio alarms in an emer-gency situation. To implement this, youcan use an embedded audio codec in com-bination with the logiI2S IP core. The plat-form-process communication can beestablished by using the on-board CANinterface and logiCAN IP core.

    If you wish to connect the platform to aPC, you can do that through the platform’sRS 232 interface. To host all of this function-ality, logiCRAFT 3 utilizes a Spartan-3

    XC3S1200E FPGA, which gives you enoughroom to develop the optimal configuration.

    However, your actual final productionconfiguration may require less FPGAresources, so a smaller and less-expensiveFPGA would suffice. The logiCRAFT 3addresses this issue by providing pin-com-patible scalability between Spartan-3XC3S500E and XC3S250E FPGAs, thusdelivering an additional feature for tailoringyour final product.

    ConclusionThe value of the LogiCRAFT 3 compactmultimedia display development platformfrom Xylon lies in the high number ofsupported display types; the innovativesystem architecture, small form factor, andbroad feature set; and the ability to beconfigured for performance, price, lowdevelopment, and production cost withvirtually no obsolescence.

    Based on the Xilinx Spartan-3E family,with its low cost-per-gate and feature-richarchitecture, the logiCRAFT 3 provides anexcellent base on which to build.

    For more information about theLogiCRAFT 3 compact multimedia displaydevelopment platform and logicBRICKSXylon IP library, please e-mail [email protected] or visit www.logicbricks.com.

    24 Xcell Journal First Quarter 2008

    SDRAM

    FLASH

    8

    CAN

    RS232

    FPGA

    Control

    ButtonsGPIO Bus

    logiCAN

    I2C Controller

    MicroBlaze

    Processor

    logi2D

    logiWIN

    logiMEM

    logiCVC-ML

    Touch Screen

    ControllerTouch Panel

    DISPLAY

    logiUART

    CAN Interface

    RS232 Interface

    PAL/NTSC/SECAM

    Decoder

    SAA7113A

    Measured

    Values

    Surveillance/

    Process

    Monitoring

    Camera

    logiCRAFT 3

    Audio Codec

    TLV320AIC23

    logil2S

    Figure 6 – Platform/FPGA structure for industrial application

    A U T O M O T I V E

  • by Kevin TanakaWorldwide Automotive Marketing and Product Planning ManagerXilinx, [email protected]

    Over the past 10 years, in-vehicle network-ing architectures have become much morecomplex. Although the number of in-vehi-cle networking protocols has been reduced,the number of networks actually beingdeployed has increased dramatically. Thisleads to network architecture scalabilityissues and semiconductor device optimiza-tion to match each application and net-work’s actual needs.

    FPGAs, once thought of as a solutionfor development purposes only, havecome down in price to the point wheremany issues can be resolved and put intoproduction at a lower overall system costthan the traditional ASIC or ASSP solu-tion. All of the major FPGA suppliers tothe automotive market are now ISO-TS16949 certified, making programma-ble logic devices a mainstream technologyin the automotive market.

    In-Vehicle Network Electrical ArchitectureDuring the last ten years, many propri-etary OEM automaker networking proto-cols have made way for more standardizedglobal protocols like CAN, MOST, andFlexRay. This lets semiconductor vendorsconcentrate on building devices with thosespecific protocols built in, bringing morecompetition and lower prices to tier-onesand more module interoperability at theOEM level. However, in today’s vehicleelectrical architectures, both OEMs andtier-ones still struggle with many issues.

    Engineers can partition and build net-working strategies in several different ways.High-end vehicles can have anywhere upto seven different network buses runningsimultaneously. For instance, a single vehi-cle could have a LIN loop for mirrors, alow-speed CAN loop at 500 Kbps for low-end functions like seat or door control, a

    high-speed CAN loop at 1 Mbps for bodycontrol, another high-speed CAN loop fordriver information systems, a FlexRay loopat 10 Mbps for real-time driver assistancedata, and a MOST loop at 25 Mbps forcontrol and media streaming within oracross various infotainment systems likenavigation or rear-seat entertainment.

    On the other hand, low-end vehiclesmay have no more than a single LIN orCAN loop, with all of the other modulesworking on their own with almost no inter-action. Each OEM automaker deals withinter-module communication and vehiclenetwork topology differently, and eachvehicle platform is different, making it dif-ficult for tier-ones to develop reusablemodule architectures with the correct inter-faces. Uncertainty of the final architectureinto which a module will go is an areawhere FPGAs excel.

    First Quarter 2008 Xcell Journal 25

    Scalable and Flexible In-Vehicle NetworkingFPGAs and full IP solutions give automotive engineersoptions in optimizing their electrical architectures.

    First appeared in Chip Design magazine, June 26, 2007. Copyright Extension Media. Reprinted with permission. A U T O M O T I V E

  • 26 Xcell Journal First Quarter 2008

    Because of their fixed hardware archi-tecture, ASICs, ASSPs, and microcon-trollers are usually either under- orover-resourced with no flexibility. The pro-grammability (and re-programmability) ofthe FPGA allows for the simple additionor subtraction of on-chip channels (forexample, channels of CAN), along withthe re-use of IP. With this flexibility, anoptimized solution for the number andtype of networking interfaces can be builtinto a module quickly.

    Semiconductor Implementation of Network ProtocolsThe scalability of the FPGA for the num-ber and types of interfaces is not its onlymerit. In the case of ASSPs, ASICs, andmicrocontrollers, the peripheral macrosare implemented in hardware, makingthem inherently inflexible. In an FPGAenvironment, the networking interfaceIP itself can be optimized depending onthe IP being used.

    For example, with Xilinx® LogiCORE™CAN or FlexRay networking IPs, userscan flexibly program the number of trans-mit and receive buffers along with thenumber of filters. In traditional hardwaresolutions, an engineer working with aCAN controller would typically only havethree configuration choices: 16, 32, or 64message buffers. The Xilinx scalableMOST network interfacing solutionincludes network controller IP that can beconfigured for either master or slave oper-ation and a host of IP, such as asynchro-nous sample rate converters (ASRC), datarouters, or encryption engines for copyprotection, depending on the level of sys-tem functionality and available processingoutside of the FPGA.

    The IP allows for optimization and theability to push into lower density devicesfor low-end solutions and higher density

    devices for high-end solutions, oftenusing the same package footprint on themodule target board. Also, for each mainprotocol, middleware stacks and drivershave been developed to round out thesolution. This type of scalability as well asthe versatility of an FPGA-based solutionis just not possible in a traditional auto-motive hardware solution.

    All of the major FPGA vendors havesoft microprocessors that can be efficientlyimplemented in the fabric for control func-tions and can run at speeds that rival someof those embedded in hardware. Anothermajor advantage of the FPGA architectureis the ability to offload processing functionsfrom the microprocessor and partition byusing the parallel DSP processing capabili-ties found in either multipliers or hardMACs on-chip, increasing overall perform-ance and throughput.

    We’ve Come a Long WayProgrammable logic devices have come along way in becoming a mainstream tech-nology in the automotive market. The fieldhas evened on the reliability side, andFPGA technologies are allowing scalableand flexible integration that has neverbefore been possible in traditional ASIC,ASSP, or microcontroller architectures.Overall production system costs arereduced because of shortened developmentcycles, advanced process technologies usedby programmable logic device vendors, andthe economies of scale that a programma-ble device inherently brings with it.

    With the key IP and solutions for in-vehicle networking coming to fruition andthe added performance capabilities ofFPGA architectures, programmable logicdevices will become a major player in help-ing alleviate some of the engineering diffi-culties inherent in developing in-vehicleelectrical architectures.

    • Download more information about the Xilinx Automotive NetworkingLogiCORE solution.

    • Buy a Xilinx Automotive ECU Development Kit.

    TAKE THE NEXT STEP (Digital Edition: www.xcellpublications.com/subscribe/)

    FPGA Powered – That‘s it!

    FPGA-Module:TQM hydraXC – smallest, most universal Hardware Platform for Reconfi gurable Computing• Based on XILINX Spartan 3,

    Virtex 4 and Virtex 5 technology• Ethernet 10/100, USB 2.0, RTC• SPI-, NAND-Flash, DDR2 / SDRAM• Size 2.13 Inch x 1.73 Inch

    (54 mm x 44 mm)• Programmable VCC IOs

    Embedded solution with TQM hydraXC for • Fast time to market• Economical series production• Highest fl exibility• Hardware reduction:: Starter kits available ::

    Email: [email protected]

    Infoline: (+49 ) 81 53 / 93 08 - 333

    Starter kit with module

    A U T O M O T I V E

  • Hit your target by advertising your product or service in the Xilinx Xcell Journal, you’llreach thousands of qualified engineers, designers, and engineering managers worldwide.

    The Xilinx Xcell Journal is an award-winning publication, dedicated specifically to helping programmable logic users – and it works.

    We offer affordable advertising rates and a variety of advertisement sizes to meet any budget!

    Call today : (800) 493-5551 or e-mail us at [email protected]

    Join the other leaders in our industry and advertise in the Xcell Journal!

    Let Xcell Publications help you get your message out to thousands of

    programmable logic users.

    Get on Target

    Rwww.xilinx.com/xcell/

  • Complete development solution with pre-verified reference designs and IPs for digital image processing applications.Complete development solution with pre-verified reference designs and IPs for digital image processing applications.

    Spartan™-3 GenerationDisplay SolutionsSpartan™-3 GenerationDisplay Solutions

    Spartan-3A Display Solutions BoardTB-3S-1400A-IMGFeaturesXilinx Device: XC3S1400A-FGG484, XCF08P VO48Memory: DDR SDRAM 512Mb x 16bit x 4(32bit x 2ch)Interfaces: RS-232C x1

    High Speed I/O Connector x4 Option Board: DVI Tx and Rx

    FeaturesXilinx Device: XC3S1600E-FG484C, XCF08P-FS48Memory: DDR SDRAM 512Mb x 16bit x 4 (32bit x 2ch)Flash Memory: 16Mbit SPIInterfaces: RS-232C x1

    High Speed I/O Connector x4 Option Board: DVI Tx and Rx, Pin header adapter cards x2

    Spartan-3E Display Development KitHW-SPAR3E-DISP-DK-UNI-G-PROMO

    Reference Designs (for Free):- 7:1 LVDS Rx/Tx display link- RSDS/Mini LVDS Tx- 266Mbps DDR SDRAM Controller

    - Color Temperature Correction- Precise Gamma Correction(PGC)- Image Dithering Engine(IDE) etc.

    IPs (from Xilinx Partners):Apical Limited- Dynamic Range Compression(iridix)- Noise Reduction(NR)

    Choose “A” or “E” !!

  • by Arthur YangTechnical Marketing Manager, Micro Scale DivisionXilinx, [email protected]

    Asking for directions is becoming a foreignconcept. It’s fast dying out, much like theart of folding a map or a newspaper. Itsimpending extinction can be attributed tothe increasing popularity of the GlobalPositioning System (GPS).

    GPS is present in a growing number ofproducts: automobiles, cell phones, person-al data assistants, even wristwatches. Witheach GPS vendor showcasing a product lineof several dozen GPS products, consumersare overwhelmed with the selection.

    Therefore, success lies in product differ-entiation and specialization. Xilinx®

    CoolRunner™-II CPLDs are the idealchips to add features or interface withanother device to make your GPS productstand out from the rest – without breakingthe power budget.

    The Power AdvantageBoth portable and in-dash GPS devices mustadhere to a strict power budget.CoolRunner-II CPLDs have the advantageof minimal power consumption without theneed for sleep mode states. The smallestCoolRunner-II device has a quiescent powerof 13 µA. In some portable applications, asleep mode is sufficient and a wake-up timein the hundreds of milliseconds is acceptable.

    In some cases, however, the currentdesign states are lost. When using sleepmode, your entire device shuts down. Youmust rely on a secondary device to poll forinterrupts and initiate a wake-up sequence.CoolRunner-II devices offer a unique sleepmode without the associated designheadaches through its DataGATE feature,a self-contained and user-configurable cir-cuit that allows you to disable as much ofthe device as you desire.

    By enabling DataGATE, you can turnoff whichever inputs you choose in sever-al nanoseconds, thereby shifting thepower consumed by the CPLD closer to aquiescent state. This could be done peri-odically, such as when polling for an inter-rupt, or it could be dependant on a

    First Quarter 2008 Xcell Journal 29

    Designing GPS Systems Using CoolRunner-II CPLDs

    Designing GPS Systems Using CoolRunner-II CPLDsExpanding functionality using low-power CoolRunner-II CPLDs.Expanding functionality using low-power CoolRunner-II CPLDs.

    P O R T A B L E H A N D S E T S

  • particular state of operation. Thus, por-tions of the CoolRunner-II device canremain active while others are in standby.

    Let’s look at an example to explain fur-ther. The CPLD sits on an address and databus between a microprocessor, mobileSDRAM, and SD flash card. Data movesbetween each of the devices. The CPLDmonitors the data activity and blocks traf-fic based on the particular function. If thecurrent task is to move data from themicroprocessor to the SD card, then theCPLD blocks any data to and from theSDRAM using DataGATE.

    Within the CPLD, you can write codeto simply decode the function being per-formed (either from watching the addresslines or by parsing frame data) and thenenable/disable whichever data path isrequired. This is a trivial example that ispossible to a much lesser degree with otherprogrammable logic devices (PLDs) byusing output 3-states.

    The advantage of DataGATE is that iteffectively 3-states at the input of theCPLD. Power savings increase because theCPLD I/O as well as core circuitry areplaced in a quiescent state, whereas alter-nate solutions require the entire PLD tostay in active mode.

    The Security AdvantageGPS system pricing makes it an attractivetarget for product cloning. To help preventthis, you can utilize CoolRunner-II CPLD’sread/write protect security to implement asecurity system that prevents cloning byoverbuilding. Overbuilding occurs when acontract manufacturer orders extra compo-nents for a given production run and thenbuilds extra products that are identical tothe authentic versions.

    The concept is that the system requiresinteraction with the CPLD to perform anydesired function. You can implement thissecurity in any number of ways. The moststraightforward solution would be to have aCPLD act as a data-traffic cop, directing databetween the individual devices on the board.

    A more complex solution involves usingthe CPLD to implement a block cipher.This would have the microprocessor sub-mit a random stream of data to be encrypt-

    blank CPLDs is not useful without accessto the programming file.

    Achieving Product Differentiation in GPS UnitsOriginal consumer GPS units werestraightforward. They simply gave locationinformation in the form of latitude andlongitude. Today’s GPS units not only offerreal-time maps and directions, they offerMP3 playback or integration with cellphones via Bluetooth. There are also mar-ket-specific GPS systems with features suchas traffic updates for in-car navigation,

    ultra-small units for runners or cyclists tomeasure their pace, units with sonar forfishermen – even GPS-enabled collars forkeeping tabs on the family pet.

    Each product requires an interface tosometh