/ the right development

Reliable signal processing Design examples

/ the right development

Technology solutions Simplicity is the soul of quality

/ focus areas

We cover the complete system:

The Physical System

Sensor Processing Actuators

Rest of world System Control

• Electronics Design (Analog & Digital)

• Programmable Logic

• Embedded Software

• System Control

• User interaction

• User app development

• 16 M pixel 40 fps analog acquisition

• flex technology

• 10 Gbit/s data rate

• vacuum environment & feedthrough

TEM – Electron microscope imaging

/ transmission electron microscope

/ transmission electron microscope

Power

Data

Sensor Package PCB

Camera Control Unit

Power

User Link

to TEM controller

(GbE)

I/O link

(GbE)

Positioning

Camera Support Unit

Cooler

/ sensor package

• CMOS 2D pixel sensor

• Analog read-out

• Vacuum

• Cooling

• < -10° Celsius

/ camera control unit

• Controlling analog

sensor electronics,

timing, modes

• Digitizing read-out

electronics

• Pixel correction

• Ethernet packetization

/ camera support unit

• Controlling settings,

position, cooling, safety

• Digital image (pre-)

processing & compression

• Buffering

• Systems Engineering

• Analog & digital electronics

• Mechanical / Thermal design

• Vacuum

• Software

Multi-disciplinary design

/ the right development

• Tropomi instrument on Sentinel 5-P

• 4 spectrometers: UV / UVIS / NIR / SWIR

• Generates Level-0 data: • Unprocessed instrument measurement & housekeeping data

• Data sorted by instrument mode/application process

• Payload on Astrabus AS250 Platform

• LEON3 OBC / RTEMS OS

Imaging in Space

/ a reference case

• Tropomi instrument

/ tropomi

CMOS/CCD sensors

Front-end electronics

Digital processing

Data storage

/ tropomi

OBC PDHU

ICU

PDHU

ICU

/ tropomi

/ the right development

Power

Data

Sensor Package PCB

Camera Control Unit

Power

User Link

to TEM controller

(GbE)

I/O link

(GbE)

Positioning

Camera Support Unit

Cooler

CSU

• High-throughput data

• Pre-process & compress

• Distributed & scalable Analog Digital Hardware Software

• Standardization

• Modularity

/ image processing

ICU Sensor

CCU Sensor

DEM

Data Acquisition Software

• Camera Abstraction Layer

• Data Storage

ESA’s next-generation DSP for Space

• To match sensor improvements

• Increased data rates and data volume

• Pre-process & filter data in space

• Send useful information to earth

• Demand for European fault-tolerant high-performance processing technology: • Radiation-hard multi-core DSP System-on-Chip • Fault-tolerant Network-on-Chip architecture

Need for high-speed data processing in Space

/ Processing in space

Fault-tolerant DSP subsystem combined with

proven Leon subsystem:

• NoC-based multi-core DSP

• Heterogeneous and scalable

MPPB: Multi-core DSP FPGA prototype

XentiumDARE: Rad.-hard prototype IC

SSDP: Rad.-hard multi-core DSP IC

Scalable DSP systems

/ Scalable DSP in space

/ Scalable SoC

NoC

Xentium0 Xentium1

Memory

tile

ADC/DAC

bridge

DAC ADC

SpW1 SpW2 I/O SDRAM 1

AHB

DMA

controller

LEONtimers RTC

SpW0

RMAPGPIO UART LCD SDRAM0Flash

Leon-b

ase

d

GP

P s

ubsyste

m

sca

lable

DS

P s

ubsyste

m

NoC

bridge

XentiumDARE

/ Radiation-hard prototype IC

IP validated under radiation:

• Xentium IP

• NoC router

• NoC interfaces (Master/Slave)

• NoC-SpW interface

• NoC-ADC/DAC interface

• ASIC Prototype • DARE180 CMOS technology

• Available area: 5x10 mm2

• Architecture • 1 Xentium core @100MHz • Network-on-Chip • SpW-RMAP interface • Interface to external ADC/DAC • Small memory tile

Rad.-hard prototyping in DARE180

/ XentiumDARE

• High instruction-level parallelism • 10 parallel execution units

• Data precision • 32/40-bit fixed-point datapath • Single-Precision floating-point • 16-bit SIMD

• Features • Single-cycle latency Data Memory • Single-cycle latency Instruction Cache • Short 3-cycle pipeline • Hardware debug infrastructure

• Efficient complex MAC execution:

2 16-bit complex MACs/cycle

• Register bypass (latency, energy, code size) • Loop buffer (energy, code size)

Programmable

high-performance DSP core

/ Xentium DSP

CMOS Fixed-point

performance

Floating-point

performance

Clock

65 nm

90 nm

180nm

1.4 GMAC/s

0.88 GMAC/s

0.40 GMAC/s

2.1 GFLOPS

1.32 GFLOPS

0.60 GFLOPS

350 MHz

220 MHz

100 MHz

datapath

control

logic

instruction

cache

tightly coupled

data memory

Common bus

interface

Xentium core Bus

/ Xentium datapath

• Xentium C compiler (LLVM/Clang) • ANSI/ISO-standard C • Built-in functions for Xentium specific

operations • Mix C and assembly function calls

• Xentium assembler • Clean and readable • Extensive built-in preprocessor • Standard assembler directives

• Compile, assemble & link a program in a single step

• Xentium ISS (Instruction Set Simulator) • Trace program execution • Interactive debugging • Program profiling

Software Development

Environment

/ Xentium DSP C source files

Object files

Object file library

Assembler source

Executable object file

C compiler

Assembler

Linker

Simulator

Archiver

Object file utilities

Xentium core

Debugger Profiler

Profiler info

• 32-bit packet-switched 2D-Mesh

• XY-routing, deadlock free

• 5-port routers featuring 4 prioritized services (QoS)

• Fault-tolerance • Adaptive XY-routing to provide

data rerouting in the NoC • Flit-level flow control • Enable the insertion of EDAC

on data links to increase robustness

Fault-tolerant NoC

/ Network-on-chip

R R R R

R R R R

R R

R R

NI-MS

NoC IF

IP

NI-MS

NoC IF

IP

NI-MS

NoC IF

IP

NI-MS

NoC IF

IP

NI-MS

NoC IF

IP

Xentium 0

NI-MS

AHB-NoC Bridge

NI-MS NI-MS

NoC IF

IP

NI-MS

NoC IF

IP

NI-MS

NoC IF

IP

NI-MS

NoC IF

IP

NI-MS

NoC IF

IP

• Xentium DSP and NoC will become available as IP cores

• IP validated under radiation in rad.-hard XentiumDARE IC (TRL 6)

• Contact Technolution for licensing & support

• Xentium SDE

• FPGA-based evaluation options

www.recoresystems.com/products

IP availability

/ ESA IP cores

• hardware

• RV32IMAS

• 32bits, mul/div, atomic, supervisor

• 5 stages - Harvard arch

• iMMU, dMMU (1 - 128 entries)

• 8 way associative cache (4 - 32k)

• cache coherency (DMA)

• IO space

• software

• Linux

• Buildroot

FreNox-S FreNox-E

• hardware

• RV32I(M)

• 32bits, mul/div

• 5 stages - Harvard arch

• cache or internal RAM

• IO space

• software

• Bare metal

• FreeRTOS

• ThreadX

Embedded processor Application processor

• Continuous Integrated Development

• Programmable Logic / FPGA design

• VHDL design / ASIC front-end design

• Electronics Design (Analog & Digital)

• Embedded Software

• Application Software / Algorithms

• Multi-disciplinary Project Management

• Mission-, safety-, security-critical

• Xentium DSP, FreNox RISC-V and Network-on-Chip IP reuse • IP licensing & support

Our services for customers

/ Technology solutions

• Powerful Digital Signal Processor

• Xentium DSP IP

• Software Development Environment

• Reliable general purpose processor

• FreNox RISC-V IP

• Software Development Environment

• Fault-tolerant on-chip interconnect

• Network-on-Chip IP

/ IP & system design

Our unique IP

Flexible & programmable

digital signal processing

-

Scalable multi-processor

architectures

Secure control & processing

/ the right development

Gerard Rauwerda Business Developer T: +31 182 59 4000 E: Gerard.Rauwerda@technolution.nl