Universidade Federal de Santa Catarina Centro Tecnológico Computer Science & Electrical Engineering Lectures 33 to 36 Combinational Circuits in CMOS Digital

Universidade Federal de Santa CatarinaCentro Tecnológico

Computer Science & Electrical Engineering

Lectures 33 to 36Combinational Circuits in CMOS

Digital Integrated CircuitsINE 5442 / EEL 7312

Prof. José Luís Güntzel [email protected]

2 Lectures 33 to 36Prof. Güntzel

Combinational Circuits in CMOS

INE 5442 / EEL 7312Digital Integrated Circuits

• Complementary CMOS

• Pass-Transistor Logic

Agenda




Combinational vs. Sequential Logic

CombinationalLogic

in0

in1

...

ink

out0

out1

...

outjCombinational

Logic

in0

in1

...

inm

out0

out1

...

outn

StateOutput values depend only on the current input values (no feedback, no storage element).

Output values depend on the current input values and on previous input values (feedback with/without storage element).




Logic Families in CMOS

• Static CMOS Logic

– Complementary CMOS

– Ratioed Logic

– Pass-Transistor Logic

• Dynamic CMOS Logic




Metrics for Choosing a Gate Design/Family

• Area in silicon (related to number of transistors)

• Speed (propagation delay)

• Energy consumption/Power dissipation

• Robustness to noise

• Reliability

• Manufacturability

“Depending on the application, the emphasis will be on different metrics.” (Rabaey; Chandrakasan; Nikolic, 2005)




Static CMOS Logic

Features:

• Robustness (low sensitivity to noise).

• Good performance.

• Low power consumption (no static consumption, except for leakage currents).

• Easy to design (good for novice designers…)




Truth-table

Logic-level symbolTransistor schematics

in out

in out

0 1

1 0

in out

Vdd

Complementary Logic: the inverter




Complementary Logic: mask layout for an inverter

NNNNP wellP well

P-implant

PPPP

N SubstrateN Substrate

P channelP channel N channelN channelVdd

N-implantN-implant

Gnd




Steady-state operation

in out

0 1

1 0

• Transistors seemed as ideal electronic switches • Capacitance represents the total charge at the gate´s output

in=0 out=1

CL= Vdd

Vdd

in=1 out=0

CL= 0 V

Vdd

(in=Vdd)

Complementary Logic: the inverter




Complementary Logic

in1in2in3

Vdd

GND

out = f(in1, in2, in3)

PMOS onlymakes f(in1, in2, in3) = 1

NMOS onlymakes f(in1, in2, in3) = 0

pull-up network

pull-downnetwork

in1in2in3

• Pull-up and pull-down networks are mutually exclusive transistor associations (dual)

• In steady state, there is always a path to either Vdd or GND! (In steady state, the output is always a low-impedance node.)




Discharging the output capacitance…

Charging the output capacitance…

Static CMOS Logic

output

CL

0 Vdd

Vdd

S

D

output

CL

Vdd |VTp|

S

D

output

CLVdd

Vdd 0

D

S

output

CL

Vdd

0 Vdd - VTn

Vdd

D

S

VGS

VGS




NMOS Series/Parallel Associations

A

X

B

Y

X=Y if A=1 AND B=1

control variables

Problem: NMOS transistors pass a weak “1” (but a strong “0”)

X=Y if A=1 OR B=1

A

X

B

Y

control variables




PMOS Series/Parallel Associations

X=Y if A=0 AND B=0

A

X

B

Y

X=Y if A=0 OR B=0

A

X

B

Y

Problem: PMOS transistors pass a weak “0” (but a strong “1”)

control variables

control variables




Complementary Logic

in1in2in3

Vdd

GND

out = f(in1, in2, in3)

PMOS only;makes f(in1, in2, in3) = 1

NMOS only;makes f(in1, in2, in3) = 0

pull-up network

pull-downnetwork

in1in2in3

• Only negative logic functions are implemented (e.g.: inverter, NAND, NOR, XNOR…)

• Design procedure: – use the “0” of the gate function

to design the pull-down network

– Apply De Morgan´s theorem to find the pull-up network.

• An n-input logic gate requires 2n transistors.




A B S

0 0 1

0 1 1

1 0 1

1 1 0

A SB

A

S

B

A B

Vdd

Complementary Logic: 2-input Nand

Truth-table

Logic-level symbol Transistor schematics




A

Out

VDD

GND

B

A

S

B

A B

Vdd

Complementary Logic: 2-input Nand mask layout




Steady state behavior:

4 possible input combinationsA=0

S=1

B=0

A=0 B=0

CL=Vdd

Vdd

A=0S=1

B=1

A=0 B=1

CL=Vdd

Vdd

A=1

S=0

B=1

A=1 B=1

CL=0 V

Vdd

A=1

S=1

B=0

A=1 B=0

CL=Vdd

VddA B S

0 0 1

0 1 1

1 0 1

1 1 0





Delay characterization through electric-level simulation (e.g., Spice)


B

A

S

tpLH(A) tpHL(A)tpLH(B) tpHL(B)

A SB

inputtpLH

(ps)tpHL

(ps)

A

B

Evaluates the individual contribution of each input (the others are kept at their non-controlling values)




A

Out

VDD

GND

B

A

S

B

A B

Vdd





A B S

0 0 1

0 1 0

1 0 0

1 1 0

A SB

A

S

B

A

B

Vdd

Truth-table

Logic-level symbol Transistor schematics

Complementary Logic: 2-input Nor




S = A+B·CExample:

A

S

B

C

Building Complementary CMOS Complex Gates

1. If the logic gate equation is not negated, imagine it as it were. At the end, an extra inverter will have to be added . (Alternatively, apply De Morgan´s theorem…)

2. Take the non-inverting equation of the logic gate to design the pull-down network




S = A+B·CExample:

A

S

B

A

B

C

C

Vdd

3. Design the pull-up network by finding the dual of the pull-down network, already designed:

1. Each series NMOS association gives rise to a parallel PMOS association

2. Each parallel NMOS association gives rise to a series PMOS association

Building Complementary CMOS Complex Gates




Properties of Complementary CMOS Gates

• Full rail-to-rail swing; high noise margins (VOH=Vdd , VOL=GND)

• Logic levels not dependent upon the relative device sizes; ratioless

• Always a path to Vdd or Gnd in steady state; low output impedance

• Extremely high input resistance; nearly zero steady-state input current

• No direct path steady state between power and ground; no static power dissipation

• Propagation delay function of load capacitance and resistance of transistors

Source: Rabaey; Chandrakasan; Nikolic, 2005




Rp

A

Rp

A

Rn CL

B

Rp

A

Rp

A

Rn

B

Rn CL

Cint

NAND2 INV NOR2

CL

B

Rn

A

Rp

B

Rp

A

Rn Cint

Switch Delay Models for Complementary Gates





• Delay is dependent on the pattern of inputs

• Low to high transition– both inputs go low

• delay is 0.69 Rp/2 CL

– one input goes low• delay is 0.69 Rp CL

• High to low transition– both inputs go high

• delay is 0.69 2Rn CL

Delay Depends on the Input Pattern


CL

B

Rn

A

Rp

B

Rp

A

Rn Cint





-0,5

0

0,5

1

1,5

2

2,5

3

0 100 200 300 400

A=B=10

A=1, B=10

A=1 0, B=1

time [ps]

Vo

ltag

e [V

]

NMOS = 0.5m/0.25 mPMOS = 0.75m/0.25 mCL = 100 fF

Sized for tpLH =~ tpHL


Entradas Atraso (ps)

A=B=01 69

A=1, B=01 50

A= 01, B=1 62

A=B=10 35

A=1, B=10 57

A= 10, B=1 76





-0,5

0

0,5

1

1,5

2

2,5

3

0 100 200 300 400

A=B=10

A=1, B=10

A=1 0, B=1

time [ps]

Vo

ltag

e [V

]

NMOS = 0.5m/0.25 mPMOS = 0.75m/0.25 mCL = 100 fF

Sized for tpLH =~ tpHL


B=1

S=0

A=1

A=1 B=1

CL=0 V

Vdd

Cint=0 V

B=1

S=1

A=0

A=0 B=1

CL=Vdd

Vdd

Vdd-VTn




• The VT of the two NMOS transistors are calculate by:

The “Body Effect”


VTn2 = Vtn0 + (( 2f + Vint)0.5 – (2f)0.5)

VTn1 = Vtn0

B

S

A

A B

Vdd

M1

M2

int




Transistor Sizing

Distributed RC model (“Elmore Delay”)

tpHL = 0,69 (R1 C1+ (R1+R2) C2 +

+ (R1+R2+R3) C3 + (R1+R2+R3+R4) CL)

If R1=R2=R3=R4 then:

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

CL

C

R7

D

R8

A

R4

B

R3C3

A

R5

B

R6

C

R2

D

R1C1

C2

Considering intra-cell capacitances




Gates with more than 4 inputs should be avoided…

tpLH

t p (

ps)

fanin

0

250

500

750

1000

1250

2 4 6 8 10 12 14 16

tpHL

quadratic

linear

tp

Propagation Delay as a Function of Fan-In


Propagation delay of CMOS NAND gate




2 4 6 8 10 12 14 16

tpNOR2

t p (

pse

c)

eff. fan-out

All gates have the same drive current.

tpNAND2

tpINV

Slope is a function of “driving strength”

Propagation Delay as a Function of Fan-Out





• Fan-in: quadratic due to increasing resistance and capacitance

• Fan-out: each additional fan-out gate adds two gate capacitances to CL

tp = a1FI + a2FI2 + a3FO

Propagation Delay as a Function of Fan-Out





• Transistor sizing

– Desde que a capacitância de saída domine

• Progressive sizing

InN CL

C3

C2

C1In1

In2

In3

M1

M2

M3

MNRC distribuído

WM1 > WM2 > WM3 > … > WMN

(o trans. mais próximo da saída tema a menor resistência de canal.)

Pode reduzir o atraso da porta em até 20% (segundo Rabaey)

Design Techniques for Static CMOS Gates





Transistor ordering

C2

C1In1

In2

In3

M1

M2

M3 CL

C2

C1In3

In2

In1

M1

M2

M3 CL

Critical path

1

01

charged1

O Atraso é determinado pelo tempo para descarregar CL, C1

e C2

1

1

01

charged

charged

Critical path

charged

charged

charged

O Atraso é determinado pelo tempo para descarregar CL






• Explorando a Decomposição Lógica

F = ABCDEFGH

Lógica de 2 níveis em CMOS

Elevando fanin (evitar)

Faninlimitado a 2, fanout unitário Source: Rabaey; Chandrakasan; Nikolic, 2005





• Isolamento de carga elevada usando buffer

CLCL






Cell Design

• Standard Cells– General purpose logic– Can be synthesized– Same height, varying width

• Datapath Cells– For regular, structured designs (arithmetic)– Includes some wiring in the cell– Fixed height and width





Standard Cell Layout Methodology – 1980s

signals

Routingchannel

VDD

GND





Standard Cell Layout Methodology – 1990s

M2

No Routingchannels

VDD

GNDM3

VDD

GND

Mirrored Cell

Mirrored CellSource: Rabaey; Chandrakasan; Nikolic, 2005




Standard Cells

Cell boundary

N Well

Cell height 12 metal tracksMetal track is approx. 3 + 3Pitch = repetitive distance between objects

Cell height is “12 pitch”

2

Rails ~10

InOut

VDD

GND





Standard Cells

InOut

VDD

GND

In Out

VDD

GND

With silicided diffusion

With minimaldiffusionrouting

OutIn

VDD

M2

M1





Standard Cells

A

Out

VDD

GND

B

2-input NAND gate

B

VDD

A





Stick Diagrams

Contains no dimensionsRepresents relative positions of transistors

In

Out

VDD

GND

Inverter

A

Out

VDD

GNDB

NAND2





Stick Diagrams

C

A B

X = C • (A + B)

B

AC

i

j

j

VDDX

X

i

GND

AB

C

PUN

PDNABC

Logic Graph





Two Versions of C • (A + B)

X

CA B A B C

X

VDD

GND

VDD

GND





Consistent Euler Path

j

VDDX

X

i

GND

AB

C

A B C





OAI22 Logic Graph

C

A B

X = (A+B)•(C+D)

B

A

D

VDDX

X

GND

AB

C

PUN

PDN

C

D

D

ABCD





Multi-Fingered TransistorsOne finger Two fingers (folded)

Less diffusion capacitance





Pass Transistor LogicExemplo 1: uma função arbitrária (com 4 vars. de controle)

saída

A’

B’

A B

E1

E2

A B saída

0 0 E1’

0 1 E1’

1 0 E1’

1 1 E2’

Saída = ABE2’+A’E1’+B’E1’

buffer

• N transistores• Sem consumo estático




• Vx não consegue atingir Vdd, mas Vdd -VTn(Vx) (efeito de corpo)• Tensão na entrada do inversor não é suficiente para desligar o transistor

PMOS• Mensagem: não cascatear transistores de passagem, conectando-os a gates

de outras estruturas similares.

~~

O Comportamento do Transistor de Passagem

VDD

In

Outx

0.5m/0.25m0.5m/0.25m

1.5m/0.25m

0 0.5 1 1.5 20.0

1.0

2.0

3.0

Tempo [ns]

xOut

In

Ten

são

[V]





NMOS-only Switch

A = 2.5 V

B

C = 2.5 V

CL

A = 2.5 V

C = 2.5 V

BM2

M1

Mn

Threshold voltage loss causesstatic power consumption

VB does not pull up to 2.5V, but 2.5V - VTN

NMOS has higher threshold than PMOS (body effect)Source: Rabaey; Chandrakasan; Nikolic, 2005




NMOS Only Logic: Level Restoring Transistor

M2

M1

Mn

Mr

OutA

B

VDDVDDLevel Restorer

X

• Advantage: Full Swing

• Restorer adds capacitance, takes away pull down current at X

• Ratio problemSource: Rabaey; Chandrakasan; Nikolic, 2005




Restorer Sizing

0 100 200 300 400 5000.0

1.0

2.0

W/Lr =1.0/0.25 W/Lr =1.25/0.25

W/Lr =1.50/0.25

W/Lr =1.75/0.25

Vol

tage

[V]

Time [ps]

3.0•Upper limit on restorer size•Pass-transistor pull-downcan have several transistors in stack





Solution 2: Single Transistor Pass Gate with VT=0

Out

VDD

VDD

2.5V

VDD

0V 2.5V

0V

WATCH OUT FOR LEAKAGE CURRENTS Source: Rabaey; Chandrakasan; Nikolic, 2005




Complementary Pass Transistor Logic

A

B

A

B

B B B B

A

B

A

B

F=AB

F=AB

F=A+B

F=A+B

B B

A

A

A

A

F=AÝ

F=AÝ

OR/NOR EXOR/NEXORAND/NAND

F

F

Pass-Transistor

Network

Pass-TransistorNetwork

AABB

AABB

Inverse

(a)

(b)





Solution 3: Transmission Gate

A B

C

C

A B

C

C

B

CL

C = 0 V

A = 2.5 V

C = 2.5 V





Resistance of Transmission Gate

Vout

0 V

2.5 V

2.5 VRn

Rp

0.0 1.0 2.00

10

20

30

Vout, V

Res

ista

nce

, oh

ms

Rn

Rp

Rn || Rp





Pass-Transistor Based Multiplexer

AM2

M1

B

S

S

S F

VDD

GND

VDD

In1

In2

S S

S S





Transmission Gate XOR

A

B

F

B

A

B

B

M1

M2

M3/M4





Delay in Transmission Gate Networks

V1 Vi-1

C

2.5 2.5

0 0

Vi Vi+1

CC

2.5

0

Vn-1 Vn

CC

2.5

0

In

V1 Vi Vi+1

C

Vn-1 Vn

CC

In

ReqReq Req Req

CC

(a)

(b)

C

Req Req

C C

Req

C C

Req Req

C C

Req

C

In

m

(c)





Delay Optimization





Transmission Gate Full Adder

A

B

P

Ci

VDDA

A A

VDD

Ci

A

P

AB

VDD

VDD

Ci

Ci

Co

S

Ci

P

P

P

P

P

Sum Generation

Carry Generation

Setup

Similar delays for sum and carrySource: Rabaey; Chandrakasan; Nikolic, 2005

Documents

Universidade Federal de Santa Catarina Centro Tecnológico Computer Science & Electrical Engineering Lectures 33 to 36 Combinational Circuits in CMOS Digital