Upload
phamdiep
View
215
Download
0
Embed Size (px)
Citation preview
11/7/2012
1
© Synopsys 2012 1
Will Everything Start To Look Like An SoC?
Janick Bergeron, Synopsys
Verification Futures Conference 2012
France, Germany, UK
November 2012
© Synopsys 2012 2
SystemVerilog Inherits the Earth
• SystemVerilog and UVM are now mainstream– Previous languages / methodologies will persist . . .
. . . but new developments will be slow
. . . and new users will be rare.
2002 2004 2006 2008 2010
eRM
RVM
uRM
AVM1.0/2.0/3.0
OVM1.0/2.0
VMM 1.0
SystemCTLM 1.0
SystemCTLM 2.0
VMM 1.2
UVM 1.0/1.1
e
OV
SV
SC
SVVMM 1.1
2012
UVM 1.2
11/7/2012
2
© Synopsys 2012 3
Methodology Deployment Ecosystem
ProtocolDebug
Template Generators
VerificationPlanning
VerificationManagement
UVM-AwareDebug
ConstraintSolver
Coverage & Analysis
NativeUVM VIP
UVM TLM/SC AdaptorsUVM AMS
Testbench
© Synopsys 2012 4
Will Everything Look Like an SoC?
Processor
High-performanceInternal Architecture
Data ProcessingSoftware
Mobile
Low-powerExternal StandardsGraphics ProcessingSoftwareLinks to Analog
Performance/power OptimisationInternal and External Standards
Links to AnalogMultiple ProcessorsMultiple Protocols
Software
System on Chip
ScientificIndustrial InfrastructureAerospace MilitaryMedicalAutomotive
SoC-targeted Tool Developments Will Benefit ALL chip Designs
11/7/2012
3
© Synopsys 2012 5
Needs Accelerated Innovation
• 10x Performance
• 10x Capacity
• 10x VIP Productivity
• 10x Constraints & Coverage
• Advanced LP solutions
• High-speed AMS Simulation
• 10x Debug Productivity
• 10x Reuse methodology
• Hw/Sw Co-Verification
Significant Challenges RemainConvergence Driving SoC Complexity
Platform Convergence
• Increasing complexity of specs
• Shrinking time to market
• Exploding SW content
• Increasing development cost
CPU + Graphics + ModemMultimedia + Networking
PC + Mobile Increasing
HW Functionality
1
10X Increase InVerification Complexity
2
10X Increase Needed inProductivity
3
Today’s Verification Complexity
• 44M+ lines of RTL & Testbench
• 168GB+ memory required
• 10+ protocols
• TB of coverage data
• 300,000+ assertions
• 200+ power domains
• Debug 35% of verification
• 2:1 verif/design engineers
• 2X CPU farm
© Synopsys 2012 6
10x Performance, 10x Capacity
• Massive Parallelism– Many designs have repeated structures
– Many tests are run on the same DUT
– Can we automatically utilise this in order to increase performance?
• New Compute Platforms– Are CPUs the best simulation platform?
– Can we use FPGAs for acceleration?− SIMD, Single-Instruction-Multiple-Data
– What of other computing platforms?− Employ GPU via OPENCL compilers?
− Cloud-based simulation?
11/7/2012
4
© Synopsys 2012 7
VIP Productivity Challenge
More protocols in use per chip, each protocol evolving
© Synopsys 2012 8
VIP Productivity Challenge
A small step in for a protocol . . . . . . can be a giant leap in complexity.
AMBA AHBUSB2.0
AMBA APB
UART
I2CSDIO
MMC-SD
PCI
USB 2.0 Traffic
AMBA4 AXI
USB2.0
AMBA4 ACE
UART
HDMI
I2C
SDIOMMC-SD
GPIO
USB3.0
MIPI DSI
MIPI CSIMIPI LLISLIM Bus
HDMI
HDMI
USB OTG SATA
MIPI HSI
PCIeUSB 3.0
USB 3.0 Traffic
10X Protocols Increasing complexity per protocol (20x scenarios, 10x data)
11/7/2012
5
© Synopsys 2012 9
Today’s VIP Productivity Challenges
Configuration & Test Development
• 20x increase in scenarios
• 2-4 weeks before the first test
Performance• 3M+ lines of VIP code
per SOC
• Multiple layers of PLI wrappers
Debug• Several days to find
root cause, due to limited visibility
• Current debug tools not protocol-aware
Coverage Closure• 2 man-months to
create coverage plan per title
• 3 man-months to implement coverage and scenarios
Current VIP technology running out of steam
SV Interface
Vera
UVMOVMVMM
UVMOVM
SV Interface
eRM
‘e’
VMM
SV Interface
C
OVM UVM
‘e’ and C based VIP
Vera-based VIP
© Synopsys 2012 10
Native UVM / VMM / OVMNative UVM / VMM / OVM
Sequence Collection
ConfigurationCreator
Customization
Coverage Database
User Verification
Plan
Protocol Test Plan
Coverage
Protocol Analyzer
VIP
Source
Visibility
DVE
Debug
Testbench
NativeSystemVerilog Protocol VIP
Test Suite
User Tests
DUT
Monitor
Coverage Model
Sequencer
Protocol L2
Link L1
Physical Driver
Virtual S
equencer
Configuration
AIP
• 100% SystemVerilog
• High Performance
• Ease of Use
• Native Methodology Support
• Sequence Collections
• Built-in Coverage
• Built-in Verification Plans
• Protocol Aware Debug
VIP Moves to SystemVerilog20+ Industry Experts collaborated on Requirements and Architecture
11/7/2012
6
© Synopsys 2012 11
10x Constraints and Coverage Efficiency
Plan
Ana
lyze
Manage
Verification&
Coverage
Data
• Interactiveauthoring
• Annotation
• Trend analysis• Grading• Exclusions
• Integratedexecution
• Regressionmonitoring
© Synopsys 2012 12
Advanced Low-Power Solutions
• VCS-NLP provides a unique voltage-aware modeling engine combined with industry leading native compiled-code simulation
• 50% faster and higher capacity than non-native mode– Minimal runtime impact vs. non-LP simulation
• Ease-of-use– Supports industry-standard IEEE 1801 (UPF)
– Leverages VCS use model including testbench, coverage, and debug
– Single compile step
– All VCS command line options supported
• Ease-of-debug– Enhanced low power debug
11/7/2012
7
© Synopsys 2012 13
Verdi Debug
10x Debug Productivity
Methodology-aware DebugSupports VMM-UVM-OVM
Windows for:Class Object ResourceFactoryPhaseSequence
Transactions Handshaking
Transcript
Protocol-aware Debug
Transaction Recording
© Synopsys 2012 14
Partnership with Industry Leaders
VCS customer spotlights on EE Times: