© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63., by Deepali KamthaniaU1. 1
UNIT-IIBASIC COMPUTER
ORGANIZATION AND DESIGN
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 2
• System Bus •Instruction Codes
• Computer Registers
• Computer Instructions
• Timing and Control
• Instruction Cycle
• Memory Reference Instructions
• Input-Output and Interrupt
• Complete Computer Description
• Design of Basic Computer
• Design of Accumulator Logic
LEARNING OBJECTIVES
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 3
STRUCTURE
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 4
• The major computer system components (processor, main memory, I/O modules) need to be interconnected in order to exchange data and control signals
• A bus is a communication pathway connecting two or more devices
• A bus that connects major computer components (processor, memory, I/O) is called a system bus.
• Bus = a shared transmission medium. Only one device at a time Can successfully transmit.
shared system bus consisting of multiple lines
a hierarchy of buses to improve performance.
• Key design elements for buses include: Arbitration, Timing, width
SYSTEM BUSES
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 5
SYSTEM BUSES
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 6
• In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay.
• The bus may become a bottleneck as the aggregate data transfer demand approaches the capacity of the bus.
MULTIPLE BUS HIERARCHIES
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• Synchronous buses include a clock line between the control lines, line that is controlled by a clock quartz oscillator, usually between 5 - 133 MHz
• All the transfers on the system bus has a fixed protocol related to the clock signal, and it is developed along an integer number of cycles, called bus cycles.
• The advantages of a synchronous bus are a high speed of transfer, the very simple implied logic
• The disadvantage comes from transfers that can be shorter than the time corresponding to the integer number of bus cycles.
SYNCHRONOUS BUSES
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INTRODUCTION
• Every different processor type has its own design (different registers, buses, microoperations, machine instructions, etc)
• Modern processor is a very complex device
• It contains
Many registers
Multiple arithmetic units, for both integer and floating point calculations
The ability to pipeline several consecutive instructions to speed execution etc.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 9
INTRODUCTION
• However, to understand how processors work, we will start with a simplified processor model
• This is similar to what real processors were like ~25 years ago
• M. Morris Mano introduces a simple processor model he calls the Basic Computer
• We will use this to introduce processor organization and the relationship of the RTL model to the higher level computer processor
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 10
BASIC COMPUTER
• The Basic Computer has two components, a processor and memory
• The memory has 4096 words in it
4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long
CPU RAM0
4095
015
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INSTRUCTIONSInstruction codes
• Program
A sequence of (machine) instructions
• (Machine) Instruction
A group of bits that tell the computer to perform a specific operation (a sequence of micro-operation)
• The instructions of a program, along with any needed data are stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the instruction into the sequence of microoperations necessary to implement it
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INSTRUCTION FORMATInstruction codes
• A computer instruction is often divided into two parts
An opcode (Operation Code) that specifies the operation for that instruction
An address that specifies the registers and/or locations in memory to use for that operation
• In the Basic Computer, since the memory contains 4096 (= 212) words, we needs 12 bit to specify which memory address this instruction will use
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 13
INSTRUCTION FORMATInstruction codes
• In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0: direct addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits long, that leaves 3 bits for the instruction’s opcode
Opcode Address
Instruction Format
15 14 12 0I
11
Addressing mode
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ADDRESSING MODESInstruction codes
The address field of an instruction can represent either Direct address: the address in memory of the data to use (the
address of the operand), or Indirect address: the address in memory of the address in memory of
the data to use
Effective Address (EA) The address, that can be directly used without modification to access
an operand for a computation-type instruction, or as the target address for a branch-type instruction
0 ADD 45722
Operand457
1 ADD 30035
1350300
Operand1350
+
AC
+
AC
Direct addressing Indirect addressing
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PROCESSOR REGISTERSInstruction codes
• A processor has many registers to hold instructions, addresses, data, etc
• The processor has a register, the Program Counter (PC) that holds the memory address of the next instruction to get Since the memory in the Basic Computer only has 4096
locations, the PC only needs 12 bits
• In a direct or indirect addressing, the processor needs to keep track of what locations in memory it is addressing: The Address Register (AR) is used for this The AR is a 12 bit register in the Basic Computer
• When an operand is found, using either direct or indirect addressing, it is placed in the Data Register (DR). The processor then uses this value as data for its operation
• The Basic Computer has a single general purpose register – the Accumulator (AC)
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 16
PROCESSOR REGISTERSInstruction codes
• The significance of a general purpose register is that it can be referred to in instructions e.g. load AC with the contents of a specific memory location;
store the contents of AC into a specified memory location
• Often a processor will need a scratch register to store intermediate results or other temporary data; in the Basic Computer this is the Temporary Register (TR)
• The Basic Computer uses a very simple model of input/output (I/O) operations Input devices are considered to send 8 bits of character data
to the processor The processor can send 8 bits of character data to output
devices
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PROCESSOR REGISTERS
• The Input Register (INPR) holds an 8 bit character gotten from an input device
• The Output Register (OUTR) holds an 8 bit character to be send to an output device
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 18
BASIC COMPUTER REGISTERS
List of BC RegistersDR 16 Data Register Holds memory operandAR 12 Address Register Holds address for memoryAC 16 Accumulator Processor registerIR 16 Instruction Register Holds instruction codePC 12 Program Counter Holds address of instructionTR 16 Temporary Register Holds temporary dataINPR 8 Input Register Holds input characterOUTR 8 Output Register Holds output character
Registers
Registers in the Basic Computer
11 0PC
15 0IR
15 0
TR
7 0
OUTR
15 0
DR
15 0AC
11 0
AR
INPR0 7
Memory
4096 x 16
CPU
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COMMON BUS SYSTEMRegisters
• The registers in the Basic Computer are connected using a bus
• This gives a savings in circuitry over complete connections between registers
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COMMON BUS SYSTEMRegisters
S2S1S0
Bus
Memory unit4096 x 16
LD INR CLR
Address
ReadWrite
AR
LD INR CLR
PC
LD INR CLR
DR
LD INR CLR
ACALUE
INPR
IRLD
LD INR CLR
TR
OUTRLD
Clock
16-bit common bus
7
1
2
3
4
5
6
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 21
COMMON BUS SYSTEMRegisters
AR
PC
DR
L I C
L I C
L I C
AC
L I C
ALUE
IR
L
TR
L I C
OUTR LD
INPRMemory
4096 x 16
Address
Read
Write
16-bit Common Bus
7 1 2 3 4 5 6
S0 S1 S2
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COMMON BUS SYSTEMRegisters
• Three control lines, S2, S1, and S0 control which register the bus selects as its input
• Either one of the registers will have its load signal activated, or the memory will have its read signal activated Will determine where the data from the bus gets loaded
• The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the high order 4 bit positions
• When the 8-bit register OUTR is loaded from the bus, the data comes from the low order 8 bits on the bus
0 0 0 x0 0 1 AR0 1 0 PC0 1 1 DR1 0 0 AC1 0 1 IR1 1 0 TR1 1 1 Memory
S2 S1 S0 Register
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 23
BASIC COMPUTER INSTRUCTIONS
• Basic Computer Instruction Format
15 14 12 11 0
I Opcode Address
Memory-Reference Instructions (OP-code = 000 ~ 110)
Register-Reference Instructions (OP-code = 111, I = 0)
Input-Output Instructions (OP-code =111, I = 1)
15 12 11 0Register operation0 1 1 1
15 12 11 0I/O operation1 1 1 1
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BASIC COMPUTER INSTRUCTIONS
Hex CodeSymbol I = 0 I = 1 DescriptionAND 0xxx 8xxx AND memory word to ACADD 1xxx 9xxx Add memory word to ACLDA 2xxx Axxx Load AC from memorySTA 3xxx Bxxx Store content of AC into memoryBUN 4xxx Cxxx Branch unconditionallyBSA 5xxx Dxxx Branch and save return addressISZ 6xxx Exxx Increment and skip if zero
CLA 7800 Clear ACCLE 7400 Clear ECMA 7200 Complement ACCME 7100 Complement ECIR 7080 Circulate right AC and ECIL 7040 Circulate left AC and EINC 7020 Increment ACSPA 7010 Skip next instr. if AC is positiveSNA 7008 Skip next instr. if AC is negativeSZA 7004 Skip next instr. if AC is zeroSZE 7002 Skip next instr. if E is zeroHLT 7001 Halt computer
INP F800 Input character to ACOUT F400 Output character from ACSKI F200 Skip on input flagSKO F100 Skip on output flagION F080 Interrupt onIOF F040 Interrupt off
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INSTRUCTION SET COMPLETENESS
• Instruction Types
A computer should have a set of instructions so that the user can construct machine language programs to evaluate any function that is known to be computable.
Functional Instructions - Arithmetic, logic, and shift instructions - ADD, CMA, INC, CIR, CIL, AND, CLATransfer Instructions - Data transfers between the main memory
and the processor registers - LDA, STAControl Instructions - Program sequencing and control - BUN, BSA, ISZInput/Output Instructions - Input and output - INP, OUT
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CONTROL UNIT
• Control unit (CU) of a processor translates from machine instructions to the control signals for the microoperations that implement them
• Control units are implemented in one of two ways• Hardwired Control
CU is made up of sequential and combinational circuits to generate the control signals
• Microprogrammed Control A control memory on the processor contains microprograms that
activate the necessary control signals
• We will consider a hardwired implementation of the control unit for the Basic Computer
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 27
HARDWIRED/MICROPROGRAMMED
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TIMING AND CONTROL
Control unit of Basic Computer
Instruction register (IR)15 14 13 12 11 - 0
3 x 8decoder
7 6 5 4 3 2 1 0
ID0
15 14 . . . . 2 1 04 x 16
decoder
4-bitsequence
counter(SC)
Increment (INR)Clear (CLR)
Clock
Other inputs
Controlsignals
D
T
T
7
15
0
CombinationalControl
logic
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TIMING SIGNALS
Clock
T0 T1 T2 T3 T4 T0
T0
T1
T2
T3
T4
D3
CLR SC
- Generated by 4-bit sequence counter and 416 decoder- The SC can be incremented or cleared.
- Example: T0, T1, T2, T3, T4, T0, T1, . . . Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC 0
Timing and control
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INSTRUCTION CYCLE
• In Basic Computer, a machine instruction is executed in the following cycle:– Fetch an instruction from memory– Decode the instruction– Read the effective address from memory if the instruction has
an indirect address– Execute the instruction
• After an instruction is executed, the cycle starts again at step 1, for the next instruction
• Note: Every different processor has its own (different) instruction cycle
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 31
FETCH and DECODE
• Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)T1: IR M [AR], PC PC + 1 (S0S1S2=111, T1=1)T2: D0, . . . , D7 Decode IR(12-14), AR IR(0-11), I IR(15)
S2
S1
S0
Bus
7Memory
unitAddress
Read
AR
LD
PC
INR
IR
LD Clock
1
2
5
Common bus
T1
T0
Instruction Cycle
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DETERMINE THE TYPE OF INSTRUCTION
D'7IT3: AR M[AR]D'7I'T3: NothingD7I'T3: Execute a register-reference instr.D7IT3: Execute an input-output instr.
Instruction Cycle
= 0 (direct)
StartSC
AR PCT0
IR M[AR], PC PC + 1T1
AR IR(0-11), I IR(15)Decode Opcode in IR(12-14),
T2
D7= 0 (Memory-reference)(Register or I/O) = 1
II
Executeregister-reference
instructionSC 0
Executeinput-outputinstructionSC 0
M[AR]AR Nothing
= 0 (register)(I/O) = 1 (indirect) = 1
T3 T3 T3 T3
Executememory-reference
instructionSC 0
T4
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REGISTER REFERENCE INSTRUCTIONS
r = D7 IT3 => Register Reference InstructionBi = IR(i) , i=0,1,2,...,11
- D7 = 1, I = 0- Register Ref. Instr. is specified in b0 ~ b11 of IR- Execution starts with timing signal T3
Instruction Cycle
Register Reference Instructions are identified when
r: SC 0CLA rB11: AC 0CLE rB10: E 0CMA rB9: AC AC’CME rB8: E E’CIR rB7: AC shr AC, AC(15) E, E AC(0)CIL rB6: AC shl AC, AC(0) E, E AC(15)INC rB5: AC AC + 1SPA rB4: if (AC(15) = 0) then (PC PC+1)SNA rB3: if (AC(15) = 1) then (PC PC+1)SZA rB2: if (AC = 0) then (PC PC+1)SZE rB1: if (E = 0) then (PC PC+1)HLT rB0: S 0 (S is a start-stop flip-flop)
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MEMORY REFERENCE INSTRUCTIONS
AND to ACD0T4: DR M[AR] Read operandD0T5: AC AC DR, SC 0 AND with AC
ADD to ACD1T4: DR M[AR] Read operandD1T5: AC AC + DR, E Cout, SC 0 Add to AC and store carry in E
- The effective address of the instruction is in AR and was placed there during timing signal T2 when I = 0, or during timing signal T3 when I = 1- Memory cycle is assumed to be short enough to complete in a CPU cycle- The execution of MR instruction starts with T4
MR Instructions
SymbolOperationDecoder
Symbolic Description
AND D0 AC AC M[AR]ADD D1 AC AC + M[AR], E Cout
LDA D2 AC M[AR]STA D3 M[AR] ACBUN D4 PC ARBSA D5 M[AR] PC, PC AR + 1ISZ D6 M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1
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MEMORY REFERENCE INSTRUCTIONS
Memory, PC after execution
21
0 BSA 135
Next instruction
Subroutine
20
PC = 21
AR = 135
136
1 BUN 135
Memory, PC, AR at time T4
0 BSA 135
Next instruction
Subroutine
20
21
135
PC = 136
1 BUN 135
Memory Memory
LDA: Load to ACD2T4: DR M[AR]D2T5: AC DR, SC 0
STA: Store ACD3T4: M[AR] AC, SC 0
BUN: Branch UnconditionallyD4T4: PC AR, SC 0
BSA: Branch and Save Return AddressM[AR] PC, PC AR + 1
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MEMORY REFERENCE INSTRUCTIONS
MR Instructions
BSA: D5T4: M[AR] PC, AR AR + 1D5T5: PC AR, SC 0
ISZ: Increment and Skip-if-ZeroD6T4: DR M[AR]D6T5: DR DR + 1D6T4: M[AR] DR, if (DR = 0) then (PC PC + 1), SC 0
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FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS
Memory-reference instruction
DR M[AR] DR M[AR] DR M[AR] M[AR] ACSC 0
AND ADD LDA STA
AC AC DRSC 0
AC AC + DRE CoutSC 0
AC DRSC 0
D T0 4 D T1 4 D T2 4 D T3 4
D T0 5 D T1 5 D T2 5
PC ARSC 0
M[AR] PCAR AR + 1
DR M[AR]
BUN BSA ISZ
D T4 4 D T5 4 D T6 4
DR DR + 1
D T5 5 D T6 5
PC ARSC 0
M[AR] DRIf (DR = 0)then (PC PC + 1)SC 0
D T6 6
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INPUT-OUTPUT AND INTERRUPT
• Input-Output Configuration
INPR Input register - 8 bitsOUTR Output register - 8 bitsFGI Input flag - 1 bitFGO Output flag - 1 bitIEN Interrupt enable - 1 bit
A Terminal with a keyboard and a Printer
Input-outputterminal
Serialcommunication
interfaceComputerregisters andflip-flops
Printer
Keyboard
Receiverinterface
Transmitterinterface
FGOOUTR
AC
INPR FGI
Serial Communications PathParallel Communications Path
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INPUT-OUTPUT AND INTERRUPT
- The terminal sends and receives serial information
- The serial info. from the keyboard is shifted into INPR
-The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal serially and with the AC in parallel.
- The flags are needed to synchronize the timing difference between I/O device and the computer
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PROGRAM CONTROLLED DATA TRANSFER
loop: If FGI = 1 goto loop
INPR new data, FGI 1
loop: If FGO = 1 goto loop
consume OUTR, FGO 1
-- CPU -- -- I/O Device --
/* Input */ /* Initially FGI = 0 */ loop: If FGI = 0 goto loop AC INPR, FGI 0
/* Output */ /* Initially FGO = 1 */ loop: If FGO = 0 goto loop OUTR AC, FGO 0
I/O and Interrupt
Start Input
FGI 0
FGI=0
AC INPR
MoreCharacter
END
Start Output
FGO 0
FGO=0
MoreCharacter
END
OUTR AC
AC Data
yes
no
yes
no
FGI=0 FGO=1
yes
yesno
no
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INPUT-OUTPUT INSTRUCTIONS
D7IT3 = pIR(i) = Bi, i = 6, …, 11
p: SC 0 Clear SCINP pB11: AC(0-7) INPR, FGI 0 Input char. to AC OUT pB10: OUTR AC(0-7), FGO 0 Output char. from AC SKI pB9: if(FGI = 1) then (PC PC + 1) Skip on input flag SKO pB8: if(FGO = 1) then (PC PC + 1) Skip on output flagION pB7: IEN 1 Interrupt enable onIOF pB6: IEN 0 Interrupt enable off
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PROGRAM-CONTROLLED INPUT/OUTPUT
• Program-controlled I/O
- Continuous CPU involvement I/O takes valuable CPU time- CPU slowed down to I/O speed- Simple- Least hardware
I/O and Interrupt
Input
LOOP, SKI DEV BUN LOOP INP DEV
Output
LOOP, LDA DATA LOP, SKO DEV BUN LOP OUT DEV
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INTERRUPT INITIATED INPUT/OUTPUT
- Open communication only when some data has to be passed --> interrupt.
- The I/O interface, instead of the CPU, monitors the I/O device.
- When the interface founds that the I/O device is ready for data transfer, it generates an interrupt request to the CPU
- Upon detecting an interrupt, the CPU stops momentarily the task it is doing, branches to the service routine to process the data transfer, and then returns to the task it was performing.
* IEN (Interrupt-enable flip-flop)- can be set and cleared by instructions- when cleared, the computer cannot be interrupted
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FLOWCHART FOR INTERRUPT CYCLE
R = Interrupt f/f
I/O and Interrupt
Store return address
R =1=0
in location 0M[0] PC
Branch to location 1PC 1
IEN 0 R 0
Interrupt cycleInstruction cycle
Fetch and decodeinstructions
IEN
FGI
FGO
Executeinstructions
R 1
=1=1
=1
=0
=0
=0
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INTERRUPT CYCLE
- The interrupt cycle is a HW implementation of a branch and save return address operation.- At the beginning of the next instruction cycle, the instruction that is read from memory is in address 1.-At memory address 1, the programmer must store a branch instruction that sends the control to an interrupt service routine- The instruction that returns the control to the original
program is "indirect BUN 0"
I/O and Interrupt
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REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE
Register Transfer Statements for Interrupt Cycle- R F/F 1 if IEN (FGI + FGO)T0T1T2 T0T1T2 (IEN)(FGI + FGO): R 1
- The fetch and decode phases of the instruction cycle must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :
RT0: AR 0, TR PC
RT1: M[AR] TR, PC 0
RT2: PC PC + 1, IEN 0, R 0, SC 0
After interrupt cycle
0 BUN 112001
PC = 256255
1 BUN 0
Before interrupt
MainProgram
1120I/O
Program
0 BUN 11200
PC = 1
256255
1 BUN 0
Memory
MainProgram
1120I/O
Program
256
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FURTHER QUESTIONS ON INTERRUPT
• How can the CPU recognize the device requesting an interrupt ?
• Since different devices are likely to require different interrupt service routines, how can the CPU obtain the starting address of the appropriate routine in each case ?
• Should any device be allowed to interrupt the CPU while another interrupt is being serviced ?
• How can the situation be handled when two or more interrupt requests occur simultaneously ?
I/O and Interrupt
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COMPLETE COMPUTER DESCRIPTIONFlowchart of Operations
Description
=1 (I/O) =0 (Register) =1(Indir) =0(Dir)
startSC 0, IEN 0, R 0
R
AR PCR’T0
IR M[AR], PC PC + 1R’T1
AR IR(0~11), I IR(15)D0...D7 Decode IR(12 ~ 14)
R’T2
AR 0, TR PCRT0
M[AR] TR, PC 0RT1
PC PC + 1, IEN 0R 0, SC 0
RT2
D7
I I
ExecuteI/O
Instruction
ExecuteRR
Instruction
AR <- M[AR] IdleD7IT3 D7I’T3 D7’IT3 D7’I’T3
Execute MRInstruction
=0(Instruction =1(Interrupt Cycle) Cycle)
=1(Register or I/O) =0(Memory Ref)
D7’T4
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COMPLETE COMPUTER DESCRIPTION MICROOPERATIONS`
Description
Fetch
Decode
IndirectInterrupt
Memory-Reference AND
ADD
LDA
STA BUN BSA
ISZ
RT0: RT1:RT2:
D7IT3:
RT0:RT1:RT2:
D0T4:D0T5:D1T4:D1T5:D2T4:D2T5:D3T4:D4T4:D5T4:D5T5:D6T4:D6T5:D6T6:
AR PCIR M[AR], PC PC + 1D0, ..., D7 Decode IR(12 ~ 14),
AR IR(0 ~ 11), I IR(15)AR M[AR]
R 1AR 0, TR PCM[AR] TR, PC 0PC PC + 1, IEN 0, R 0, SC 0
DR M[AR]AC AC DR, SC 0DR M[AR]AC AC + DR, E Cout, SC 0DR M[AR]AC DR, SC 0M[AR] AC, SC 0PC AR, SC 0M[AR] PC, AR AR + 1PC AR, SC 0DR M[AR]DR DR + 1M[AR] DR, if(DR=0) then (PC PC + 1), SC 0
T0T1T2(IEN)(FGI + FGO):
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 50
Register-Reference
CLA CLE CMA CME CIR CIL INC SPA SNA SZA SZE HLT
Input-Output
INP OUT SKI SKO ION IOF
D7IT3 = rIR(i) = Bi r: rB11: rB10: rB9: rB8: rB7: rB6: rB5: rB4: rB3: rB2: rB1: rB0:
D7IT3 = p IR(i) = Bi p: pB11: pB10: pB9: pB8: pB7: pB6:
(Common to all register-reference instr)(i = 0,1,2, ..., 11)SC 0AC 0E 0AC ACE EAC shr AC, AC(15) E, E AC(0)AC shl AC, AC(0) E, E AC(15)AC AC + 1If(AC(15) =0) then (PC PC + 1)If(AC(15) =1) then (PC PC + 1)If(AC = 0) then (PC PC + 1)If(E=0) then (PC PC + 1)S 0
(Common to all input-output instructions)(i = 6,7,8,9,10,11)SC 0AC(0-7) INPR, FGI 0OUTR AC(0-7), FGO 0If(FGI=1) then (PC PC + 1)If(FGO=1) then (PC PC + 1)IEN 1IEN 0
Description
COMPLETE COMPUTER DESCRIPTION MICROOPERATIONS
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 51
DESIGN OF BASIC COMPUTER(BC)
Hardware Components of BC A memory unit: 4096 x 16.Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SCFlip-Flops(Status): I, S, E, R, IEN, FGI, and FGODecoders: a 3x8 Opcode decoder a 4x16 timing decoderCommon bus: 16 bitsControl logic gates:Adder and Logic circuit: Connected to AC
Control Logic Gates- Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S2, S1, S0 Controls to select a register for the bus
- AC, and Adder and Logic circuit
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 52
CONTROL OF REGISTERS AND MEMORY
Scan all of the register transfer statements that change the content of AR:
LD(AR) = R'T0 + R'T2 + D'7IT3
CLR(AR) = RT0
INR(AR) = D5T4
Address Register; AR
R’T0: AR PC LD(AR)R’T2: AR IR(0-11) LD(AR)D’7IT3: AR M[AR] LD(AR)RT0: AR 0 CLR(AR)D5T4: AR AR + 1 INR(AR)
Design of Basic Computer
AR
LDINR
CLR
Clock
To bus12
From bus12
D'I
TT
RTDT
7
32
0
4
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 53
CONTROL OF FLAGS
pB7: IEN 1 (I/O Instruction)pB6: IEN 0 (I/O Instruction)RT2: IEN 0 (Interrupt)
p = D7IT3 (Input/Output Instruction)
IEN: Interrupt Enable Flag
Design of Basic Computer
D
I
T3
7
J
K
Q IENp
B7
B6
T2
R
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 54
CONTROL OF COMMON BUS
For AR D4T4: PC ARD5T5: PC AR
x1 = D4T4 + D5T5
Design of Basic Computer
x1x2x3x4x5x6x7
Encoder
S 2
S 1
S 0
Multiplexer
bus select
inputs
x1 x2 x3 x4 x5 x6 x7 S2 S1 S0selectedregister
0 0 0 0 0 0 0 0 0 0 none1 0 0 0 0 0 0 0 0 1 AR0 1 0 0 0 0 0 0 1 0 PC0 0 1 0 0 0 0 0 1 1 DR0 0 0 1 0 0 0 1 0 0 AC0 0 0 0 1 0 0 1 0 1 IR0 0 0 0 0 1 0 1 1 0 TR0 0 0 0 0 0 1 1 1 1 Memory
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 55
DESIGN OF ACCUMULATOR LOGIC
Circuits associated with AC
All the statements that change the content of AC
16
16
8
Adder and
logic circuit
16ACFrom DR
From INPR
Control
gates
LD INR CLR
16
To bus
Clock
D0T5: AC AC DR AND with DRD1T5: AC AC + DR Add with DRD2T5: AC DR Transfer from DRpB11: AC(0-7) INPR Transfer from INPRrB9: AC AC ComplementrB7 : AC shr AC, AC(15) E Shift rightrB6 : AC shl AC, AC(0) E Shift leftrB11 : AC 0 ClearrB5 : AC AC + 1 Increment
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 56
CONTROL OF AC REGISTER
Gate structures for controlling the LD, INR, and CLR of AC
AC
LDINR
CLR
Clock
To bus16From Adder and Logic
16
AND
ADD
DR
INPR
COM
SHR
SHL
INC
CLR
D0
D1
D2
B11
B9
B7
B6
B5
B11
r
p
T 5
T 5
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 57
ALU (ADDER AND LOGIC CIRCUIT)
One stage of Adder and Logic circuit
AND
ADD
DR
INPR
COM
SHR
SHL
J
K
QAC(i)
LD
FA
C
C
FromINPRbit(i)
DR(i) AC(i)
AC(i+1)
AC(i-1)
i
i
i+1
I
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 58
CONCLUSIONS
•Designing of the instructions format •Types of Computer cycles•Design of Control Logic
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 59
SUMMARY
• Computer’s structure indicates its internal connections Functional structure identifies functional block and relationship
between these blocks Physical structure identifies the physical modules and
interconnection between them.
• Computer function indicates the behavior. At overall level its function is program execution.
• Relation between computer organization and architecture.• Design of ALU• Design of bus, its interconnection and control logic
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63., by Deepali KamthaniaU1. 60
CONTROL UNIT DESIGN
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 61
• Microprogammed Control Unit• Control Unit Design• Introduction to Pipelining
LEARNING OBJECTIVES
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MICROPROGRAMMED CONTROL
• Control Memory
• Sequencing Microinstructions
• Microprogram Example
• Design of Control Unit
• Microinstruction Format
• Nanostorage and Nanoprogram
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 63
COMPARISON OF CONTROL UNIT IMPLEMENTATIONS
Control Unit ImplementationCombinational Logic Circuits (Hard-wired)
Microprogram
I R Status F/Fs
Control Data
CombinationalLogic Circuits
ControlPoints
CPU
Memory
Timing State
Ins. Cycle State
Control Unit's State
Status F/Fs
Control Data
Next AddressGenerationLogic
CSAR
ControlStorage
(-program memory)
Memory
I R
CSDR
CPs
CPUD
}
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 64
TERMINOLOGY
Microprogram
- Program stored in memory that generates all the control signals required to execute the instruction set correctly - Consists of microinstructions
Microinstruction
- Contains a control word and a sequencing word Control Word - All the control information required for one
clock cycleSequencing Word - Information needed to decide the
next microinstruction address - Vocabulary to write a microprogram
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 65
Cont….
Control Memory(Control Storage: CS)
- Storage in the microprogrammed control unit to store the microprogram
Writeable Control Memory(Writeable Control Storage:WCS)
- CS whose contents can be modified -> Allows the microprogram can be changed -> Instruction set can be changed or modified
Dynamic Microprogramming
- Computer system whose control unit is implemented with a microprogram in WCS
- Microprogram can be changed by a systems programmer or a user
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 66
Cont…
Sequencer (Microprogram Sequencer) A Microprogram Control Unit that determines
the Microinstruction Address to be executed in the next clock cycle
- In-line Sequencing - Branch - Conditional Branch - Subroutine - Loop - Instruction OP-code mapping
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 67
MICROINSTRUCTION SEQUENCING
Instruction code
Mappinglogic
Multiplexers
Control memory (ROM)
Subroutineregister(SBR)
Branchlogic
Statusbits
Microoperations
Control address register(CAR)
Incrementer
MUXselect
select a statusbit
Branch address
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 68
MICROINSTRUCTION SEQUENCING
Sequencing Capabilities Required in a Control Storage
- Incrementing of the control address register- Unconditional and conditional branches- A mapping process from the bits of the machine instruction to an address for control memory- A facility for subroutine call and return
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CONDITIONAL BRANCH
Unconditional Branch Fixing the value of one status bit at the input of the multiplexer to 1
Sequencing
Conditional Branch
If Condition is true, then Branch (address from the next address field of the current microinstruction) else Fall Through Conditions to Test: O(overflow), N(negative), Z(zero), C(carry), etc.
Control address register
Control memoryMUX
Load address
Increment
Status(condition)
bits
Micro-operationsCondition select
Next address
...
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 70
MAPPING OF INSTRUCTIONSSequencing
ADD RoutineAND RoutineLDA RoutineSTA RoutineBUN Routine
ControlStorage
00000001001000110100
OP-codes of Instructions ADD AND LDA STA BUN
00000001001000110100
.
.
.
Direct Mapping
Address
10 0000 010
10 0001 010
10 0010 010
10 0011 010
10 0100 010
MappingBits 10 xxxx 010
ADD Routine
Address
AND Routine
LDA Routine
STA Routine
BUN Routine
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 71
MAPPING OF INSTRUCTIONS TO MICROROUTINES
Mapping function implemented by ROM or PLA
OP-code
Mapping memory(ROM or PLA)
Control address register
Control Memory
Mapping from the OP-code of an instruction to the address of the Microinstruction which is the starting microinstruction of its execution microprogram
1 0 1 1 Address
OP-code
Mapping bits
Microinstruction address
0 x x x x 0 0
0 1 0 1 1 0 0
MachineInstruction
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 72
MICROPROGRAM EXAMPLEMicroprogram
Computer Configuration
MUX
AR10 0
PC10 0
Address Memory2048 x 16
MUX
DR15 0
Arithmeticlogic andshift unit
AC15 0
SBR6 0
CAR6 0
Control memory128 x 20
Control unit
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 73
MACHINE INSTRUCTION FORMAT
Microinstruction Format
EA is the effective addressSymbol OP-code Description
ADD 0000 AC AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC EA)
STORE 0010 M[EA] AC
EXCHANGE 0011 AC M[EA], M[EA] AC
Machine instruction format
I Opcode15 14 11 10
Address
0
Sample machine instructions
F1 F2 F3 CD BR AD
3 3 3 2 2 7
F1, F2, F3: Microoperation fieldsCD: Condition for branching BR: Branch fieldAD: Address field
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 74
MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3
F1 Microoperation Symbol
000 None NOP
001 AC AC + DR ADD
010 AC 0 CLRAC
011 AC AC + 1 INCAC
100 AC DR DRTAC
101 AR DR(0-10) DRTAR
110 AR PC PCTAR
111 M[AR] DR WRITE
F2 Microoperation Symbol
000 None NOP
001 AC AC - DR SUB
010 AC AC DR OR
011 AC AC DR AND
100 DR M[AR] READ
101 DR AC ACTDR
110 DR DR + 1 INCDR
111 DR(0-10) PC PCTDR
F3 Microoperation Symbol
000 None NOP
001 AC AC DR XOR
010 AC AC’ COM
011 AC shl AC SHL
100 AC shr AC SHR
101 PC PC + 1 INCPC
110 PC AR ARTPC
111 Reserved
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 75
MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR
CD Condition Symbol Comments00 Always = 1 U Unconditional branch01 DR(15) I Indirect address bit10 AC(15) S Sign bit of AC11 AC = 0 Z Zero value in AC
BR Symbol Function
00 JMP CAR AD if condition = 1
CAR CAR + 1 if condition = 0
01 CALL CAR AD, SBR CAR + 1 if condition = 1
CAR CAR + 1 if condition = 0
10 RET CAR SBR (Return from subroutine)
11 MAP CAR(2-5) DR(11-14), CAR(0,1,6) 0
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 76
SYMBOLIC MICROINSTRUCTIONS
• Symbols are used in microinstructions as in assembly language• A symbolic microprogram can be translated into its binary equivalent
by a microprogram assembler.
Sample Format five fields: label; micro-ops; CD; BR; AD
Label: may be empty or may specify a symbolic address terminated with a colon Micro-ops: consists of one, two, or three symbols separated by commas
CD: one of {U, I, S, Z}, where U: Unconditional Branch I: Indirect address bit S: Sign of AC Z: Zero value in AC
BR: one of {JMP, CALL, RET, MAP} AD: one of {Symbolic address, NEXT, empty}
Microprogram
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 77
SYMBOLIC MICROPROGRAM - FETCH ROUTINE -
AR PCDR M[AR], PC PC + 1AR DR(0-10), CAR(2-5) DR(11-14), CAR(0,1,6) 0
Symbolic microprogram for the fetch cycle:
ORG 64PCTAR U JMP NEXT READ, INCPC U JMP NEXT DRTAR U MAP
FETCH:
Binary equivalents translated by an assembler
1000000 110 000 000 00 00 10000011000001 000 100 101 00 00 10000101000010 101 000 000 00 11 0000000
Binaryaddress F1 F2 F3 CD BR AD
During FETCH, Read an instruction from memoryand decode the instruction and update PC
Sequence of microoperations in the fetch cycle:
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 78
SYMBOLIC MICROPROGRAM• Control Storage: 128 20-bit words• The first 64 words: Routines for the 16 machine instructions• The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)• Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines are 0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60
ORG 0NOPREADADD
ORG 4NOPNOPNOPARTPC
ORG 8NOPACTDRWRITE
ORG 12NOPREADACTDR, DRTACWRITE
ORG 64PCTARREAD, INCPCDRTARREADDRTAR
IUU
SU IU
IUU
IUUU
UUUUU
CALLJMPJMP
JMPJMPCALLJMP
CALLJMPJMP
CALLJMPJMPJMP
JMPJMPMAPJMPRET
INDRCTNEXTFETCH
OVERFETCHINDRCTFETCH
INDRCTNEXTFETCH
INDRCTNEXTNEXTFETCH
NEXTNEXT
NEXT
ADD:
BRANCH:
OVER:
STORE:
EXCHANGE:
FETCH:
INDRCT:
Label Microops CD BR AD
Partial Symbolic Microprogram
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 79
This microprogram can be implemented using ROM
Microprogram
Address Binary MicroinstructionMicro Routine Decimal Binary F1 F2 F3 CD BR AD
ADD 0 0000000 000 000 000 01 01 1000011 1 0000001 000 100 000 00 00 0000010
2 0000010 001 000 000 00 00 1000000
3 0000011 000 000 000 00 00 1000000
BRANCH 4 0000100 000 000 000 10 00 0000110 5 0000101 000 000 000 00 00 1000000 6 0000110 000 000 000 01 01 1000011 7 0000111 000 000 110 00 00 1000000
STORE 8 0001000 000 000 000 01 01 1000011 9 0001001 000 101 000 00 00 0001010 10 0001010 111 000 000 00 00 1000000 11 0001011 000 000 000 00 00 1000000
EXCHANGE 12 0001100 000 000 000 01 01 1000011 13 0001101 001 000 000 00 00 0001110 14 0001110 100 101 000 00 00 0001111 15 0001111 111 000 000 00 00 1000000
FETCH 64 1000000 110 000 000 00 00 1000001 65 1000001 000 100 101 00 00
1000010 66 1000010 101 000 000 00 11 0000000
INDRCT 67 1000011 000 100 000 00 00 1000100 68 1000100 101 000 000 00 10 0000000
BINARY MICROPROGRAM
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 80
DESIGN OF CONTROL UNIT - DECODING ALU CONTROL INFORMATION -
microoperation fields
3 x 8 decoder
7 6 5 4 3 2 1 0
F1
3 x 8 decoder
7 6 5 4 3 2 1 0
F2
3 x 8 decoder
7 6 5 4 3 2 1 0
F3
Arithmeticlogic andshift unit
ANDADD
DRTAC
ACLoad
FromPC
FromDR(0-10)
Select 0 1Multiplexers
ARLoad Clock
AC
DR
DR
TA
R
PC
TA
R
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 81
MICROPROGRAM SEQUENCER - NEXT MICROINSTRUCTION ADDRESS
LOGIC -
Subroutine CALL
MUX-1 selects an address from one of four sources and routes it into a CAR
- In-Line Sequencing CAR + 1 - Branch, Subroutine Call CS(AD) - Return from Subroutine Output of SBR - New Machine instruction MAP
3 2 1 0SS
10
MUX1
External(MAP)
SBRL
Incrementer
CARClock
Address source selection
In-LineRETURN form Subroutine
Branch, CALL Address
Control Storage
S1S0 Address Source 00 CAR + 1, In-Line 01 SBR RETURN 10 CS(AD), Branch or CALL 11 MAP
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 82
MICROPROGRAM SEQUENCER- CONDITION AND BRANCH
CONTROL -
InputlogicI0
I1
TMUX2
Select
1I
SZ
Test
CD Field of CS
From CPU BR field
of CS
L(load SBR with PC) for subroutine Call
S0
S1
for next addressselection
I0I1T Meaning Source of Address S1S0 L
000 In-Line CAR+1 00 0 001 JMP CS(AD) 10 0 010 In-Line CAR+1 00 0 011 CALL CS(AD) and SBR <- CAR+1 10 1 10x RET SBR 01 0 11x MAP DR(11-14) 11 0
L
S0 = I0
S1 = I0I1 + I0’TL = I0’I1T
Input Logic
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 83
MICROPROGRAM SEQUENCER
3 2 1 0S1 MUX1
External(MAP)
SBRLoad
Incrementer
CAR
Inputlogic
I0
T
MUX2
Select
1ISZ
Test
Clock
Control memory
Microops CD BR AD
L
I1
S0
. . .. . .
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 84
MICROINSTRUCTION FORMAT
Information in a Microinstruction - Control Information - Sequencing Information - Constant Information which is useful when feeding into the system
These information needs to be organized in some way for - Efficient use of the microinstruction bits - Fast decoding
Field Encoding
- Encoding the microinstruction bits - Encoding slows down the execution speed due to the decoding delay - Encoding also reduces the flexibility due to the decoding hardware
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 85
HORIZONTAL AND VERTICAL MICROINSTRUCTION FORMAT
Horizontal Microinstructions Each bit directly controls each micro-operation or each control point Horizontal implies a long microinstruction word Advantages: Can control a variety of components operating in parallel. --> Advantage of efficient hardware utilization Disadvantages: Control word bits are not fully utilized --> CS becomes large --> CostlyVertical Microinstructions A microinstruction format that is not horizontal Vertical implies a short microinstruction word Encoded Microinstruction fields --> Needs decoding circuits for one or two levels of decoding
One-level decoding
Field A2 bits
2 x 4Decoder
3 x 8Decoder
Field B3 bits
1 of 4 1 of 8
Two-level decoding
Field A2 bits
2 x 4Decoder
6 x 64Decoder
Field B6 bits
Decoder and selection logic
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 86
NANOSTORAGE AND NANOINSTRUCTION
The decoder circuits in a vertical microprogram storage organization can be replaced by a ROM
=> Two levels of control storage First level - Control Storage Second level - Nano Storage
Two-level microprogram
First level -Vertical format Microprogram Second level -Horizontal format Nanoprogram - Interprets the microinstruction fields, thus converts a vertical
microinstruction format into a horizontal nanoinstruction format.
Usually, the microprogram consists of a large number of short microinstructions, while the nanoprogram contains fewer words with longer nanoinstructions.
Control Storage Hierarchy
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 87
TWO-LEVEL MICROPROGRAMMING EXAMPLE
* Microprogram: 2048 microinstructions of 200 bits each* With 1-Level Control Storage: 2048 x 200 = 409,600 bits* Assumption: 256 distinct microinstructions among 2048* With 2-Level Control Storage: Nano Storage: 256 x 200 bits to store 256 distinct nanoinstructions Control storage: 2048 x 8 bits To address 256 nano storage locations 8 bits are needed* Total 1-Level control storage: 409,600 bits Total 2-Level control storage: 67,584 bits (256 x 200 + 2048 x 8)
Control Storage Hierarchy
Control address register
11 bits
Control memory2048 x 8
Microinstruction (8 bits)Nanomemory address
Nanomemory256 x 200
Nanoinstructions (200 bits)
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 88
CONCLUSIONS
• Micro programmed control organization• Address Sequencing• Mapping of instruction • Design of micro instructions• Symbolic/Binary Micro program• Design of control unit
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 89
CENTRAL PROCESSING UNIT
• Introduction
• General Register Organization
• Stack Organization
• Instruction Formats
• Addressing Modes
• Data Transfer and Manipulation
• Program Control
• Reduced Instruction Set Computer
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 90
MAJOR COMPONENTS OF CPUIntroduction
• Storage Components Registers Flags
• Execution (Processing) Components Arithmetic Logic Unit(ALU) Arithmetic calculations, Logical computations, Shifts/Rotates
• Transfer Components Bus
• Control Components Control Unit Register
File ALU
Control Unit
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 91
REGISTERS
• In Basic Computer, there is only one general purpose register, the Accumulator (AC)
• In modern CPUs, there are many general purpose registers• It is advantageous to have many registers
Transfer between registers within the processor are relatively fast Going “off the processor” to access memory is much slower
• How many registers will be the best ?
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 92
GENERAL REGISTER ORGANIZATION
MUXSELA{ MUX } SELB
ALUOPR
R1R2R3R4R5R6R7
Input
3 x 8decoder
SELD
Load(7 lines)
Output
A bus B bus
Clock
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 93
OPERATION OF CONTROL UNITThe control unit Directs the information flow through ALU by - Selecting various Components in the system - Selecting the Function of ALU
Example: R1 R2 + R3[1] MUX A selector (SELA): BUS A R2[2] MUX B selector (SELB): BUS B R3[3] ALU operation selector (OPR): ALU to ADD[4] Decoder destination selector (SELD): R1 Out Bus
Control Word
Encoding of register selection fields BinaryCode SELA
SELB SELD000 Input
Input None001 R1
R1 R1010 R2
R2 R2011 R3
R3 R3100 R4
R4 R4101 R5
R5 R5110 R6
R6 R6111 R7
R7 R7
SELA SELB SELD OPR
3 3 3 5
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 94
ALU CONTROL
Encoding of ALU operations
OPRSelect Operation Symbol
00000 TransferA TSFA00001 Increment A INCA00010 ADD A + B ADD00101 Subtract A - B SUB00110 Decrement A DECA01000 AND A and B AND01010 OR A and B OR01100 XOR A and B XOR01110 Complement A COMA10000 Shift right A SHRA11000 Shift left A SHLA
Control
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 95
ALU CONTROL
Examples of ALU Microoperations
Symbolic Designation
Microoperation SELA SELB SELD OPR Control Word
Control
R1 R2 R3 R2 R3 R1 SUB 010 011 001 00101
R4 R4 R5 R4 R5 R4 OR 100 101 100 01010
R6 R6 + 1 R6 - R6 INCA 110 000 110 00001
R7 R1 R1 - R7 TSFA 001 000 111 00000
Output R2 R2 - None TSFA 010 000 000 00000
Output Input Input - None TSFA 000 000 000 00000
R4 shl R4 R4 - R4 SHLA 100 000 100 11000
R5 0 R5 R5 R5 XOR 101 101 101 01100
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REGISTER STACK ORGANIZATION
Register Stack
Push, Pop operations
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */
PUSH POP
Stack Organization
SP SP + 1 DR M[SP]
M[SP] DR SP SP 1If (SP = 0) then (FULL 1) If (SP = 0) then (EMPTY 1)
EMPTY 0 FULL 0
Stack - Very useful feature for nested subroutines, nested interrupt services - Also efficient for arithmetic expression evaluation - Storage which can be accessed in LIFO - Pointer: SP - Only PUSH and POP operations are applicable
ABC
01234
63
Address
FULL EMPTY
SP
DR
Flags
Stack pointer
stack
6 bits
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MEMORY STACK ORGANIZATION
- A portion of memory is used as a stack with a processor register as a stack pointer
- PUSH: SP SP - 1 M[SP] DR
- POP: DR M[SP] SP SP + 1
Memory with Program, Data, and Stack Segments
40014000399939983997
3000
Data(operands)
Program(instructions)
1000
PC
AR
SPstack
Stack growsIn this direction
- Most computers do not provide hardware to check stack overflow (full stack) or underflow (empty stack) must be done in software
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REVERSE POLISH NOTATION
A + B Infix notation+ A B Prefix or Polish notationA B + Postfix or reverse Polish notation
- The reverse Polish notation is very suitable for stack manipulation
• Evaluation of Arithmetic Expressions Any arithmetic expression can be expressed in parenthesis-free Polish notation, including reverse Polish notation
(3 * 4) + (5 * 6) 3 4 * 5 6 * +
Stack Organization
• Arithmetic Expressions: A + B
3 3 12 12 12 12 424 5 5
630
3 4 * 5 6 * +
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PROCESSOR ORGANIZATION
• In general, most processors are organized in one of 3 ways
• Single register (Accumulator) organization Basic Computer is a good example Accumulator is the only general purpose register
• General register organization Used by most modern computer processors Any of the registers can be used as the source or destination for
computer operations
• Stack organization All operations are done using the hardware stack For example, an OR instruction will pop the two top
elements from the stack, do a logical OR on them, and push the result on the stack
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INSTRUCTION FORMAT
OP-code field - specifies the operation to be performedAddress field - designates memory address(es) or a processor register(s)Mode field - determines how the address field is to be interpreted (to
get effective address or the operand)
• The number of address fields in the instruction format depends on the internal organization of CPU
• The three most common CPU organizations:Single accumulator organization:
ADD X /* AC AC + M[X] */General register organization:
ADD R1, R2, R3 /* R1 R2 + R3 */ ADD R1, R2 /* R1 R1 + R2 */
MOV R1, R2 /* R1 R2 */ ADD R1, X /* R1 R1 + M[X] */Stack organization:
PUSH X /* TOS M[X] */ ADD
• Instruction Fields
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• Three-Address Instructions
Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1 M[A] + M[B] */ ADD R2, C, D /* R2 M[C] + M[D] */ MUL X, R1, R2 /* M[X] R1 * R2 */
- Results in short programs - Instruction becomes long (many bits)
• Two-Address Instructions
Program to evaluate X = (A + B) * (C + D) :
MOV R1, A /* R1 M[A] */ADD R1, B /* R1 R1 + M[A] */MOV R2, C /* R2 M[C] */ADD R2, D /* R2 R2 + M[D] */MUL R1, R2 /* R1 R1 * R2 */MOV X, R1 /* M[X] R1 */
Instruction Format
THREE AND TWO-ADDRESS INSTRUCTIONS
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ONE AND ZERO-ADDRESS INSTRUCTIONS
• One-Address Instructions- Use an implied AC register for all data manipulation- Program to evaluate X = (A + B) * (C + D) :
Instruction Format
LOAD A /* AC M[A] */ADD B /* AC AC + M[B] */STORE T /* M[T] AC */LOAD C /* AC M[C] */ADD D /* AC AC + M[D] */MUL T /* AC AC * M[T] */STORE X /* M[X] AC */
• Zero-Address Instructions- Can be found in a stack-organized computer- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS A */PUSH B /* TOS B */ADD /* TOS (A + B) */PUSH C /* TOS C */PUSH D /* TOS D */ADD /* TOS (C + D) */MUL /* TOS (C + D) * (A + B) */ POP X /* M[X] TOS */
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ADDRESSING MODES
• Addressing Modes
* Specifies a rule for interpreting or modifying the address field of the instruction (before the operand is actually referenced) * Variety of addressing modes
- to give programming flexibility to the user - to use the bits in the address field of the instruction
efficiently
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TYPES OF ADDRESSING MODES
• Implied ModeAddress of the operands are specified implicitly in the definition of the instruction
- No need to specify address in the instruction - EA = AC, or EA = Stack [SP]
- Examples from Basic ComputerCLA, CME, INP
• Immediate Mode Instead of specifying the address of the operand, operand itself is specified - No need to specify address in the instruction - However, operand itself needs to be specified - Sometimes, require more bits than the address - Fast to acquire an operand
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TYPES OF ADDRESSING MODES
Register Mode Address specified in the instruction is the register address - Designated operand need to be in a register - Shorter address than the memory address - Saving address field in the instruction - Faster to acquire an operand than the memory addressing - EA = IR(R) (IR(R): Register field of IR)
• Register Indirect ModeInstruction specifies a register which contains
the memory address of the operand - Saving instruction bits since register address is shorter than the memory address - Slower to acquire an operand than both the register addressing or memory addressing - EA = [IR(R)] ([x]: Content of x)
• Autoincrement or Autodecrement Mode - When the address in the register is used to access memory, the
value in the register is incremented or decremented by 1 automatically
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TYPES OF ADDRESSING MODES
• Direct Address Mode Instruction specifies the memory address which can be used directly to access the memory - Faster than the other memory addressing modes - Too many bits are needed to specify the address for a large physical memory space - EA = IR(addr) (IR(addr): address field of IR)
• Indirect Addressing ModeThe address field of an instruction specifies the address of a memory
location that contains the address of the operand - When the abbreviated address is used large physical memory can be
addressed with a relatively small number of bits - Slow to acquire an operand because of an additional memory access - EA = M[IR(address)]
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TYPES OF ADDRESSING MODES
• Relative Addressing Modes The Address fields of an instruction specifies the part of the address
(abbreviated address) which can be used along with a designated register to calculate the address of the operand
- Address field of the instruction is short - Large physical memory can be accessed with a small number of
address bits - EA = f(IR(address), R), R is sometimes implied 3 different Relative Addressing Modes depending on R; * PC Relative Addressing Mode (R = PC) - EA = PC + IR(address) * Indexed Addressing Mode (R = IX, where IX: Index Register) - EA = IX + IR(address) * Base Register Addressing Mode
(R = BAR, where BAR: Base Address Register) - EA = BAR + IR(address)
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ADDRESSING MODES - EXAMPLES -
AddressingMode
EffectiveAddress
Contentof AC
Direct address 500 /* AC (500) */ 800Immediate operand - /* AC 500 */ 500Indirect address 800 /* AC ((500)) */ 300Relative address 702 /* AC (PC+500) */ 325Indexed address 600 /* AC (RX+500) */ 900Register - /* AC R1 */ 400Register indirect 400 /* AC (R1) */ 700Autoincrement 400 /* AC (R1)+ */ 700Autodecrement 399 /* AC -(R) */ 450
Load to AC ModeAddress = 500
Next instruction
200201202
399400
450700
500 800
600 900
702 325
800 300
MemoryAddress
PC = 200
R1 = 400
XR = 100
AC
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DATA TRANSFER INSTRUCTIONS
Load LDStore STMove MOVExchange XCHInput INOutput OUTPush PUSHPop POP
Name Mnemonic• Typical Data Transfer Instructions
Direct address LD ADR AC M[ADR]Indirect address LD @ADR AC M[M[ADR]]Relative address LD $ADR AC M[PC + ADR]Immediate operand LD #NBR AC NBRIndex addressing LD ADR(X) AC M[ADR + XR]Register LD R1 AC R1Register indirect LD (R1) AC M[R1]Autoincrement LD (R1)+ AC M[R1], R1 R1 + 1Autodecrement LD -(R1) R1 R1 - 1, AC M[R1]
Mode AssemblyConvention
Register Transfer
• Data Transfer Instructions with Different Addressing Modes
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DATA MANIPULATION INSTRUCTIONS
• Three Basic Types: Arithmetic instructionsLogical and bit manipulation instructionsShift instructions
• Arithmetic InstructionsName Mnemonic
Clear CLRComplement COMAND ANDOR ORExclusive-OR XORClear carry CLRCSet carry SETCComplement carry COMCEnable interrupt EIDisable interrupt DI
Name MnemonicLogical shift right SHRLogical shift left SHLArithmetic shift right SHRAArithmetic shift left SHLARotate right RORRotate left ROLRotate right thru carry RORCRotate left thru carry ROLC
Name Mnemonic
• Logical and Bit Manipulation Instructions • Shift Instructions
Increment INCDecrement DECAdd ADDSubtract SUBMultiply MULDivide DIVAdd with Carry ADDCSubtract with Borrow SUBBNegate(2’s Complement) NEG
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FLAG, PROCESSOR STATUS WORD
• In Basic Computer, the processor had several (status) flags – 1 bit value that indicated various information about the processor’s state – E, FGI, FGO, I, IEN, R
• In some processors, flags like these are often combined into a register – the processor status register (PSR); sometimes called a processor status word (PSW)
• Common flags in PSW are C (Carry): Set to 1 if the carry out of the ALU is 1 S (Sign): The MSB bit of the ALU’s output Z (Zero): Set to 1 if the ALU’s output is all 0’s V (Overflow): Set to 1 if there is an overflow
Status Flag Circuit
c7
c8
A B8 8
8-bit ALU
V Z S CF7
F7 - F0
8
F
Check forzero output
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PROGRAM CONTROL INSTRUCTIONS
PC
+1In-Line Sequencing (Next instruction is fetched from the next adjacent location in the memory)
Address from other source; Current Instruction, Stack, etc; Branch, Conditional Branch, Subroutine, etc
• Program Control Instructions
Name MnemonicBranch BRJump JMPSkip SKPCall CALLReturn RTNCompare(by ) CMPTest(by AND) TST
•CMP and TST instructions do not retain their results of operations ( and AND, respectively).•They only set or clear certain Flags.
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CONDITIONAL BRANCH INSTRUCTIONS
BZ Branch if zero Z = 1BNZ Branch if not zero Z = 0BC Branch if carry C = 1BNC Branch if no carry C = 0BP Branch if plus S = 0BM Branch if minus S = 1BV Branch if overflow V = 1BNV Branch if no overflow V = 0
BHI Branch if higher A > BBHE Branch if higher or equal A BBLO Branch if lower A < BBLOE Branch if lower or equal A BBE Branch if equal A = BBNE Branch if not equal A B
BGT Branch if greater than A > BBGE Branch if greater or equal A BBLT Branch if less than A < BBLE Branch if less or equal A BBE Branch if equal A = BBNE Branch if not equal A B
Unsigned compare conditions (A - B)
Signed compare conditions (A - B)
Mnemonic Branch condition Tested condition
Program Control
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SUBROUTINE CALL AND RETURN
Call subroutineJump to subroutineBranch to subroutineBranch and save return address
• Fixed Location in the subroutine (Memory)• Fixed Location in memory• In a processor Register• In memory stack - most efficient way
Program Control
• Subroutine Call
• Two Most Important Operations are Implied;
* Branch to the beginning of the Subroutine - Same as the Branch or Conditional Branch
* Save the Return Address to get the address of the location in the Calling Program upon exit from the Subroutine
• Locations for storing Return Address CALL
SP SP - 1 M[SP] PC
PC EA
RTN PC M[SP]
SP SP + 1
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PROGRAM INTERRUPT Types of Interrupts
External interrupts External Interrupts initiated from the outside of CPU and Memory - I/O Device → Data transfer request or Data transfer complete - Timing Device → Timeout - Power Failure - Operator
Internal interrupts (traps) Internal Interrupts are caused by the currently running program - Register, Stack Overflow - Divide by zero - OP-code Violation - Protection Violation
Software Interrupts Both External and Internal Interrupts are initiated by the computer HW. Software Interrupts are initiated by the executing an instruction. - Supervisor Call → Switching from a user mode to the supervisor mode → Allows to execute a certain class of operations
which are not allowed in the user mode
Program Control`
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INTERRUPT PROCEDURE
• The interrupt is usually initiated by an internal or an external signal rather than from the execution of an instruction (except for the software interrupt)
• The address of the interrupt service program is determined by the hardware rather than from the address field of an instruction
• An interrupt procedure usually stores all the information necessary to define the state of CPU rather than storing only the PC.
• The state of the CPU is determined from;
• Content of the PC
• Content of all processor registers
• Content of status bits
• Many ways of saving the CPU state depending on the CPU architectures
Program Control
Interrupt Procedure and Subroutine Call
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RISC: HISTORICAL BACKGROUND• IBM System/360, 1964
• The real beginning of modern computer architecture• Distinction between Architecture and Implementation• Architecture: The abstract structure of a computer
seen by an assembly-language programmer
• Continuing growth in semiconductor memory and microprogramming A much richer and complicated instruction sets CISC(Complex Instruction Set Computer)
High-LevelLanguage
InstructionSet
Hardware
Compiler-program
Architecture
Implementation
Hardware
Hardware
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ARGUMENTS ADVANCED AT THAT TIME
• Richer instruction sets would simplify compilers• Richer instruction sets would alleviate the software
crisis move as much functions to the hardware as possible
• Richer instruction sets would improve architecture quality
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ARCHITECTURE DESIGN PRINCIPLES
- IN 70’s -RISC
• Large microprograms would add little or nothing to the cost of the machine Rapid growth of memory technology Large General Purpose Instruction Set
• Microprogram is much faster than the machine instructions Microprogram memory is much faster than main memory Moving the software functions into microprogram for the high performance machines
• Execution speed is proportional to the program size Architectural techniques that led to small program High performance instruction set
• Number of registers in CPU has limitations Very costly Difficult to utilize them efficiently
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COMPARISONS OF EXECUTION MODELS
A B + C Data: 32-bit
RISC
Load rB BLoad rC C
Add rAStore rA A
rB rC
Load BAdd C
Store A
Add B C A
• Register-to-register
• Memory-to-register
• Memory-to-memory
I = 104b; D = 96b; M = 200b
I = 72b; D = 96b; M = 168b
I = 56b; D = 96b; M = 152b
8 4 16
8 16
8 16 16 16
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RISCFOUR MODERN ARCHITECTURES IN 70’s
Year# of instrs.Control mem. sizeInstr. size (bits)TechnologyExecution model
Cache size
1973208420 Kb
16-48ECL MSIreg-memmem-memreg-reg
64 Kb
1978303480 Kb
16-456TTL MSIreg-memmem-memreg-reg
64 Kb
1978270136 Kb
8-24ECL MSI
stack
64 Kb
1982222420 Kb
6-321NMOS VLSIstackmem-mem
64 Kb
IBM 370/168 VAX-11/780 Dorado iAPX-432DEC Xerox Intel
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COMPLEX INSTRUCTION SET COMPUTER
• These computers with many instructions and addressing modes came to be known as Complex Instruction Set Computers (CISC)
• One goal for CISC machines was to have a machine language instruction to match each high-level language statement type
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VARIABLE LENGTH INSTRUCTIONS
• The large number of instructions and addressing modes led CISC machines to have variable length instruction formats
• The large number of instructions means a greater number of bits to specify them
• In order to manage this large number of opcodes efficiently, they were encoded with different lengths: More frequently used instructions were encoded using short opcodes. Less frequently used ones were assigned longer opcodes.
• Also, multiple operand instructions could specify different addressing modes for each operand For example,
Operand 1 could be a directly addressed register, Operand 2 could be an indirectly addressed memory location, Operand 3 (the destination) could be an indirectly addressed register.
• All of this led to the need to have different length instructions in different situations, depending on the opcode and operands used
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• For example, an instruction that only specifies register operands may only be two bytes in length One byte to specify the instruction and addressing mode One byte to specify the source and destination registers.
• An instruction that specifies memory addresses for operands may need five bytes One byte to specify the instruction and addressing mode Two bytes to specify each memory address
Maybe more if there’s a large amount of memory.
• Variable length instructions greatly complicate the fetch and decode problem for a processor
• The circuitry to recognize the various instructions and to properly fetch the required number of bytes for operands is very complex
Cont…
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COMPLEX INSTRUCTION SET COMPUTER
• Another characteristic of CISC computers is that they have instructions that act directly on memory addresses For example,
ADD L1, L2, L3that takes the contents of M[L1] adds it to the contents of M[L2] and stores the result in location M[L3]
• An instruction like this takes three memory access cycles to execute• That makes for a potentially very long instruction execution cycle
• The problems with CISC computers are
The complexity of the design may slow down the processor, The complexity of the design may result in costly errors in the processor design and
implementation, Many of the instructions and addressing modes are used rarely, if ever
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SUMMARY: CRITICISMS ON CISC
High Performance General Purpose Instructions
- Complex Instruction → Format, Length, Addressing Modes → Complicated instruction cycle control due to the complex
decoding HW and decoding process
- Multiple memory cycle instructions → Operations on memory data → Multiple memory accesses/instruction
- Microprogrammed control is necessity → Microprogram control storage takes substantial portion of CPU chip area → Semantic Gap is large between machine instruction and microinstruction
- General purpose instruction set includes all the features required by individually different applications
→ When any one application is running, all the features required by the other applications are extra burden to the application
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• In the late ‘70s and early ‘80s there was a reaction to the shortcomings of the CISC style of processors
• Reduced Instruction Set Computers (RISC) were proposed as an alternative
• The underlying idea behind RISC processors is to simplify the instruction set and reduce instruction execution time
• RISC processors often feature:
Few instructions Few addressing modes Only load and store instructions access memory All other operations are done using on-processor registers Fixed length instructions Single cycle execution of instructions The control unit is hardwired, not microprogrammed.
REDUCED INSTRUCTION SET COMPUTERS
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• Since all but the load and store instructions use only registers for operands, only a few addressing modes are needed
• By having all instructions the same length, reading them in is easy and fast
• The fetch and decode stages are simple, looking much more like Mano’s Basic Computer than a CISC machine
• The instruction and address formats are designed to be easy to decode
• Unlike the variable length CISC instructions, the opcode and register fields of RISC instructions can be decoded simultaneously
• The control logic of a RISC processor is designed to be simple and fast
• The control logic is simple because of the small number of instructions and the simple addressing modes
• The control logic is hardwired, rather than microprogrammed, because hardwired control is faster
Cont…
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ARCHITECTURAL METRICA B + CB A + CD D - B
RISC
• Register-to-register (Reuse of operands)
• Register-to-register (Compiler allocates operands in registers)
• Memory-to-memory
I = 228b D = 192b M = 420b
I = 60b D = 0b M = 60b
I = 168b D = 288b M = 456b
Load rB BLoad rC CAdd rAStore rA A
rB rC
8 4 16
Add rB rA rCStore rB BLoad rD DSub rD rD rBStore rD D
Add rA rB rCAdd rB rA rCSub rD rD rB
8 4 4 4
Add B C A8 16 16 16
Add A C BSub B D D
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CHARACTERISTICS OF INITIAL RISC MACHINES
IBM 801 RISC I MIPSYear 1980 1982 1983Number of instructions 120 39 55Control memory size 0 0 0Instruction size (bits) 32 32 32Technology ECL MSI NMOS VLSI NMOS VLSIExecution model reg-reg reg-reg reg-reg
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ADD rA rB register operand
rC
OP DEST SOUR1 SOUR2
ADD rA rA immediate operand
1
SUB rD rD register operand
rB
32b memory port
ADD (3 operands)
register operand
B register operand
C register operand
A
INC (1 operands)
register operand
A SUB (2 operands)
register operand
B
register operand
D
3 operands in memory
B C ...
... C AADD
ADD
1 operand in memory
AINC
INC
2 operands in memory D ...B
... D SUB
RISC 1
VAX
432
RISC
COMPARISON OF INSTRUCTION SEQUENCE
A B + CA A + 1 D D - B
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REGISTERS
• By simplifying the instructions and addressing modes, there is space available on the chip or board of a RISC CPU for more circuits than with a CISC processor
• This extra capacity is used to Pipeline instruction execution to speed up instruction
execution Add a large number of registers to the CPU
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PIPELINING
• A very important feature of many RISC processors is the ability to execute an instruction each clock cycle
• This may seem nonsensical, since it takes at least once clock cycle each to fetch, decode and execute an instruction.
• It is however possible, because of a technique known as pipelining We’ll study this in detail later
• Pipelining is the use of the processor to work on different phases of multiple instructions in parallel
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• For instance, at one time, a pipelined processor may be Executing instruction it Decoding instruction it+1
Fetching instruction it+2 from memory
• So, if we’re running three instructions at once, and it takes an average instruction three cycles to run, the CPU is executing an average of an instruction a clock cycle
• As we’ll see when we cover it in depth, there are complications For example, what happens to the pipeline when the processor branches
• However, pipelined execution is an integral part of all modern processors, and plays an important role
Cont…
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REGISTERS
• By having a large number of general purpose registers, a processor can minimize the number of times it needs to access memory to load or store a value
• This results in a significant speed up, since memory accesses are much slower than register accesses
• Register accesses are fast, since they just use the bus on the CPU itself, and any transfer can be done in one clock cycle
• To go off-processor to memory requires using the much slower memory (or system) bus
• It may take many clock cycles to read or write to memory across the memory bus The memory bus hardware is usually slower than the processor There may even be competition for access to the memory bus by other devices in
the computer (e.g. disk drives)• So, for this reason alone, a RISC processor may have an advantage
over a comparable CISC processor, since it only needs to access memory for its instructions, and occasionally to load or store a memory value
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UTILIZING RISC REGISTERS -REGISTER WINDOW-
<Weighted Relative Dynamic Frequency of HLL Operations>
The procedure (function) call/return is the most time-consuming operations in typical HLL programs
Pascal C Pascal C Pascal C
DynamicOccurrence
Machine-InstructionWeighted
MemoryReferenceWeighted
ASSIGN 45 38 13 13 14 15LOOP 5 3 42 32 33 26CALL 15 12 31 33 44 45IF 29 43 11 21 7 13GOTO 3Other 6 1 3 1 2 1
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RISC
CALL-RETURN BEHAVIOR
Call-return behavior as a function of nesting depth and time
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• Observations•Weighted Dynamic Frequency of HLL Operations •Procedure call/return is the most time consuming operations
•Locality of Procedure Nesting •The depth of procedure activation fluctuates within a
relatively narrow range•A typical procedure employs only a few passed
parameters and local variables• Solution•Use multiple small sets of registers (windows), each assigned to
a different procedure•A procedure call automatically switches the CPU to use a
different window of registers, rather than saving registers in memory
•Windows for adjacent procedures are overlapped to allow parameter passing
RISC
REGISTER WINDOW APPROACH
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OVERLAPPED REGISTER WINDOWS
RISC
R15
R10
R15
R10
R25
R16
Common to D and A
Local to D
Common to C and D
Local to C
Common to B and C
Local to B
Common to A and B
Local to A
Common to A and D
Proc D
Proc C
Proc B
Proc AR9
R0
Common to allprocedures
Globalregisters
R31
R26
R9
R0
R15
R10
R25
R16
R31
R26
R41
R32
R47
R42
R57
R48
R63
R58
R73
R64
R25
R16
R31
R26
R15
R10
R25
R16
R31
R26
R15
R10
R25
R16
R31
R26
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OVERLAPPED REGISTER WINDOWS
• There are three classes of registers: Global Registers
Available to all functions Window local registers
Variables local to the function Window shared registers
Permit data to be shared without actually needing to copy it
• Only one register window is active at a time The active register window is indicated by a pointer
• When a function is called, a new register window is activated This is done by incrementing the pointer
• When a function calls a new function, the high numbered registers of the calling function window are shared with the called function as the low numbered registers in its register window
• This way the caller’s high and the called function’s low registers overlap and can be used to pass parameters and results
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• In addition to the overlapped register windows, the processor has some number of registers, G, that are global registers This is, all functions can access the global registers.
• The advantage of overlapped register windows is that the processor does not have to push registers on a stack to save values and to pass parameters when there is a function call Conversely, pop the stack on a function return
• This saves Accesses to memory to access the stack. The cost of copying the register contents at all
• And, since function calls and returns are so common, this results in a significant savings relative to a stack-based approach
Cont…
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BERKELEY RISC I
- 32-bit integrated circuit CPU- 32-bit address, 8-, 16-, 32-bit data- 32-bit instruction format- total 31 instructions- three addressing modes: register; immediate; PC relative addressing- 138 registers 10 global registers 8 windows of 32 registers each
Berkeley RISC I Instruction Formats
RISC
Opcode RsRd 0 Not used S231 24 23 19 18 14 13 12 5 4 0
8 5 5 1 8 5
Opcode RsRd 1 S231 24 23 19 18 14 13 12 0
8 5 5 1 13
Opcode COND Y31 24 23 19 18 0
8 5 19
Regsiter mode: (S2 specifies a register)
Register-immediate mode (S2 specifies an operand)
PC relative mode
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• Register 0 was hard-wired to a value of 0.• There are eight memory access instructions
Five load-from-memory instructions Three store-to-memory instructions.
• The load instructions:LDL load longLDSU load short unsignedLDSS load short signedLDBU load byte unsignedLDBS load byte signed
Where long is 32 bits, short is 16 bits and a byte is 8 bits
• The store instructions:STL store longSTS store shortSTB store byte
Cont…
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LDL Rd M[(Rs) + S2] load long
LDSU Rd M[(Rs) + S2] load short unsignedLDSS Rd M[(Rs) + S2] load short signed
LDBU Rd M[(Rs) + S2] load byte unsignedLDBS Rd M[(Rs) + S2] load byte signed
STL M[(Rs) + S2] Rd store longSTS M[(Rs) + S2] Rd store shortSTB M[(Rs) + S2] Rd store byte
• Here the difference between the lengths is A long is simply loaded, since it is the same size as the register (32 bits). A short or a byte can be loaded into a register
Unsigned - in which case the upper bits of the register are loaded with 0’s. Signed - in which case the upper bits of the register are loaded with the sign bit of
the short/byte loaded.
Cont…
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INSTRUCTION SET OF BERKELEY RISC I
Data manipulation instructionsADD Rs,S2,Rd Rd Rs + S2 Integer addADDC Rs,S2,Rd Rd Rs + S2 + carry Add with carrySUB Rs,S2,Rd Rd Rs - S2 Integer subtractSUBC Rs,S2,Rd Rd Rs - S2 - carry Subtract with carrySUBR Rs,S2,Rd Rd S2 - Rs Subtract reverseSUBCR Rs,S2,Rd Rd S2 - Rs - carry Subtract with carryAND Rs,S2,Rd Rd Rs S2 ANDOR Rs,S2,Rd Rd Rs S2 ORXOR Rs,S2,Rd Rd Rs S2 Exclusive-ORSLL Rs,S2,Rd Rd Rs shifted by S2 Shift-leftSRL Rs,S2,Rd Rd Rs shifted by S2 Shift-right logicalSRA Rs,S2,Rd Rd Rs shifted by S2Shift-right arithmetic
Opcode Operands Register Transfer Description
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• Data transfer instructions• LDL (Rs)S2,Rd Rd M[Rs + S2] Load long• LDSU (Rs)S2,Rd Rd M[Rs + S2] Load short unsigned
• LDSS (Rs)S2,Rd Rd M[Rs + S2] Load short signed
• LDBU (Rs)S2,Rd Rd M[Rs + S2] Load byte unsigned
• LDBS (Rs)S2,Rd Rd M[Rs + S2] Load byte signed• LDHI Rd, Y Rd Y Load immediate high
• STL Rd,(Rs)S2M[Rs + S2] Rd Store long• STS Rd,(Rs)S2M[Rs + S2] Rd Store short• STB Rd,(Rs)S2 M[Rs + S2] Rd Store byte• GETPSW Rd Rd PSW Load status word• PUTPSW Rd PSW Rd Set status word
RISC
Opcode Operands Register Transfer Description
Cont…
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Program control instructionsJMP COND,S2(Rs) PC Rs + S2 Conditional jumpJMPR COND,Y PC PC + Y Jump relativeCALL Rd,S2(Rs) Rd PC, PC Rs + S2 Call subroutine& CWP CWP - 1
Change windowCALLR Rd,YRd PC, PC PC + Y Call relative and
CWP CWP - 1 change windowRET Rd,S2 PC Rd + S2 Return and
CWP CWP + 1 change windowCALLINT Rd Rd PC,CWP CWP - 1 Call an
interrupt pr.
RETINT Rd,S2 PC Rd + S2Return from
CWP CWP + 1 interrupt pr.GTLPC Rd Rd PC Get last PC
INSTRUCTION SET OF BERKELEY RISC I
Opcode Operands Register Transfer Description
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CHARACTERISTICS OF RISC
• RISC Characteristics
• Advantages of RISC
- VLSI Realization- Computing Speed- Design Costs and Reliability- High Level Language Support
RISC
- Relatively few instructions- Relatively few addressing modes- Memory access limited to load and store instructions- All operations done within the registers of the CPU- Fixed-length, easily decoded instruction format- Single-cycle instruction format- Hardwired rather than microprogrammed control
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ADVANTAGES OF RISC
• Computing Speed- Simpler, smaller control unit faster- Simpler instruction set; addressing modes; instruction format
faster decoding- Register operation faster than memory operation- Register window enhances the overall speed of execution- Identical instruction length, One cycle instruction execution suitable for pipelining faster
RISC
• VLSI Realization
Control area is considerably reduced
Example:RISC I: 6%RISC II: 10%MC68020: 68%general CISCs: ~50%
RISC chips allow a large number of registers on the chip
- Enhancement of performance and HLL support - Higher regularization factor and lower VLSI design cost
The GaAs VLSI chip realization is possible
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ADVANTAGES OF RISC• Design Costs and Reliability
- Shorter time to design reduction in the overall design cost and reduces the problem that the end product will be obsolete by the time the design is completed
- Simpler, smaller control unit higher reliability
- Simple instruction format (of fixed length) ease of virtual memory management
• High Level Language Support- A single choice of instruction shorter, simpler compiler
- A large number of CPU registers more efficient code
- Register window Direct support of HLL
- Reduced burden on compiler writer
RISC
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CONCLUSIONS
• CPU Organizations• Addressing Modes• Address Instructions• Classification of computer instructions• RISC/CISC
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OBJECTIVE QUESTIONS
1. A CPU’s microinstruction format has five separate control fields. The number of micro operations in each fields are as follows F1=4, F2 = 4, F3 = 3, F4 = 12, F5 = 21
i. What is the total length of microinstrcution needed to accommodate the five control fields
ii. If pure horizontal microprogramming is followed without encoding, what will be the length of microinstruction?
2. Pick out the incorrect RTL statement and indicate the problems
1. PC:= MAR, PC:= PC+1 2. MR:=1, Pc:=PC+1
3. NOOP instruction requires nothing (no action) to be performed for the instruction. This is true for macro operation level but false for the microoperation level. The control unit must perform one microoperation which is necessary for any instruction. Identify the essential micro operation which is performed for NOOP instruction.
4. Is nano and micro programming same?
5. The address of stack is stored in _____________
6. In ___________________addressing mode the content of PC is added to address part of the instruction in order to obtain the effective address
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7. Control word specifies ________________
8. Memory unit that stores the control word is ___________
9. ________ is program which convert symbolic language into machine code.
10. ________ is also called nexr address generator.
11. The instructions which copy information from one location to another either in the processor’s internal register set or in the external main memory are called
a. Data transfer instructions. b. Program control instructions.
c. Input-output instructions. d. Logical instructions.
12. If the value V(x) of the target operand is contained in the address field itself, the addressing mode is
a. immediate. b. direct. c. indirect. d. implied.
13. A microprogram sequencer
a. generates the address of next micro instruction to be executed.
b. generates the control signals to execute a microinstruction.
c sequentially averages all microinstructions in the control memory.
d. enables the efficient handling of a micro program subroutine.
Cont…
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14. During what CPU cycle is an instruction moved from primarystorage to the control unit?a. fetchb. executionc. accessd. refresh
15. What type of processor does not directly implement instructions that combine data movement and manipulation?a. CISCb. RISCc. microprocessord. PSW
16. When the control unit fetches an instruction from memory, it storesit in the ____.a. instruction pointerb. program status wordc. op coded. instruction register
Cont…
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17. Which of the following is a storage location that holds inputs andoutputs for the ALU?a. Control unitb. ALUc. I/O deviced. Register
18. The ____ tests the bit values in the source location and places copiesof those values in the destination location.a. LOADb. MOVEc. STOREd. ADD
Cont…
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SHORT QUESTIONS
1. The instruction length and operand address field is 36 bits and 14 bits respectively. If two – operand instructions of 240 numbers are used, then how many one operand instructions are possible?
2. The stack based CPU don’t have registers for storing the operands. Can we conclude that the stack based CPU has less hardware circuit and cheaper than register based CPU?
3. The instruction format of a CPU is designed for the two types (a) op-code and three fields for register address; (b) op-code and one field for memory address. Identify different formats for instructions.
4. Difference between horizontal and vertical instruction format.
5. What is firmware? How it is different from software and hardware?
6. A register based CPU can be viewed as multiple accumulators based CPU. Justify this statement
7. A micro programmed CPU has 1K words in the control memory. Each instruction needs 8 microinstructions. Assuming that the op-code in the macro instruction is of 5 bits length, propose a mapping scheme to generate control memory address for the op-code.
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8. Name some functions of control unit.9. What is the difference between internal and software interrupts?10. A computer has 32 bit instructions and 12 bit addresses. If there are 250
two address instruction, how many one address instruction can be formulated?
11. What is the Fetch routine in Micro programmed control unit12. The instructions are classified on the basis of following factors
1. Op-code: ______________2. Data:_________________,__________________, etc3. Operand location: __________,______________4. Operand addressing: ______________________5. Instruction length:_______,_________,_____6. No. of address field____________,________,_______
Cont…
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 158
LONG QUESTIONS
1. Write an assembly language program to derive the expression X=(A+B)-(C+D) for an accumulator, register and stack based CPU
2. What is addressing mode? Discuss different types of addressing modes with its advantages and disadvantages.
3. A program has three jump instructions in three consecutive words (locations) in memory: 0111, 1000and 1001.The corresponding jump addresses are 1001, 0111, 0111 respectively. Suppose we load 0111.Initially in PC and start the CPU, how many times will the instruction in location be fetched and executed?
4. A 32-bit CPU has 16-bit instruction and 12-bit memory address. Its memory is organized as 4K of 32-bits each. Each memory word stores two instructions. The instruction format has 4-bits for op-code. The CPU’s instruction register can accommodate two instructions. Suggest a design strategy for the instruction cycle sequence.
5. What is the basic difference between a branch instruction, a call subroutine instruction, and a program interrupt? Explain various types of interrupts and give examples of each.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1. 159
6. A processor has following hardware configuration a. No. of registers=8b. ALU operations: arithmetic 8,logic 8c. Shifter : 4 operationsd. Bus: single bus
Design the microinstruction format for this CPU7. A digital computer has a common bus system for 12 registers of 9 bits each. The bus
is constructed with multiplexers.a. How many selection inputs are there in each multiplexer? b. What size of multiplexers are needed? c. How many multiplexers are there in the bus? d. Draw a diagram of the bus system using three-state buffers and a decoder instead of multiplexers?
8.The system uses a control memory of 1024 words of 32 bits each. The microinstruction has three fields for micro-operations. select a status bit and Brach address field. The micro-operation field has 16 bits.a. How many bits are there in the branch address field and select field?b. If there are 16 status bits in the system, how many bits of the branch logic are used to select a status bit?c. How many bits are left to select the input to the multiplexers?
Cont..
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Cont..9. Write micro operation for BSA and ISZ 10. A computer has following registers PC(12 bits), MAR(16), MBR(12),
I(1),OPR(3), E(1), AC(16) and six timing signal t0 to t5 and one flip-flop F for cycle control. Fetch cycle is performed when F=0 and execute cycle when F=1. List the micro-operations and control functions for the computer(i) When F=0(ii) For Executing XOR, SWAP (AC and memory Word) ADD (M M+AC)
11. A digital system has 16 registers, each with 32-bits.It is necessary to provide parallel data transfer from each register to every other register a. How many lines are needed for direct parallel transfer?b. If we need to link these register to a common bus c. How many Multiplexer will be required?d. How many input lines are required for each multiplexer
12. In a seven register bus organization of CPU the propagation delays are given, 30s for multiplexer, 60 ns to perform the add operation in the ALU and 20 ns in the destination decoder, and 10 ns to clock the data into destination register. What is the minimum cycle time that can be used for the clock
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RESEARCH PROBLEM
1. What are the differences between CISC and RISC architectures? Which types of applications are properly suited for each of these categories of architecture?
Compare and contrast CISC architecture and RISC architecture. Make sure to include the strengths and weaknesses of each as well as applications to which they would be most suited. You may also compare/contrast them with any architecture that may be considered as future replacements for either or both of these two.
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REFERENCES
1. Hayes P. John, Computer Architecture and Organisation, McGraw Hill Comp., 1988.
2. Mano M., Computer System Architecture, Prentice-Hall Inc. 1993.
3. Patterson, D., Hennessy, J., Computer Architecture - A
Quantitative Approach, second edition, Morgan Kaufmann
Publishers, Inc. 1996;
4. Stallings, William, Computer Organization and Architecture, 5th edition, Prentice Hall International, Inc., 2000.
5. Tanenbaum, A., Structured Computer Organization, 4th ed., Prentice- Hall Inc. 1999.
6. Hamacher, Vranesic, Zaky, Computer Organization, 4th ed., McGraw Hill Comp., 1996.