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SOLUTIONS FOR A PROGRAMMABLE WORLD 91 2015 All Programmable Abstraction: 慣れた言語でプログラマブル デバイスのプログラミングが容易に FPGA のビデオ ウォーターマーキング用 OpenCL アプリケーションを最適化 周波数ドメインの基本を把握 プロ仕様ビデオ用の JPEG 2000 ネットワークを実現 FPGA ベースの OpenCL データ センター サーバーの 制約を解消 japan.xilinx.com/xcell 低コストの FPGA ボードに インプリメントされる Oberon システム ページ 28

ザイリンクス Xcell Journal 日本語版 91 号

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Xcell Journal 91 号のカバーストーリーでは、ザイリンクスの All Programmable Abstraction 戦略と、新しい SDAccel™ および SDSoC™ 開発環境についてご紹介します。この SDAccel および SDSoC 開発環境は、システムパフォーマンスを加速するため、システムエンジニアとソフトウェアエンジニアの方がザイリンクスの FPGA および SoC のロジックをプログラムし、設計チームの生産性を向上させることを可能にします。

Text of ザイリンクス Xcell Journal 日本語版 91 号

  • S O L U T I O N S F O R A P R O G R A M M A B L E W O R L D

    9 1 2015

    All Programmable Abstraction:

    FPGA OpenCL

    JPEG 2000

    FPGA OpenCL

    japan.xilinx.com/xcell

    FPGA Oberon

    28

  • L E T T E R F R O M T H E P U B L I S H E R

    Xcell Journal 2015 91All Pro-grammable Abstraction 3 All Program-mable Abstraction FPGA All Programmable FPGA/SoC All Programmable Abstraction 2012 Vivado (HLS) MathWorks National Instruments SDx 3 (SDNet SDAccel SDSoC ) FPGA SoC FPGA 10 SDx All Programmable SDAccel 2 36 40 (Niklaus Wirth) Spartan-3 FPGA Pascal ( ) Project Oberon ( ) Digilent Spartan-3 Spartan-3 Oberon 52 Daniel Michek Vivado System Generator for DSP

    Mike Santarini

    Xcell journal

    Jacqueline Damian

    Scott Blair

    / Teie, Gelwicks & Associates

    [email protected]

    Xcell Journal 91

    2015 6 30

    Xilinx, Inc2100 Logic DriveSan Jose, CA 95124-3400

    141-0032 1-2-2 4F

    2015 Xilinx, Inc. All Right Reserved.

    XILINX Xcell Xilinx

    Xilinx, Inc.

    Xilinx, Inc.

    [email protected]

    Mike [email protected]+1-408-626-5981

  • ASIC

    () TEL (03) 5792-8210 [email protected]() TEL (045) 477-2001 [email protected] 2015 Xilinx, Inc. All rights reserved. ARMEUARM Limited

  • Cover Story 6

    28

    12

    16

    VIEWPOINTS

    Letter From the Publisher

    2

    Xcellence in Broadcast

    JPEG 2000 12

    Xcellence in Scientific Applications White Rabbit : 16

    Xcellence in Wireless Communications

    RF-DAC 24

    Xperiment

    FPGA Oberon 28

    XCELLENCE BY DESIGN APPLICATION FEATURES

    All Programmable Abstraction:

  • 46

    40

    56

    Excellence in Magazine & Journal Writing2010, 201

    Excellence in Magazine & Journal Design2010, 2011, 2012

    9 1

    Xplanation: FPGA 101

    46

    Xplanation: FPGA 101

    SoC System Generator for DSP 52

    Xplanation: FPGA 101

    ADC 56

    THE XILINX XPERIENCE FEATURES

    Xcellence in Data Centers

    FPGA OpenCL 36

    Xcellence in Data Centers

    FPGA OpenCL 40

    XCELLENCE BY DESIGN APPLICATION FEATURES

  • C O V E R S T O R Y

    All Programmable Abstractions: Programming Your Way

    All Programmable Abstraction: SDx Vivado IPIHLS

    6 Xcell Journal 91

  • C O V E R S T O R Y

    / SDx UltraScale FPGA MPSoC SDAccel SDSoC 2014 SDNet (Xcell Journal 87 ) SDx FPGA time-to-market FPGA

    All Programmable Abstraction 2008 CEO (Moshe Gavrielov) FPGA3D ICZynq-7000 All Programmable SoC 7 All Programmable 7 All Programmable FPGA FPGA

    All Programmable Abstractions: Programming Your Way Mike Santarini Publisher, Xcell Journal Xilinx, Inc. [email protected]

    All Pro-grammable FPGASoC3D IC SDx 2 SDAccel FPGA OpenCLC C++ FPGA FPGA GPU/CPU ( / ) SDSoC SDSoC FPGA C C++ Zynq-7000 All Programmable SoC UltraScale+ MPSoC SDx All Program-mable Abstraction (Steve Glaser) SDNetSD-AccelSDSoC CPU/GPU/ASSP 10 100 any-to-anyAll Programmable

    All Programmable Abstraction:

    http://japan.xilinx.com/ 7

  • C O V E R S T O R Y

    MathWorks National Instruments FPGA All Programmable time-to-market All Programmable FPGA Zynq SoC FPGA 10 (

    C C++ (Verilog VHDL) ASSP (SoC) Vivado HLS C C++ Vivado HLS RTL IP FPGA IP ( ) ( ) RTL IP (IPI) IP ( ) FPGA Vivado HDL FPGA / All Programmable (Zynq SoC MPU ) (SDK) Eclipse SDK 32 MicroBlaze Zynq SoC FPGA 10 SDK ( DSP 8/16/32 MCU/MPU Virtex-4 Virtex-5 FPGA 32 PowerPCZynq SoC 32 ARM Zynq UltraScale+ MPSoC 64

    ) All Programmable Abstraction ( 1)

    Vivado HLS IPI : 2011 (HLS) AutoESL 2012 ISE Design Suite Vivado Design Suite HLS AutoESL Berkeley Design Automation AutoESL HLS EDA HLS EDA

    1 SDx All Programmable

    8 Xcell Journal 91

  • C O V E R S T O R Y

    ARM )

    10 Na-tional Instruments Math-Works National Instruments ( ) / NI RIO FPGA Zynq SoC National Instruments LabVIEW Vivado Design Suite National Instruments FPGA RIO LabVIEW NI MathWorks ( ) 10 MATLABSimulinkHDL Coder Embedded Coder FPGA ISE Vivado ( ) FPGA FPGA System Generator 10 ISE Vivado Design Suite FPGA MathWorks

    TOPIC Embedded Systems Silicon Software 2 TOPIC Embedded Systems ( ) DYPLO (Xcell Journal 89 )Zynq SoC Zynq MPSoC ( ) C C++ Zynq SoC ARM Cortex -A9 (Vivado HLS ) C FPGA Zynq SoC TOPIC Silicon Software ( ) All Programmable 4 VisualApplets Zynq SoC 2013 SPS Drives Silicon Software VisualApplets VisualApplets

    Zynq SoC FPGA 10

    SDx FPGA SoC SDx SDAccel SDSoC Vivado Vivado SDNet Vivado HLS 2 1 C SDNet RTL RTL FPGA 2 SDNet SDAccel SDSoc 2 SDx

    SDACCEL Data Center Journal 2014 3 GoogleFacebookAmazonLinked-In 3% 2 CO2 600

    http://japan.xilinx.com/ 9

  • C O V E R S T O R Y

    1 SoC FPGA ARM 64 IP FPGA x86 CPU GPU OpenCL 2 OpenCL FPGA SDAccel OpenCLC C++ FPGA (Tom

    / 5G Data Center Journal 2017 7.7 x86 MPU ( ) ( ) MPU Graphics Processing Unit (GPU) GPU CPU GPU CPU FPGA FPGA FPGA CPU 1 1 SoC x86 FPGA

    Feist) OpenCLCC++ SDAccel CPU/GPU 25 20nmKintex UltraScale FPGA x86 CPU SDAccel ( 2 SDAccel ) OpenCL CPU SDAccel FPGA (Vivado )CPU

    CPU/GPU 25

    2 SDAccel (Henry Styles) SDAccel Alpha Data ADM-PCIE-7V3

    x86 64

    10 Xcell Journal 91

  • C O V E R S T O R Y

    SD-Accel (36 ) 1 SDAccel (40 )

    SDSoC SDNet SDAccel SDSoC SDSoC Zynq SoC SDSoC C C++ Zynq SoC SDSoC (Nick Ni)

    ASSP ASIC

    SDSoC ASSP Zynq SoC MPSoC SDSoC Zynq SoC Zynq UltraScale+ MPSoC Eclipse IDE C C++ SDSoC C C++ Zynq SoC Zynq SoC SDSoC SDSoC FPGA SDSoC Vivado Zynq SoC SDSoC

    ( 3 SDSoC )SDSoC Zynq SoC C/C++ SDSoC Vivado Design Suite IP SDSoC ZC702 ZC706 Zynq All Programmable SoC ZedBoardMicroZedZYBO / (BSP) Zynq SoC SDSoC BSP SDSoC Zynq SoC SDSoC Zynq SoC FPGA SDSoC C C++ FPGA FPGA Vivado IP SDSoC Xpedite ( 66 ) All Programmable Abstraction http://japan.xilinx.com/products/design-tools/all-programmable-abstractions.html

    3 SDSoC (Jim Hwang) SDSoC 60

    HD 1080p

    http://japan.xilinx.com/ 11

  • X C E L L E N C E I N B R O A D C A S T

    Enabling a JPEG 2000 Network for Professional Video

    Jean-Marie Cloquet Manager, Image Processing DivisionBarco Silex [email protected]

    JPEG 2000

    12 Xcell Journal 91

  • X C E L L E N C E I N B R O A D C A S T

    JPEG 2000 JPEG 2000 2013 4 (IP) Video Services Forum (VSF) TR-01 ( ) Barco Silex Barco Silex VSF TR-01 JPEG 2000 Video-over-IP Web Barco Silex IP ( ) Barco Silex 2014 & ( 1)

    Enabling a JPEG 2000 Network for Professional Video JPEG 2000 JPEG JPEG MPEG 2004 JPEG 2000 Digital Cinema Initiatives (DCI) JPEG 2000 JPEG 2000 ( ) ( 2)JPEG 2000 MPEG JPEG 2000 JPEG 2000 1 JPEG 2000 (FEC) JPEG 2000 /

    JPEG 2000 /

    IP 2007 (SMPTE) Video Transport over IP SMPTE 2022 MPEG-2 (CBR) IP ( SMPTE 2022 1 2 SMPTE 2022 5 6)Video Ser-vices Forum (VSF) 2013 VSF TR-01 (MPEG-2 TS over IP JPEG 2000 ) VSF VSF TR-01 Serial Digital Interface (SDI) ( )

    JPEG 2000

    Barco Silex JPEG 2000

    http://japan.xilinx.com/ 13

  • X C E L L E N C E I N B R O A D C A S T

    JPEG 2000 MPEG-2 SMPTE2022 Real-time Transport Protocol (RTP) IP RTP/IP MPEG-2 JPEG 2000 SDI

    FPGA 2012 9 VSF Barco Silex Video-over-IP IP ( ) Barco Silex (SMPTE 2022SMPTE SDI MAC) Barco Silex JPEG 2000 DDR3

    SMPTE 2022-1/2 Video-over-IP 1G TEMAC 10GEMAC 10G PCS/PMA 10 10GEMAC SMPTE 2022-5/6 Video-over-IP SMPTE SDI SDI 10GEMAC SMPTE 2022-1/2 Video-over-IP TS JPEG 2000 SDI SMPTE SDI 4

    Barco Silex Zynq-7000 All Programmable SoC Kintex-7 FPGA 2 SMPTE 2022 MAC LogiCORE IP UltraScale FPGA Barco Silex JPEG 2000 IP

    Video-over-IP Barco Silex 4 / ( 3)VSF TR-01 4 SDI (HD) (1080p30) JPEG 2000 1Gbps ( ) 10Gbps ( ) IP 4 SDI HD SMPTE SDI SDI SDI SMPTE 2022-5/6 Video-over-IP 10 MAC (10GEMAC) 10G PCS/PMA SDI JPEG 2000 Barco Silex TS VSF TR-01 MPEG-2

    1 Barco Silex JPEG 2000 2014 &

    (Luc PloumhansSake BuwaldaFranois MarsinJean-Franois MarbehantJean-Marie CloquetVincent Cousin

    14 Xcell Journal 91

  • X C E L L E N C E I N B R O A D C A S T

    IP 720p30/601080i1080p30/60 2K/4K/8K JPEG 2000 / FPGA JPEG 2000 Barco Silex DDR3 SDRAM Barco Silex

    2014 2 1 VidTrans 1 VSF 10 (ArtelBarco SilexEricssonEvertzImagine Communi-cationsIntoPIXMedia LinksMacnicaNevion ) JPEG 2000 720p30 1080i60 HD Barco Silex 4K (UHD)

    1 4K 1080p 4 4 SDI (4 SDI 4K ) 4K IP 4K

    FPGA Barco Silex FPGA Barco JPEG 2000 IP FPGA

    2

    SDI source

    SDI source

    SDI source

    SDI source

    SDI Rx

    BA317

    VideoEnc

    SDI

    JP2K TS

    10GEMACTX

    SFP+

    VideoDec

    JP2K TS

    SDI

    ClockRecovery

    buffer level

    Monitor

    Monitor

    Monitor

    Monitor BA317

    OZ745

    OZ745

    10GPCS/PMA

    SMPTE20225/6Dec

    SMPTE20221/2Dec

    10GEMACRX

    10GPCS/PMA

    JPEG2000Dec

    VideoOut2

    SDITS Dec

    SDI Rx

    PIXCO

    JPEG2000Enc

    TS EncSDI2

    Videocin

    SMPTE20221/2Enc

    SMPTE20225/6Enc

    3 /

    http://japan.xilinx.com/ 15

  • X C E L L E N C E I N S C I E N T I F I C A P P L I C AT I O N S

    White Rabbit: When Every Nanosecond Counts

    Dr. Javier Daz Chief Executive OfficerSeven Solutions SL [email protected]

    Rafael Rodrguez-GmezChief Technical OfficerSeven Solutions SL [email protected]

    Dr. Eduardo Ros Chief Operating OfficerSeven Solutions SL [email protected]

    White Rabbit :

    16 Xcell Journal 91

  • X C E L L E N C E I N S C I E N T I F I C A P P L I C A T I O N S

    100G 5G ( ) GPS Galileo GNSS CERN ( ) White Rabbit White Rabbit PTPv2 (IEEE-1588v2) White Rabbit Seven Solutions SL White Rabbit (WR) 2009 WR All Pro-grammable WR ZEN (Zynq Embedded Node) White Rabbit

    White Rabbit: When Every Nanosecond Counts

    FPGA SoC

    http://japan.xilinx.com/ 17

  • X C E L L E N C E I N S C I E N T I F I C A P P L I C A T I O N S

    ( ) ( ) 3 1 ( ) ( ) (CSAC) ( )

    ( ) (

    Precision Time Protocol (PTPv2 IEEE-1588v2) (SyncE) PTPv2 Network Time Protocol (NTP) PTPv2 2 SyncE PTPv2 SyncE

    CERN LHC CTASKAKM3NeT IT GPS GNSS GNSS ( )

    ) 1 ( ) 2 ( ) PPS (Pulse-Per-Second) 3 ( ) ( ) ( ) (PPS) 3 GPS (10 50MHz)PPS ( NMEA ) GPS PPS IRIG-B IRIG-B IRIG-B SDH/SONET

    18 Xcell Journal 91

  • X C E L L E N C E I N S C I E N T I F I C A P P L I C A T I O N S

    White Rabbit White Rabbit (http://www.whiterabbit-solution.com/) 2009 CERN / White Rabbit White Rabbit Open Hardware Repository (OHWRhttp://www.ohwr.org) Seven Solutions (www.sevensols.com)

    White Rabbit (WR) Seven Solutions WR White Ra-bbit Precision Time Protocol (IEEE-1588v3) 1 WR

    White Rabbit White Rabbit ( )

    WR PTP DMTD (Digital Dual-Mixer Time Difference) Seven Solutions ZEN White Rabbit 1 ( 2) Zynq-7000 All Programmable SoC ZEN White Rabbit (WRC) MAC WRC

    ( ) :

    1 White Rabbit

    http://japan.xilinx.com/ 19

  • X C E L L E N C E I N S C I E N T I F I C A P P L I C A T I O N S

    SyncE

    : ( ) (PTP ) FPGA DMTD

    : PTPv2 White Rabbit ( ) PTP White Rabbit

    FPGA WRC White Rabbit PLL 1 ZEN WRC (D-WRC) WRC

    Seven Solutions 7 D-WRC 2 White Rabbit ZEN D-WRC Zynq SoC Linux OS ARM Cortex -A9 Linux Web SNMP ZEN

    IRIG-B I/O ZEN

    2 Zynq SoC White Rabbit

    20 Xcell Journal 91

  • X C E L L E N C E I N S C I E N T I F I C A P P L I C A T I O N S

    18 White Rabbit Virtex-6 (LX240T) FPGA Linux OS (ARM926E) 18 GTX SFP 40 GPIO (LEDSFP ) Seven Solutions White Ra-bbit LEN Artix FPGA ( 3) OHWR Seven Solutions Zynq SoC White Rabbit WR-ZEN

    D-WRC Cortex 2 UART-USB

    ZEN Zynq SoC

    White Rabbit White Rabbit CERN Open Hardware (Open Hardware RepositoryOHWR) Seven Solutions SPEC 2 Spartan-6 (1 1 ) White Rabbit White Rabbit Seven Solutions (CERNGSI ) MicroTCA

    ARM 2 10/100/1000 / (NTPsNTPPTPv2 )

    WR 2 SFP

    SMA ZEN ( GPS ) WR

    FMC WR FMC ZEN

    SDDDR3

    3 Artix FPGA White Rabbit LEN () Zynq SoC ZEN ()

    http://japan.xilinx.com/ 21

  • X C E L L E N C E I N S C I E N T I F I C A P P L I C A T I O N S

    Seven Solutions White Rabbit

    White Rabbit White Rabbit White Rabbit (CERN GSI ) KM3NeTHISCORE WR

    2014 White Rabbit 2 VSL 125km MIKES 1,000km GPS ( ) GPS

    (U.S. Air Force Chief Warns against Over-Reliance on GPSInside GNSS News 2010 1 20 )White Rabbit Seven Solutions White Rabbit White Rabbit 4 WR-LEN GPS

    4 White Rabbit WR-LEN

    22 Xcell Journal 91

  • X C E L L E N C E I N S C I E N T I F I C A P P L I C A T I O N S

    White Rabbit White Rabbit IEEE-1588v3 ( ) WR Seven Solutions White Rabbit Seven Solutions Web SNMP / Seven Solutions RF ( )

    WR ( km) White Rabbit White Rabbit ( ) GPS 100G 5G WR

    IRIG-B PTPv2 PTPv2 PTP 5 ZEN LEN CSAC FMC

    White Rabbit

    5 ZEN

    http://japan.xilinx.com/ 23

  • Evaluating the Linearity of RF-DAC Multiband Transmitters

    X C E L L E N C E I N W I R E L E S S C O M M U N I C AT I O N S

    Lei Guan Member of Technical StaffBell Laboratories, Alcatel Lucent Ireland [email protected]

    RF-DAC FPGAMATLAB RF DAC

    24 Xcell Journal 91

  • X C E L L E N C E I N W I R E L E S S C O M M U N I C A T I O N S

    RF ( RF DAC RF ADC) RF 2 TX TX RF DAC RF DAC RF DAC RF DAC / 3

    FPGA IP ( ) MATLAB FPGA Analog Devices RF-DAC (AD9129 AD9739a) ML605 ML605 Virtex-6 XC6VLX240T-1FFG1156 FPGA FPGA RF DAC I/O ( 710MHz) SERDES ( 5Gbps) FPGAIP MATLAB

    RF DAC (CW) (xDDS) (xRAM)

    2 RF CW (DDS) 4 2 1 2 RF DAC 4 RF DAC (spurs) CW RF DAC UMTS (2.1GHz)/LTE (2.6GHz) / RF DAC 2 BRAM 1

    1

    http://japan.xilinx.com/ 25

  • X C E L L E N C E I N W I R E L E S S C O M M U N I C A T I O N S

    : FPGA 1 FPGA DDS RAM 2 ( BRAM cRAM BRAM dRAM ) PC UART RF DAC FPGA

    FPGA 2 (S0) UART 3 MATLAB 2

    RF DAC BRAM 1 2 2 RAM RAM 16 192k PC FPGA UART 921.6kbps (115.2 / ) cRAM (18 ) 0.16 dRAM ( 384 ) 3.33 VHDL Verilog FPGA AD9739a AD9129 RF DAC Analog Devices LVDS IP (CPRIJESD204B )

    : MATLAB DSP GUI MATLAB (DSP) MATLAB MATLAB (GUI) GUIDE MATLAB DSP

    FF01 (cRAM ) DDS FF10 FF11 (dRAM ) S1x FF01 S2x S3x 2 / DDS

    cRAM 2 cRAM_rd_done DDS 4 MATLAB cRAM FPGA DDS 2

    2

    26 Xcell Journal 91

  • X C E L L E N C E I N W I R E L E S S C O M M U N I C A T I O N S

    DSP UART 4 GUI RF DAC ( ) xDDS xRAM MATLAB

    xDDS fs fc phase_incr = fc*2nbits/fs ( nbits DDS )Start 3 2 UART cRAM FPGA xRAM MATLAB

    ( 16 ) UART dRAM Start FPGA MATLAB UART R&S SMU200A RF DAC RF DAC RF DAC

    RF / RF FPGA IP JESD204B RF DAC FPGA ML605 Zynq-7000 All Programmable SoC ZC706 DSP PC Zynq SoC ([email protected])

    3

    4

    http://japan.xilinx.com/ 27

  • X P E R IM EN T

    Oberon System Implemented on a Low-Cost FPGA Board

    Niklaus Wirth Professor (retired)Swiss Federal Institute of Technology (ETH)Zurich, Switzerland [email protected]

    FPGA Oberon

    28 Xcell Journal 91

  • X P E R I M E N T

    1988 (Jrg Gutknecht) Pascal Modula-2 2 Oberon [1,2] Modula-2 Oberon 1990 OS Oberon Oberon Oberon (Project Oberon) ( ) (Paul Reed) 1 FPGA FPGA 1990

    Xcell Journal (Niklaus Wirth) Pascal ACM IEEE

    Spartan-3 Oberon

    http://japan.xilinx.com/ 29

  • X P E R I M E N T

    RISC 1 RAM (SRAM) Digilent Spartan-3 SD projectoberon.com [3,4,5] S3RISCinstall.zip ( ) SD (Spartan-3 PROM ) FPGA SD /

    RISC (ALU)16 32 ( (IR) (PC) ) Verilog RISC5

    1024 768 1 = 98,304 ( 1 10%) VGA SD 80 SD 32 SPI PS-2 RS-232 8 I/O

    20 4 / / 4 4 4 2 2 RISC5 RISC5Top RISC5Top ( ) SRAM (256M 32 ) ( 1) Verilog ( )

    1 Verilog

    RISC5TOP

    RISC5

    Multiplier Divider FPAdder FPMultiplier FPDivider

    VID SPI PS2 Mouse RS232

    RISC5Top environment 194RISC5 processor 201Multiplier integer arithmetic 47Divider 24FPAdder floating-point arithmetic 98FPMultiplier 33FPDivider 35SPI SD card and transmitter/receiver 25VID 1024 x 768 video controller 73PS2 keyboard 25Mouse mouse 95RS232T RS232 transmitter 23RS232R RS232 receiver 25

    30 Xcell Journal 91

  • X P E R I M E N T

    RISC5Top 1

    Oberon Oberon System M.P (P M )M Kernel 2

    2 Spartan-3 112,640 (21%) 16,128 (3%) 3 ( )

    2

    Oberon Oberon Oberon

    ORP.Compile @ (BEGINEND+ ) Compiler Construction[6,7] ( ) ( ) R14 ( ) R13 R12 R15 RISC ( ) R0 R11 4 ( )

    ( ) 115,912 (22%) 17,508 (4%) 65 25MHz RISC [8] NIL 2 Spartan-3

    Kernel 271 (inner core)FileDir 352Files 505Modules (loader) 226Viewers 216 (outer core)Texts 532Oberon 411MenuViewers 208TextFrames 874System 420Edit 233

    ORP parser 968 ORG code generator 1120ORB base def 435 ORS scanner 311

    http://japan.xilinx.com/ 31

  • Lola HDL Lola Verilog Lola (HDL) 1990 FPGA Lola (FPGA ) Algotronix Inc. Concurrent Logic Inc. Oberon FPGA Lola FPGA Lola Verilog Lola Lola

    MODULE Counter0 (IN CLK50M, rstIn: BIT; IN swi: BYTE; OUT leds: BYTE);

    TYPE IBUFG := MODULE (IN I: BIT; OUT O: BIT) ^;VAR clk, tick0, tick1: BIT; clkInBuf: IBUFG; REG (clk) rst: BIT; cnt0: [16] BIT; (*half milliseconds*) cnt1: [10] BIT; (*half seconds*) cnt2: BYTE;

    BEGIN leds := swi.7 -> swi : swi.0 -> cnt1[9:2] : cnt2; tick0 := (cnt0 = 49999); tick1 := tick0 & (cnt1 = 499); rst := ~rstIn; cnt0 := ~rst -> 0 : tick0 -> 0 : cnt0 + 1; cnt1 := ~rst -> 0 : tick1 -> 0 : cnt1 + tick0; cnt2 := ~rst -> 0 : cnt2 + tick1; clkInBuf (CLK50M, clk) END Counter0.

    Lola-2 RISC5 Lola

    Lola Lola Oberon (http://www.inf.ethz.ch/perso-nal/wirth/Lola/Lola2.pdf ) Lola 1 ( 1)

    X P E R I M E N T

    SYSTEM ( PUT COPY) SYSTEM Oberon

    Digilent Spartan-3 RAM ( ) RAM

    RAM ( ) RAM

    1 LED Lola

    32 Xcell Journal 91

  • BYTE 8

    Lola Lola Lola LSC.Compile @ (BEGINEND+ ) Compiler Construction (Part 1 Part 2) Verilog 1 Verilog LSV. List outputfile.v VHDL

    4 ( )

    Lola Verilog ( ) http://www.inf.ethz.ch/personal/wirth/Lola/LolaCompiler.pdf

    HDL (PL) HDL Verilog C VHDL AdaLola Oberon 2 ( )

    ( ) 1 ( ) 1 HDL 1 (John von Neu-mann) 1 ALU Lola-2 Oberon HDL Lola Verilog Lola RISC Lola (http://www.inf.ethz.ch/personal/wirth/Lola/index.html ) (Niklaus Wirth)

    LSS scanner 159LSB base 52LSC compiler/parser 503LSV Verilog generator 215

    X P E R I M E N T

    40 C.A.R. (C.A .R. Hoare)

    1975 (J. ) Oberon (1986 1988 )

    http://japan.xilinx.com/ 33

  • X P E R I M E N T

    3

    System

    RISC5

    Multiplier Divider FPAdder FPMultiplier FPDivider

    VID SPI PS2 Nouse RS232

    RISC5TOP

    RS232

    Oberon

    TextFrame

    MenuView

    Oberon

    Input

    Viewers Texts Input

    Kernel

    Display Modules Fonts

    Files

    FileDir

    ( )

    Oberon ( )

    1

    (Paul Reed)

    Project Oberon FPGA SD SPIPS-2 VID Verilog

    1. http://www.inf.ethz.ch/personal/wirth/

    Oberon/Oberon07.Report.pdf

    2. http://www.inf.ethz.ch/personal/wirth/Oberon/PIO.pdf

    3. www.inf.ethz.ch/personal/wirth/Pro-jectOberon/index.html

    4. www.inf.ethz.ch/personal/wirth/Oberon/PIO.pdf

    5. www.inf.ethz.ch/personal/wirth/Oberon/Oberon07.Report.pdf

    6. http://www.inf.ethz.ch/personal/wirth/CompilerConstruction/CompilerCon-struction1.pdf

    7. http://www.inf.ethz.ch/personal/wirth/CompilerConstruction/CompilerCon-struction2.pdf

    8. http://www.inf.ethz.ch/personal/wirth/ProjectOberon/PO.Applications.pdf (Ch. 12)

    34 Xcell Journal 91

  • !!

    FPGA

    FPGA/SoC

    FPGA/SoC

    FPGA FPGA FPGA

    FPGA

    FPGA FPGA

    30! FPGA

    UltraScale

    AMBA AXI4

    FPGA PlanAhead 1 2 3

    Zynq SoC

    Zynq SoC

    All Programmable

    All Programmable

    15! FPGA

    7

    http://japan.xilinx.com/webseminar/

    All Programmable FPGA SoC 3D IC

    Zynq-7000 SoC

    UltraScale

    28nm 7 FPGA

    FPGA/SoC

  • X C E L L E N C E I N D AT A C E N T E R S

    Removing the Barrier for FPGA-Based OpenCL Data Center Servers

    FPGA OpenCL SDAccel CPU FPGA

    36 Xcell Journal 91

  • X C E L L E N C E I N D A T A C E N T E R S

    NRDC (Natural Resources Defense Council) 1 2013 2 910 kWh 2020 1,400 kWh [1] (GPU) (DSP) (FPGA) SDAccel CPU/GPU FPGA

    Amazon Web ServicesGoogle Com-puteMicrosoft AzureFacebook Baidu Google

    16,000 1 CPU Baidu FPGA CPU/GPU [2] 7 Ultra- Scale 28nm 20nm FPGA FPGA FPGA CPU GPU 20 CPU 50 75 FPGA ( ) RTL (VHDL Verilog) FPGA Open Computing Language (OpenCL )

    Devadas Varma Senior Engineering DirectorSDAccel and Vivado High-Level Synthesis Xilinx, Inc. [email protected]

    Tom Feist Senior Director Design Methodology Marketing Xilinx, Inc. [email protected]

    http://japan.xilinx.com/ 37

  • X C E L L E N C E I N D A T A C E N T E R S

    OpenCL CPUGPUDSPFPGA OpenCL (C99 ) (API) OpenCL

    OpenCL SDAccel 10 /

    OpenCL OpenCL CPUGPUFPGADSP Apple Inc. Khronos Group [3] OpenCL CPUGPUFPGA ( ) OpenCL API CPU/GPU/FPGA OpenCL 1 20nm C

    OpenCL SDAccel SDAccel ( 1) FPGA OpenCL SDAccel FPGA Eclipse (IDE) IDE CPU/GPU SDAccel CPU

    1 SDAccel CPU/GPU

    38 Xcell Journal 91

  • X C E L L E N C E I N D A T A C E N T E R S

    2 CPUGPUFPGA OpenCL FPGA

    ( Auviz AuvizCV )

    FPGA FPGA SDAccel SDAccel FPGA CC++OpenCL SDAccel CPU 10 GPU 10 1 FPGA FPGA SDAccel OpenCL ( )math.h

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    Nvidia GTX 750Ti GPU, Cuda 6.0

    Xilinx 7 Series, Current (100MHz),AuvizCV Beta

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    1. http://www.nrdc.org/energy/data-center-efficiency-assessment.asp

    2. http://www.pcworld.com/article/2464260/microsoft-baidu-find-speedier-search-results-through-specialized-chips.html

    3. https://www.khronos.org/opencl

    http://japan.xilinx.com/ 39

  • X C E L L E N C E I N D AT A C E N T E R S

    Optimizing an OpenCL Application for Video Watermarking in FPGAs

    Jasmina Vasiljevic Researcher University of Toronto [email protected]

    Fernando Martinez Vallina, PhD Software Development Manager Xilinx, Inc. [email protected]

    FPGA OpenCL SDAccel

    40 Xcell Journal 91

  • X C E L L E N C E I N D A T A C E N T E R S

    SDAccel OpenCL FPGA Alpha Data ADM-PCIE-7V3 1080p (HD) 30fps ( / ) SDAccel FPGA OpenCL FPGA SDAccel

    1

    2 PCIe x86 Alpha Data ADMPCIE- 7V3

    FPGA FPGA BRAM

    YCbCr 2 YCbCr 3 Y Cb Cr 8 1 24 2

    Logo Mask Input video Output video

    1

    out_y[x][y] = (255-mask[x][y]) * in_y[x][y] + mask[x][y] * logo_y[x][y]

    out_cr[x][y] = (255-mask[x][y]) * in_cr[x][y] + mask[x][y] * logo_cr[x][y]

    out_cb[x][y] = (255-mask[x][y]) * in_cb[x][y] + mask[x][y] * logo_cb[x][y]

    http://japan.xilinx.com/ 41

  • X C E L L E N C E I N D A T A C E N T E R S

    FPGA 3 3 FPGA FPGA FPGA 4 FPGA SDAccel Alpha Data 0.5 fps

    (24 / 20 = 504 )SDAccel 5 char20 12 fps

    30fps 20 20 / 6 DDR BRAM

    4 /

    FPGA 1 SDAccel FPGA Alpha Data 512 SDAccel AXI 512 20

    2

    42 Xcell Journal 91

  • X C E L L E N C E I N D A T A C E N T E R S

    memcpy 1 1920 54 20 ( 7 )

    memcpy memcpy DDR

    20 38 fps 30 fps

    Host Codefor (i=0; i

  • char20 l_in_y[BLOCK_WIDHT*BLOCK_HEIGHT/20]; char20 l_in_cr[BLOCK_WIDHT*BLOCK_HEIGHT/20]; char20 l_in_cb[BLOCK_WIDHT*BLOCK_HEIGHT/20];

    char20 l_out_y[BLOCK_WIDHT*BLOCK_HEIGHT/20]; char20 l_out_cr[BLOCK_WIDHT*BLOCK_HEIGHT/20]; char20 l_out_cb[BLOCK_WIDHT*BLOCK_HEIGHT/20];

    for (block_id=0; block_id

  • X C E L L E N C E I N D A T A C E N T E R S

    SDAccel GPU FPGA SDAccel PCIe IP SDAccel SDAccel

    7

    Get Published

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    Xcell Publications ?

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    Xcell Publication Mike Santarini ([email protected])

    http://japan.xilinx.com/ 45

  • X P L A N AT I O N : F P G A 1 0 1

    Coming to Grips with the Frequency Domain

    Adam P. Taylor Chief Engineer e2v [email protected]

    46 Xcell Journal 91

  • X P L A N A N T I O N : F P G A 1 0 1

    FPGA IP

    1 2

    FPGA

    http://japan.xilinx.com/ 47

  • X P L A N A N T I O N : F P G A 1 0 1

    3

    (

    x[i] i 0 N-1 k 0 N/2

    ReX ImX ImX[k] ReX[k] N/2 ReX ImX ReX[0] ReX[N/2] ImX[k] ReX[k] N (IDFT) ( )DFT IDFT OctaveMATLAB Excel DFT

    )Z FPGA (DFT) DFT A/D n DFT 2 N DFT N/2+1 N/2+1 2 ( 1) n n/2 DFT

    0 1 2 3 4 5 6 7

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    Time Domain

    Real Result Imaginary Result

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    1 N n/2 n/2

    48 Xcell Journal 91

  • X P L A N A N T I O N : F P G A 1 0 1

    DFT DFT IDFT DFT IDFT

    FPGA DFT FPGA DFT (FIR) (Xcell Journal 78 Ins and Outs of Digital Filter Design and Implementation )DFT DFT IDFT DFT IDFT DFT IDFT DFT FPGA DFT FPGA

    FPGA DFT IDFT N DFT

    DFTtime = N * N * Kd ft

    Kdft FPGA DFT (FFT) FFT FFT DFT DFT FFT n/2 n DFT 0 FPGA FFT 2 HDL FFT Vivado Design Suite IP FFT IP IP IP FFT Log2 N (N ) FFT 1 Log2 N FFT DFT FFT

    FFTtime = K f ft * N Log2 N

    DFT FPGA FFT FFT FFT FFT

    n FFTSize FFT FPGA 2 ( 2565121,024 )

    (FS) 100MHzFFT 128 0.39Hz 0.39Hz

    FPGA FFT (1 2 ) 1 ADC 3GHz 2.5GHz 1.25GHz 1

    http://japan.xilinx.com/ 49

  • X P L A N A N T I O N : F P G A 1 0 1

    1st NYQUISTZONE

    2nd NYQUISTZONE

    3rd NYQUISTZONE

    4th NYQUISTZONE

    0.5fs

    fa

    1.5fs 2fsfs

    II I

    2

    pipelined Q point FFT

    pipelined Q point FFT

    pipelined Q point FFT

    pipelined Q point FFT par

    alle

    l P p

    oin

    t F

    FT

    x[0] / x[4] / ...

    x[1] / x[5] / ...

    x[2] / x[6] / ...

    x[3] / x[7] / ...

    X[0] / X[1] / ...

    X[128] / X[129] / ...

    X[256] / X[257] / ...

    X[384] / X[385] / ...

    X'[0.m2]

    X'[1.m2]

    X'[2.m2]

    X'[3.m2] X''[3.m2]

    X''[2.m2]

    X''[1.m2]

    X''[0.m2]

    pipelined Q point FFT

    pipelined Q point FFT

    pipelined Q point FFT

    pipelined Q point FFTpar

    alle

    l P p

    oin

    t F

    FT

    reo

    rder

    ing

    X'[n1.0]

    X'[n1.1]

    X'[n1.2]

    X'[n1.3] X''[n1.3]

    X''[n1.2]

    X''[n1.1]

    X''[n1.0] X[0] / X[4] / ...

    X[1] / X[5] / ...

    X[2] / X[6] / ...

    X[3] / X[7] / ...

    X[0] / x[1] / ...

    x[128] / x[129] / ...

    x[256] / x[257] / ...

    x[384] / x[385] / ...

    x[0] / x[4] / ...

    x[1] / x[5] / ...

    x[2] / x[6] / ...

    x[3] / x[7] / ...

    3 FFT FFT

    50 Xcell Journal 91

  • X P L A N A N T I O N : F P G A 1 0 1

    2

    Fharm = N FfundIF (Fharm = Odd Nyquist Zone)

    Floc = Fharm Mod FfundElse

    Floc = Ffund-(Fharm Mod Ffund)End

    N 2500MHz 1807MHz 1 693MHz FFT ADC DAC FPGA ADC FS/2 ( 2.5Gbps) ( FS/4 FS/2) ( ) FPGA DFT FPGA 1 3 FFT FFT IP

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  • X P L A N AT I O N : F P G A 1 0 1

    Marrying SoC Platform Designs with System Generator for DSP

    Daniel E. MichekSenior Manager, System-Level Product Marketing Xilinx, Inc. [email protected]

    SoC System Generator for DSP

    Vivado System Generator SoC

    52 Xcell Journal 91

  • X P L A N A N T I O N : F P G A 1 0 1

    FPGA FPGA FPGA IP ( ) FPGA APU All Programmable SoC FPGA RTL IP ARM Advanced eXtensible Interface (AXI) System Generator for DSP Vivado Design Suite Vivado

    IP IP DSP ( )

    IP All Programmable 2 AXI4-Lite Simulink AXI4-Stream System Generator Vivado IP

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    SoC System Generator for DSP

    http://japan.xilinx.com/ 53

  • X P L A N A N T I O N : F P G A 1 0 1

    All Program-mable DSP IP AXI System Generator System Generator IP AXI 1 AXI4-Lite

    System Generator 2 S_AXIS TDATA ( ) TVALID IP AXI4-Lite AXI4-Stream AXI4- Lite Simulink AXI4-Stream 1 IP

    Vivado Design Suite (Vivado ) / API AXI4-Stream System Generator AXI4-Stream ACLK TVALID

    2 AXI4-Lite AXI4-Stream

    54 Xcell Journal 91

  • X P L A N A N T I O N : F P G A 1 0 1

    1 IP 1 TREADY Simulink Signal Workspace TDATA 2 M_AXIS AXI4-Stream FIFO IP System Generator AXI ( ) IP

    System Generator for DSP Vivado IP RTL IP SDK IP DSP 3

    DSP

    IP System Generator for DSP http://japan.xilinx.com/products/design-tools/vivado/integration/sysgen.html Daniel Michek (Tel : (858) 207-5213e-mail : [email protected])

    3 DSP

    http://japan.xilinx.com/ 55

  • X P L A N AT I O N : F P G A 1 0 1

    Rethinking Digital Downconversion in Fast, Wideband ADCs

    Ian Beavers Contributing Technical Expert Analog Devices [email protected]

    ADC

    56 Xcell Journal 91

  • X P L A N A N T I O N : F P G A 1 0 1

    GSPS ( / ) / (ADC) ADC / ADC FPGA FPGA ADC (FDM) FPGA GSPS ADC (DDC) FPGA ADC ADC GSPS ADC DDC

    ADC ADC ADC decimate-by-M M M

    ADC

    GSPS ADC FPGA (DDC)

    http://japan.xilinx.com/ 57

  • X P L A N A N T I O N : F P G A 1 0 1

    ADC ( ) ( )

    DDC DDC DDC / DDC

    % (85%90% ) 8 10 ( fs/10) DDC

    DDC DDC DDC DC

    (FIR) FIR

    DDC DDC 2 (24816 ) DDC

    -fs/2 -3fs/8 -fs/4 -fs/8 0 fs/23fs/8fs/4fs/8

    -fs/2 -3fs/8 -fs/4 -fs/8 0 fs/23fs/8fs/4fs/8

    Real Input to ADC

    After Frequency Translation within ADC

    NCO tunes to signal of interest

    DecimationFilter

    image

    Signal of interestSignal of interest image

    Signal of interest afterfrequency translation

    1 NCO

    58 Xcell Journal 91

  • X P L A N A N T I O N : F P G A 1 0 1

    (NCO) 1 2 NCO ( 1) NCO

    2 8 DDC Artix-7 16 GTP 6.6Gbps 8 ADC ( ADC 2 JESD204B I/Q )

    2 ADC ( ADC 8 )

    2 48 NCO NCO DDC DC DDC

    6dB NCO 6dB NCO DC DDC +6dB

    ADCDDC

    ADCDDC

    ADCDDC

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    ADCArtix-7FPGA

    GTPTRxx16

    Artix-7FPGA

    GTPTRxx16

    http://japan.xilinx.com/ 59

  • X P L A N A N T I O N : F P G A 1 0 1

    ADC DDC SNR 1 DDC ADC SNR 2 14 18 116 1 ... +3 dB

    SNR () =6.02*N + 1.76 dB + 10log10(fs/(2*BW))

    DDC DDC SFDR DDC ADC 1 2 3 SFDR DDC 2 3 SFDR DDC NCO

    ADC ADC I Q I Q 16 8 1 ADC JESD204B ADC 1 FPGA DDC ADC ADC 8 DDC 1 ADC 2 Artix-7 FPGA 4 ADC Artix-7 FPGA 16 GTP DDC 8 ADC ( 2) FPGA FDM

    DDC SNR SFDR DDC (SNR) (SFDR)

    DDC ADC DDC DDC ADC DDC DDC NCO

    ADC DDC FPGA ADC 1 DDC ADC DDC DDC NCO FPGA FDM ADC ADC DDC ADC DDC SNR SFDR Artix-7 FPGA

    60 Xcell Journal 91

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  • Xcell Journal Daily Blog Xcell Journal Daily Blog

    Recent n Adam Taylors MicroZed Chronicles Part 88: SDSoC Part 4a look under the hood

    n How do you design backplanes for 25+ Gbps operation? Teraspeeds Scott McMorrow tells you how in two videos

    n Adam Taylors MicroZed Chronicles Part 87: Getting SDSoC up and running Part 3

    n Warning! Only days left before Xcell Journals latest caption contest deadline. Your prize: a Zynq-based Digilent ZYBO dev board.

    n Hyperspectral GigE video cameras from Photonfocus see the unseen @ 42fps for diverse imaging applications

    : www.forums.xilinx.com/t5/Xcell-Daily/bg-p/Xcell

    Xcell Journal

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    All Programmable Smarter System

    Xcell91_cover_japan_0625Xcell91_ID01_japan_0624Xcell91_XilinxAD_p3Xcell91_contents_japan_0625Xcell91_ID02_japan_0624Xcell91_ID03_japan_0625Xcell91_ID04_japan_0625Xcell91_ID05_japan_0625Xcell91_ID06_japan_0625Xcell91_Webseminar_0623Xcell91_ID07_japan_0625Xcell91_ID08_japan_0625Xcell91_ID09_japan_0625Xcell91_ID10_japan_0625Xcell91_ID11_japan_0625Xcell91_training_p63_0625Xcell91_DailyBlog_japan_0623