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japan.xilinx.com/xcell SOLUTIONS FOR A PROGRAMMABLE WORLD 90 2015 1 ワット当たり性能を 2 5 倍に向上させる 16nm UltraScale+ デバイス 60GHz ミリメートル波 バックホール リンクによる 大容量通信の実現 2 つのコアを利用して Zynq SoC の性能を 最大限に引き出す方法 ザイリンクス FPGA PetaLinux を移植する方法 ザイリンクス FPGA を使用 したソーラー オービターの オンボード データ処理 ページ 12

ザイリンクス Xcell Journal 日本語版 90 号

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Xcell Journal 90 号のカバーストーリーでは、新しい UltraScale+ の プロダクトポートフォリオである FPGA、3DIC、Zynq® All Programmable SoC の 次世代「Zynq UltraScale+ MPSoC」 が、28nm 7シリーズデバイスと比べて、どのように 1 ワット当たりのシステム性能を 2 倍~5 倍に向上したかを説明しています。

Text of ザイリンクス Xcell Journal 日本語版 90 号

  • japan.xilinx.com/xcell

    S O L U T I O N S F O R A P R O G R A M M A B L E W O R L D

    9 0 2015

    1 2 5 16nm UltraScale+

    60GHz

    2 Zynq SoC

    FPGA PetaLinux

    FPGA

    12

  • L E T T E R F R O M T H E P U B L I S H E R

    2011 All Programmable SoC / / Zynq SoC Xcell Journal Xcell Daily Blog Zynq SoC ARM Cortex -A9 MPCore 7 FPGA 1 Zynq SoC Zynq SoC 3,000 ASSP/ASIC + FPGA 2 FPGA ASSP I/O ( BOM ) 1 2 1 Zynq SoC 4 All Programmable SoC Zynq UltraScale+ MPSoC 16nm UltraScale+ 1 Zynq SoC All Programmable MPSoC 1 Zynq SoC 1 UltraScale+ (FPGA3D ICMPSoC) TSMC 16nm FFT+ 1 2 UltraRAM SmartConnect 1 Zynq UltraScale+ MPSoC 1 Zynq MPSoC All Programmable SoC 64 APU RPU Zynq MPSoC 1 28nm Zynq SoC 5 Zynq SoC Zynq UltraScale+ MPSoC

    Get Ready for More Innovations from Xilinx

    Mike Santarini

    Xcell journal

    Jacqueline Damian

    Scott Blair

    / Teie, Gelwicks & Associates

    [email protected]

    Xcell Journal 90

    2015 4 13

    Xilinx, Inc2100 Logic DriveSan Jose, CA 95124-3400

    141-0032 1-2-2 4F

    2015 Xilinx, Inc. All Right Reserved.

    XILINX Xcell Xilinx

    Xilinx, Inc.

    Xilinx, Inc.

    [email protected]

    Mike [email protected]+1-408-626-5981

    Xcell Journal Dan Teie 2015 1

  • Xcell Journal Daily Blog Xcell Journal Daily Blog

    Recent n A Double-Barreled Way to Get the Most from Your Zynq SoC

    n New video shows successful 400G and 25G Ethernet interoperability demos at last weeks OFC 2015

    n How do you boost the floating-point performance of a quad-core Intel Core i7 PC by 1.7x? Add Zynq

    n How to cut through the thicket of multiple interface standards in your Broadcast and Pro A/V designs

    n Testing 10Gbps Optical Modules: Simplify Your Hot Testing with Xilinxs Zynq SoC

    : www.forums.xilinx.com/t5/Xcell-Daily/bg-p/Xcell

    Xcell Journal

    Xcell Daily Blog

    All Programmable Smarter System

  • Cover Story

    430

    12

    18

    VIEWPOINTS

    Letter From the Publisher

    2

    Xcellence in Aerospace

    FPGA 12

    Xcellence in WirelessCommunications

    60GHz 18

    Xcellence in Data Centers

    MACsec IP 24

    Xcellence in Data Centers

    Zynq SoC 30

    XCELLENCE BY DESIGN APPLICATION FEATURES

    1 2 5 16nm UltraScale+

  • 42

    5234

    Excellence in Magazine & Journal Writing2010, 2011

    Excellence in Magazine & Journal Design2010, 2011, 2012

    9 0

    Xplanation: FPGA 101

    2 Zynq SoC 34

    Xplanation: FPGA 101

    FPGA PetaLinux 42

    Xplanation: FPGA 101

    Vivado HLS 52

    THE XILINX XPERIENCE FEATURES

  • C O V E R S T O R Y

    Xilinx 16nm UltraScale+ Devices Yield 2-5X Performance/Watt Advantage

    Mike Santarini Publisher, Xcell Journal Xilinx, Inc. [email protected]

    1 2 5 16nm UltraScale+

    4 Xcell Journal 90

  • C O V E R S T O R Y

    28nm 7 All Programmable 20nm UltraScale 16nm UltraScale+16nm UltraScale+ 28nm 1 2 5 1 TSMC 16FF+ (16nm FinFET Plus) UltraRAM SmartConnect 3 2 Zynq All Programmable SoC Zynq UltraScale SoC (MPSoC) 64 ARM Cortex -A53 32 ARM Cortex-R5 ARM Mali-400MP 16nm FPGA (UltraRAM ) 1 Zynq UltraScale+ MPSoC 28nm Zynq SoC 1 5

    FinFET UltraScale Dave Myron 16nm UltraScale+ LTE Advanced 5G (ADAS) IoT ( )

    TSMC 16nm FinFET UltraRAM SmartConnect

    http://japan.xilinx.com/ 5

  • C O V E R S T O R Y

    UltraScale+UltraScale TSMC 20nm ( ) TSMC 16FF+ (2015 4 ) 2 16nm UltraScale+ Virtex FPGA 3D IC Kintex FPGA Zynq UltraScale+ MPSoC Mark Moran 2013 TSMC 16FF+ 20nm UltraScale ( 28nm ) 20nm 1 Moran

    16nm UltraScale+ 16nm UltraScale+ 1 Myron Myron UltraScale+ FPGA 3D IC 28nm 7 1 2 Zynq UltraScale+ MPSoC 28nm Zynq SoC 1 5 ( 1)

    TSMC 16FF+ 1 16nm FinFET 28nm 7 1 2 Myron TSMC 16FF+

    UltraScale+ 1 1 20nm UltraScale 16nm 20nm FinFET 16nm 1 16nm 20nm 20nm 16nm UltraScale+ Myron Virtex UltraScale+ 20nm Virtex UltraScale 1 20nm UltraScale

    1 16nm UltraScale+ FPGA Zynq UltraScale+ MPSoC 1

    6 Xcell Journal 90

  • C O V E R S T O R Y

    TSMC UltraScale+ ( )UltraScale+ 28nm 7 1 2 20nm UltraScale FinFET Xcell Journal 84 6UltraScale+ 3D-on-3D TSMC 16FF+ 3D 3 3D IC Myron 7 3D IC 1 IC 3D IC 28nm FPGA 2

    FPGA 28nm UltraScale+ 3D IC Myron

    UltraRAM 1 Myron UltraScale+ UltraRAM 28nm 1 UltraScale+ UltraRAM Myron LUT RAM/ RAM RAM DDR SRAM RAM

    I/O BOM UltraRAM 1 Myron LUT/ RAM RAM BRAM UltraRAM UltraScale+ SRAM ( 2) RAM (SRAMRLDRAMTCAM) BOM UltraScale+ VU13P 432 UltraRAM

    SmartConnect 1 1 SmartConnect UltraScale+ 1

    2 UltraRAM

    http://japan.xilinx.com/ 7

  • C O V E R S T O R Y

    Myron 3 8 Myron 2 1 SmartConnect 20%

    16nm UltraScale+ FPGA FPGA 1 48 CPRI / 28nm

    SmartConnect Myron IP ( ) Myron SmartConnect Vivado Design Suite SmartConnect AXI 16nm UltraScale+ 16nm UltraScale+ 16nm FinFET 1

    Virtex-7 FPGA 56W ( ) ( 4) 16nm Virtex UltraScale+ FPGA 27W (55% )1 2.1 UltraRAM SmartConnect 1 Virtex UltraScale+ 1 28nm Virtex-7 FPGA 2.7 63% FPGA 15W PCI 28nm Virtex-7 525Ops (Ope-rations Per Second) 16nm UltraScale 1,255Ops 1 2.4 UltraRAM

    3 SmartConnect 20% 20%

    8 Xcell Journal 90

  • C O V E R S T O R Y

    SmartConnect Virtex UltraScale+ 1 28nm Virtex-7 FPGA 3.6

    Zynq UltraScale+ MPSoC 1 5 2 All Programmable SoC TSMC 20nm TSMC 16nm FinFET 16nm Zynq UltraScale+ MPSoC 16nm UltraScale 1 16nm Zynq UltraScale+ MPSoC 28nm Zynq SoC 5

    2014 UltraScale MPSoC Zynq UltraScale+ MPSoC Zynq UltraScale+ MPSoC ( 5) 28nm Zynq SoC ARM 1 ( 84Gbps ) 3,000 Zynq SoC (PS) (PL) PS PL 1 FPGA ASSP 2 16nm UltraScale+ MPSoC 500Gbps

    6,000 All Pro-grammable SoC Barrie Mullins

    Zynq UltraScale+ MPSoC 28nm Zynq SoC 6 ASSP + FPGA 2 Mullins Zynq UltraScale+ MPSoC 64 ARM Cortex-A53 28nm Zynq SoC Cortex-A9 2 ARM TrustZone

    4 16nm UltraScale+ 1

    http://japan.xilinx.com/ 9

  • C O V E R S T O R Y

    Zynq UltraScale+ MPSoC ARM Cortex-R5 Zynq UltraScale+ MPSoC ARM Mali -400MP CPU GPU H.265 / 8Kx4K (15 / ) 4Kx2K (60 / ) DisplayPort DisplayPortP TX

    Zynq UltraScale+ MPSoC UltraScale+ Zynq UltraScale+ MPSoC RAM UltraRAM Zynq UltraScale+ MPSoC L1 L2 Zynq UltraScale+ MPSoC ECC 72 DDR (64 + ECC 8 ) 32GB DRAM DDR4 2,400Mbps Zynq UltraScale+ MPSoC M2M & Zynq UltraScale+ MPSoC

    150G Interlaken100G MACPCIe Gen4 AMS ( ) System Monitor ( ) MPSoC Zynq UltraScale+ MPSoC (PMU) ( ) PMU

    5 16nm Zynq UltraScale+ MPSoC

    10 Xcell Journal 90

  • C O V E R S T O R Y

    Myron 16nm 1 Zynq UltraScale+ MPSoC 28nm Zynq SoC 5 1

    16nm Zynq UltraScale+ MPSoC Zynq UltraScale+ MPSoC 1 3 ( 6) 1080p 1 Zynq SoC H.264 ASSP Zynq UltraScale+ MPSoC

    1 Zynq UltraScale+ MPSoC 4K x2K UHD 2 5 1 SoC Sumit Shah 1 Zynq SoC 2 ASSP 1 Zynq UltraScale+ MPSoC 47% 2.5 1 4.8 Shah 2 28nm Zynq SoC 1 Zynq UltraScale+ MPSoC

    2 2.5 50% 1 5 UltraScale+ 2015 2 UltraScale+ 2015 4 16nm UltraScale 1 http://japan.xilinx.com/ultrascale Zynq UltraScale+ MPSoC http://japan.xilinx.com/products/technology/ultrascale-mpsoc.html

    6 Zynq UltraScale+ MPSoC 16nm 28nm Zynq SoC 1 5

    http://japan.xilinx.com/ 11

  • X C E L L E N C E I N A E R O S P A C E

    Solar Orbiter Will Process Data Onboard Using Xilinx FPGAs

    Tobias Lange Design EngineerBraunschweig University of Technology (Germany), Institute of Computer and Network Engineering (IDA) [email protected]

    Holger Michel Design EngineerBraunschweig University of Technology, IDA

    Bjrn Fiethe Senior EngineerBraunschweig University of Technology, IDA

    Harald Michalik Professor Braunschweig University of Technology, IDA

    FPGA

    12 Xcell Journal 90

  • X C E L L E N C E I N A E R O S P A C E

    1 2017 (PHI) (MPS) PHI SRAM FPGA FPGA Venus Express (VMC) Dawn (DawnFC) FPGA PHI 2 Virtex-4 FPGA FPGA FPGA PHI

    PHI PHI (

    Virtex FPGA

    http://japan.xilinx.com/ 13

  • X C E L L E N C E I N A E R O S P A C E

    ) (RTE) ( ) 3.2 100 64 1 PHI 2 ( 1) 2 Virtex FPGA ( 1 ) 2,048 x 2,048

    PHI 2 50MHz GR712 LEON3-FT ASIC CPU 2 SDRAM FPGA 1 NOR

    FPGA NAND 2 Virtex-4 FPGA RTE ( 1 ) RTE RTE FPGA

    1 (PHI)

    FPGA Conguration:

    FPGA Conguration: Acquisition Processing

    100 Mbit/setDetector14 bit/px10 fps

    OnlineImage

    Accumulation

    Storagein FlashMemory

    OfinePreprocessing

    OfineRTE

    Inversion

    Bit DepthReduction

    &Data

    Compr.

    Spacecraft590 Mbit/s 3.2 Gbit/min 3.2 Gbit/min355 Mbit

    3.2 Gbit/min

    2 PHI

    PowerSupply

    SpacecraftSpW I/Fs ISS Sensors &

    Actuators

    DetectorsCmd & HK

    Fast ImageMemory Buer

    JTAG

    JTAG

    Memory Bus Data

    Data

    Red Interface

    Main Interface

    LEON3-FTProcessor ASIC

    (GR712)System Controller

    Radiation-HardenedFPGA

    Conguration Controller,System Supervisor,

    NAND-Flash Controller

    Main Memory

    CongurationMemory

    NonvolatileImage Data Storage

    (Flash Memroy)

    Image Stabilization

    RTE Inversion

    Data AcquisitionDetector

    Image Data

    Red Interface

    Preprocessing

    14 Xcell Journal 90

  • X C E L L E N C E I N A E R O S P A C E

    RTE 2 Virtex-4QV FPGA 2 FPGA LEON3 2 Virtex-4 FPGA FPGA I/O FPGA 2 JTAG 2 Virtex-4

    3

    NAND 4 FPGA NAND NAND FPGA FPGA 2 Virtex-4 FPGA NAND

    Virtex-4QV FPGA

    2 SRAM FPGA 1 SRAM ( ) ( )

    http://japan.xilinx.com/ 15

  • X C E L L E N C E I N A E R O S P A C E

    Virtex-4QV Virtex-4 FPGA BGA Virtex-4QV

    Virtex-4QV 2012 Virtex-4QV CF1140

    4 PHI

    (TMR) (EDAC) FPGA TMR

    16 Xcell Journal 90

  • X C E L L E N C E I N A E R O S P A C E

    6 CF1140 3 ( 3) X PCB ( )

    Virtex-4 20cm x 20cm 550g (NAND ) 15W 2 Virtex FPGA 4 Virtex-4 2 FPGA 23 Zynq-7000 All Programmable SoC SRAM FPGA 1 SoC

    Xcell journal PR

    Xcell Journal

    9,000

    Web iPad

    Xcell Journal E-mail

    [email protected]

    Get on Target

    http://japan.xilinx.com/ 17

  • X C E L L E N C E I N W I R E L E S S

    60G Millimeter-Wave Backhaul Link Is Poised to Boost Cellular Capacity

    John Kilpatrick Consulting EngineerAnalog Devices [email protected]

    Robbie Shergill Strategic Applications ManagerAnalog Devices [email protected]

    Manish Sinha Product Marketing ManagerXilinx, Inc. [email protected]

    60GHz

    18 Xcell Journal 90

  • X C E L L E N C E I N W I R E L E S S

    2030 5,000 [1] 5 20 50 5GHz 5GHz 60GHz 6GHz 9GHz 60GHz ( Analog Devices ) Hittite Microwave 60GHz ( 1) Analog Devices 1 2 ( ) Tx ( ) Rx (DPLL ) FPGA SoC 500MHz QPSK 256QAM

    Zynq SoC 60GHz

    http://japan.xilinx.com/ 19

  • X C E L L E N C E I N W I R E L E S S

    3.5Gbps (FDD) (TDD) LDPC

    28nm Zynq-7000 All Programmable SoC Kintex-7 FPGA 2 Zynq SoC

    (SyncE) (LDPC) (FEC) FEC LPDC FEC FEC LDPC FPGA SNR LDPC (GUI) 1 3.5Gbps IP 440MHz ADC DAC 5 (GT) 10GbE CPRI GT

    (PS) (PL) ARM Cortex -A9 I/O (SoC) 2 PHY XPIC PL PL DAC/ADC SerDes I/O IP (ACM) ( ) (DPD) RF

    1

    20 Xcell Journal 90

  • X C E L L E N C E I N W I R E L E S S

    2014 Analog Devices 2 (SiGe) 60GHz HMC6300 57GHz 66GHz 250MHz 64QAM 16dBm IF RF

    2 All Programmable SoC

    SPI PLL/VCO 3 HMC6300 1.8GHz MSK DAC 1.8Gbps HMC6301

    P1dB -20dBmIIP3 -9dBm 6dB 57GHz 66GHz 64QAM ( )IF RF 4 HMC6301 / (OOK) AM FM FM MSK

    http://japan.xilinx.com/ 21

  • X C E L L E N C E I N W I R E L E S S

    3 HMC630060GHz IC

    4 HMC630160GHz IC

    QPSK QAM IQ HMC6300 HMC6301 4 x 6mm BGA HMC6300BG46 HMC6301BG46 2015

    / 5 FPGA AD9234 12 1 / ADCAD9144 16 2.8GSPS ( / ) Tx-DACHMC7044

    (ADC IC DAC IC ) JESD204B

    Analog Devices KC705 (ADCDAC 2 FMC ) FPGA

    22 Xcell Journal 90

  • X C E L L E N C E I N W I R E L E S S

    ( 6) PC RF KC705 WBM256 IP Kintex-7 XC7K325T-2FFG900C FPGA KC705 FMC 60GHz MMPX

    SMA 250MHz 1.1Gbps

    FFPGA OEM FPGA 7 FPGA/SoC

    IP FPGA SoC GT / 3.5Gbps IC Analog Devices Analog Devices IC Analog Devices

    1. Evolutionary and Disruptive Visions Towards Ultra High Capacity Net-works, IWPC, April 2014

    5 Analog Devices IC

    6

    http://japan.xilinx.com/ 23

  • MACsec IP

    X C E L L E N C E I N D AT A C E N T E R S

    MACsec IP Improves Data Center Security

    Paul Dillien ConsultantHigh Tech Marketing [email protected]

    Tom Kean, PhDManaging DirectorAlgotronix Ltd. [email protected]

    24 Xcell Journal 90

  • X C E L L E N C E I N D A T A C E N T E R S

    IT IT 1 FPGA MACsec Algotronix FPGA IP ( ) FPGA

    2 IPsec IEEE 802.1AE ( MACsec)

    MACsec IP Improves Data Center Security FPGA

    http://japan.xilinx.com/ 25

  • X C E L L E N C E I N D A T A C E N T E R S

    Algotronix IP (Algotronix MACsec IPsec IP MACsec IPsec IP )MACsec

    MACsec 3/4

    3 IPsec 2 3 MACsec MACsec (DOS)

    MACsec MACsec FPGA MACsec FPGA Algotronix AES-GCM MACsec 1G10G 40G Artix Kintex Virtex FPGA Virtex UltraScale 100G FPGA IP 10GbE ( ) (40G 100G ) MACsec MAC ( 1 )FPGA

    IPsec MACsec LAN MACsec LAN LAN MACsec (SecY) SecY MACsec 1G LAN 1 MAC MACsec SecY MACsec IEEE 801.1X-2010 Internet Key Exchange (IKE) IKE 2

    1 MACsec IP FPGA

    26 Xcell Journal 90

  • X C E L L E N C E I N D A T A C E N T E R S

    IT 1 FPGA FPGA Algotronix S-Box FPGA RAM (LUT) 2 MACsec RAM RAM S-Box BRAM LUT S-Box

    MACsec MACsec CAM

    MACsec

    AES-GCM MACsec MACsec MACsec 128 128 10 ( ) MACsec 256 256 14 MACsec MACsec MACsec MACsec (MAC) MACsec 1G MACsec MAC (TEMAC) MACsec IPsec MACsec MACsec 2

    MACsec 3 MAC Security TAG (SecTAG) SecTAG EtherType ICV ICV ( MACsec ) FPGA MACsec LUT RAM FPGA 128 256 SecY MACsec 1 MACsec MACsec CAM (Secure Channel Identifier) 1 SecY MAC

    http://japan.xilinx.com/ 27

  • X C E L L E N C E I N D A T A C E N T E R S

    IEEE 802.1AE

    2 MACsec 1 10 IP Kintex Virtex FPGA 10Gbps IP MACsec MACsec FPGA

    Algotronix HDL

    2

    LAN MACsec SecY A B MACsec ( 4 ) MACsec

    3 MACsec MAC Security TAG (SecTAG) EtherType

    28 Xcell Journal 90

  • X C E L L E N C E I N D A T A C E N T E R S

    / FPGA

    ModelSim MACsec MACsec IP

    SecY IP 10G MACsec 6,638 20,916 LUT53 BRAM Algotronix FPGA Algo-tronix MACsec

    4 MACsec

    http://japan.xilinx.com/ 29

  • X C E L L E N C E I N D AT A C E N T E R S

    Simplify Your Hot Testing with Xilinxs Zynq SoC

    Lei Guan Member of Technical StaffBell Laboratories, Alcatel Lucent Ireland [email protected]

    Zynq SoC

    30 Xcell Journal 90

  • X C E L L E N C E I N D A T A C E N T E R S

    2 1 (10Gbps) 1 1 2 Alcatel Lucent Ireland Zynq 7000 All Programmable SoC IP ( )

    Simplify Your Hot Testing with Xilinxs Zynq SoC Zynq SoC IP

    http://japan.xilinx.com/ 31

  • X C E L L E N C E I N D A T A C E N T E R S

    XFP 10Gbps IR ZC706 ZC706 Zynq-7000 SoC XC7Z045 ( 2) GTX 10Gbps Zynq SoC ARM (PS) Kintex-7 FPGA (PL) PL 10Gbps / PS Finisar

    FPGA GTX XFP 1 ISE Design Suite 3 1 CORE Generator IBERT IBERT 7 GTX (ChipScope Pro) IBERT IBERT (P pin location = H9N pin location = G9 200MHz ) GTX QUAD 111 Max Rate = 10Gbps GTX Refclk = 156.25 MHz Refclk source = MGTREFCLK1 111

    XFP FDB-1022 10Gbps XFP SMA SMA 1/64 ( 156.25 MHz = 10GHz/64)

    7 FPGA Integrated Bit Error Ratio (IBERT) Zynq SoC GTX (MMCM)

    1

    32 Xcell Journal 90

  • X C E L L E N C E I N D A T A C E N T E R S

    2 CORE Generator MMCM CORE Generator Clocking Wizard

    (200MHz) 50% 156.25MHz MMCM 2 (RESET LOCKED) 3

    ISE Design Suite 14.4 Vivado Design Suite ISE IBERT (example_ibert_gtx.vhdibert_ gtx_top.ucfibert_core.ngcicon_zynq.ngc) ISE MMCM ( 2) mmcm_core.vhd ISE example_ ibert_gtx.vhd mmcm_core 3 (CLK_ OUTPUT_PCLK_OUTPUT_NLED_REFCLK) ibert_gtx_top.ucf

    .bit FPGA 10Gbps XFP 2 ( 1 )ChipScope Pro .bit IBERT ( 2 )Clk 2x (1010.) PRBS ( ) ZC706 1 XFP [email protected]

    2 ChipScope Pro

    http://japan.xilinx.com/ 33

  • X P L A N AT I O N : F P G A 1 0 1

    A Double-Barreled Way to Get the Most from Your Zynq SoC

    Adam P. Taylor Chief Engineer, Electrical Systems e2v [email protected]

    2 Zynq SoC Zynq SoC 2 ARM A9

    34 Xcell Journal 90

  • X P L A N A N T I O N : F P G A 1 0 1

    Zynq-7000 All Program-mable SoC 1 2 ARM Cortex -A9 Zynq SoC (PS) 2 ARM 1 1 /RTOS 2 Linux HMI

    2 ( ) 2 (AMP) Zynq SoC 2 Zynq SoC AMP

    0 1

    0 1 ( )

    0 1

    Zynq SoC AMP ARM 2 L1 ( ) I/O Interrupt Controller Distributor (ICD)L2 DDR ( 1 ) PS 1 ARM DDR

    AMP Zynq SoC AMP 2 XAPP1079 AMP (FSBL) OS ZIP 2 (FSBL OS) SRC design FSBL OS (SDK) SDK

    http://japan.xilinx.com/ 35

  • X P L A N A N T I O N : F P G A 1 0 1

    SDK SDK [Xilinx tools] [repositories] [new] < >\app1079\design\work\sdk_repo ( 2 )

    AMP Zynq SoC 4

    OCM (SCU) ( AXI ACP ) SCU SCU OCM SCU low SCU OCM

    256 SRAM

    (SCU)

    AXI ACP ( ) SCU

    AXI

    (OCM)

    OCM

    OCM

    Zynq-7000 AP SoC

    Processing SystemApplication Processor Unit

    High-Performance Ports

    Notes;1) Arrow direction shows control (master to slave)2) Data flows in both directions: AXI 32bit/64bit, AXI 64bit, AXI 32bit, APB 32bit, Custom

    Programmable Logic

    EMIO General-PurposePorts

    DMASync

    IRQXADC12 bit ADC

    ConfigAES/SHA

    SelectIOResources

    ACP

    DAP

    DevC

    CoreSightComponents

    MemoryInterfaces

    IRQ

    OCMInterconnect

    256KSRAM

    512 KB L2 Cache & Controller

    Snoop Controller, AWDT, TimerGIC

    32 KBI-Cache

    32 KBD-Cache

    MMUARM Cortex-A9

    CPU

    FPU and NEON Engine

    32 KBI-Cache

    32 KBD-Cache

    MMUARM Cortex-A9

    CPU

    FPU and NEON EngineSWDT

    TTC

    SystemLevel

    ControlRegs

    DMA 8Channel

    ResetClockGeneration

    I/OPeripherals

    SRAWNOR

    ONFI 1.0NANDQ-SPICTRL

    2x USB

    2x GigE

    2x SD

    MIO

    MemoryInterfaces

    USB

    USB

    GigEGigESD

    SDIOSD

    SDIOGPIOUARTUARTCANCANI2CI2CSPISPI

    CentralInterconnect

    DDR2/3. 3LLPDDR2

    Controller

    Programmable Logic to MemoryInterconnect

    1 Zynq SoC (PS)

    36 Xcell Journal 90

  • X P L A N A N T I O N : F P G A 1 0 1

    OCM 128 PS 4 64 3 64 64 ( 5)

    I/O OCM Xil_IO.h CPU 8 /16 /32 char /short

    2

    /int

    2

    ( )

    ( C )

    Xil_Out8(0xFFFF0000,0x55);read_char = Xil_In8(0xFFFF0000);

    #define LED_PAT 0xFFFF0000

    #define LED_OP (*(volatile unsigned int *)(0xFFFF0000))

    http://japan.xilinx.com/ 37

  • X P L A N A N T I O N : F P G A 1 0 1

    (Generic Interrupt Controller) Xcell Journal 87 34P

    Zynq SoC xscugic.h XScuGic_SoftwareIntr

    AMP 3

    1 I/O

    Zynq SoC 16 1

    AMP (FSBL) 0 1 SDK FSBL [file new application project] AMP FSBL FSBL [Zynq FSBL for AMP] ( 3 )AMP FSBL 1 0 0 BSP ( 4 ) DDR

    3 AMP

    XScuGic_SoftwareIntr(, , )

    38 Xcell Journal 90

  • X P L A N A N T I O N : F P G A 1 0 1

    5 DDR DDR 0 1

    0 0 AMP

    0 0 1 0 6 1 1 0 Set Event (SEV) 1 1 1 BSP PS OS (standalone_amp 7 ) 0 BSP CPU 1 1 BSP 1 BSP BSP DUSE_ AMP=1 1 1 1 BSP 1 DDR 0 1 0 1 4 0 BSP

    5 0 DDR

    http://japan.xilinx.com/ 39

  • X P L A N A N T I O N : F P G A 1 0 1

    2

    AMP FSBL ELF

    0 ELF

    1 ELF

    AMP Zynq

    BIT

    Zynq SoC .bin BIN BIF BIF BIN SDK

    create Zynq ISE Design Suite ( \design\work\bootgen ) XAPP1079 BAT BIF cpu1_bootvec.bin cpu1_bootvec.bin FSBL FSBL BIN 3 ELF bootgen BIF ELF ( 8 ) ISE bootgen boot-gen createboot.bat 9 boot.bin

    #include #include xil_io.h#include xil_mmu.h#include xil_exception.h|#include xpseudo_asm.h>#include xscugic.h>

    #define sev() _asm_(sev)#define CPU1STARTADR 0xfffffff0#define COMM_VAL (*(volatile unsigned long *)(0xFFFF0000))

    int main(){

    //Disable cache on OCM Xil_SetT1bAttributes(0FFFF0000,0x14de2); // s=b1 TEX=b100 AP=bll, Domain=bllll, C=b0, B=b0 Xil_Out32(CPU1STARTADR, 0x00200000); dmb(); //waits until write has finished sev();

    6

    7 1 BSP

    40 Xcell Journal 90

  • X P L A N A N T I O N : F P G A 1 0 1

    Zynq SoC Zynq SoC Zynq SoC 2 DDR

    the_ROM_image{

    [bootloader] amp_fsbl.elf download.bit amp_cpu0.elf app_cpu1.elf

    //write start vector address 0xFFFFFFF0 with 0xFFFFFFF00 //This load address triggers fsbl to continue [load = 0xFFFFFFF0] cpu1_bootvec.bin}

    8 BIF

    9 Zynq SoC boot.bin

    Get Published

    japan.xilinx.com/xcell/

    Xcell Publications ?

    Xcell

    Xcell Publication Mike Santarini ([email protected])

    http://japan.xilinx.com/ 41

  • X P L A N AT I O N : F P G A 1 0 1

    How to Port PetaLinux Onto Your Xilinx FPGA

    Sweta Postgraduate Student, Department of Telecommunication PES Institute of Technology, Bangalore, India [email protected]

    Srikanth Chintala Research Engineer, Satellite and Wireless Group Centre for Development of Telematics (C-DOT), Bangalore, India [email protected]

    Manikandan J Professor and Domain Head, Signal Processing DomainDepartment of Electronics and Communication (EC) andProfessor, Crucible of Research and Innovation (CORI) PES University, Bangalore, India [email protected]

    FPGA PetaLinux

    42 Xcell Journal 90

  • FPGA PetaLinux

    X P L A N A T I O N : F P G A 1 0 1

    FPGA 1 / FPGA PetaLinux OS PetaLinux MicroBlaze CPU ARM FPGA PetaLinux PES C-DOT Kintex-7 XC7K325T FPGA KC705 PetaLinux PetaLinux

    PetaLinux FPGA OS FPGA OS PetaLinux Clinux Xilkernel Clinux Linux Linux Linux OS (MMU) [1]Clinux Xilkernel Clinux [2] PetaLinux FPGA (SoC) Linux PetaLinux Linux PetaLinux (SDK) [3] ( ) PetaLinux FPGA FPGA

    http://japan.xilinx.com/ 43

  • X P L A N A T I O N : F P G A 1 0 1

    Xilkernel Clinux [4]PetaLinux Xilkernel [5] PetaLinux PetaLinux 1 Telnet ( ) FPGA

    PetaLinux PetaLinux 12.12 Kintex-7 (BSP) PetaLinux SDK /opt/Petalinux-v12.12-final

    PetaLinux SDK .xilinx .Petalogix SDK

    PetaLinux PetaLinux /opt/PetaLinux-v12.12-final BSP BSP ( ) Quick Emulator (QEMU) BSP /opt bsp KC705 BSP ZIP

    PetaLinux 2 1 Linux PetaLinux ( 1 ) 2 GUI ( 2 )Linux PetaLinux PetaLinux OS GUI PetaLinux SDK PetaLinux SDK PetaLinux Eclipse SDK PetaLinux GUI ( 2) GUI PetaLinux

    Kintex-7 FPGA KC705 RS232 FPGA JTAG PetaLinux SDK Xilinx Platform Studio (XPS) [6,7] (SDK) [7]

    1 Linux

    @ cd /[email protected] cd /opt/[email protected] tar zxf PetaLinux-v12.12-final-full.tar.gz

    @ cd /opt/PetaLinux-v12.12-final @ source settings.sh

    @ echo $PETALINUX

    @ cd /opt/[email protected] source [email protected] source /opt/Xilinx/14.4/ISE_DS/[email protected] PetaLinux-install-bsp /bsp/Xilinx-KC705 -v12.12-final.bsp

    44 Xcell Journal 90

  • X P L A N A T I O N : F P G A 1 0 1

    XPS Base System Builder (BSB) MicroBlaze BSB

    2 PetaLinux SDK

    8 115,200bps RS232 UARTLED

    3 FPGA

    http://japan.xilinx.com/ 45

  • X P L A N A T I O N : F P G A 1 0 1

    data2mem system.bitsystem_bd.bmmfsboot.elf FPGA download.bit 1 PetaLinux OS MicroBlaze

    PetaLinux

    c CPU ( MicroBlaze )v ( Xilinx)p ( KC705) PetaLinux ( /opt/PetaLinuxv12.12/software/PetaLinux-dist/vendors/Xilinx/KC705) PetaLinux-copy-autoconfig Xilinx-KC705.dtsxparameters.hconfig.mk

    ( 3)MicroBlaze PetaLinux MMU CPU XPS microblaze_0 MMU Linux 3 XPS FPGA FPGA XPS system.bit system_ bd.bmm SDK SDK system.xml SDK [Xilinx Tools] [Repository] [New] SDK PetaLinux PetaLinux $PetaLinux/Hardware/edk_user_repository [File] [Board support package] [PetaLinux] PetaLinux BSP PetaLinux BSP BSP (fs-boot) BSP SDK fsboot.elf

    4

    $ cd/opt/PetaLinuxv12.12$ PetaLinux-new-platform c v p

    46 Xcell Journal 90

  • X P L A N A T I O N : F P G A 1 0 1

    GUI ([PetaLinux SDK] [Kernel Configuration])Linux Linux

    [Kernel Configuration] ( 4 ) / (UIO) UIO PetaLinux C C++ [8] Makefile PetaLinux GUI ([File] [PetaLinux New Application]) Linux

    gpio-dev-mem-test gpio-uio-test GUI PetaLinux ( 2 ) Linux make

    OS

    PetaLinux PetaLinux MicroBlaze RAM (fs-boot) fs-boot.elf

    U-Boot (Universal Bootloader) (U-Boot fs-boot )fs-boot U-Boot U-Boot DDR3 JTAG Quick Emulator (QEMU) QEMU PetaLinux OS / [9]3 JTAG FPGA JTAG FPGA [Xilinx Tool] [Program the FPGA] download.bit GUI ([PetaLinux SDK] [BOOT JTAG [Linux]]) ( 2 )Linux

    U-Boot PetaLinux GUI ([PetaLinux SDK] [BOOT JTAG [U-Boot]]) JTAG U-Boot

    6 U-Boot FPGA XPS U-Boot IP U-Boot IP

    (PC) (KC705 ) IP netboot

    $ cd /opt/PetaLinux_v12.12$ PetaLinux-config-kernel

    $ cd /opt/PetaLinux_v12.12$ PetaLinux-config-apps

    $ cd $PETALINUX/software/ PetaLinux-dist$ make

    $ cd/opt/PetaLinux_v12.12/software/ PetaLinux-dist$ PetaLinux-jtag-boot -i images/image.elf

    $ cd $PETALINUX/software/ PetaLinux-dist$ PetaLinux-jtag-boot -i images/u-boot.elf

    u-boot>print serverip // prints 192.168.25.45(server ip)u-boot>print ipaddr // prints IP address of the board as // 192.168.25.68u-boot>set serverip // Host IP 192.168.25.68u-boot>set serverip 192.168.25.68

    http://japan.xilinx.com/ 47

  • X P L A N A T I O N : F P G A 1 0 1

    PetaLinux

    netboot PetaLinux ( 5 )GUI ([PetaLinux SDK] [BOOT QEMU [Linux]]) QEMU

    7

    6 U-Boot (Universal Bootloader)

    PetaLinux Peta-Linux MicroBlaze Kintex-7 FPGA (*.dts) DDR3 /dev/mem GPIO UIO GPIO 4

    1. DDR3 DDR3-test.c PetaLinux DDR3 DDR3 DDR3 SDRAM DDR3 (0xC0000000) (0xC7FFFFFF) 512 Linux DDR3 DDR3 Linux DDR3

    DDR3-test g

    $ cd $ PETALINUX/software/ PetaLinux-dist$ PetaLinux-qemu-boot -i images/image.elf

    7 QEMU PetaLinux

    #DDR3-test g 0xc7000000 o 15

    5 OS PetaLinux

    u-boot> run netboot

    $ cd $ PETALINUX/software/ PetaLinux-dist$ PetaLinux-qemu-boot -i images/image.elf

    48 Xcell Journal 90

  • UIO UIO CompatibilityLED GPIO GPIO UIO [email protected] [email protected] PetaLinux UIO GPIO UIO

    UIO /sys/ class/uio/uioX UIO GPIO LED

    gpio-uio-test d o 255 UIO GPIO GPIO LED

    4. ( PC KC705 ) TFTP (Trivial File Transfer Protocol) TFTP PC /tftpboot test Hello World ( 8 )

    KC705 PetaLinux get (-g)

    X P L A N A T I O N : F P G A 1 0 1

    DDR3 o 15 DDR3 0xc7000000 DDR3

    15 DDR3

    2. /dev/mem GPIO gpio-dev-mem-test.c PetaLinux I/O (GPIO) 8 LED GPIO /dev/mem mmap() LED GPIO 0x40000000 0x4fffffff GPIO (GPIO_DATA) (GPIO_TRI_ OFFSET) 2 GPIO 1 ( GPIO_TRI_OFFSET=1) GPIO 0 PetaLinux GPIO

    gpio-dev-mem-test g GPIO o 255 (LED ) GPIO LED

    3. UIO GPIO GPIO / (UIO) gpio-uio-test.c PetaLinux UIO GPIO 8 LED GPIO UIO /dev/uioX UIO GPIO /dev/uioX sys/class/uio/ui0 mmap()

    #DDR3-test g 0xc7000000 i

    #gpio-dev-mem-test g 0x40000000 o 255

    # ls /sys/class/uio/ uio0 uio1 uio2

    @ echo Hello World > /tftpboot/[email protected] more /tftpboot/test

    # cd /sys/class/uio/uioX# gpio-uio-test -d /dev/uio1 -o 255

    http://japan.xilinx.com/ 49

  • X P L A N A T I O N : F P G A 1 0 1

    test ( 9 ) 9 more

    PetaLinux OS test1 PetaLinux put (-p) ( 10 )

    test1 11 FPGA Peta-Linux

    1. Kynan Fraser, MicroBlaze Running uClinux, Advanced Computer Architecture from http://www.cse.unsw.edu.au/~cs4211

    2. Xilkernel Version 3.0 (Xilinx Inc., 2006 12 )

    3.PetaLinux SDK (UG976) (Xilinx Inc., 2013 4 )

    4. Gokhan Ugurel and Cuneyt F. Bazlamacci, Context Switch-ing Time and Memory Footprint Comparison of Xilkernel and C/OS-II on MicroBlaze, 7th International Conferenceon Electrical and Electronics Engineering, December 2011, Bursa, Turkey, pp.52-55

    5. Chenxin Zhang, Kleves Lamaj, Monthadar Al Jaberi and Praveen Mayakar, Damn Small Network Attached Stor-age (NAS), Project Report, Advanced Embedded Systems Course, Lunds Tekniska Hogskola, November 2008

    6.Platform Studio (UG113) (Version 1.0) (Xilinx Inc., 2004 3 )

    7.EDK : (UG683) (Version 14.1) (Xilinx Inc., 2012 4 )

    8.PetaLinux SDK : (UG981) (Xilinx Inc., 2013 4 )

    9.PetaLinux SDK : QEMU (UG982) (Xilinx Inc., 2013 11 )

    # tftp -r test1 -p 192.168.25.68

    10

    11

    9

    8

    # tftp -r test -g 192.168.25.68 # ls a

    50 Xcell Journal 90

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  • Vivado HLS

    X P L A N AT I O N : F P G A 1 0 1

    Try Algorithm Refactoring to Generate an Efficient Processing Pipeline with Vivado HLS

    Shaoyi ChengPhD Candidate University of California, Berkeley [email protected]

    52 Xcell Journal 90

  • X P L A N A N T I O N : F P G A 1 0 1

    Vivado

    Design Suite (HLS) C FPGA DMA ( ) Vivado HLS ( )

    Vivado HLS Vivado HLS ( ) (CDFG) CDFG CPU

    http://japan.xilinx.com/ 53

  • X P L A N A N T I O N : F P G A 1 0 1

    1(a) curInd 2(a)

    ( )

    / 1 1 1 FIFO 1(b)

    FPGA RAM (naively)HLS 2(b) ( )

    float foo (float* x, float* product, Int* Ind){ float curProd = I.0; for(Int I=0; I

  • X P L A N A N T I O N : F P G A 1 0 1

    2(c) FIFO

    2 : (a) (b) (c)

    CDFG 3 1 Vivado HLS CDFG

    FIFO 2 2

    float foo (float* x, float* product, Int* Ind){ float curProd = I.0; for(Int I=0; I

  • X P L A N A N T I O N : F P G A 1 0 1

    Vivado HLS ( ) 1 ( ) (SCC) ( ) 2 3 ( ) SCC 3 1

    HLS C FIFO IP 1

    HLS C x[curInd] curInd FIFO C FIFO

    FIFO FIFO Vivado HLS FIFO FIFO Verilog Vivado HLS

    FIFO FIFO FPGA FIFO

    3

    float foo (float* x, float* product, Int* Ind){ float curProd = I.0; for(Int I=0; I

  • X P L A N A N T I O N : F P G A 1 0 1

    4

    i Product[i]

    3 1

    AXI C C

    23 (DPP) HLS (Nave) Nave DPP Vivado HLS 150MHz ACP HP 64 ZedBoard Zynq-7000 XC7Z020 All Programmable SoC Zynq SoC ARM DMA

    for (w = 1; w oprion1? 1:0;}

    5

    http://japan.xilinx.com/ 57

  • X P L A N A N T I O N : F P G A 1 0 1

    1 : 4 opt_without w n opt 5 (DPP) HLS (Nave) ARM n ( ) 40 w ( ) 100 3,200 Vivado HLS Zynq SoC ARM

    Vivado HLS ARM

    ( 4.5 )DPP

    2 : (SpMV)

    7

    6

    for(s =0; s

  • X P L A N A N T I O N : F P G A 1 0 1

    SpMV Vivado HLS 6 CSR (Compressed Sparse Row) 7 1/16 32 2,048 FPGA 64 DPP 2

    DPP

    3 : - - 2 DMA 2 40 160 3 1 ( 2 ) 3 DPP FPGA

    9 -

    8 -

    for(k=0; k

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    () TEL (03) 5792-8210 [email protected]() TEL (045) 477-2001 [email protected] 2015 Xilinx, Inc. All rights reserved. ARMEUARM Limited

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  • Xilinx IntroducesVivado Design Suite UltraFast

    UltraFast

    : japan.xilinx.com/ultrafast

    () TEL (03) 5792-8210 [email protected]() TEL (045) 477-2001 [email protected] 2015 Xilinx, Inc. All rights reserved.