LC vertex detector technology options

July 14 2003 C Damerell LC technologies Cornell U

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LC vertex detector technology options

Chris Damerell

The transition from microstrips to pixels, for vertex detectors

Detector requirements

Detector architectures

•CCDs

•Monolithic APS (including FAPS)

•DEPFET

•Hybrid APS

•SOI-inspired

RF pickup suppression

Correlated double sampling

The route to convergence

Synergy with other science


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• Since late’70s, successful vertex detectors (for heavy flavour tagging) were mainly based on silicon microstrips

• Interesting paradigm shift is under way. Within 5 years, will mostly be based on silicon pixels

• Why is this?

• highest performance b and charm tagging in dense track environments has come from a series of pixel-based detectors, NA32 in ’80s, SLD in ’90s

• extreme radiation environments in the inferno close to IP at future hadron colliders

• high track density in core of jets at future e+e- colliders

• The disparate requirements at hadron and e+e- colliders have very different solutions, and are supported by contrasting R&D programmes

• The transition to pixels implies valuable synergies for other areas of science, where images taken with IR, visible, UV, X-rays benefit from the technologies being developed for HEP vertex detectors, and vice versa


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Of course, it will definitely be silicon pixels at the LC, or will it?


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Detector requirements

• Most were mentioned in LCFI talk: concentric barrels, thinnest possible layers, micron-level precision and stability

• Budget of inactive material (eg in endcaps) is also extremely important

• With ~109 channels, suppression of noise and pickup may be decisive


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• Historically, some vertex detectors have diminished the capability of their experiments for leading edge physics:

• the possible top signal at 40 GeV in UA1 (early ’80s)

• the possible Higgs signal in LEP (late 90’s)

• Success at the LC should not be taken for granted.

• Rbp could strike again …

• Intensive R&D in several technologies will surely be justified (cost effective) in terms of LC physics reach

• This is an area in which there is a distinct technical advantage (hence enhanced physics potential) wrt the inferno at the heart of LHC


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Detector architectures


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•MAPS

•‘Standard CMOS process’ so signal charge is collected from undepleted bulk or epitaxial layer

•However this isn’t obligatory – early S Parker developments with 300 µm fully depleted devices were highly successful

•Early results have been based on few mm2 devices and minimal in-pixel logic

•Recently, using 0.35 µm CMOS, increasing functionality is being implemented at the periphery of the chip by the Strasbourg group

•Flexible active pixel idea (Renato Turchetta at RAL) could lead the way to a TESLA-compatible architecture


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•DEPFET

•Based on detector-grade high resistivity silicon, fully depleted

•Requirement of supporting CMOS chips on 2 sides may be a significant limitation

•Has advantage (wrt current MAPS) of fast CDS, given promise of pulsed clear of entire signal charge after each row readout, so equivalent noise performance and pickup suppression to CCD option

•HAPS (incl new SoI-inspired)

•Read 1 in N pixels, by analogy with capacitive charge division in strip detectors

•Resolution tends to be somewhat unstable

•Implications for 2-track resolution?

•SoI approach could reduce material, but looks pretty complex (?)


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MIMOSA-5

Strasbourg group


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• MIMOSA-6 incorporates ‘rolling shutter’ CDS in pixel

• device size 3.6x0.84 mm: plan to extend to ‘sideways’ columns on ladder

•Discriminators, but not yet ADCs or data sparsification, on chip periphery


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• FAPS could be extended to a full 20 samples per train, stored in pixel

• Again, limited to ‘rolling shutter’ CDS

• Idea is to relax the requirement for fast, precise, signal transmission to chip periphery during train, and so render long columns feasible, with all processing logic out of the detector active volume, as for the CCD architecture

FAPS

RAL group


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MOS transistor instead of JFET

A pixel size of ca. 20 x 20 µm² is achievable using 3µm minimum feature size.

DEPFET

Bonn/Munich group


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• thin detector-area down to 50µm• frame for mechanical stability carries readout- and steering-chips

first thinned samples:

[L.Andricek, MPI Munich]

steering chips

readout chips

520 x 4000 pixelDEPFET-Matrix

(25 x 25 µm pixel)

readout chips

matrix is read out row-wise


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DEPFET pixel matrix

- Read filled cells of a row- Clear the internal gates of the row - Read empty cells

Low power consumption

Fast random access to specific array regions


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Hybrid Pixel Detector with Interleaved Pixels

Charge carriers generated underneath one of the interleaved pixel cells induce a signal on the capacitively coupled read-out pixels, leading to

a spatial accuracy improvement by a proper signal interpolation.

p+

n

PolyresistorInterleaved pixelReadout pixelreadout pitch = n x pixel pitch

Large enough to house the

VLSI front-end cell

Small enough for an effective

sampling

HAPS

Insubria/Krakow group


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Charge Sharing Studies – Resolution

• Resolution:– Interleaved pixels (efficient charge

sharing): 3 m

parameterization allows a coordinate reconstruction and resolution measurement

function Average resolution Resolution vs. spot position


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SOI Imager – Main Concept

Detector handlable wafer– High resistivity– 300 m thick

Electronics active layer

– Low resistivity– 1.5 m thick– Readout pixels (min

charge sharing): 10 m

Detector: conventional p+-n, DC-coupled

Electronics: preliminary solution – conventional bulk MOS technology on the thick SOI substrate

Insubria/Krakow group


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RF pickup suppression

• Beam-associated RF radiation penetrating the beam-pipe (even 0.25 mm Be) is presumably negligible (provided it isn’t CF as tried in UA1)

• However, flanges, BPM cables, etc can permit RF radiation to leak out

• SLD experience:

• analogue signals stored securely in CCD buried channel

• Digital logic (PLL in optical links) was disrupted – fortunately could be restored within some s of end of bunch train)

• NLC/JLC:

• could envisage similar settling/restoration before readout

• TESLA:

• need to read detector repeatedly during train, to internal storage of sparsified data

• each internal frame readout spans ~150 BX, so electronics is hit repeatedly by whatever RF is present

• For SLD VTX, this would have been fatal

• As part of the verification procedure of any prototype ladder, suggest testing in a final focus lab where machine bunches are simulated by current pulses down wires in the ‘beam-pipe’, and all other FF equipment is in and running – needed as part of the GAN


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Correlated double sampling?

• CDS is the term invented circa 1972 for the form of pedestal subtraction used to suppress reset noise in CCD front-end circuits

• Simplest CDS involves:

Reset***measure V-out***transfer signal charge***re-measure V-out

Used to reduce the system noise from tens of e- to ~1 e- by suppressing the fluctuations in post-reset V-out

• DEPFET shares robust CDS capability with CCD, in LC application:

read pedestal+signal***reset – ie remove signal Q***read pedestal alone

• However, MAPS CDS involves subtraction over full frame period of 50 s or whatever

• could in principle be resolved by incorporating 1-pixel CCD, or DEPFET structure, within the CMOS pixel

• CDS with = 50 s?

• SLD was OK in inter-train period with 200 s CDS sampling period

• might get away with it at NLC, after some settling time

• might not work at TESLA due to RF activity within train


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Extended row filter, SLD


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Effectiveness of ERF in suppressing ‘noise’ hits (including pickup in operational conditions)


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Route to convergence

Preferred technology(ies) to be selected on basis of full-size, fully operational prototype ladders (around 2010?)

Choice probably time dependent: what can be ready for startup could well be superseded later[eg at SLC: silicon microstrips were replaced by CCDs in 1990]

Convenient access to IR is an essential requirement (for the entire inner detector system) R&D groups should resist pressure from funding agencies to ‘pick the winner’

Premature choice of technology could seriously degrade the physics potential

Good world-wide communication is building a proto-collaboration for the VTX (eg phone conference at time of Arlington LC workshop)


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Construction, commissioning, operation and physics

•When choice is made, some groups (technically oriented) will prefer to develop ‘their technology’ for other applications or possible upgrades

Others (particle physics oriented) will wish to contribute to the construction of the first detector(s)

The detector construction should be encouraged as a world-wide endeavour, in spirit of GDN

SLD ladders (via UPS)

SanJose SLAC e2V Brunel SLAC Yale MIT SLAC Make mbds Test mbds Fit CCDs Mech QC Functional test Fit blocks Opt survey Intstall • Exploration of this ‘new continent’ is at an early stage: don’t jump to premature conclusions


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Synergy with other science

• Pixel detectors are uniquely inter-disciplinary

• Example from ‘fall of the wall’ in structural biology (J Hajdu, TESLA colloquium)

• 120 Hz frame rate needed at LCLS (with 14 bit dynamic range)

• SNAP (600 Mpixels), XEUS, biological cell imaging, …

• Fast Gigapixel-scale imaging systems are widely needed, and the LC vertex detector community is making a strong contribution to their development

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LC vertex detector technology options