p Logic Devices

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Why programmable logic?

Programmable logic technologies

Read-Only Memory (ROM)

Programmable Logic Array (PLA)

Programmable Array Logic (PAL)

Examples of using programmable logic


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Facts:

It is most economical to produce an IC in large volumes

Many designs required only small volumes of ICs

Need an IC that can be: Produced in large volumes

Handle many designs required in small volumes

A programmable logic part can be:

Made in large volumes Programmed to implement large numbers of different

low-volume designs


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Many programmable logic devices are field- programmable, i. e.,

can be programmed outside of the manufacturing environment

Most programmable logic devices are erasable and

reprogrammable.

Allows updating a device or correction of errors

Allows reuse the device for a different design - the ultimate in re-usability!

Ideal for course laboratories

Programmable logic devices can be used to prototype design that

will be implemented for sale in regular ICs.

Complete Intel Pentium designs were actually prototype with specialized

systems based on large numbers of VLSI programmable devices!


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Read Only Memory(ROM) - a fixed array of ANDgates and a programmable array of OR gates

Programmable Array Logic (PAL) - aprogrammable array of AND gates feeding a fixedarray of OR gates.

Programmable Logic Array(PLA) - aprogrammable array of AND gates feeding aprogrammable array of OR gates.

Complex Programmable Logic Device (CPLD)/Field- Programmable Gate Array(FPGA) -complex enough to be called architectures


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ROM, PAL and PLA Configurations

(a) Programmable read-only memory (PROM)

InputsFixed

AND array(decoder)

ProgrammableOR array

OutputsProgrammableConnections

(b) Programmable array logic (PAL) device

Inputs ProgrammableAND array

FixedOR array

OutputsProgrammable

Connections

(c) Programmable logic array (PLA) device

Inputs ProgrammableOR array

OutputsProgrammable

Connections

Programmable

ConnectionsProgrammable

AND array


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Chapter 3 - Part 2 6

Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines) The fixed "AND" array is a

decoder with 3 inputs and 8

outputs implementing minterms.

The programmable "ORarray uses a single line to

represent all inputs to an

OR gate. An X in the

array corresponds to attaching the

minterm to the OR

Read Example: For input (A2, A1, A0)

= 001, output is (F3,F2,F1,F0 ) = 0011.

Read Only Memory Example

D7D6

D5D4D3D2D1D0

A2

A1

A0

A

B

C

F0F1F2F3

X XX

X

X

X

X

X

X

X


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What are functions F3, F

2, F

1and F

0in terms of (A

2, A

1, A

0)?

F3 = D7 + D5 + D2 = A2A0 + A2A1A0

F2 = D7 + D0 = A2A1A0 + A2A1A0

F1 = D4 + D1 = A2 A1A0 + A2A1A0 F0 = D7 + D5 + D1 = A2A0 + A1A0

Read Only Memory Example

D7D6

D5D4D3D2D1D0

A2

A1

A0

A

B

C

F0F1F2F3

X XX

X

X

X

X

X

X

X


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Programmable AND array

Fixed OR array

Each output line permanently connected to a

specific set of product terms

Number of switching functions that can be

implemented with PAL are more limited than

PROM and PLA


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The PAL is the opposite of the ROM, having a programmableset of ANDs combined with fixed ORs.

Disadvantage ROM guaranteed to implement any M functions of N

inputs. PAL may have too few inputs to the OR gates.

Advantages For given internal complexity, a PAL can have larger N and M

Some PALs have outputs that can be complemented, adding POSfunctions

No multilevel circuit implementations in ROM (without externalconnections from output to input). PAL hasoutputs from OR terms as internal inputs to all ANDterms, making implementation of multi-level circuits easier.


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Programmable Array Logic Example

4-input, 4-output PALwith fixed, 3-input OR

terms

What are the equations

for F1 through F3?F1 = +

F2 = B + AC + A

F3 = AD + BD + F1

= AD + BD + +

0 91 2 3 4 5 6 7 8

AND gates inputs

0 9

Productterm

1

2

3

4

5

6

7

8

9

10

11

12

F1

F2

F3

F4

I3=C

I2=B

I1=A

1 2 3 4 5 6 7 8

I = D4

X X

X X

XX X

X X

X

X

X

XX

X

X X

X

X X

B CA

A C B

B CA


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PAL Implications

Number of product terms per output >

number of product terms in each sum-of-

product expression

No sharing of product terms between outputs


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Programmable Logic Array (PLA)

Compared to a ROM and a PAL, a PLA is the most flexiblehaving a programmable set of ANDs combined with aprogrammable set of ORs.

Advantages A PLA can have large N and M permitting implementation of

equations that are impractical for a ROM (because of the number

of inputs, N, required) A PLA has all of its product terms connectable to all outputs,

overcoming the problem of the limited inputs to the PAL ORs

Some PLAs have outputs that can be complemented, adding POSfunctions

Disadvantage Often, the product term count limits the application of a PLA.

Two-level multiple-output optimization reduces the number ofproduct terms in an implementation, helping to fit it into a PLA.


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Programmable Logic Array

13

kAND

gatesm OR gates

k X m links m outputs

n inputs n x k links

n x k links

n x k x m PLA has 2n x k + k x m links

Sum of products

Programmable AND array + programmable OR array


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Programmable Logic Array Example

3-input, 2-output PLAwith 4 product terms

F1

= AB +BC + AC

F2= (AB + AB) = AB + AB

Fuse intact

Fuse blown

1

F1

F2

X

A

B

C

C C B B A A 0

1

2

3

4X

XX

X X

X

X

X

X

X

X

X

X

X A B

A C

B C

A B

X


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55:032 - Introduction to Digital Design Page 15

PAL Logic Implementation

Programmed PAL:

4 product terms per each OR gate

Minimized Functions:

W = A + B D + B CX = B CY = B + CZ = A B C D + B C D + A D + B C D

A B C D

A B C D

ABD

BC

0

0

0

0

B

C

0

0

BC

BCD

AD

BCD

W X Y Z


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Programmable Logic Array

Finite number of AND gates => simplify

function to minimum number of product

terms

Number of literals in a product term is not

important since we have all the input variables

Sharing of product terms between outputs =>

multiple-output minimization


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PALs and PLAsWhat is difference between Programmable Array Logic (PAL) and

Programmable Logic Array (PLA)?

PAL concept implemented by Monolithic MemoriesAND array is programmable, OR array is fixed at fabrication

A given column of the OR arrayhas access to only a subset of

the possible product terms

PLA concept Both AND and OR arrays are programmable


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PALs and PLAs

Of the two organizations the PLA is the mostflexible

One PLA can implement a huge range of logic

functions BUT many pins; large package, higher cost

PALs are more restricted / you trade numberof OR terms vs number of outputs

Many device variations needed

Each device is cheaper than a PLA


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PLD (Programmable Logic Device)

All layers already exist

Designers can purchase an IC

Connections on the IC are either created or destroyed

to implement desired functionality Field-Programmable Gate Array (FPGA) very popular

Benefits

Low NRE costs, almost instant IC availability

Drawbacks Bigger, expensive (perhaps $30 per unit), power

hungry, slower


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PLD Definition

Programmable Logic Device (PLD):

An integrated circuit chip that can be configured

by end use to implement different digital

hardware Also known as Field Programmable Logic Device

(FPLD)


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PLD Advantages

Short design time

Less expensive at low

volume

Volume

Nonrecurring engineering cost

PLD

ASIC


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CPLD Logic Block

Simple PLD

Inputs

Product-term array

Product term allocation function

Macro-cells (registers)

Logic blocks executes sum-of-product expressions and stores

the results in micro-cell registers

Programmable interconnects route signals to and from logic

blocks


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Major CPLD Resources

Number of macro-cells per logic block

Number of inputs from programmable

interconnect to logic block

Number of product terms in logic block


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Structure of FPGA (Xilinx)

Logic Block

I/O Block

Interconnect


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