THE CHALLENGES OF NON WET OPEN BGA SOLDER DEFECT

Dudi Amir, Satyajit Walwadkar, Srinivasa Aravamudhan, and Lilia May Intel Corporation

Hillsboro, OR. USA dudi.amir@intel.com

ABSTRACT There is an increase in the incidences of a SMT non-wet type of solder joint defect where the BGA ball does not solder to the printed circuit board (PCB) land. This defect is called Non Wet Open (NWO) and is a new phenomenon found during surface mount assembly reflow process. This defect is hard to detect with conventional inspection techniques and is sometimes misconstrued as a pad wetting issue or no paste printed. This paper will report on the NWO defect in Flip Chip Ball Grid Array (FCBGA) packages observed after surface mount assembly. A previous study has described the formation mechanism of the non-wet defect [1]. This paper will define the NWO and describe the critical SMT assembly factors that can influence SMT yield. Results from the surface mount assembly processes, such as printing and reflow, as well as materials, that are affecting NWO defect formation will be shared in the following paper. Further, the paper will provide guidelines for a SMT engineer on how to mitigate the defect during surface mount assembly and optimize the SMT process for high yields. Finally, the paper will compare the NWO to the well known head on pillow defect. INTRODUCTION Over the last few years the trend in the mobile electronics products industry has been moving toward thinner and larger component form factors with thinner board and system designs. Demand for thinner systems is driving FCBGA package height down by using thinner package substrate and smaller solder balls. Demand for more features and increased functionality is calling for larger packages with larger silicon die. Also, environmentally friendly manufacturing is driving the use of Lead Free, RoHS Compliant SMT material and processes, which increased the processing temperatures of the component and board assemblies. All of these trends increase the challenges of board assembly. One of these challenges is the reduction in solder joint yields due to the increase in the occurrence of SMT Non Wet Open (NWO) solder joint defects. This defect is known by many other names such as non wet, lifted ball, hanging ball, ball on pad and ball on land. They all refer to the same phenomenon that is defined as a joint that is comprised of one metallurgical mass formed from the BGA ball and reflowed solder paste or flux with incomplete or no coalescence to the PCB pad. In most

cases there is no evidence of solder on the PCB lands. Figure 1 (a) shows a typical optical side view image of a non wet open defect and figure 1 (b) displays a cross section image of the defect.

(a) (b)

Figure 1. NWO defect As seen in Figure 1, the BGA ball is sitting on the PCB land with no physical connection between them. Figure 1 (a) shows the brownish color of the Cu/OSP PCB land and dry flux at the bottom of the solder ball as it will be seen through a microscope. This defect signature of NWO could be a result of different formation modes such as clogged stencil aperture that leaves little or no paste on the PCB land, interference between top and bottom packages during package on package (PoP) assembly, contamination on PCB land and interaction between dynamic warpage and paste adhesion. This paper will address the NWO defect as a result of dynamic warpage and paste adhesion where sufficient paste was printed on the PCB land. It will explain NWO defect in FCBGA packages caused by these modulators and describe the critical SMT assembly factors that can impact SMT yield. Additionally it will provide tools to evaluate the SMT process for a NWO risk, and give guidelines for a robust solder joint formation with an optimized SMT process and materials that can overcome the NWO and result in acceptable SMT yields. NON WET OPEN (NWO) DEFECT FORMATION A description of the NWO defect formation can be found in more details in a previous study [1]. It shows a typical SMT reflow profile with the different stages of NWO defect formation. As the BGA on the PCB enters the reflow soldering oven, its temperature increases, and flux in the solder paste starts to activate. Due to a mismatch between coefficients of thermal expansion (CTE) in materials within FCBGA packages, solder and PCB, the FCBGA solder balls lift off from the paste [1]. Figure 2 shows the initiation of the NWO defect formation. As the

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package and the solder paste start to move away from each other due to the dynamic warpage, two scenarios could occur depending on the type of paste formulation used. Figure 2(c) shows a scenario where there is a separation of the package ball from the printed paste. During reflow at high temperature the package will collapse and the solder ball will coalesce with the molten paste. Figure 2(b) shows another scenario where the paste is separated from the PCB land and lifted with the package solder ball.

Figure 2. NWO defect formation The path described in scenario 2(b), where the paste is lifted from the PCB land, will cause a NWO defect. At reflow the paste will melt into the package solder ball and when the package collapses during cool down, solder ball will sit on the PCB land causing a NWO defect. A video visualization method was used to look at the defect formation at real time. A part was placed on a printed board and reflowed.

(a) (b) (c)

Figure 3. NWO defect formation pre-reflow Figure 3 shows still images from this video of one corner joint of an FCBGA package. The FCBGA is placed on the printed solder paste as seen in Figure 3(a). It has a convex shape and the package solder balls in contact with the printed solder paste. As the board enters the reflow, it starts heating up, as temperature increases the package starts to change to concave shape causing the solder paste to stretch and lift up from the PCB land [Figure 3 (b)]. The paste lifting process will continue as the temperature increases until solder melting ocuurs [Figure 3 (c)]. The paste lift as shown in Figure 3(b) occurs in pre-reflow zone at temperatures below the melting point of the solder paste and the BGA ball around 150 to 190 ºC. At this temperature range, when the defect is initiated, the dynamic warpage of the package is only about 40-70% of the maximum dynamic warpage that the package will experience at the peak reflow temperature. Figure 4 shows an image of a corner edge of FCBGA. This unit was artificially bent to create a large gap during reflow between the PCB and the package. It clearly shows how

the solder paste is adhering to the package solder balls leaving the PCB land with no solder paste.

Figure 4. Lifted solder paste

At reflow the paste that was adhering to the package solder ball starts to melt and coalesces with the melted ball to produce unified solder mass in form of a large solder ball. Figure 5(a) shows the beginning stage of melting when the solder paste is detaching from the PCB land and start wetting to the FCBGA ball. Figure 5(b) shows the developing stage of the defect where the solder paste is completely lifted from PCB pad and melting with solder ball. Figure 5 (c) shows the image where the solder paste has melted with the solder ball forming a large solder ball. This event is fairly quick and takes about 8 to 15 seconds depending on the paste type and reflow conditions.

(a) (b) (c)

Figure 5. NWO defect formation at reflow The package collapse time is very important and is determined by the time it takes to melt the inner ball. If complete collapse happened during stage (a) or (b) in Figure 5, then a good joint can be formed since the flux will still be active and can reduce the oxides from the PCB land. However, if the collapse is delayed, the PCB land is exposed to high reflow temperature and grows more oxide. The paste and flux do not wet to the oxidized land, but instead coalesce with the ball. When the package collapses the package solder ball will just rest on the PCB land creating a NWO solder joint defect with no electrical continuity. IMPACT OF SOLDER PASTE PROPERTIES ON NWO DEFECTS FORMATION In order to investigate the impact of solder paste formulation on the NWO defect, four solder pastes from two different suppliers (A and B) were used. To determine the impact of halogen content on SMT performance of solder pastes, pastes with both halogenated (H) and zero halogen (ZH) fluxes were selected for testing. Table 1 summarizes information on chosen solder pastes. Table 1. Solder Paste Information

Solder Paste Supplier

Solder Paste Designation

Flux Type

A1 H A

A2 ZH

B B1 ZH

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Activity Wetting balance techniques are usually used to evaluate solderability of solder materials to the surface of interest through wetting force and time measurements. High wetting force and short wetting time are desired characteristics of a good soldering material. In case of solder pastes, wettability of solder paste to PCB land and BGA ball is dependent on activity of flux within the solder paste. In this paper, activity of the flux is defined as the ability/strength of flux to clean metal-oxides (e.g., SnO, SnO2, CuO and etc…) from the surface of PCB lands and BGA balls. Reduction of the oxides promotes wettability and thus improves solderability of solder paste to PCB land and solder ball on the package resulting in good solder joint. NWO defect mechanism depicted in Figure 1(b) suggests that wettability of solder paste to PCB land is poor. In order to explore this theory, Rhesca Solder Checker SAT-5100* was used to collect solder paste wetting force and time data using a Cu wire. Copper wire was chosen to mimic Cu/OSP surface finish of PCB lands with which majority of NWO defects have been observed with some solder pastes. Details of experimental setup and procedure are described in the paper by Kondrachova et. al. [1]. Figure 6 shows plot of average wetting force vs. wetting time for solder pastes A1, A2 and B1. When these solder pastes were tested using 1:1 pad to stencil aperture size ratio printing condition in SMT assembly of package B (see Table 3 for package details) onto PCBs with OSP surface finish, resulted unit level SMT yield of 100%, 100% and 10% for solder pastes A1, A2 and B1, correspondingly. Extremely low SMT yield recorded with solder paste B1 was due to formation of NWO solder joint defects.

Figure 6. Plot of averaged wetting force vs. wetting time measurements Data in Figure 6 indicates that solder pastes with high wetting force and short wetting time to the PCB surface finish of interest are good candidates for eliminating NWO defects. These results point out to much higher/stronger Cu-oxide cleaning activity of fluxes in solder pastes A1 and A2 in comparison to paste B1. Additionally, extremely short wetting times observed for solder pastes A1 and A2 suggest that these pastes have faster flux activation rates and possibly longer flux activity life during solder paste heating cycle than paste B1. Finally, halogen content is not an important factor for selecting solder pastes since both halogenated and zero-halogen pastes (A1 and A2) demonstrate comparable performance. Overall, selection of activators that are more

aggressive toward oxides on PCB lands rather than oxides on BGA balls might help reduce formation of NWOs. Tackiness Solder paste flux undergoes drastic changes during the heating stage of the reflow profile due to evaporation, decomposition and chemical transformation of its numerous chemical components. As a result of these changes, the solder paste physical properties are irreversibly altered. NWO formation mechanism suggests that tackiness or ability of paste to stick/adhere and maintain contact between PCB land and BGA ball might also play important role in mitigation of this defect. To elucidate impact of temperature on tackiness and correlate change in tackiness to SMT performance of solder pastes, IPC Solder Paste Tack Test 2.4.44 method [2] was used to set test conditions and perform variable temperature data collection employing Malcom TK-1 Tackiness Tester*. Figure 7(a) shows IPC tackiness data collected at different temperatures (25, 50 and 100 ºC) for solder pastes A1, A2 and B1. On average tackiness values for pastes A1 and A2 did not significant change with increase in temperature which implies good thermal stability of flux vehicle within these solder pastes. In contrast, tackiness of solder paste B1 dropped substantially as temperature increased from 25 to 100 ºC. Based on these results one would expect solder pastes A1 and A2 to maintain good adhesion to the surfaces of both PCB lands and BGA balls at elevated temperatures. However, under the same conditions paste B1 would dry out and adhere to the surface to which it has higher propensity to wet. The wetting force data discussed above indicates that the paste will not wet to Cu lands of PCB substrates.

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Figure 7. (a) Plot of tackiness data for different solder pastes as a function of selected temperatures. (b) Plot of average SMT yield % vs absolute rate of tack change Plotting SMT yield vs rate of tack force change at temperatures from 25 to 100 ºC allows one to recognize effect of tackiness on occurrence rate of NWO defects. Data in Figure 7(b) clearly illustrates that thermally stable flux formulations in solder pastes A1 and A2 excel at elimination of solder joint defects producing 100% SMT yield. On the other hand, solder paste B1with the rate of tack change more than three times higher than the rates calculated for pastes A1 and A2 results in SMT yield of only 10%. In general, SMT yield can be improved through use of solder paste with low rate of tack change which means selection of flux components resistant to degradation at elevated temperatures. Paste Bake Screening Test In a previous study on mechanism of NWO defect formation [1], a bake test, also known as paste bake test, was identified as solder paste screening test for NWO defects. Summary of procedure for the paste bake test is shown in Figure 8. According to test conditions, paste printed on PCB, and FCBGA is placed on the board [Figure 8(a)]. PCB/BGA sandwich is moved to a stand-along baking oven [Figure 8(b)] and baked for 6 min at 180 ºC. The FCBGA is pulled off the board after cooling down to room temperature [Figure 8(c),(d)] and the PCB land is being inspected under microscope. Good solder paste candidate will result in ≥ 70% of PCB lands retaining paste deposits.

(a) (b) (c) (d)

Figure 8. Paste bake test Conversely, bad paste would have solder paste prints completely lifted off PCB lands with BGA balls for majority of BGA footprint. Figure 9 shows a number of bare cooper PCB lands which failed the test by completely lifting solder paste off the lands.

Figure 9. Paste bake test inspection image In order understand the effect of bake conditions on test results, different bake temperatures were selected for further testing. Figure 10(a) displays heating profiles for the chosen bake conditions acquired through thermo-couples attached to PCB/BGA sandwich during the bake test. Note that parts never reach set temperatures of 140, 160 and 180 ºC. On average, parts spend around 3 out of 6 min at temperatures 20 ºC or less below the set temperature.

Figure 10. (a) Comparison of the paste bake test heating profiles (b) Plot of paste bake test yields collected under different heating conditions Paste bake test yield (number of PCB lands that retained paste deposits divided by the total number of lands and multiplied by 100) results for solder pastes A2 and B1 under various bake condition are shown in Figure 10(b). Pastes A2 and B1 were selected for this type of testing

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because both materials are contain zero halogens yet demonstrate drastically different performance during SMT assembly (100 vs 10 % SMT yield for A2 vs B1solder paste). Interestingly, bake yield data in Figure 10(b) illustrates completely different trend for each solder paste. Paste A2 clearly shows temperature and time dependence of bake response whereas data for paste B1 implies no such dependency. For paste A2 bake yield increases with increase in bake temperature and time. However, bake yield stays practically the same for paste B1. The differences in results come from the fact that both solder paste have significantly different flux activation temperatures toward Cu/CuO cleaning. From wetting balance results explained above we know that paste A2 has much more aggressive CuO activator package than B1. Figure 10(b) data suggests that paste A2 has high activation temperature since yield improves as temperature increases (higher number of PCB lands retain solder paste deposits). Because data at 160 ºC shows bake time impact on the yield, one might propose that paste A2 activates around 160 ºC. This paste might be nearly inert toward Cu-oxide cleaning until it gets to ~160 ºC, and when paste activates, bake yield improves due to enhanced adhesion/wetting of paste to Cu/OSP PCB lands. As to solder paste B1, the clear conclusion is harder to reach because activity of this solder paste is so weak with respect to CuO. This paste might have much lower activation temperature than paste A2, yet the activator package is primarily designed to clean Sn-oxides, so bake results show more PCB lands where paste got lifted off with BGA balls. This data highlights the impact that paste bake test conditions might have on the results and thus on selection of solder paste candidates for SMT assembly. Additionally, it once more emphasizes the difference between different paste suppliers’ flux formulations even if halogen levels are the same. Tape in Cavity Screening Test This test was designed to simulate package gap during reflow by introducing a tape with controlled thickness (~ 50 um greater than the ball size) to create a gap during reflow. The paste that was in contact with the FCBGA balls at room temperature will be either lifted up with the ball or stay on the PCB pad, depending on the solder paste formulation. The tape under the cavity comes into contact with the PCB at reflow and restricts the solder ball from touching the PCB pads after package collapse. This experiment is done on the SMT line using high volume manufacturing process. After SMT, the packages are pulled from the PCB and the number of NWO defects are counted and compared between different paste formulations.

Tape

PCB

Substrate

Die

Tape

(a) (b) Figure 11. Tape in cavity test

Figure 11(a) shows a bottom view of the FCBGA and the tape location in the cavity. Figure 11(b) shows a cross section view of a mounted package with a tape in cavity. An experiment was done with two solder paste formulations. The data are summarized in Figure 12.

Figure 12. Tape in cavity test results The data shown in the table indicates a different magnitude between the two types of paste in the number of NWO defects found after reflow. It also indicates that using an overprint stencil will reduce the test sensitivity to NWO defect.

(a) (b)

Figure 13. Defects after reflow Figure 13 shows a side view of two packages mounted using two different solder pastes after tape in cavity test. Figure 13 (a) shows the NWO defects produced by paste B1 where all the paste is lifted away from the pads, while Figure 13 (b) shows Head On Pillow (HoP) generated by paste A1where the solder paste did not adhere to solder balls. The data shown from this test can indicate sensitivity of the solder paste for NWO defect and can help assess the risk of NWO from a particular paste formulation in the SMT process. IMPACT OF SMT PROCESS PARAMETERS ON NWO DEFECTS In order to understand the role played by SMT process parameters on formation of NWO defects, several designed experiments were performed to quantify the impact, and results are shared in the following section. Two different BGA packages were used for the evaluation and are referred to as Package A and Package B in this publication. Differences between these BGA packages are summarized in Table 2 below.

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Package Attributes Package A Package B Package Size 31x24mm 32x37.5mm Minimum Pitch 0.65mm 0.7mm BGA Ball Size 16mil 17mil Corner Pad Size 15mil 16mil

Table 2. Package Attributes BGA packages were assembled on to a test board with a dimension of 142.24 mm x 160.02 mm (5.6inch x 6.3inch), and thickness of 1.02mm (0.040inch). Test board was made with halogen free laminate material and coated with organic solderability preservative (OSP) surface finish on Cu lands. SAC 305, type 4 solder pastes were printed onto the boards using DEK Galaxy* printing machine and the volume of solder paste deposits was measured by Koh Young KY-3030VAL*. After paste printing, packages were placed on test boards using the Genesis GSM* pick-and-place machine and transferred to the Furukawa Salamander* reflow oven for SMT assembly. Boards were reflowed in air using standard lead-free reflow profile. After SMT, boards were pulled to inspect for NWO defects. NWO defect rate was calculated at unit level and at joint level. Paste Volume To understand the role played by paste volume for NWO defects, designed experiments were performed with two BGA packages. Package with high warpage was used to force failure with smaller sample size. Except for solder paste, the rest of the SMT factors were held constant. The Majority of FCBGA packages warp with a concave shape at reflow temperature. At Room temperature package is in convex shape and as the temperature increases the package shape changes from convex to concave as shown in Figure 14. As the package warps away from the PCB, corners of the FCBGA are at high risk for open defects (HoP, HoP-Open and NWO). Risk at corner joints can be mitigated by increasing solder paste volume at the corners joints. Stencil openings can be designed to mimic package warpage shape (i.e., more solder paste volume at corners area and less solder paste volume at interior area). Additional solder paste volume provides margin to overcome open defects.

Figure 14. FCBGA warpage shape FCBGA stencil openings are designed based on the BGA pad sizes. Most of the time, stencil openings follow 1:1 design (PCB pad size = stencil opening) and this type of design do not provide margin for thinner FCBGA packages. To overcome the risk associated with FCBGA increased solder paste volume is added in risk area. Examples of two stencil designs used in the evaluation that provides additional paste volume at the package corners are shown in Figure 15.

(a) (b) Figure 15. (a) Square over-print stencil design. (b) Additional over-print stencil design Results from designed experiment (Table 3) show that for the evaluated solder pastes and package types, increasing the paste volume in the risk area reduces the NWO defect rate.

Package Type 

DOE Leg

Solder Paste

Normalized Paste Volume

@ Corner Pads

SMT Qty

NWO Defect Rate

1 B2 1.0x 25 96%

(24/25)A

2 B2 1.6x 25 8%

(2/25)

3 B1 1.6x 20 95%

(19/20)

4 B1 2.7x 20 80%

(16/20)B

5 B1 4.8x 20 55%

(11/20)Table 3. Paste volume impact to NWO defect rate Results highlights that additional paste volume provides significant margin against NWO defects. Additional paste helps to

Maintain the contact between solder ball and solder paste when the package/PCB separates during the reflow process

Increases the adhesion of solder paste to the PCB pads due to increase in the contact surface area which prevents lift off of the solder paste from the PCB pads during separation of the package balls from PCB

However paste volume alone cannot provide enough margin to completely overcome the NWO defect. As discussed in previous section solder paste formulations play a very critical role in modulating NWO defect formation. Reflow Parameters Detailed experiments were performed to understand the impact of reflow parameters to NWO defect with multiple solder pastes. Three solder pastes (see Table 1) and the following reflow parameters were evaluated in the experiment.

Peak Temperature Time Above Liquidus (≥ 220 oC) Soak Time Reflow Ambient (Air vs. N2)

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Data analysis indicated that only a single solder paste showed the impact of soak time to NWO among the three solder paste evaluated. Results from the experiments are shared below SOAK TIME To understand the impact of soak time on NWO defects, two reflow profiles with similar peak reflow temperature but with differences in soak time and time above liquidus (TAL) (as shown in Figure 16) were used for evaluation. Package B with 1.6x normalized paste volume at corner pads and B1 solder paste was used for the evaluation. Boards were assembled with packages of similar warpage in Air reflow.

Re

flow

Te

mp

era

ture

(d

eg

c)

Figure 16. Reflow profile comparison

Reflow Profile Attributes DOE

Leg Peak

Soak Time (150 to 200 o C)

TAL (≥ 220 o C)

SMT Qty

NWO Defect Rate

Joint Level NWO Defect Rate

Long soak

235 to

239

145 to 147

43 to 49

10 70%

(7/10) 0.25%

(34/13640)

Short soak

236 to

239 70 to 71

63 to 74

10 90%

(9/10) 1.15%

(157/13640)

Table 4. Reflow profile soak time results At unit level, long soak reflow profile show marginally improved results when compared to short soak reflow profile (70% defect rate vs. 90% defect rate). However, joint level failure rate showed significant reduction in defective joints (only 34 failing joints) for long soak profile when compared to short soak profile (157 failing joints). Figures 17 and 18 show the failure location map for short soak reflow profile and long soak reflow profile. Majority of the failures are observed at the corner and few interior joints.

Figure 17. Failure location map for short soak reflow profile

Figure 18. Failure location map for long soak reflow profile Improved performance of long soak time can be attributed to ability of solder paste to clean the copper oxide and adhere to PCB pads instead of the solder balls during board/package separation (due to availability of additional contact time between paste and pad). Shorter soak time experiments not provide the time needed by flux to clean the copper oxide.

Short Soak

Long Soak

REFLOW AMBIENT One of the other reflow parameter that may modulate NWO defect is reflow ambient. It is known that N2 reflow atmosphere provided significant margin for HoP joints [4] and a designed experiment was performed to evaluate the impact of N2 on NWO defect. Solder Paste B1 with high package warpage was used for the designed experiment.

DOE Leg

Reflow Ambient

SMT Qty NWO Defect Rate

Joint Level NWO Defect

Rate

1 Air 20 90%

(18/20) 2.8%

(458/16368)

2 N2 (≤ 500

PPM of O2)20

100% (0/20)

1.2% (200/16368)

Table 5. Reflow ambient designed experiment results Results from the designed experiment (Table 5) demonstrated that N2 reflow do not provide significant margin to mitigate NWO defects. Unit level SMT defect rates are comparable between Air and N2 reflow ambient. MULTIPLE REFLOW In motherboard assembly, BGA can be placed on primary or secondary side of the board and depending on the BGA location, the BGA lands might have experienced additional reflow can lead to PCB surface finish oxidation. To understand the impact of additional reflow of PCB surface finish to NWO defect, a designed experiment was performed with solder paste B1 and OSP surface finish. Results from the designed experiment are shown in Table 6. Table 6. OSP pre-condition results

DOE Leg

OSP Additional

Reflow SMT Qty

NWO Defect Rate

Joint Level NWO Defect

Rate

1 No 10 100%

(10/10) 0.79%

(108/13640)

2 Yes 10 100%

(10/10) 1.1%

(154/13640)

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Designed experiment results showed no significant impact of the additional reflow to NWO defect generation. Since OSP has poor wetting characteristics (when compared to other PCB surface finish) to being with, the additional reflow doesn’t significantly change the NWO defect generation. PCB SURFACE FINISH As shown in previous section, when the package starts to separate from the PCB, the solder paste adheres to either the PCB pads or BGA solder balls. PCB surface finish can have an impact on the adhesion force between the solder paste and PCB. To evaluate the impact of PCB surface finish onto NWO defect, a designed experiment was performed with 3 different surface finishes commonly used in the industry and solder paste B1(Table 7).

DOE Leg

PCB Surface Finish

SMT QtyNWO Defect Rate

Joint Level NWO Defect

Rate

1 OSP 20 90%

(18/20) 2.8%

(458/16368)

2 ImAg 20 70

(14/20) 0.3%

(45/16368)

3 LF HASL 20 100% (0/20)

3.0% (500/16368)

Table 7. PCB surface finish designed experiment results Designed experiment results showed that ImAg provided best margin to overcome NWO defects when compared to OSP and LF HASL surface finishes. ImAg surface finish provides better wetting surface finish when compared to OSP and this additional wetting can help the solder paste adhere with PCB pads instead of lifting it with the BGA balls. Surprisingly, LF-HASL surface finish did not provide any margin to overcome the NWO defects. Performance of LF HASL is comparable to OSP at unit and joint level yield. Based on the wettability of the surface finishes, LF HASL should be better when compared to OSP due to similarity in composition to SAC alloys in solder paste and BGA balls, yet the designed experiment results did not show a similar trend. Investigation to why LF HASL provided more defects is in progress. IMPACT OF BOARD WARPAGE ON NWO DEFECTS As the soldering process involves changes from room temperature to reflow temperature, understanding the warpage behavior of the PCB is important to insure good solder joint quality. PCBs consist of one or more layers of metal, bonded onto insulating substrates that are fabricated from the glass-fiber-reinforced thermosetting resin. There have been numerous attempts to reduce thermal warpage in PCB’s by balancing the copper amounts through layers placed on the opposite sides of the center core; however, warpage still continues to daunt the PCBs. PCB warpage can occurs in either a convex or a concave direction. The warpage will change the gap between the package and as a byproduct of this phenomenon different failure modes can arise in FCBGA packages depending on the directionality of the PCB

warpage as shown in Figure 19. To improve SMT yield the PCB warpage needs to be controlled (forcing board to stay flat). Pallets are typically used in industry to support the PCBs so that they remain relatively flat as the PCB goes through the SMT process.

Figure 19. PCB warpage shape and SMT defects

In order to study the impact of PCB warpage on the SMT yield and in particular to the NWO defect, a novel method was developed at Intel Corporation to consistently produce PCB warpage to understand the sensitivity of different solder paste material to SMT defects. With the help of fixtures, PCBs were put under constraints to exhibit convex and concave warpage as they go through the reflow oven as shown in Figure 20.

Figure 20. Convex & Concave fixtures for controlling PCB warpage. Due to interaction of package and PCB warpage shapes it was easy to generate defects during SMT using the fixtures. Validity of the fixtures was tested before using them for actual experiments. The validation was done by dialing different PCB warpage levels from low to high using 3 different set levels. The defect rate generated during SMT due to different PCB warpage were calculated by prying the components off the PCBs and counting number of defective joints in case of convex fixture and performing x-ray and cross-sectioning of the assembled PCBs in case of concave fixture. Figure 21(a) shows the plot of defect density obtained for different PCB warpage levels on convex fixture. It is observed that as the PCB warpage increases the solder joint defect density increases too. These results were used as a catalyst to establish PCB warpage cliff for solder paste sensitivity experiments to NWO defects. Figure 21 (b) shows solder joint height maps obtained through cross-section for different PCB warpage levels on concave fixture. It is observed that as the PCB warpage increases the solder

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joints at the package edges get compressed whereas those in the center get stretched. Solder bridging defect was observed at the package corners for highest level of concave PCB warpage.

Figure 21( a). Solder joint defect density as function of PCB warpage for convex fixture

Figure21(b). solder joint height maps for different level of PCB warpage for concave fixture Solder paste sensitivity between two different solder paste suppliers was tested by dialing fixed PCB warpage level of 113 microns using the convex fixture. Packages selected for this study had similar coplanarity at room temperature. All the printing, placement and reflow conditions were kept identical to avoid confounding effects. Figure 22 shows results obtained for both solder paste suppliers. Supplier A showed predominantly HoP-open defects whereas supplier B showed primarily NWO defects. For similar warpage level, it was observed that the defect mode can be changed from NWO to HoP by changing the paste material. This has served as a litmus test for selection of good vs bad solder paste material to solve paste lifting and NWO defect among different solder paste suppliers.

Figure 22. Solder Paste sensitivity test. PCB warpage was held constant Controlling PCB warpage using convex and concave fixtures has made it possible to evaluate the impact of warpage magnitude and shape on the formation of solder joint defects particularly NWO. Based on the above results it is clear that PCB warpage can impact SMT assembly yield and careful consideration needs to be given in industry to control this variable. COMPARISON BETWEEN HOP AND NWO DEFECTS This section will discuss the similarities and differences between the HoP and NWO defects. Figure 23 shows a typical reflow profile and the differences in the solder joint defects’ formation. Both of these defects occur on FCBGA packages when a gap is developed due to dynamic warpage induced by the reflow process. The main difference is that in HoP the gap exists between the paste and the FCBGA ball (Figure 23 top), while in NWO the gap exists between the printed solder paste and the PCB land. During reflow in case of HoP defect, the solder paste will melt on the PCB land and form an inter-metallic layer (Figure 23 top), while in case of NWO defect the solder paste will melt with the package ball and the PCB land will remain bare with no inter-metallic layer formed.

Figure 23. Formation of SMT defects An important observation to note is that the main mechanism of NWO is the lifting of the solder paste from the PCB lands. This stage occurs when the package

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dynamic warpage is fairly low. However HoP’s main mechanism is the ball to paste gap that exist during reflow when the dynamic warpage is at the highest point. NWO defect elimination becomes challenging if the paste formulation is not favorable. Increased paste volume has been shown to mitigate HoP defects [3], however, for the same package, the process window of solder volume to eliminate NWO will be much smaller than for HoP.

Figure 24. HoP and NWO process window Figure 24 shows the differences in solder paste volume working process window for HoP and NWO on the same package with comparable warpage level. The chart shows that the solder paste volume process window for NWO is much smaller. After the solder paste has been lifted from PCB pads, there is only a small window of opportunity to contact the PCB land in sufficient time, and create a good joint, before the solder paste is coalesces and consumed completely into the solder ball. Figure 25 illustrates the window of opportunity to create HoP and NWO. It is described with respect to the gap during reflow of a corner joint between the FCBGA ball and the paste or the PCB land.

Figure 25. Corner joint gap size during reflow The gap during reflow is represented by line A and the reflow profile by line B. Since the corner ball is touching the paste at room temperature, line A starts with zero gap that increases as the package is heated. L1 is the liquidus point when the package reaches the high temperature warpage. At this point the inner balls are melting and the package collapses. As a result, the gap is reduced. The flat

zone at the top of line 3 illustrates collapse time delay, or liquidus time delay [4]. It is the delay in collapse due to the outer balls melting first and inner balls melting last because of temperature gradient. The slope of the line indicates the rate of collapse. Both of these parameters are impacted by temperature delta and heat transfer efficiency to the center of the package. In Figure 25 the zone for HoP risk is starting at point t3. Even though there is contact between the ball and the paste in this zone, it does not have sufficient TAL to create a good joint. If the package gap is maintained behind point t4, as represented by package gap line 3, there will be no good joint form. In this case, the gap still exists at time of solidification and HoP opens where there is a visual gap after reflow is formed. The NWO window of opportunity to have a good joint is very small because the solder paste is lifted away from the pad at an early stage. In order to have a good joint, the gap needs to be closed as fast as possible before the solder paste on the ball will have sufficient time to merge with the ball. The window is shown in Figure 25 by points t1 and t2. A package that follows package gap line 1 will have a good joint. Because there is a small window of opportunity to create a good joint after solder paste was lifted, the impact of reflow parameters is very limited on NWO which was shown previously in the SMT process parameters impact section. If a package follows line 2 it will have an NWO, if the paste was lifted, however if a different solder paste formulation is used and the paste is not lifted, a good joint will be formed. An increase in ball oxidation by baking of FCBGA parts is known to increase the HoP defects [3]. Part bake has a different effect on NWOs: baking reduces NWO defects but can switch the defect mode to HoP, as shown in Table 8. Improved performance of baking to NWO can be attributed to reduction in the solder ball adhesion force due to increase oxide.

DOE Leg

Solder Paste

Bake SMT Qty

SMT Yield

# of Failing Joints

Comments

1 B1 No 10 0% (0/10)

3120 NWO failure mode

2 B1 Yes 10 33% (3/9)

12 HoP failure mode

Table 8. Bake impact on NWO Another important difference between NWO and HoP was found to be the defect detection. While HoP was known to have many defect escapes in electrical circuit test[5], the NWO defect usually fail in circuit test. The non wetted pad fails electrically even with pressure applied to it with the tester. The similarities and differences between the HoP and NWO defects discussed in this paper are summarized in Table 9.

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3. D. Amir, Raiyo Aspandiar, Scott Buttars, Wei Wei Chin, Paramjeet Gill, ‘Head-and-Pillow SMT failures modes, SMTAI proceeding, 2009

4. Chris Oliphant, et. Al. “Head and Pillow- a pain in the neck or solder defect” APEX proceeding, 2009

5. Vandervoort, et. al. ‘Head and Pillow defects in BGA sockets’ SMTAI proceeding ,2009

ACKNOWLEDGMENTS The authors would like to thank Wade Hezeltine for digital imaging of NWO, Jinlin Wang and Rajen Sidhu for tackiness and Rhesca testing support, Garrett Cogburn for paste bake test data collection and Suddho Nad for failure analysis.

Table 9. HoP and NWO comparison table CONCLUSION This paper discussed the NWO defect in FCBGA packages. It described the defect signature as a ball on the PCB land without the formation of IMC. It also explained the formation mechanism with printed solder paste lifted from the PCB land at an early stage of the reflow profile. It discussed the solder paste properties that can be identified as being sensitive to cause NWO defects like the activity of the flux and high temperature tackiness. The paper additionally proposed screening tests, like solder paste bake test or tape in cavity test to be able to rank different pastes with respect to the risk of NWO defect formation. The impacts of different SMT process parameters were presented, and the sensitivity to NWO was tested. It was found that increasing solder paste volume at the package corners reduces the NWO defect rate. The reflow parameters had low impact on the NWO failure rate and only one paste showed sensitivity to soak time. N2 environment did not show significant margin to mitigate NWO defects. The effect of PCB warpage was explored with a special design pallet that warped the PCBs to a known warpage values. NWO defects were produced with different degrees of PCB warpage indicating sensitivity to paste formulation. The paper offers a comparison summary between the HoP and the NWO defects. Although both defects are causing FCBGA open joints, there are differences in the formation of the defect and also in the way to reduce and eliminate the defects. Unlike HoP, when an NWO occurs there is a small process window to overcome the defect with increased paste print volume, and an even smaller opportunity to impact it with the reflow process. The only way to ensure there is no NWO defect is to ensure the solder paste used at SMT does not lift from the pad. REFERENCES 1. L. Kondrachova, S. Aravamudhan, R. Sidhu, D.

Amir, and R. Aspandiar, ‘Fundamentals of the Non-Wet Open BGA Solder Joint Defect Formation, ICSR Proceedings, 2012

2. Test Method 2.4.44, IPC-TM-650, Test Methods Manual, 1998

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