Ultrasound TX Pulser Evaluation Board User's Guideww1.microchip.com/downloads/en/DeviceDoc/20005656B.pdf · Ultrasound Transmit Pulser and the MD1730 8-Channel ±6V Low ... HV7321

2016 Microchip Technology Inc. DS20005656B

HV7321Ultrasound TX Pulser

Evaluation BoardUser’s Guide

DS20005656B-page 2 2016 Microchip Technology Inc.

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ISBN: 978-1-5224-1068-3

Object of Declaration: HV7321 Ultrasound TX Pulser Evaluation Board

2016 Microchip Technology Inc. DS20005656B-page 3

NOTES:


HV7321 ULTRASOUND TX PULSER

EVALUATION BOARD USER’S GUIDE

Table of Contents

Preface ........................................................................................................................... 7

Chapter 1. Product Overview1.1 Introduction ................................................................................................... 111.2 HV7321 IC – Description .............................................................................. 111.3 MD1730 IC – Description ............................................................................. 111.4 HV7321 Ultrasound TX Pulser Evaluation Board

– Features .............................................................................................. 121.5 HV7321 Ultrasound TX Pulser Evaluation Board and MUPB001

– Functional Description ......................................................................... 121.6 HV7321 Ultrasound TX Pulser Evaluation Board

– Technical Specifications ...................................................................... 141.7 Device Summary .......................................................................................... 141.8 What the HV7321 Ultrasound TX Pulser Evaluation Board Kit Includes ...... 14

Chapter 2. Installation and Operation2.1 Getting Started ............................................................................................. 152.2 Setup Procedure .......................................................................................... 152.3 Interface Connections .................................................................................. 172.4 Operating the HV7321 Ultrasound TX Pulser Evaluation Board .................. 192.5 Microchip Ultrasound Platform Board (MUPB001) ....................................... 20

Chapter 3. Software Description3.1 FPGA code Configuration ............................................................................ 233.2 Getting Started ............................................................................................. 233.3 MUPB001 – HV7321_MD1730 GUI Installation ........................................... 233.4 MUPB – HV7321_MD1730 GUI Description ................................................ 273.5 GUI Elements Specific to CW Mode-0 ......................................................... 323.6 GUI Elements Specific to CW Mode-1 ......................................................... 343.7 Configuring the Transmission of Signals Using the GUI .............................. 35

Chapter 4. PCB Design and Layout Notes4.1 PCB Layout Techniques for HV7321 & MD1730 Ultrasound Pulser ............ 41

Appendix A. Schematic & LayoutsA.1 Introduction .................................................................................................. 45A.2 ADM00659 – Schematic .............................................................................. 46A.3 ADM00659 – Top Copper and Silk .............................................................. 47A.4 ADM00659 – Top Copper ............................................................................ 47A.5 ADM00659 – Inner 1 – GND ........................................................................ 48A.6 ADM00659 – Inner 2 – PWR ....................................................................... 48A.7 ADM00659 – Bottom Copper ....................................................................... 49


HV7321 Ultrasound TX Pulser Evaluation Board User’s Guide

A.8 ADM00659 – Bottom Copper and Silk ......................................................... 49A.9 ADM00679 – Schematic (Connection) ......................................................... 50A.10 ADM00679 – Schematic (Power Supply) ................................................... 51A.11 ADM00679 – Schematic (USB to SPI) ....................................................... 52A.12 ADM00679 – Schematic (Programmable Clock) ....................................... 53A.13 ADM00679 – Schematic (FPGA) ............................................................... 54A.14 ADM00679 – Schematic (FPGA Decoupling Capacitors) .......................... 55A.15 ADM00679 – Schematic (Connectors) ...................................................... 56A.16 ADM00679 – Top Silk ................................................................................ 57A.17 ADM00679 – Top Copper and Silk ............................................................ 57A.18 ADM00679 – Top Copper .......................................................................... 58A.19 ADM00679 – Inner 1 .................................................................................. 58A.20 ADM00679 – Inner 2 .................................................................................. 59A.21 ADM00679 – Inner 3 .................................................................................. 59A.22 ADM00679 – Inner 4 .................................................................................. 60A.23 ADM00679 – Bottom Copper ..................................................................... 60A.24 ADM00679 – Bottom Copper and Silk ....................................................... 61A.25 ADM00679 – Bottom Silk ........................................................................... 61

Appendix B. Bill of Materials (BOM)

Appendix C. HV7321 Ultrasound TX Pulser Evaluation Board Typical WaveformsC.1 Board Typical Waveforms ............................................................................ 69

Worldwide Sales and Service .....................................................................................73




Preface

INTRODUCTION

This chapter contains general information that will be useful to know before using the HV7321 Ultrasound TX Pulser Evaluation Board. Items discussed in this chapter include:

• Document Layout

• Conventions Used in this Guide

• Recommended Reading

• The Microchip Web Site

• Customer Support

• Document Revision History

DOCUMENT LAYOUT

This document describes how to use the HV7321 Ultrasound TX Pulser Evaluation Board as a development tool to evaluate the HV7321 4-Channel 5-Level ±80V 2.5A Ultrasound Transmit Pulser and the MD1730 8-Channel ±6V Low-Noise CW Beamformer ICs. The manual layout is as follows:

• Chapter 1. “Product Overview” – Important information about the HV7321 Ultrasound TX Pulser Evaluation Board.

• Chapter 2. “Installation and Operation” – This chapter includes a detailed description of each function of the evaluation board and instructions on how to begin using the HV7321 Ultrasound TX Pulser Evaluation Board.

• Chapter 3. “Software Description” – This chapter explains the installation steps for installing the MUPB001 (Microchip Ultrasound Platform Board) GUI, provides an in-depth description of the elements of the MUPB001 GUI, and includes a step-by-step guide for generating signals at the HV7321 output.

• Chapter 4. “PCB Design and Layout Notes” – This chapter explains important points of PCB design and layout of high voltage ultrasound systems.

NOTICE TO CUSTOMERS

All documentation becomes dated, and this manual is no exception. Microchip tools and documentation are constantly evolving to meet customer needs, so some actual dialogs and/or tool descriptions may differ from those in this document. Please refer to our website (www.microchip.com) to obtain the latest documentation available.

Documents are identified with a “DS” number. This number is located on the bottom of each page, in front of the page number. The numbering convention for the DS number is “DSXXXXXXXXA”, where “XXXXXXXX” is the document number and “A” is the revision level of the document.

For the most up-to-date information on development tools, see the MPLAB® IDE online help. Select the Help menu, and then Topics to open a list of available online help files.



• Appendix A. “Schematic & Layouts” – Shows the schematic and PCB layout diagrams for the HV7321 Ultrasound TX Pulser Evaluation Board and for the MUPB001.

• Appendix B. “Bill of Materials (BOM)” – Lists the parts used to build the HV7321 Ultrasound TX Pulser Evaluation Board and the MUPB001.

• Appendix C. “HV7321 Ultrasound TX Pulser Evaluation Board Typical Waveforms” – Describes the various demonstration waveforms for the HV7321 Ultrasound TX Pulser Evaluation Board.

CONVENTIONS USED IN THIS GUIDE

This manual uses the following documentation conventions:

DOCUMENTATION CONVENTIONS

Description Represents Examples

Arial font:

Italic characters Referenced books MPLAB® IDE User’s Guide

Emphasized text ...is the only compiler...

Initial caps A window the Output window

A dialog the Settings dialog

A menu selection select Enable Programmer

Quotes A field name in a window or dialog

“Save project before build”

Underlined, italic text with right angle bracket

A menu path File>Save

Bold characters A dialog button Click OK

A tab Click the Power tab

N‘Rnnnn A number in verilog format, where N is the total number of digits, R is the radix and n is a digit.

4‘b0010, 2‘hF1

Text in angle brackets < > A key on the keyboard Press <Enter>, <F1>

Courier New font:

Plain Courier New Sample source code #define START

Filenames autoexec.bat

File paths c:\mcc18\h

Keywords _asm, _endasm, static

Command-line options -Opa+, -Opa-

Bit values 0, 1

Constants 0xFF, ‘A’

Italic Courier New A variable argument file.o, where file can be any valid filename

Square brackets [ ] Optional arguments mcc18 [options] file [options]

Curly brackets and pipe character: { | }

Choice of mutually exclusive arguments; an OR selection

errorlevel {0|1}

Ellipses... Replaces repeated text var_name [, var_name...]

Represents code supplied by user

void main (void){ ...}


Preface

RECOMMENDED READING

This user's guide describes how to use HV7321 Ultrasound TX Pulser Evaluation Board. Other useful documents are listed below. The following Microchip documents are available and recommended as supplemental reference resources:

• HV7321 Data Sheet - “HV7321 - 4-Ch. 5-Level ±80V High-Voltage Ultrasound Pulser with T/R Switches” (DS20005639)

• MD1730 Data Sheet - “High Speed 8-Channel Ultra-Low Phase Noise Continuous Waveform Transmitter with Beamformer” (DS200005586)

THE MICROCHIP WEB SITE

Microchip provides online support via our website at www.microchip.com. This website is used as a means to make files and information easily available to customers. The web site contains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.

Technical support is available through the web site at: http://www.microchip.com/support.

DOCUMENT REVISION HISTORY

Revision A (October 2016)

• Initial release of this document.

Revision B (November 2016)

The following is the list of modifications:

• Updated Appendix B. “Bill of Materials (BOM)”.

• Minor typographical corrections.


www.microchip.com

http://www.microchip.com/support

http://www.microchip.com/support


NOTES:




Chapter 1. Product Overview

1.1 INTRODUCTION

The HV7321 Ultrasound TX Pulser Evaluation Board (ADM00659) works with Micro-chip Technology Inc.’s Ultrasound Platform Board (ADM00679) to provide a 4-Channel, 5-Level, ±80V, 2.5A ultrasound transmit pulser demonstration platform including a very low phase noise, 8-Channel ±6V CW beamforming waveform generator. The HV7321 Ultrasound TX Pulser Evaluation Board features one HV7321 IC and one MD1730 IC used as a 4-channel CW waveform generator.

1.2 HV7321 IC – DESCRIPTION

The HV7321 is a 4-Channel, 5-Level, ±80V, 2.5A ultrasound transmit pulser with inte-grated transmit/receive switches. It is designed for medical ultrasound imaging, non-destructive testing (NDT) and other transducer drive applications.

The output transistors can provide up to ±2.5A of current at ±80V in Brightness mode (B-mode) and ±300 mA current in Continuous Wave Doppler mode (CW mode). In CW mode-0 (MODE = PWS = 0), VPP1/VNN1 voltage rails are used and the output cur-rent is ±300 mA. This reduces the power dissipation on the chip in CW Mode-0.

The HV7321 also integrates 20 T/R and RX damp switches in each channel. 500 auto bleeding switches are used for true-zero voltage and minimizing the received noise.

The 220 MHz clock re-timing capability provides low jitter in CWD, PW or B-mode. The clock synchronization realigns the logic input signals to a master clock that reduces various propagation delays caused by FPGA inaccuracies and/or by long PCB traces.

The built-in gate driver floating voltage regulators of the IC provide VPP and VNN high-voltage rails changing interdependently or freely from 0 to ±80V. Output voltage overshoot clamping diodes clamp to the highest level of the supply pin of VPP0 or VNN0 respectively. The control inputs (+2.5/+3.3V voltages) are designed to work with FPGA or LVCMOS logic families directly.

The built-in high-voltage CW pulser switches enable the use of external low-voltage CW generators with much better phase CW waveform source.

1.3 MD1730 IC – DESCRIPTION

The MD1730 is an 8-channel low-phase noise CW transmitter with programmable phase delay used for CW beamforming.

The MD1730 is designed for high-end ultrasound imaging systems. In CW Mode-1, the MD1730’s 8-channel CW output signals can directly drive two HV7321 external CW inputs (CWIN) through the built-in high-voltage analog switches to drive the probe transducer elements.

The frequency and phase delay of MD1730 outputs can be programmed via a SPI inter-face. High-speed SPI read/write enables the CW focusing feature.



In CW mode, dedicated CW signal paths are designed to minimize jitter and phase noise. The CW outputs can have up to ±6V voltage swing. Each CW output has a sep-arate programmed phase delay time value. If the CW frequency is set at 5 MHz, the phase delay step size is 6.25 ns, an angular resolution of 11.25° increments when CLK frequency is 160 MHz.

The MD1730 also features two clock output buffers that can drive two HV7321 ICs with single-ended synchronization clock inputs up to 220 MHz.

1.4 HV7321 ULTRASOUND TX PULSER EVALUATION BOARD – FEATURES

• Four channels of HV7321 ultrasound transmitters

• Designed to work with Microchip Ultrasound Platform Board (MUPB001)

• 5-level voltage pulse waveforms outputs

• Dual rails pair of VPP0/VNN0 and VPP1/VNN1 up to ±80V high voltages

• On-board 220 pF//1K dummy load per channel

• ±2.5A source and sink current capability

• Built-in active return-to zero (RTZ) MOSFETs

• Built-in high-voltage analog damp switches for “true-zero” RTZ.

• On-board wide band op amp LNA emulation circuits for T/R switch outputs

• Re-timing clock on-board option sources up to 200 MHz frequency

• Fully programmable waveform generation from PC GUI via the MUPB001 board

• Connection-ready for external sync/trigger/clock signals

• On-board 5V-to-2.5V conversion LDO for VLL supply

1.5 HV7321 ULTRASOUND TX PULSER EVALUATION BOARD AND MUPB001 – FUNCTIONAL DESCRIPTION

The HV7321 Ultrasound TX Pulser Evaluation Board can drive transducers as a 5-level and 4-channel transmitter for ultrasound imaging applications and NDT systems. The evaluation board features one HV7321-G 9 x 9 mm 64-lead VQFN packaged inte-grated circuit and one MD1730 6 x 6 mm 36-lead VQFN packaged integrated circuit.

The board uses two high-speed 20 signal pair carrying capable right-angle backplane connector, which is designed to work with Microchip Ultrasound Platform Board (MUPB001) (ADM00679) as the control signal source.

The MUPB001 has a FPGA, used for demo waveform generation, and a USB-bridge IC that connects the MUPB001 to a PC. By means of a Microsoft® Windows® driver and GUI, the user can generate many optional waveforms and choose several modes to evaluate the ultrasound-imaging transmit-pulser, including the FPGA re-programma-ble features.

The on-board timing clock management IC allows flexible clock frequency selection. The user can select different clock frequencies using the MUPB001 built-in clock source via GUI, or activate the LVDS output clock oscillator on the HV7321 Ultrasound TX Pulser Evaluation Board by installing 0 resistors at the output of the IC oscillator. The LVDS signal is used solely by the MD1730.

These clock frequencies can be further utilized via the on-board clock buffer to drive the single-ended re-timing clock input CLK on the HV7321 if FPGA timing logic inputs are not desired.

The additional buffer on MD1730 can also be used to let the FPGA clock system syn-chronized with the target evaluation board.

On connectors J5 and J23 there are additional uncommitted pins available to further customize the synchronization or the use of triggers signals. If the HV7321 Ultrasound TX Pulser Evaluation Board is connected to the MUPB001, these signals are all


connected to the FPGA I/O/clock pins. The users can connect the board to their own control signal source or system via the high-speed backplane connectors J5 and J23 (see Figure 1-1).

The HV7321 has built-in T/R switches per channel. Received signals at the output of the T/R switches can be evaluated by using the output (LNAOUT test point on board) of the wide-band transimpedance op-amp. The desired T/R switch output is connected to the op-amp input via jumper. The op-amp has active termination load that emulates the LNA (Low Noise Amplifier) input impedance similar to the one in receiver AFE (Active Front End) Circuit.

There are seven color LEDs on the HV7321 Ultrasound TX Pulser Evaluation Board to indicate the input control signal states.

Jumpers close to SMA connectors are for connecting the on-board dummy R-C load (220 pF//1K) optionally to the transmit (TX) output.

The 220 MHz clock re-timing capability provides low jitter in CWD (Continuous Wave Doppler), PW or B-mode. The clock synchronization realigns the logic input signals to a master clock that reduces various propagation delays caused by FPGA inaccuracies and/or by long PCB traces.

FIGURE 1-1: HV7321 Ultrasound TX Pulser Evaluation Board - Simplified Block Diagram.

U2MD1730

J22

TX0-3 TP30 J4TX3

XDCR350

1K

+10V

VDD

+2.5V

VLL

0 to +80V

VPF1

-2 to - V

GND DAP VSS

-10V

SUB

0 to -80V

VPP0

VNN0

0 to -80V

0 to +80V

1 of 4 Channels

CW0

+2 to + V

+5V

VDD

Decode&

LevelShift

CWIN0

NEG0

SEL0

NEG3

SEL3

CWIN3U1HV7321

GND

OTP

+2.5V

VLL

PWS

POS3

VSUB

SUB

MODE

REN

CLK

VDF

CLK

CLK LVDS CLK

SDO

SDI

CS

SPI

SCK

Other CWChannels

POS0

CW3

249

RX0-3

VNF1

RGND

VSFCW

Fre.Dvdr& Phase

Delay

RTZSW

CWSW

TRSW

RXDMP

TRSW

CW4-7TP52...

+10V

VGP

-10V

OEN

VGN

J5TE6469169-1Connector to

Clock & I/Os onMUPB Board

CWIN2CW2

CWIN1CW1

TXRW

CTRN[3:0]

DT[63:0]

HIZ[7:0]

VLL

CLKCLK

CBE1CKB1

1 of 8 Ch.

SPIB

CBE0,1

CLKCLK

CBE0CKB0

MODEPWSCBE0

SEL0

MDENOEN

X1

LVDSOSC.

+2.5V

MCP661-

+

J6-J9

VDD /2

TP45

LNAOUTTP50

VCW+

OTP

CKB1

OTP

50

R35

R36(inf)

(inf)

J21

J3TX2

XDCR250

1K

J20

J2TX1

XDCR150

1K

J19

J1TX0

XDCR050

1K

+2.5V

+5V, ±10V, 0 to ± V, 0 to ±80V, 0to ±80VPower Supply Connectors J10-13

VDDVCC

VGPVGN

VCW+ VPP0VNN0

TXTRIG

+5V

PWR

J10-1VCC

(Option)

VIN VOUT

U3MCP1727

GND+5VTP66 TP67

RXTRIG

NCTP27-28

PWR

MDEN

OSCEN

TP17

TP9

TP1

VLL

VPP1

VNN1

pF220

pF220

pF220

pF220

VPF0

VNF0

EN

VCW+

EN VCW-

VCW-

VPP1VNN1



1.6 HV7321 ULTRASOUND TX PULSER EVALUATION BOARD – TECHNICAL SPECIFICATIONS

1.7 DEVICE SUMMARY

The HV7321 Ultrasound TX Pulser Evaluation Board demonstrates the following Microchip products on board:

• HV7321, 4-Channel 5-Level ±80V 2.5A Ultrasound Transmit Pulser

• MD1730, 8-Channel, ±6V Low-Noise CW Beamformer

The evaluation board also uses the additional IC:

• MCP1727, 1.5A Low-Voltage, Low-Quiescent Current LDO Regulator

1.8 WHAT THE HV7321 ULTRASOUND TX PULSER EVALUATION BOARD KIT INCLUDES

The HV7321 Ultrasound TX Pulser Evaluation Board kit includes:

• HV7321 Ultrasound TX Pulser Evaluation Board (ADM00659)

• Important Information Sheet

Parameter Value

Modes of Operation B, PW, CW

B-Mode Output Pulses Peak Voltage and Current (SEL = 0) up to ±80V and ± 2.5A typical

B-Mode Output Pulses Peak Voltage and Current (SEL = 1) up to ±80V and ± 2.0A typical

CW Output Peak Voltage and Current (MODE = 1) 0 to ±6V and ±800 mA typical. Use CWIN0–3 and MD1730

CW Output Peak Voltage and Current (MODE = 0, PWS = 0) 0 to ±6V and ±700 mA typical. Use VPP1/VNN1 CW

HV7321 Re-timing Clock Input Frequency 200 MHz max. LVCMOS 2.5V

MD1730 CW Clock Input Frequency 250 MHz max. LVDS/SSTL 2.5/LVCMOS 2.5V

Low-Phase Noise CW Test LVDS Clock Oscillator Options included

Interface of FPGA Control Signals and USB PC-GUI Software J5 and J23 Connects to MUPB001 (ADM00679) Interface Board

Logic circuitry 2.5V VLL Voltage Supply LDO Regulator Built-in, with optional voltage source from MUPB001/J10

TX R-C Test-Load and User Transducer Interface Built-in, 220 pF//1K per channel with jumper and 50 SMA

On-Board LED Indicator of Signals SEL0, MODE, PWS, CBE0, MDEN, OEN and OTP

Overtemperature Protection Overtemperature Protection open-drain output to J5 to MUPB001 included

Floating Gave Driver Voltage Regulators and UVLO Built-in regulators in HV7321 and MD1730 w/ UVLO

PCB Board Dimensions 127 x 102 mm (5.0 x 4.0 inch)




Chapter 2. Installation and Operation

2.1 GETTING STARTEDThe HV7321 Ultrasound TX Pulser Evaluation Board is fully assembled and tested. For basic waveforms generation the board requires five power supply voltage rails of +5V, ±10V and ±80V. Nine power supply voltage rails are necessary for the full functional demonstration: +5V, ±10V, 0 to ±6V, 0 to ±50V, and 0 to ±80. It is strongly recom-mended that these power supply sources feature adjustable current-limit functions.

2.1.1 Additional Tools Required for Operation

The HV7321 Ultrasound TX Pulser Evaluation Board also requires:

1. an oscilloscope with minimum 500 MHz BW and two high-impedance probes

- make sure the grounds of the power supply sources are correctly connected to the same ground as the testing oscilloscope ground

In order to demonstrate the HV7321 Ultrasound TX Pulser Evaluation Board wave-forms and features, the following additional tools are required:

2. a Microchip Ultrasound Platform Board (MUPB001) (ADM00679)

3. a Microsoft Windows® 7 PC that has the Microchip Ultrasound Platform Board evaluation driver and running the HV7321 Ultrasound TX Pulser Evaluation Board GUI software

- connect J5 and J23 on the HV7321 Ultrasound TX Pulser Evaluation Board (see Figure 2-1) to the MUPB001 FPGA control-board

- connect the MUPB001 FPGA control-board via USB to the Windows-7 PC (see Figure 2-2)

Download the latest ultrasound platform evaluation driver and GUI software from the Microchip website at www.microchip.com.

2.2 SETUP PROCEDURE

To operate the HV7321 Ultrasound TX Pulser Evaluation Board, the following steps must be followed:

1. connect J5 and J23 (Figure 2-1) to a Microchip Ultrasound Platform Board (MUPB001) (ADM00679) (Figure 2-2).

2. connect all HV7321 Ultrasound TX Pulser Evaluation Board jumpers on J6, J15, J19, J20, J21 and J22 for the R-C load. See Figure 2-1.

3. connect all power supplies to the voltage supply input connectors J10, J11, J12 and J13 as indicated in Table 2-1 by observing the polarity. See Figure 2-1.

TABLE 2-1: POWER SUPPLY VOLTAGES AND CURRENT-LIMIT SETTINGS

Terminal Rail Name Voltage Average-Current Limit

J10-1 VCC/PWR +5V +50 mA

J10-2 VDD +5V +20 mA

J10-3 VGN -10V -30 mA

J10-4 GND 0V —


http://www.microchip.com/


FIGURE 2-1: HV7321 Ultrasound TX Pulser Evaluation Board – Front View.

J10-5 GND 0V —

J10-6 VGP +10V +30 mA

J11-1 VCW+ 0 to +6V +200 mA

J11-2 GND 0V —

J11-3 VCW- 0 to -6V -200 mA

J12-1 VPP0 0 to +80V +5 mA

J12-2 GND 0V —

J12-3 VNN0 0 to -80V -5 mA

J13-1 VPP1 0 to VPP0 +5 mA

TABLE 2-1: POWER SUPPLY VOLTAGES AND CURRENT-LIMIT SETTINGS (CONTINUED)

Terminal Rail Name Voltage Average-Current Limit

WARNING

Observe the polarity of each power supply rail and set the voltage and currentlimit carefully. Note that ±80V is the maximum limit for VPP0/VNN0. VPP1/VNN1

voltages have to be equal or within VPP0/VNN0 voltage range.

J5

J23

J10 J11 J12 J13

J21

J19

J20

J22

TP50

TP30

TP1

J6

J15


4. turn on the HV7321 Ultrasound TX Pulser Evaluation Board VDD +5V and the MUPB001 VDD +5V

5. connect the MUPB001 USB cable to the PC (see Section 2.5). Make sure the MUPB001 software driver is installed correctly and the MUPB001 USB connec-tion to the PC is established.

6. run the MUPB001 GUI software. Check that the LEDs on the HV7321 Ultrasound TX Pulser Evaluation Board are under PC user interface control. Set OEN LED off.

7. turn on VGP/VGN ±10V, VPP0/VNN0 ±25V and VPP1/VNN1 ±15V

8. connect the oscilloscope probe ground lead to TP50, apply the probe tip to TP1 or TP30 with the scope trigger source set to the probe and the trigger-level to DC +5V; set the scanning time base to 200 ns per division.

9. enable the TX Pulsed-Echo mode in the GUI to evaluate the waveforms (see Section 3.4.11)

10. if it is necessary to increase the VPP/VNN voltage, adjust the VPP0/VNN0 in small increments up to ±80V maximum, with the current limiting on

2.2.1 Recommended power-up and power-down sequences

Table 2-2 shows the recommended power-up sequence of the HV7321 Ultrasound TX Pulser Evaluation Board.

Note: Powering the HV7321 Ultrasound TX Pulser Evaluation Board up/down in any arbitrary sequence will not cause any damage to the device. The power up/down sequences in table below are only recommended in order to mini-mize possible inrush current.

2.3 INTERFACE CONNECTIONS

Table 2-3 shows the board J5 control interface signals.

TABLE 2-2: BOARD POWER-UP AND POWER-DOWN SEQUENCES

Step Power-Up Sequence Step Power-Down Sequence

1 VLL on with logic signal low 1 OEN and logic control signal go low

2 VDD, VGP and VGN ON 2 VPP0,1 and VNN0,1 OFF

3 REN = 1 3 REN = 0

4 VPP0,1 and VNN0,1 ON 4 VDD, VGP and VGN OFF

5 OEN = 1 and logic control signal active 5 VLL OFF

TABLE 2-3: J5 CONTROL INTERFACE SIGNALS

Pin # Name Test Point I/O Type Signal Discretion

J5-A1 PWR TP68 (1) +5V Power Input External +5V power supply via diode D8B to LDO U3 for VLL onlyJ5-B1 PWR TP68 (1) +5V Power Input

J5-C1 VLL(1) TP5 2.5V Pull Up Connected to R39 1K resistor pull-up to +2.5V VLL

J5-D1 OTP TP10 Open Drain Output OTP U1-20 HV7321 w/ 200 & LED to +2.5V VLL

J5-A2 NEG0 TP16 LVCMOS-2.5V Input NEG0 control input pin for U1 HV7321 Channel-0

J5-B2 POS0 TP14 LVCMOS-2.5V Input POS0 control input pin for U1 HV7321 Channel-0

J5-C2 OEN TP11 LVCMOS-2.5V Input Output enable input pin for U1 HV7321

J5-D2 REN TP12 LVCMOS-2.5V Input Gate-Regulator enable input pin for HV7321

J5-A3 NEG1 TP19 LVCMOS-2.5V Input NEG1 control input pin for U1 HV7321 Channel-1

Note 1: Connected indirectly with in-serial resistor or capacitor. For more details, refer to Appendix A. “Schematic & Layouts”.



J5-B3 POS1 TP20 LVCMOS-2.5V Input POS1 control input pin for U1 HV7321 Channel-1

J5-C3 NEG2 TP22 LVCMOS-2.5V Input NEG2 control input pin for U1 HV7321 Channel-2

J5-D3 POS2 TP23 LVCMOS-2.5V Input POS2 control input pin for U1 HV7321 Channel-2

J5-A4 SEL0 TP13 LVCMOS-2.5V Input SEL0 control input pin for U1 HV7321 Channel-0

J5-B4 SEL1 TP18 LVCMOS-2.5V Input SEL1 control input pin for U1 HV7321 Channel-1

J5-C4 NEG3 TP25 LVCMOS-2.5V Input NEG3 control input pin for U1 HV7321 Channel-3

J5-D4 POS3 TP26 LVCMOS-2.5V Input POS3 control input pin for U1 HV7321 Channel-3

J5-A5 SEL2 TP21 LVCMOS-2.5V Input SEL2 control input pin for U1 HV7321 Channel-2

J5-B5 SEL3 TP24 LVCMOS-2.5V Input SEL3 control input pin for U1 HV7321 Channel-3

J5-C5 MODE TP29 LVCMOS-2.5V Input MODE pin of HV7321, if Hi, CWIN[3:0] & MD1730 used

J5-D5 PWS TP31 LVCMOS-2.5V Input PWS pin of HV7321, if Lo, use VPP1/VNN1 for CW

J5-A6 SCK TP48 LVCMOS-2.5V Input SCK pin, SPI interface clock of U2 MD1730

J5-B6 CS TP49 LVCMOS-2.5V Input SCK pin, SPI interface chip-select of U2 MD1730

J5-C6 MDEN TP44 LVCMOS-2.5V Input EN pin, chip-enable of U2 MD1730, if Lo, CW[7:0] Hi-Z

J5-D6 SPIB TP46 LVCMOS-2.5V Input SPIB SPI broadcasting-mode enable of U2 MD1730

J5-A7 SDI TP51 LVCMOS-2.5V Input SDI pin, SPI interface clock of U2 MD1730

J5-B7 SDO TP53 LVCMOS-2.5V Output SDO pin, SPI data output from U2 MD1730

J5-C7 CBE0 TP37 LVCMOS-2.5V Input Clock Buffer-0 enable input pin on U2 MD1730

J5-D7 CBE1 TP40 LVCMOS-2.5V Input Clock Buffer-1 enable input pin on U2 MD1730

J5-A8 TXTRIG TP66 LVCMOS-2.5V I/O FPGA TX launch trigger signal input or output of MUPB

J5-B8 RXTRIG TP67 LVCMOS-2.5V I/O FPGA RX mode trigger signal input or output of MUPB

J5-C8 TXRW TP47 LVCMOS-2.5V Input CW transmit or SPI read/write control of U2 MD1730

J5-D8 CKB1 TP59 (1) LVCMOS-2.5V Output Clock Buffer-1 output from U2 MD1730

J5-A9 NC NA LVCMOS-2.5V Input Not used by the PCB

J5-B9 NC NA LVCMOS-2.5V Input Not used by the PCB

J5-C9 TP27 TP27 LVCMOS-2.5V Input Connected to TP27 on the PCB

J5-D9 TP28 TP28 LVCMOS-2.5V Input Connected to TP28 on the PCB

J5-A10 OSCEN TP32 LVCMOS-2.5V Input On-board crystal oscillator X1 enable signal

J5-B10 SYNC TP33 LVCMOS-2.5V Input Via R31 (INF) to CLK pin of HV7321 as a clock option

J5-C10 CLK_N (1) TP58 (1) LVDS / SSTL2.5 Input LVDS clock input from MUPB001 to U2 MD1730 CLK

J5-D10 CLK_P (1) TP56 (1) LVDS / SSTL2.5 Input LVDS clock input from MUPB001 to U2 MD1730 CLK

J5-xGx GND TP50,61,65 Ground / 0V / Return Ground, 0V reference, shielding or PWR supply return

TABLE 2-3: J5 CONTROL INTERFACE SIGNALS (CONTINUED)

Pin # Name Test Point I/O Type Signal Discretion

Note 1: Connected indirectly with in-serial resistor or capacitor. For more details, refer to Appendix A. “Schematic & Layouts”.


2.4 OPERATING THE HV7321 ULTRASOUND TX PULSER EVALUATION BOARD

Refer to Appendix C. “HV7321 Ultrasound TX Pulser Evaluation Board Typical Waveforms” for HV7321 Ultrasound TX Pulser Evaluation Board typical waveforms and voltages.

2.4.1 B-Mode Multi-Level TX Pulser Operation (PWS = 1, MODE = 0)

In B-Mode multi-level ultrasound transmit pulse generation, the user can select the fol-lowing options or combinations of options, using a MUPB001 connected to a PC via USB and running the dedicated GUI. These are the options available:

1. ultrasound waveform frequency, fixed frequency 1 to 20 MHz with step of 100 kHz

2. number of half cycles in TX launch burst, from 2 to 16

3. change launch burst Pulse Repetition Frequency (Line Duration) from 5 kHz to 20 kHz, or an interval of 50 to 200 µs

4. change the half-cycle polarity: positive first only, negative first only, or alternating between positive first and negative first

5. change the VPP0/VNN0 and VPP1/VNN1 pluses pair order in the launch burst

6. change the pulse(s) damping condition: pulse(s) followed by return-to-zero (RTZ) or not

7. change the receive time (RX-time) T/R switch(es) condition: RTZ, RTZ+, or high Z

8. change the number of levels: 2-level, 3-level or 5-level operation

9. change the duty cycle of pulses: PWM% or Pulse Width with a range of 2 ns to 500 ns according to the frequency of the pulse(s)

10. change the peak voltages of the pulse(s) by changing the VPP and VNN rail sup-ply voltages.

2.4.2 CW Mode-0 Using Voltage of VPP1/VNN1 Rails Operation (PWS = 0, MODE = 0, SEL = 1)

Connecting the HV7321 Ultrasound TX Pulser Evaluation Board to a MUPB001 linked to a PC via USB, and running the dedicated MUPB001 GUI allows the user to use the VPP1/VNN1 voltage rail with reduced voltages and currents in CW Mode-0. The condi-tions for this mode of operation are: VPP1/VNN1 must be between 0 to ±6V, PWS = 0, and MODE = 0. The following options become available:

1. CW Doppler mode waveform frequency, fixed frequency 1 to 7 MHz with step of 100 kHz

2. selection of the CW frequency source: the MUPB001 built-in clock-generator or the low-phase noise crystal-oscillator X1 on the HV7321 Ultrasound TX Pulser Evaluation Board via the MD1730 clock-buffer to re-time synchronize with the FPGA CW waveforms from POS/NEG with SEL = 1

3. changing the CW Doppler mode waveform peak-to-peak voltages by adjusting VPP1/VNN1 supply rail voltages.

Note: Normal ranges are within 2 to 6V peak-to-peak at TX3:0 outputs. Higher volt-ages may overheat the IC(s) and/or components on the PCB, and may even damage them permanently.



2.4.3 Low Phase-Noise CW Beamforming Operation via CWSW and MD1730, Supplied by VCW+/VCW- Rails (PWS = 1, MODE = 1)

In CW Mode-1, the CW Beamforming mode features lower phase-noise by using the built-in high-voltage analog switch in the HV7321. In this mode, the low-voltage CW waveform generator sends the lower phase-noise CW waveforms with a predefined beamforming phase delay.

The CW waveform peak-to-peak voltage swing is defined by the voltage supply rail of VCW+/VCW- on the MD1730. The voltage range of the VCW+ /VCW- is 0 to ±6V, with PWS = 1 and MODE = 1 control conditions. By using a MUPB001 connected to a PC via USB and by running the dedicated GUI, the user has access to these options:

1. CW beamforming (CW Mode-1) waveform frequency, frequency 1 to 8 MHz with step of 100 kHz, generated by programming the CW frequency divider number CWFD[7:0] in the MD1730 SPI register via the MUPB001 PC GUI

2. programming the beamforming phase delay PHDCH[7:0] to define the relative phase delay between channels of the CW waveforms

3. selecting the channel (or channels) set in Doppler receiving mode, by program-ming the bits of HIZCH in the MD1730 SPI register

4. selection of the CW frequency source: the MUPB001 built-in clock-generator or the low-phase noise crystal-oscillator X1 on the HV7321 Ultrasound TX Pulser Evaluation Board via the MD1730 built-in CW frequency divider

5. changing the CW Doppler mode waveform peak-to-peak voltages by adjusting the VCW+/VCW- supply rail voltages.

Note: Normal ranges are within 2 to 6V peak-to-peak at TX3:0 outputs. Higher volt-ages may overheat the IC(s) and/or components on the PCB, and may even damage them permanently.

2.5 MICROCHIP ULTRASOUND PLATFORM BOARD (MUPB001)

The MUPB001 is used to generate the control signals for the HV7321 Ultrasound TX Pulser Evaluation Board. It features a flexible ultra-low jitter clock synthesizer and a Spartan-6 XC6SLX9 FPGA.

2.5.1 Connecting the MUPB001 to the PC – Setup Procedure

1. Before connecting the MUPB001 to the PC, make sure that:

- the latest FPGA code on the platform flash of the MUPB001 FPGA is config-ured (Section 3.1)

- the latest GUI is installed and running on the PC (see Section 3.3).

2. With FPGA code configured and the GUI installed, connect the USB cable between the MUPB001 and the PC. Connect J5 and J23 of the HV7321 Ultra-sound TX Pulser Evaluation Board (see Figure 2-1) to J1 and J2 of the MUPB001 (see Figure 2-2).

3. Start the GUI. On the bottom left of the status bar a “Not Connected” message is displayed in red (see Section 3.4.16).

4. Connect the appropriate power supply and turn on the power switch to power up the MUPB. LD1 and DC_IN (LD2) on the MUPB001 should light up green. A “Connected” message should be displayed in green on the bottom left of the sta-tus bar GUI (see Section 3.4.16).

The MUPB001 is now configured and ready to control the HV7321.

Note: Typical voltages and waveforms are provided in Appendix C. “HV7321 Ultrasound TX Pulser Evaluation Board Typical Waveforms”.


FIGURE 2-2: Microchip Ultrasound Platform Board (MUPB001).

OFF/ONSwitch

12V/1APower

Connector

FPGA_OK (LD1)

DC_IN (LD2)

Mini-USB Connector

PWR_OK (LD4)

USB_Fault (LD5)

PROM JTAG

J1

J2



NOTES:




Chapter 3. Software Description

3.1 FPGA CODE CONFIGURATIONConnect the +12V power connector to the Microchip Platform Ultrasound Board (MUPB001) and make sure that the green DC_IN LED is ON, indicating that the power connection is successful.

Turn on the power switch of the MUPB001 and make sure that PWR_OK LED is ON, and that the USB_Fault LED (red) flashes one time. If the USB_Fault LED remains lit, that is an indication that the USB cable is not connected and/or the Windows® operat-ing system did not recognize the USB bridge.

Make sure that the FPGA_OK LED of the MUPB001 is ON. This is an indication that the FPGA code is configured (see Figure 2-2).

If the FPGA is not configured, or the user wants to modify the FPGA code, it is neces-sary to configure the FPGA platform flash PROM. The tools needed for FPGA platform flash PROM flash configuration are:

• Xilinx Platform cable USB II: This is a piece of hardware that is sold separately from this evaluation kit. It connects to a PC via USB cable and to the MUPB001 J5 connector via JTAG cables.

• iMPACT tool embedded in Xilinx ISE Project Navigator: Xilinx ISE Project Naviga-tor is the development environment for Xilinx products. It can be downloaded free of charge from the Xilinx web site. iMPACT is the name of the module in Xilinx ISE Project Navigator that provides the configuration of .mcs file to platform flash PROM.

• the .mcs file is the extension of FPGA code files that are synthesized and specifi-cally formatted for Xilinx platform flash PROM configuration.

The code resides in Xilinx platform flash PROM. The platform flash PROM loads the code to FPGA when the system is powered up.

3.2 GETTING STARTED

Download the latest ultrasound platform evaluation driver and GUI software from the Microchip website at http://www.microchip.com and install the MUPB001 – HV7321_MD1730 GUI by following the instructions in Section 3.3.

3.3 MUPB001 – HV7321_MD1730 GUI INSTALLATION

The MUPB001 – HV7321_MD1730 GUI software installer can be downloaded from the Microchip web site at http://www.microchip.com. Search for the evaluation board on the web site by part number ADM00679. The GUI can be downloaded from the board web page.

1. Open the MUPB001GUI-v.1.0.0-windows-installer.exe. The MUPB001 – HV7321_MD1730 GUI software installer will initiate by launching the Applica-tion Install dialog box. Click Next to start the installation.





FIGURE 3-1: MUPB001 GUI – Application Install Dialog Box.

2. To proceed with the installation, read the License Agreement and accept by click-ing the radio button corresponding to “I accept the agreement”, then click Next.

FIGURE 3-2: MUPB001 GUI – License Agreement Dialog Box.

3. On the Installation Directory dialog box, browse for the desired location, or click Next to install in the default location.


Software Description

FIGURE 3-3: MUPB001 GUI – Installation Directory Dialog Box.

4. Once the installation path is chosen, the software is ready to install. Click Next to proceed.

FIGURE 3-4: MUPB001 GUI – Ready-to-Install Dialog Box.

5. The installation status window appears, showing the installation progress. After the installation has completed, click Next to continue.



FIGURE 3-5: MUPB001 GUI – Installation Status Window.

6. Once the Install Complete dialog box appears, click Finish to exit the Installer.

FIGURE 3-6: MUPB001 GUI – Install Complete Dialog Box.

7. Start the software by either going to Windows Start button > All Programs > Microchip > MUPB001 GUI or by clicking the newly-created software icon on the

desktop ( ).


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Tra ain GUI elements. Some elements are sp le. The numbered entries in Figure 3-7 (1

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1

1

1

6

4 MUPB – HV7321_MD1730 GUI DESCRIPTION

e elements of the MUPB - HV7321_MD1730 Graphical User Interface are dependent on the selection being ma4.11), labeled with 11 on Figure 3-7.

nsmission Mode “Pulsed-Echo” is selected by default. This section provides a comprehensive overview of the mecific to Pulsed-Echo only, while others are shared across transmission modes, i.e., common to the GUI as a whothrough 16) are described in subsections 3.4.1 through 3.4.16.

URE 3-7: MUPB001 – HV7321_MD1730 GUI Pulsed-Echo View.

2

1

0

112

13 14

15

6

3

7

9

4 58


3.4.1 Title Bar

On the MUPB001 – HV7321_MD1730 GUI Ribbon, the Microchip Technology Inc. logo is displayed together with the name of the GUI.

3.4.2 Menu Bar

There are two menus on the Menu bar: File and Help. Click the File menu to open these submenus: Save Waveform, Load Waveform, Save Log, Refresh, and Exit. Clicking the Help menu gives users access to Show Help, and About submenus.

3.4.3 Line Duration Text Box

The user can set the line duration by entering the required value into the Line Dura-tion(ns) text box. The default value is 200000 ns.

3.4.4 Entries to Transmit Drop-Down List Box

One transmission loop makes up one line duration. During one line duration each chan-nel can be set to transmit up to 4 different group of pulses. The options available to the user are 1, 1 - 2, 1 - 2 - 3, and 1 - 2 - 3 - 4.

3.4.5 Log Status Group Box

The Log Status group box is made up of the screen area and the button area.

The Log Status screen area shows messages on the status of the initialization of the MUPB001 board transmit frequency and Pulsed-Echo Mode settings. “Initialization Started”, “Initialization Completed”, “Transmission is started”, “Transmission is stopped” are commonly displayed status messages. Figure 3-8 provides an example.

FIGURE 3-8: Log Status Screen Area.

There are two buttons in the Log Status button area: Save Log to File, and Clear.

These buttons allow the user to either save the log in a text file or clear the log screen, respectively.

Clicking the Save Log to File button brings up the Save As dialog box, which allows the user to navigate to the desired location for the log to be saved, and assign the log a file name.

3.4.6 Start/ Stop Button

The Start/Stop button starts and stops the transmission. It becomes available to use once the MUPB001 is connected to the PC via USB, and the connection is recognized by the PC.

3.4.7 Pin State Group Box

The Pin State group box is made up of Pin State check box and the Send button.

The Pin State check box includes the control signals of PWS, MODE, OEN, and REN.



PWS must be checked (ON) for Pulsed-Echo mode and unchecked (OFF) for CW Modes. MODE has to be selected (ON) for CW Mode-1 and unselected (OFF) for CW Mode-0 and Pulsed-Echo mode.

REN is an abbreviation for “Regulator Enable” and it has to be checked (ON) for turning the internal regulators on. OEN refers to “Output Enable” and it has to be selected (ON) for getting the outputs out of High Impedance (high Z) mode.

After checking the desired options, the Send button becomes available for sending the settings to the MUPB001.

3.4.8 Transmit Entry Group Box

This group box allows the users to set the parameters for the pulses that are necessary to be transmitted. The Transmit Entry group box includes:

• the Entry Index drop-down list box:

- the users can set between 1 and 4 group of pulses for each channel. The default value is 4.

• the TX Output Freq Divisor (1-255) text box:

- the users can adjust the pulse width by entering a value between 1 and 255 in this text box. If Transmit Clock Config (MHz) (see Figure 3-7) is 200 MHz then the clock period is 5 ns. The pulse width is adjusted by dividing the TX Output Freq Divisor to the Transmit Clock Frequency. The default value is 16.

• 4 Channels (0-3) Delay (ns) text boxes:

- the relative delay between channels can be defined in these text boxes. The value is expressed in nanoseconds. The default value is 16000 ns.

• 4 Channels (0-3) Waveform (Length Up to 32 Characters) text boxes:

- each group of pulses can be made up of up to 32 characters. The building blocks that make up the waveform syntax are presented in Table 3-1.

• the Set Default Values button:

- the users can set the entered input values into the Channels (0-3) Delay (ns) and Channels (0-3) Waveform (Length Up to 32 Characters) text boxes as default values.

• the Clear Entry button:

- this button clears the values entered into the Channels (0-3) Delay (ns) and Channels (0-3) Waveform (Length Up to 32 Characters) text boxes.

• the Help ( )button:

- clicking the Help button opens the Information pop-up window. See Figure 3-9.

TABLE 3-1: CHANNEL WAVEFORM SYNTAX

Building Blocks

Definition

0 = VNN0

1 = VPP0

2 = VNN1

3 = VPP1

R = Return-to-Zero (RTZ)

P = Receive Mode (RTZ+)

H = High-Impedance (high Z)



FIGURE 3-9: Information Pop-Up Window.

3.4.9 Transmit Clock Configuration (MHz) Group Box

The Transmit Clock Configuration (MHz) group box allows users to sets the clock fre-quency. The Transmit Clock Configuration (MHz) group box includes the Transmit Clock Configuration (MHz) drop-down list box and the Initialize MUPB button. Users can select between 80, 120, 160 and 200 MHz clock frequency. The Initialize MUPB button is activated once the USB connection between the PC and the MUPB001 is established.

3.4.10 Pulsed-Echo Voltages Group Box

The Pulsed-Echo Voltages group box enables users to add numeric values to the volt-age values shown on the GUI plot, for labeling purposes.

The Pulsed-Echo Voltages group box includes:

• 4 voltage text boxes each corresponding to VNN0 (V), VPP0 (V), VNN1 (V), and VPP1 (V).

• the Default State drop-down list box which allows users to select in initial state of the transmission channels. The options available are: RTZ, RTZ+ and Hi-Z.

3.4.11 Transmission Mode List Box

The user can select one of the 3 available modes of transmission by checking one option in the Transmission Mode list box. The options available are:

• Plused_Echo: There are 5 voltage levels [VPP0,VPP1, Ground (Return-To-Zero, RTZ), VNN1, VNN0] in addition to High Impedance (Hi-Z) and Receive mode (RTZ+).

• CW Mode-0 (Internally by HV7321): There are 3 voltage levels [VPP1, Ground (Return-To-Zero, RTZ), VNN1] in addition to High Impedance (Hi-Z) and Receive mode (RTZ+).

• CW Mode-1 (Externally by MD1730): There are 3 voltage levels [CW+, Ground (Return-To-Zero, RTZ), CW-) in addition to High Impedance (Hi-Z) and Receive mode (RTZ+).

3.4.12 Waveform Screen Area

The Waveform screen area displays the transmitted waveforms. The signals displayed are not the actual measurements at the HV7321 output but visual representations of what is expected at the output.

The parameters shown in the Waveform screen area are dependent on the mode of transmission selected in the Transmission Mode list box (see Section 3.4.11).



3.4.13 The Save to File button

By clicking the Save to File button, users can save the currently loaded waveforms and the delay values input in CH0-3 Delay (ns) text boxes to a text file.

Clicking this button brings up the Save As dialog box that allows the user to navigate to the desired location for the file to be saved, and assign the file a file name.

3.4.14 The Load Button

The Load button is used in conjunction with the Save button to load the previously saved waveforms and delay values.

Clicking this button activates the Open dialog box which allows the user to navigate to the location of the file to be loaded.

3.4.15 The Load Common Waveform Button

The Load Common Waveform button allows the user to access a set of 10 predefined waveform profiles (Common Waveform 1 through 10) and load them into the GUI. Only one selection can be active at a time. Depending on the selection being made, the Channels (0-3) Waveform (Length Up to 32 Characters) text boxes (Section 3.4.8) will be updated with a different waveform syntax.

Clicking the Load Common Waveform button activates the Common Waveforms dialog window. The Common Waveforms dialog window is made up of a list box including 10 items, which the users can choose from sequentially.

FIGURE 3-10: Common Waveforms Dialog Box.

3.4.16 Connection Status Indicator

The Connection Status indicator updates accordingly depending on whether there is a working connection between the PC and the MUBPB001. There are two connection status messages:


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is established.

x (3.4.11) GUI determines a change of the overview of the GUI elements specific to subsections 3.5.1 through 3.5.3.

- Not Connected (in red): the MUPB001 is not yet powered on or the USB con

- Connected (in green): the MUPB001 is powered on and the USB connection

3.5 GUI ELEMENTS SPECIFIC TO CW MODE-0

Selecting CW Mode-0 (Internally by HV7321) in the Transmission Mode list boGUI elements displayed, as shown in Figure 3-11. This section provides a short CW Mode-0. The numbered entries in Figure 3-11 (1 through 3) are described in

FIGURE 3-11: MUPB001 – HV7321_MD1730 GUI CW Mode-0 View.

1

3

2


3.5.1 CW Channels Group Box

The CW Channels group box enables users to set the frequency of the outputs and the relative delays.

The CW Channels group box includes the CW0 Freq Divisor text box and 4 channel check boxes each corresponding to CH0, CH1, CH2, and CH3.

Users can make from 1 to 4 selections at a time. Each channel text box has a Delay (ns) text box associated thatusers can use to set the channel delay value. The Delay (ns) text boxes become available once the channel text box is selected.

In CW0 Freq Divisor text box users can set the frequency of the CW signal. The CW Frequency is calculated by dividing the to twice the CW0 Freq Divisor:

CW Frequency= (Transmit Clock Config)/(2 X CW0 Freq divisor)

Selecting the CH0, CH1, CH2, CH3 check boxes causes the Waveform screen area (3.5.2) to be updated with a continuous signal waveform pattern. The waveform pat-terns are color coded: green for CH0, dark red for CH1, orange for CH2 and purple for CH3.


The Waveform Screen Area shows the active channels as continuous signals. The signals displayed are not the actual measurements at the HV7321 output but visual representations of what is expected at the output.

3.5.3 CW Voltages group box

The CW Voltages group box includes:

• 2 voltage text boxes corresponding to VCW- and VCW+: the values entered in these text boxes will cause the representations of the signals displayed in the Waveform Screen Area to change.

• the Default State drop-down list box where users can select between RTZ, RTZ+, and HI-Z.


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box (3.4.11) GUI determines a change of rt overview of the GUI elements specific to

subsections 3.6.1 through 3.6.3.

3.6 GUI ELEMENTS SPECIFIC TO CW MODE-1

Selecting CW Mode-1 (Externally by MD1730) in the Transmission Mode list the GUI elements displayed, as shown in Figure 3-12. This section provides a shoCW Mode-1. The numbered entries in Figure 3-12 (1 through 4) are described in

FIGURE 3-12: MUPB001 – HV7321_MD1730 GUI CW Mode-1 View.

1

32


3.6.1 CW Channels Group Box

In CW Mode-1, there are 8 transmission channels. The channels are selected and con-figured in the CW Channels group box. The CW Channels group box includes:

• the Channel drop-down list box in which users can select from 1 to 7 channelssequentially (CW0, CW1, CW2, CW3, CW4, CW5, CW6, CW7). Unlike othercases, the simple selection of the channel does not enable the channel.

• the Enable check box: the channels selected in the Channel drop-down list boxare enabled/disabled by checking/unchecking the Enable check box. Enabledchannels are marked with a green indicator in the channel enable status screenarea.

• the channel enable status screen area is made up of 8 status indicators (gray =disabled, green = enabled), 8 channel labels (CH0, CH1, CH2, CH3, CH4, CH5,CH6, CH7), and 8 corresponding Delay (ns) text boxes.

• the CH PHD (0-255) (Channel Phase Delay Digital Value) text box: users can set the channel phase delay digital value of the CW signal by choosing a value between 0 and 255. The value entered in this text box is used to generate the CH phase delay in nanoseconds. The equivalent delay in nanoseconds will be calcu-lated and displayed in the Delay (ns) text boxes corresponding to the channels selected. For the Delay (ns) text boxes to be automatically updated with the equivalent channel phase delay digital value, it is necessary to first input a value in the CH PHD (0-255) text box and then click outside the text box.


The Waveform Screen Area shows the active channels as continuous signals. The signals displayed are not the actual measurements at the HV7321 output but visual representations of what is expected at the output.

3.6.3 Frequency Group Box

The Frequency group box is used to modulate the frequency of the CW.

The Frequency group box includes two text boxes:

• the CWFD (0-255) (Continuous Wave Frequency Digital Value) text box: the value entered in this text box is used to generate the CW frequency in kHz.

• the CW Frequency (kHz) text box: this text box shows the equivalent value in kHz of the value entered in the CWFD (0-255) text box. For the CW Frequency (kHz) text box to be automatically updated with the equivalent CWFD value, it is neces-sary to first define the CWFD value and then click outside the text box.

Note: For frequency and delay calculation details, refer to the MD1730 Data Sheet.

3.7 CONFIGURING THE TRANSMISSION OF SIGNALS USING THE GUI

Following is a step-by-step guide for generating Pulsed-Echo signals, CW Mode-0 sig-nals and CW Mode-1 signals at the HV7321 output. After each set of instructions, an oscilloscope screen shot taken at the HV7321 output is presented.

3.7.1 Generating Pulsed-Echo Signals

1. Start the MUPB001 - HV7321_MD1730 GUI.

- make sure DC-IN LED is ON when the power input is connected to the MUPB001

2. Switch on the MUPB001 to power the board.

- check that PWR_OK, FPGA_OK LEDs are ON, and the USB_Fault LED is OFF.



- the Connection Status indicator (3.4.16) must show “Connected” (in green).

3. Set the default state in Pulsed-Echo Voltages group box (3.4.10) to RTZ (Ground) by making sure RTZ is selected in the Default State drop-down list box.

4. Set the transmit clock configuration to 200 MHz by making sure 200 MHz is selected in the Transmit Clock Config (MHz) group box. Click the Initialize MUPB button to activate the MUPB clock (3.4.9).

5. Make sure the default value of 200000 ns is input into the Line Duration (ns) text box (3.4.3).

6. Check the Log Status screen area (3.4.5) and look for the confirmation message that the initialization started and completed with no errors.

7. Check that the default transmission mode, Pulsed_Echo, is selected in the Transmission Mode list box (3.4.11).

8. In the Pin State group box, select PWS, OEN and REN by selecting the corre-sponding check boxes. Leave MODE unselected. Click the Send button (3.4.7).

9. In the Transmit Entry group box set the Entry Index (entries to transmit) to 1 and the TX Output Freq Divisor to 20 (3.4.8). This sets one group of pulses during the line duration, and a pulse of 100 ns.

10. Set the relative delay between channels by entering the following values into the Channels (0-3) Delay (ns) text boxes: 30, 60, 90, 120. Set the waveform length by inputting these values into the Channels (0-3) Waveform (Length Up to 32 Characters) text boxes: 1032R, 1010R, 3232R, 0123R. See Figure 3-13.

FIGURE 3-13: Transmit Entry Group Box Configured for Pulsed-Echo.

11. Click the Start/Stop button (3.4.6).

12. An oscilloscope screenshot of the waveform generated is shown in Figure 3-14.



FIGURE 3-14: Pulsed-Echo Output.

3.7.2 Generating CW Mode-0 Signals


- connect the +12V power connector to MUPB001 board and make sure that the green DC_IN LED is ON indicating that the power connection is successful.

2. Switch on the MUPB001 to power the board.



3. Set the default state in Pulsed-Echo Voltages group box (3.4.10) to RTZ (Ground) by making sure RTZ is selected in the Default State drop-down list box.



6. Check that the CW Mode-0 (Internally by HV7321) transmission mode is selected in the Transmission Mode list box (3.4.11).

7. In the Pin State group box, select OEN and REN by selecting the corresponding check boxes. Leave PWS and MODE unselected. Click the Send button (3.4.7).

- make sure MDEN and OEN LEDs on HV7321 Ultrasound TX Pulser Evalua-tion Board are ON.

8. In the CW Channels group box (3.5.1), enter 20 in the CW0 Output Freq Divi-sor. This sets a CW frequency of 5 MHz. Activate CH0, CH2 and CH3 by clicking the corresponding check boxes. Set the delay between channels as CH0 Delay(ns):10, CH2 Delay(ns):20, CH3 Delay(ns):40.



CH0 CH3



FIGURE 3-15: CW Mode-0 Output.

3.7.3 Generating CW Mode-1 Signals


- connect the +12V power connector to MUPB001 board and make sure that the green DC_IN LED is ON indicating that the power connection is successful.

2. Switch on the MUPB001 power switch to power the board.





5. Check that the CW Mode-1(Externally by MD1730) transmission mode is selected in the Transmission Mode list box (3.4.11).

6. In the Pin State group box, select EN and SPIB by selecting the corresponding check boxes. Leave CBE0 and CBE1 unselected (3.4.7).

- make sure MODE, MDEN and OEN LEDs on HV7321 Ultrasound TX Pulser Evaluation Board are ON.

7. In the Frequency, CWFD (0 – 255) text box (3.6.3) enter 20. This provides a CW frequency of 5 MHz. Click outside the text box to update the value shown in the CW Frequency (kHz) text box to 5000 kHz.

8. Enable CH0, CH2, and CH3 in the CW Channels group box (3.6.1). Make sure these channel status indicators are green. Set the channel delay as follows:

- CH0 Delay(ns):10 by entering 2 in the CH PHD (0-255) text box correspond-ing to CW0

- CH2 Delay(ns):20 by entering 4 in the CH PHD (0-255) text box correspond-ing to CW2

- CH3 Delay(ns):40 by entering 8 in the CH PHD (0-255) text box

CH3CH2



corresponding to CW3.



FIGURE 3-16: CW Mode-1 Output (VCW+ = +5V, VCW- = -5V).

CH0



NOTES:



EVALUATION BOARD
USER’S GUIDE
Chapter 4. PCB Design and Layout Notes

4.1 PCB LAYOUT TECHNIQUES FOR HV7321 & MD1730 ULTRASOUND PULSER

The HV7321 is a high-voltage, high-current and high-frequency nanosecond pulse generator integrated circuit. The PCB design and layout are important key develop-ment steps to guarantee the success of the design implementation.

4.1.1 High-Voltage, High-Speed Grounding, and Layout Techniques for the HV7321

The large thermal pad at the bottom of the HV7321 device is internally connected to the IC substrate (VSUB). This thermal pad should be connected to 0V or GND externally on the PCB.

The designer needs to pay attention to the connecting traces on the output TX0-3, as these are the high-voltage and high-speed traces. In particular, controlled impedance of 50to the ground plane and more trace spacing needs to be applied in this situation.

High-speed PCB trace design practices that are compatible with about 200 MHz oper-ating speeds are used for the HV7321 Ultrasound TX Pulser Evaluation Board PCB layout. The internal circuitry of the HV7321 can operate at rather high frequencies, with the primary speed limitation being the load capacitance.

Because of the high-speed and high-transient currents that result when driving capacitive loads, the supply-voltage bypass capacitors, and the driver to the FET gate-coupling capacitors should be as close to the pins as possible. The GND pin should have low inductance feed-through via connections that are connected directly to a solid ground plane. Ground plane has to be the second layer of the PCB.

It is advisable to minimize the trace length to the ground plane, and insert a ferrite bead in the power supply lead to the capacitor to prevent resonance in the power supply lines. For applications that are sensitive to jitter and noise, and when using multiple HV7321 ICs, insert an additional ferrite bead between the supply lines of each chip.

To reduce inductance particular attention should be paid to minimizing trace lengths and using sufficient trace width. Surface-mount components are highly recommended. Since the output impedance of the HV7321 high-voltage power stages is very low, in some cases, it is desirable to add a small value resistor in series with the TX3-0 outputs to obtain better waveform integrity at the load terminals after ultrasound probe long cables.

The impedance of the output resistors added to that of the HV7321 power stage output should match the probe cable impedance since at the other end of the transmission line there are normally piezoelectric elements with large parasitic capacitance to ground. However, this reduces the output voltage slew rate at the terminals of a capacitive load.

Attention should be paid to the parasitic coupling from the outputs to the input signal terminals of the HV7321. This feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 2.5V, even small coupling voltages may cause problems. The use of a solid ground plane and good power and signal layout practices can prevent this problem.



The user should also ensure that the circulating ground return current from a capacitive load cannot react with common inductance to create noise voltages in the input logic circuitry.

4.1.2 High-Frequency Differential Clock, and Low Phase Noise PCB Layout Techniques for the MD1730

The low phase noise feature has to be implemented on three aspects of the design: on the IC, on the signal clock source and on the PCB layout.

Choosing low-ESR and low-ESL decoupling capacitors, and implementing a low-EMI/RFI PCB layout, helps get the best phase noise performance on the MD1730.

The clock input of the MD1730 is designed to take LVDS, LVCMOS 2.5V or SSTL 2.5V differential signals. The suggested clock line traces impedance reference to GND plane is 50, or 100differentially.

In case multiple MD1730s need be used on the same PCB, it is highly recommended to use a differential clock buffer to drive the clock bus. The clock bus should consist of a 50/50coupled differential clock line pair. The 50termination resistor on both lines to GND should be placed next to the last device clock input pin. If the clock source or buffer is powered by a higher than 2.5V VCC, then AC coupling should be used. Refer to Figure 4-1 for details.

FIGURE 4-1: AC Coupling for MD1730 Differential Clock Inputs.

4.1.3 Selecting the Decoupling Capacitors

The voltage-supply pins (VLL, VDD, VGP, VGN, VPP0/1 and VNN0/1) can provide fast tran-sient currents of up to 2.0 to 2.8A each. Each supply pin should be connected to a low-impedance bypass capacitor. A surface-mounted ceramic capacitor of 1.0-to-2.2 μF capacitance should be used.

When it comes to capacitor voltage rating, only the capacitors from VPP0/1 and VNN0/1 pins to GND must be 100V high-voltage type. Low-voltage rating capacitors of 10 to 16V can be used for VLL, VDD, VGP, VGN, CPOS, CNEG to GND, CPF0/1 to VPP0/1, and CNF0/1 to VNN0/1 respectively.

Additional attention should be paid to what type of ceramic capacitor is selected for these bypass capacitors with regard to the low-impedance, low-voltage and low-temperature coefficient, including the very fast dV/dt of the pulse rising and falling edges. For these purposes it is recommended to use X7R, and X5R capacitors or other more advanced multilayer-ceramic types.

Differential Clock Source

+3.3V

C54 0.1 μF

C53 0.1 μF

CLK_P

CLK_N

R40100

R40100

R34100

R30100

TP56

TP58 3

2

CLK

CLK

GN

DG

ND

GN

D

37 33 5

C55 1 μF

R420

VLL

10 SDOSDICS

98

SCK7

U2MD1730

TXRW13SPIB36

EN

1

CB

E1

11C

BE

035

VLL

4

VLL

V DD

6

VDD

V GP

32

VGP

V CW

+28

VCW+

V CW

+18

CKB0 34

CW0 27CW1 26CW2 25CW3 24

CKB1 12

CW4 22CW5 21CW6 20CW7 19

CP

F29

CP

F17

CN

F31

CN

F15

V CW

-V

CW

-

V GN

3016

V GN

1423



4.1.4 Return-Current Design on PCB Layout

Many EMI problems associated with high-speed circuits occur due to improper design of the return-current path. PCB designers often put a lot of effort into carefully designing traces with the proper length or proper transmission line impedance but neglect the return-current path that completes the current loop. Such EMI problems can usually be avoided if sufficient attention is paid to the return-current path.

The decoupling capacitor should be placed on the PCB as closely as possible to the pin being decoupled. However, the location on the PCB to install the decoupling capac-itor is of equal importance. Usually a decoupling capacitor is placed where the high-voltage, high-speed return current ends. In that sense, the placement of the decoupling capacitor will also affect the EMI/RFI performance. The high-peak return current will travel, on the ground plane, from the load back to the decoupling capacitor where the ground via or vias are. The HV7321 pulser output traces on top layer or bot-tom layer carry high-peak currents, directing the return current to the ground plane, by means of the electromagnetic coupling effect. Therefore, these output traces together with the ground plane form the transmission line that supports a transverse electromag-netic (TEM) wave. In the region where the TEM pulse exists there is a time-varying electric field between the trace and the ground reference plane, the same as in simple micro-strip and strip-line cases. The electric field requires current to be in the two con-ductors. This current will be in opposite directions in the conductors, and must exist simultaneously with the pulse. The current must flow in both conductors as the pulse moves down the trace. Any discontinuity or break in these current paths, in either the trace or the ground plane, will affect the current, and compromise the signal-integrity or the EMI/RFI performance.

It is very important to keep the low-voltage logic signal traces, the middle-voltage gate driver (such as VDD, VGP, VGN, CPF, CNF), and the high-voltage output stage traces between their decoupling capacitors to the HV7321 respective pin and ground return-current paths all electromagnetically independent of each other and not too close together. These are the challenges of a good PCB layout design while maintaining ground-integrity and keeping the solid ground plane.



NOTES:



EVALUATION BOARD
USER’S GUIDE
Appendix A. Schematic & Layouts

A.1 INTRODUCTION

This appendix contains the following schematics and layouts for the HV7321 Ultra-sound TX Pulser Evaluation Board (ADM00659) and for the MUPB001 Microchip Ultra-sound Platform Board (ADM00679):

• HV7321 Ultrasound TX Pulser Evaluation Board:

- ADM00659 – Schematic

- ADM00659 – Top Copper and Silk

- ADM00659 – Top Copper

- ADM00659 – Inner 1 – GND

- ADM00659 – Inner 2 – PWR

- ADM00659 – Bottom Copper

- ADM00659 – Bottom Copper and Silk

• MUPB001 Microchip Ultrasound Platform Board:

- ADM00679 – Schematic (Connection)

- ADM00679 – Schematic (Power Supply)

- ADM00679 – Schematic (USB to SPI)

- ADM00679 – Schematic (Programmable Clock)

- ADM00679 – Schematic (FPGA)

- ADM00679 – Schematic (FPGA Decoupling Capacitors)

- ADM00679 – Schematic (Connectors)

- ADM00679 – Top Silk

- ADM00679 – Top Copper and Silk

- ADM00679 – Top Copper

- ADM00679 – Inner 1




- ADM00679 – Bottom Copper

- ADM00679 – Bottom Copper and Silk

- ADM00679 – Bottom Silk


HV

7321 Ultraso

un

d T

X P

ulser E

valuatio

n B

oard

User’s G

uid

e

DS

20005656B

-page 46

2016 M

icrochip Technolo

gy Inc.

RX0

RX0

R20.1

TP1

RX0

C5

1u 100V0V

RX1RX1

TP9

RX2RX2

VPP1

C6

1u 100V

RX3RX3

0V

TP17

R350

P36

J6

12

TP65

COM

C181u 10V

TP30

VNN1

st VPP0>=VPP1 & VNN0<=VNN1)

VPP1

J13

1 2 3

D15B1100-13

21 D16

B1100-13

21

R24499

J7

12

R2350

C19220p 250V

R161K 1W

NN0

J8

12

CPF

1C

PF1

33

TX1 42

RX1 43

RX0 45

TX2 39

CPOS41

RX336

RGND44

RGND37

RX2 38

TX335

TX0 46

J2012

TX1

J9

12

J2112

TP15

3

21

C361u 10V

J2212

V

C171u 10V

C290.22

VDD

+

-

U4AD8099

3

26

74

1

8 5

D9

BAV99/SOT_1

3

1 2

C420.01

C410.01

LNAOUT

C432pF

(+5V)

R29499

R281K

TP45R27249

3510V

TX0

0 to +/-100V VPP1/VNN1

J14

R1450 J21

23

R1750

C21220p 250V

R221K 1W

TX2

R2050

C20220p 250V

R191K 1W

RX3

J31

23

TP50

J41

23

D19B1100-13

21

TX3

C11220p 250V

R131K 1W

D20B1100-13

21

TP4

RX2

VNN0

TP8

RX1

VPP0

J11

23

J1912

A.2 ADM00659 – SCHEMATIC

TP27

VCC

R12

0

TP18

D17A

16

(+2.5V)

C301u 10V

POS2NEG2

R420

C141u 10V

TP13

C242u 16V

VDF

C39

1u 100V

PWSMODE

MDEN

TP16

MOSI

SCLKCSB

MISO

VGP

PWR

C511nF

VGP

C47

2u 16V

VGN

D17B43

NEG3SEL3

VLL

C221u 10V

D8B

43

R250.1

TP57

C49

2u 16V

C121u 10V

C540.1

VLL

POS3

C41u 10

PWR

SDO

TP38

R260.1

TP20

TP59

C131u 10V

R38200

SPIB

TP21

TP24

C321u 10V

J5 TE6469169-1

C1C1

D1D1

DG1DG1

C2C2

D2D2

DG2DG2

C3C3

D3D3

DG3DG3

C4 C4

D4 D4

DG4 DG4

C5 C5

D5 D5

DG5 DG5

C6 C6

D6 D6

DG6 DG6

C7 C7

D7 D7

DG7 DG7

C8 C8

D8 D8

DG8 DG8

C9 C9

D9D9

DG9DG9

C10C10

D10D10

DG10DG10

A1A1

B1B1

BG1BG1

A2A2

B2B2

BG2BG2

A3A3

B3B3

BG3BG3

A4A4

B4B4

BG4BG4

A5A5

B5B5

BG5BG5

A6A6

B6B6

BG6BG6

A7A7

B7B7

BG7BG7

A8A8

B8B8

BG8BG8

A9A9

B9B9

BG9BG9

A10A10

B10B10

BG10BG10

OTP

TXRW

TP25

C331u 10V

C46

1u 10V

U2

MD1730

GN

D33

GN

D5

VG

N14

VC

W-

30

CN

F15

CW6 20CW5 21CW4 22

CW3 24CW2 25CW1 26CW0 27CP

F29

VC

W+

18

VGP

32VD

D6

VLL

4

EN

1

TXRW13 SPIB36

SCK7

SDI9 CS8

SDO10

CLK2

CLK3

CB

E035

CB

E111

VG

N23

CW7 19

VC

W+

28

CP

F17

CKB0 34

CKB1 12

CN

F31

VC

W-

16

GN

D37

TP63

VGP

MH1 MH2 MH3 MH4

TP26

VLL

TP6

VNN1

C40

1u 10

VLL

PWR

J23 TE6469169-1

C1C1

D1D1

DG1DG1

C2C2

D2D2

DG2DG2

C3C3

D3D3

DG3DG3

C4C4

D4D4

DG4DG4

C5C5

D5D5

DG5DG5

C6 C6

D6 D6

DG6 DG6

C7 C7

D7 D7

DG7 DG7

C8 C8

D8 D8

DG8 DG8

C9 C9

D9 D9

DG9 DG9

C10 C10

D10 D10

DG10 DG10

A1A1

B1B1

BG1BG1

A2A2

B2B2

BG2BG2

A3A3

B3B3

BG3BG3

A4A4

B4B4

BG4BG4

A5A5

B5B5

BG5BG5

A6A6

B6B6

BG6BG6

A7A7

B7B7

BG7BG7

A8A8

B8B8

BG8BG8

A9A9

B9B9

BG9BG9

A10A10

B10B10

BG10BG10

C571u 10V

TP64

TP10

D11A

16

R391K

TP37

CKB1

TP22

TP28

C48

2u 16V

(+4.7V)

OTP

T

TP40

PWSMODE

R1850

R31INF

TP44

C261u 10V

CKB0

SDO

VCC

TP23

R34100

(Note: Mu

C251u 10V

VCW+

TP46

D5RED

12

R35INF

(+10V)

CLK_P

(-10V)

CW3

(+5V)

TP32

TP47

C151u 10V

OSCEN

0 to +/-100 VPP0&VNN0

V

R37INF

VPP0

CW2

VGN

TP48

MODEPWS

RENOEN

TP33

TP39

(+5V)

C50

2u 16V

U1

HV7321K6

PWS7

SEL062

OTP20

VN

N2

30

VN

N2

51

CN

F027

CN

F054

48

VPP

024

VPP

056

POS064

GND59 GND9

NEG063

POS214

SEL316

NEG213

SEL12

POS14

CLK8

REN11

NEG13

OEN6

VLL

10

SEL212

VN

N1

50

CN

F132

CN

F149

VN

N1

31

CN

EG40

MODE61

VN

N0

28

VN

N0

29

VN

N0

52

VN

N0

53

CWIN215

CWIN01

CWIN15

CWIN319

VD

D21

VD

D60

NEG317

POS318

VPP

134

VPP

147

CPF

055

CPF

026

VPP

057

VPP

025

VGP

23

VG

N58

GND22

VCW-

CKB1

C1

1u 10V

J12

1 2 3

CBE0

OTP

VPP0

VNN0

C3

1u 100V

TP49

TP11

CW1

C37

1u 100V

SEL2

POS3NEG3

SEL3

J10

1 2 3 4 5 6

VDD

OENREN

C530.1

D10A

16

SEL0

TP51

SYNC

D13B1100-13

21

CW0

D11B

43

R30100

C2

1u 10V

D14B1100-1

C272u 16V

TP53

VCW+ VCW-

J11

1 2 3(DAP=0)

R36INF

VLL

CSB

C112

0.1MISO

U625AA010A

CS1

SO2

WP3

VSS4

SI5SCK6HOLD7VCC8

SCLKMOSIR44

0

C161u 10

R5

200

MDENCBE0 OENMODE PWS

R11

200

D7YLW

12

D3YLW

12

R9

200

C311u 10V

R7

200

R10

200

D6RED

12

R6

200

D4YLW

12

(+5V)

D2GRN

12

D1RED

12

TP56

R8

200

SEL0

C7

0.22

OTP

VLL

(Up to 200MHz)

SCK

C341u 10V

C1u

TP58

MDEN

TXTRIG TXRWRXTRIG

SPIB

CBE1CBE0

C520.01

POS2NEG2

MDEN

TP62

R3350

R430

1

23

D18

BAV99/SOT_1

3

1 2

CS

CLK_N

TP42

OSCEN

C44

1u 10V

TP2

CW4SDI

VGN

CLK_P

TP43

D8A

16

(+2.5V)

SEL1SEL0

TP35

C551u 10V

TP29

TP12

J16

12

J15

12

J18

12

C231u 10V

J17

12

VDD

CBE0

TP31

VCW+

TP66

C38

1u 100V

CLK_N

TP41

C91u 10V

POS1NEG1

SEL2

TP34

C282u 16V

X1

FXO-LC720R-240

EN1

NC2

GN

D3

OUT25

OUT14

VD

D6

CW7

(-5V)

C81u 10V

TP67

TP52

CW6

VCW-

SCKCS

SDI

R40100

TP3

TP61

D12B

43

TP68

C45

1u 10V

C561u 10V

TP54

R321K

TP69

TP5

TP14NEG0SEL0

POS1NEG1SEL1

POS0

CW5

R10.1

CBE1

TP60

R41100

POS0NEG0

OEN

D12A

16

TP55

VDD

C102u 16V

TP19

SYNC

D10B43

+3V3

TP7

TP70

OUT1

VLLU3MCP1727-2502E/SN

VIN1

GN

D4

VOUT8

SENSE7

VIN2

SHDN3

PW

RG

D5

CD

ELAY

6


A.3 ADM00659 – TOP COPPER AND SILK

A.4 ADM00659 – TOP COPPER



A.5 ADM00659 – INNER 1 – GND

A.6 ADM00659 – INNER 2 – PWR



A.7 ADM00659 – BOTTOM COPPER

A.8 ADM00659 – BOTTOM COPPER AND SILK


HV

7321 Ultraso

un

d T

X P

ulser E

valuatio

n B

oard

User’s G

uid

e

DS

20005656B

-page 50

2016 M

icrochip Technolo

gy Inc.

IO_2V5_0_PIO_2V5_0_N







IO_2V5_11_PIO_2V5_11_N

IO_2V5_13_PIO_2V5_13_N




IO_2V5_10_PIO_2V5_10_N

IO_2V5_12_PIO_2V5_12_N

IO_2V5_14_NIO_2V5_14_P

IO_3V3_1IO_3V3_2IO_3V3_3IO_3V3_4IO_3V3_5

CLK4

CLK2_PCLK2_N

IO_2V5_15_NIO_2V5_15_P

IO_2V5_16_NIO_2V5_16_P

IO_2V5_17_NIO_2V5_17_P

IO_2V5_18_NIO_2V5_18_P

IO_2V5_19_NIO_2V5_19_P

IO_2V5_20_NIO_2V5_20_P

IO_2V5_21_NIO_2V5_21_P

CLK3_PCLK3_N

CLK5

IO_3V3_6_PIO_3V3_6_NIO_3V3_7_PIO_3V3_7_NIO_3V3_8_PIO_3V3_8_NIO_3V3_9_PIO_3V3_9_NIO_3V3_10_PIO_3V3_10_NIO_3V3_11_PIO_3V3_11_NIO_3V3_12_PIO_3V3_12_NIO_3V3_13_PIO_3V3_13_NIO_3V3_14_PIO_3V3_14_NIO_3V3_15IO_3V3_16IO_3V3_17

Connector.SchDoc

PNPNPNPNPN

PN

NP

PN

NP

PN

NP

PN

CLK2_PCLK2_N

CLK4

PNPNPNPNPN

A.9 ADM00679 – SCHEMATIC (CONNECTION)

MUPB001_PWR.SchDoc

SCK

MISOMOSI

USB_CONFIG

CSBAR

FPGA_DONE

FPGA_RSTSPI_RST

EXT_INT

GP8

GP4GP7

USB_TO_SPI.SchDoc

CTRL_OEC

CTRL_SDISDO

CTRL_OEDCTRL_OEB

CTRL_SCKCTRL_CSB

CLK0_N

CLK1_PCLK1_N

CLK2_PCLK2_N

CLK4

CLK0_P

CLK3_PCLK3_N

CLK5

40MHz_N40MHz_P

PROG_CLK.SchDoc

PROGB_IN

FPGA_DONE

SCKMOSIMISO

CSBAR

FPGA_RSTSPI_RSTUSB_CONFIG

SDO

CTRL_SCKCTRL_CSB

CTRL_OECCTRL_OEDCTRL_OEB

CLK0_PCLK0_N

IO_2V5_0_PIO_2V5_0_NIO_2V5_1_PIO_2V5_1_N

IO_2V5_2_PIO_2V5_2_NIO_2V5_3_PIO_2V5_3_NIO_2V5_4_PIO_2V5_4_NIO_2V5_5_PIO_2V5_5_N

IO_2V5_6_PIO_2V5_6_NIO_2V5_7_PIO_2V5_7_NIO_2V5_8_PIO_2V5_8_N

IO_2V5_10_PIO_2V5_10_N




GP4GP7

EXT_INT

CLK1_PCLK1_N

CTRL_SDI

IO_2V5_15_NIO_2V5_15_P

IO_2V5_16_NIO_2V5_16_P

IO_2V5_17_NIO_2V5_17_P

IO_2V5_18_NIO_2V5_18_P

IO_2V5_19_NIO_2V5_19_P

IO_2V5_20_NIO_2V5_20_P

IO_2V5_21_NIO_2V5_21_P


IO_3V3_10_PIO_3V3_10_NIO_3V3_11_PIO_3V3_11_NIO_3V3_12_PIO_3V3_12_NIO_3V3_13_PIO_3V3_13_NIO_3V3_14_PIO_3V3_14_N

40MHz_N40MHz_P

IO_3V3_15IO_3V3_16IO_3V3_17

FPGA01.SchDoc

SPI_CSBARSPI_SCKSPI_MOSISPI_MISO

FPGA_RSTSPI_RSTUSB_CONFIG

EXT_INTFPGA_DONE

PROGB_IN

GP4GP7

CTRL_OEC

CLK0_PCLK0_N

CLK1_PCLK1_N


IO_2V5_1_NIO_2V5_1_P



IO_2V5_10_IO_2V5_10_IO_2V5_11_IO_2V5_11_IO_2V5_12_IO_2V5_12_IO_2V5_13_IO_2V5_13_IO_2V5_14_IO_2V5_14_


CLK2_PCLK2_N

CLK4

CTRL_OEDCTRL_OEB

CTRL_SCKCTRL_CSBSDOCTRL_SDI

IO_2V5_15_IO_2V5_15_

IO_2V5_16_IO_2V5_16_

IO_2V5_17_IO_2V5_17_

IO_2V5_18_IO_2V5_18_

IO_2V5_19_IO_2V5_19_

IO_2V5_20_IO_2V5_20_

IO_2V5_21_IO_2V5_21_

CLK3_PCLK3_N

CLK5

40MHz_QA1_N40MHz_QA1_P

IO_3V3_6_PIO_3V3_6_NIO_3V3_7_PIO_3V3_7_NIO_3V3_8_PIO_3V3_8_NIO_3V3_9_PIO_3V3_9_NIO_3V3_10_IO_3V3_10_IO_3V3_11_IO_3V3_11_IO_3V3_12_IO_3V3_12_IO_3V3_13_IO_3V3_13_IO_3V3_14_IO_3V3_14_

2016

Microchip T

echnology Inc.D

S20005656B

page-51

A.

GND_D

3V3_VDD

GND_D

3V3_CLK

10uF10V0805

C61

10uF10V0805

C65

0.1uF50V0603

C62

0.1uF50V0603

C66

10k06031%

R29

69.8k06031%

R26

GND 4

CDELAY 6ADJ 7

VOUT 8

EP 9

ADJ DFN-8

GND 4

CDELAY 6ADJ 7

VOUT 8

EP 9

ADJ DFN-8

Via_2.5x1.5

TP5

Via_2.5x1.5

TP4

ia_2.5x1.5

TP1

P

J

10.7k06031%

R32

82k06031%

R31

(Supply to Ripple Blocker)

D430V

D630V

10 ADM00679 – SCHEMATIC (POWER SUPPLY)

23

1

SLIDE SPDT

SW1

GND_D

VIN

GND_D

GND_D

D5V

GND_D

D5V

GND_D

D5V

GND_D

D5V

PG_3

V3_V

DD

D5V

GND_D

GND_D

1V2_VCCINT

D5V

GND_D

GND_D

2V5_VDD

D5V

PG_1

V2_V

CCIN

T

D5V

GND_D

PG_3V3_CLK

PG_3V3_CLK

10uF10V0805

C51

10uF10V0805

C55

10uF10V0805

C53

10uF10V0805

C57

10uF10V0805

C59

10uF10V0805

C63

10uF10V0805

C4310uF10V0805

C4410uF10V0805

C4510uF10V0805

C46

0.1uF50V0603

C52

0.1uF50V0603

C56

0.1uF50V0603

C54

0.1uF50V0603

C58

0.1uF50V0603

C60

0.1uF50V0603

C64

0.1uF50V0603

C42

0.1uF50V0603

C5010uF35V1206

C4710uF35V1206

C4810uF35V1206

C49

22000pF50V0603

C41

10k06035%

R23

10k06035%

R24

10k06035%

R30

10k06031%

R22

10k06031%

R28

390R06035%

R19

390R06035%

R27

1k06035%

R18

51k06031%

R25

19.1k06031%

R17

39k06031%

R16

8.66k06031%

R21

VIN1

VIN2

SHDN3

PWRGD5

U6

MCP172X

VIN1

VIN2

SHDN3

PWRGD5

U7

MCP172X

VIN1

VIN2

SHDN3

GND 4PWRGD5

CDELAY 6ADJ 7

VOUT 8

EP 9

U5

MCP172X ADJ DFN-8

VIN1

VIN2

SHDN3

GND 4PWRGD5

CDELAY 6ADJ 7

VOUT 8

EP 9

U4

MCP172X ADJ DFN-8B

OO

ST10

SGN

D4

VFB 5EN9

SW 12VIN2

BO

OST

SGN

D

VFBEN

SWVIN

PGN

D14

PG 8

EP17

VIN3

PGN

D15

SW 13

SW 16

SW 1U3

GREENLD4

GREENLD2

ON-POWER ON

GND_D

20BQ030P

D1

Via_2.5x1.5

TP3

Via_2.5x1.5

TP2

V

1 2L1

XAL6060

231

OWER 2.5mm

6

3.6V

GND_DGND_D

D330V

D530V

D230V

HV

7321 Ultraso

un

d T

X P

ulser E

valuatio

n B

oard

User’s G

uid

e

DS

20005656B

-page 52

2016 M

icrochip Technolo

gy Inc.

MHz

ND_DGND_D

GND_D

GND_D

GND_D

Ground Posts for Scope Probe ground

J10 J11

J12 J13

A.11 ADM00679 – SCHEMATIC (USB TO SPI)

GND_D

ID 4

VBUS 1

GND 5

D- 2

D+ 3

0

USB MINI-B FemaleJ7 VDD 1

OSC1 2

OSC2 3

RST 4

GP0 5

GP1 6

GP2 7

GP3 8

MOSI 9

GP4 10SCK11 GP512 MISO13 GP614 GP715 GP816 VUSB17 D-18 D+19 VSS20 VDDOSC1OSC2

RSTGP0GP1GP2GP3

MOSIGP4SCK

GP5MISOGP6GP7GP8VUSBD-D+VSS

U9

MCP2210 SSOP-20

GND_D

2

31 12

X1

OSC1OSC2

G

USB_D-USB_D+

USB_D+USB_D-

3V3_VDD

3V3_VDD

0.1uF25V0603

C104

GND_D

4.7uF16V1206

C1030.1uF25V0603

C106

GND_D

SCK

MISOMOSI

10k06035%

R50

REDLD5

GND_D

150R06035%

R51

USB_CONFIG LED, ON- SUSPEND, OFF - ACTIVE

USB_CONFIG

CSBARFPGA_DONEFPGA_RST

SPI_RSTEXT_INT

GP8

4.7uF16V1206

C105

GP4

GP7

2016

Microchip T

echnology Inc.D

S20005656B

page-53

A.

CLK2_N

CLK0_P

CLK0_N

CLK2_P

252627282930313233343536

GND_DCTRL_OEB

75k06031%

R36

3V

40MHz_P

40MHz_N

0.1uF16V0603

C67

0.1uF16V0603

C68

INFR34

INFR35

GND_D

GND_D

100R06031%

R20

0.1uF16V0603

C92

0.1uF16V0603

C94

100R06031%

R40

G

3V

G

3V

GVDD

VDDOAB

VDDOAB

DNI

DNI

VDDOAB

0R0603

R49

0R0603

R52

12 ADM00679 – SCHEMATIC (PROGRAMMABLE CLOCK)

CLK4

VDDAP21

VDD2

QC13

VDDOC4

/QC15

QC26

/QC27

OEC1/2/38

QD19

VDDOD10

/QD111

VSS12

OED

1/2/

313

VD

DO

D14

QD

315

/QD

316

GN

D17

SCK

18

CSB

19

SDO

20

SDI

21

QB

222

VD

DO

B23

/QB

224

OEB1/2/3VSSQB1

/QB1OEA1/2/3VDDOA

QA2/QA2

VDDOAQA1

/QA1VDDV

DD

AP1

37V

SS38

REF

IN1

39/R

EFIN

140

VD

DI1

41V

DD

I242

XTA

L_X

IN43

XTA

L_O

UT

44R

EFIN

245

/REF

IN2

46V

SS47

VSS

48EP

AD

49 U10

SM803004

13X2XTAL-40MHz

GND_D

GND_DGND_D

GND_D

CTRL_OEC

CTRL_OED

3_CLK

0.010uF25V0603

C984700pF50V0603

C99

VDDOAB

GND_D

CTRL_SCKCTRL_CSB

SDOCTRL_SDI

0.1uF16V0603

C93

0.1uF16V0603

C95

INFR39

INFR41

GND_D

GND_D

CLK3_P

CLK3_N

CLK1_P

CLK1_N 0.1uF16V0603

C82

0.1uF16V0603

C81

100R06031%

R37

CLK5

ND_D

4.7uF16V0603

C964.7uF16V0603

C97

3_CLK

0.010uF25V0603

C854700pF50V0603

C86

VDDOCD

GND_DND_D

4.7uF16V0603

C844.7uF16V0603

C83

3_CLK

0.010uF25V0603

C714700pF50V0603

C72

VDD

GND_D

ND_D

4.7uF16V0603

C694.7uF16V0603

C70

VD

D

VDD

VD

D

VD

DO

AB

VD

DO

CD

VDDOCD

VDDOCD

DNI

DNI

10k06031%

R38

10k06031%

R33

10k06031%

R4210000pF50V0603

C10010000pF50V0603

C101

10000pF50V0603

C8810000pF50V0603

C87

10000pF50V0603

C7310000pF50V0603

C7410000pF50V0603

C7510000pF50V0603

C7610000pF50V0603

C7710000pF50V0603

C78

10000pF50V0603

C91

10000pF50V0603

C102

VOUT 1VOUTADJ 2

GND 3EN4 VIN5 VIN6U8

MIC94325YMT-TR

VOUT 1VOUTADJ 2


MIC94325YMT-TR

VOUT 1VOUTADJ 2


MIC94325YMT-TR

100k06031%

R43

10000pF50V0603

C107

100k06031%

R45

10000pF50V0603

C108

100k06031%

R47

10000pF50V0603

C109

D730V

D830V

D930V

1/10 W78.7k1%

R44

1/10 W78.7k1%

R46

1/10 W78.7k1%

R48

GND_D

GND_D

HV

7321 Ultraso

un

d T

X P

ulser E

valuatio

n B

oard

User’s G

uid

e

DS

20005656B

-page 54

2016 M

icrochip Technolo

gy Inc.

GND_D

1V2_VCCINT

3V3_VDD

3V3_VDD

3V3_VDD

2V5_VDD

2V5_VDD

LK0_PLK0_N

2V5_0_P2V5_0_N

2V5_1_P2V5_1_N

2V5_2_P2V5_2_N

2V5_3_P2V5_3_N2V5_4_P2V5_4_N

2V5_5_P2V5_5_N2V5_6_P2V5_6_N

2V5_7_P2V5_7_N

CLK1_PCLK1_N




IO_2V5_13_PIO_2V5_13_N

IO_2V5_14_PIO_2V5_14_N

EchDoc

GND3

VCCO_3 4

GND13

VCCO_3 18

VCCINT 19

VCCAUX 20

GND25

VCCINT 28

VCCO_3 31

VCCAUX 36

VCCO_2 42

GND49

VCCINT 52

VCCAUX 53

GND54

VCCO_2 63

GND68

VCCO_1 76

GND77

VCCO_1 86

VCCINT 89

VCCAUX 90

GND91

GND96

VCCO_1 103

GND108

GND113

VCCO_0 122

VCCO_0 125

VCCINT 128

VCCAUX 129

GND130

VCCO_0 135

GND136

U1A

IO_L74N_DOUT_BUSY_1 74

IO_L74P_AWAKE_1 75

IO_L47N_1 78

IO_L47P_1 79

IO_L46N_1 80

IO_L46P_1 81

IO_L45N_1 82

IO_L45P_1 83

IO_L43N_GCLK4_1 84

IO_L43P_GCLK5_1 85

IO_L42N_GCLK6_TRDY1_1 87

IO_L42P_GCLK7_1 88

IO_L41N_GCLK8_1 92

IO_L41P_GCLK9_IRDY1_1 93

IO_L40N_GCLK10_1 94

IO_L40P_GCLK11_1 95

IO_L34N_1 97

IO_L34P_1 98

IO_L33N_1 99

IO_L33P_1 100

IO_L32N_1 101

IO_L32P_1 102

IO_L1N_VREF_1 104

IO_L1P_1 105

BA

NK

1

U1E

ale

OUT1OUT2

IO_2V5_15_PIO_2V5_15_N

V5_16_PV5_16_N

IO_2V5_17_PIO_2V5_17_N

V5_18_PV5_18_N

IO_2V5_19_PIO_2V5_19_N

V5_20_PV5_20_N

V5_21_PV5_21_N

A.13 ADM00679 – SCHEMATIC (FPGA)

D01

(DNC)2

CLK3

TDI4

TMS5

TCK6

CF7

OE/RESET8

(DNC)9

CE10 GND 11(DNC) 12CEO 13(DNC) 14(DNC) 15(DNC) 16TDO 17VCCINT 18VCCO 19VCCJ 20U2

XCF04S-VOG20C

M0

M1

M0M1

0R0603

R10

0R0603

R15

3V3_VDD

GND_D

**DNI

Default config set to Master Serial M(1:0) = 01

GND_D

3V3_VDD

GND_D

4.7k06035%

R11

4.7k06035%

R14

51RR3 CCLKR

CCLKR

51RR8

3V3_VDD100R

R6

100R

R7GND_D

PROG_B

PROG_B

4.7k06035%

R4

3V3_VDD

TACT SPST

14

23

SW2

GND_D

0R0603

R5PROGB_IN

**DNI (Do Not Install)

PUSHBUTTON TO FORCE THE RECONFIGURATION

FPGA_DONE

4.7k06035%

R2

3V3_VDD

FPGA_DONE

31

2BSS123Q1FPGA_DONE

GND_D

GREENLD1

D5V

330R06035%

R12

FPGA_DONE

INIT_B

4.7k06035%

R1

3V3_VDD

INIT_B

GND_D

22RR9

DIN

DIN

123456

HDR-2.54 Male 1x6

J4 3V3_VDD

FPGA JTAG

GND_D

FPGA_TMSFPGA_TCKFPGA_TDOFPGA_TDI

FPGA_TDOFPGA_TMSFPGA_TCKFPGA_TDI

"DONE" LED

123456

HDR-2.54 Male 1x6

J5 3V3_VDD

PROM JTAG

GND_D

PROM_TMSPROM_TCKPROM_TDOPROM_TDI

PROM_TDIPROM_TMSPROM_TCK

PROM_TDO

4.7kR133V3_VDD

SCKMOSIMISO

CSBARFPGA_RST

SPI_RSTUSB_CONFIG

CC

IO_IO_

IO_IO_

IO_IO_

IO_IO_IO_IO_

IO_IO_IO_IO_

IO_IO_


GP4GP7

EXT_INT

U_FPGA_DECOUPLFPGA_DECOUPLE.S

SUSPEND73

TDO106

TMS107

TCK109

TDI110

U1B

IO_L83N_VREF_3 1

IO_L83P_3 2

IO_L52N_3 5

IO_L52P_3 6

IO_L51N_3 7

IO_L51P_3 8

IO_L50N_3 9

IO_L50P_3 10

IO_L49N_3 11

IO_L49P_3 12

IO_L44N_GCLK20_3 14

IO_L44P_GCLK21_3 15

IO_L43N_GCLK22_IRDY2_3 16

IO_L43P_GCLK23_3 17

IO_L42N_GCLK24_3 21

IO_L42P_GCLK25_TRDY2_3 22

IO_L41N_GCLK26_3 23

IO_L41P_GCLK27_3 24

IO_L37N_3 26

IO_L37P_3 27

IO_L36N_3 29

IO_L36P_3 30

IO_L2N_3 32

IO_L2P_3 33

IO_L1N_VREF_3 34

IO_L1P_3 35

BA

NK

3

U1C

PROGRAM_B_2 37

IO_L65N_CSO_B_2 38

IO_L65P_INIT_B_2 39

IO_L64N_D9_2 40

IO_L64P_D8_2 41

IO_L62N_D6_2 43

IO_L62P_D5_2 44

IO_L49N_D4_2 45

IO_L49P_D3_2 46

IO_L48N_RDWR_B_VREF_2 47

IO_L48P_D7_2 48

IO_L31N_GCLK30_D15_2 50

IO_L31P_GCLK31_D14_2 51

IO_L30N_GCLK0_USERCCLK_2 55

IO_L30P_GCLK1_D13_2 56

IO_L14N_D12_2 57

IO_L14P_D11_2 58

IO_L13N_D10_2 59

IO_L13P_M1_2 60

IO_L12N_D2_MISO3_2 61

IO_L12P_D1_MISO2_2 62

IO_L3N_MOSI_CSI_B_MISO0_2 64

IO_L3P_DO_DIN_MISO_MISO1_2 65

IO_L2N_CMPMOSI_2 66

IO_L2P_CMPCLK_2 67

IO_L1N_M0_CMPMISO_2 69

IO_L1P_CCLK_2 70

DONE_2 71

CMPCS_B_2 72

BA

NK

2

U1D

IO_L66N_SCP0_0 111

IO_L66P_SCP1_0 112

IO_L65N_SCP2_0 114

IO_L65P_SCP3_0 115

IO_L64N_SCP4_0 116

IO_L64P_SCP5_0 117

IO_L63N_SCP6_0 118

IO_L63P_SCP7_0 119

IO_L62N_VREF_0 120

IO_L62P_0 121

IO_L37N_GCLK12_0 123

IO_L37P_GCLK13_0 124







IO_L4N_0 137

IO_L4P_0 138

IO_L3N_0 139

IO_L3P_0 140

IO_L2N_0 141

IO_L2P_0 142

IO_L1N_VREF_0 143

IO_L1P_HSWAPEN_0 144

BA

NK

0

U1F

CTRL_OECCTRL_OEDCTRL_OEB

CTRL_SCKCTRL_CSB

SDO

CTRL_SDI

1

2

RF Coaxial SMA Female

J8

GND_D

1

2

RF Coaxial SMA Fem

J9

GND_D

OUT1 OUT2

OUT1 OUT2

IO_2IO_2

IO_2IO_2

IO_2IO_2

IO_2IO_2

IO_3V3_6_N

40MHz_N40MHz_P

IO_3V3_6_P




IO_3V3_10_NIO_3V3_10_P

IO_3V3_11_NIO_3V3_11_P

IO_3V3_12_NIO_3V3_12_P

IO_3V3_13_NIO_3V3_13_PIO_3V3_14_NIO_3V3_14_P

IO_3V3_15

IO_3V3_16

IO_3V3_17

**DNI

2016

Microchip T

echnology Inc.D

S20005656B

page-55

A.

UX

F

T-B

247nF16V0603

C211000pF50V0603

C221000pF50V0603

C231000pF50V0603

C241000pF50V0603

C251000pF50V0603

C26

04S

F

T-B

947nF16V0603

C371000pF50V0603

C381000pF50V0603

C391000pF50V0603

C40

14 ADM00679 – SCHEMATIC (FPGA DECOUPLING CAPACITORS)

For VCCO_03V3_VDD

33uF10VTANT-B

C1047nF16V0603

C131000pF50V0603

C141000pF50V0603

C151000pF50V0603

C16

GND_D

For VCCO_1

2V5_VDD

33uF10VTANT-B

C1147nF16V0603

C171000pF50V0603

C181000pF50V0603

C191000pF50V0603

C20

GND_D

For VCCO_2

3V3_VDD

33uF10VTANT-B

C2747nF16V0603

C301000pF50V0603

C311000pF50V0603

C32

GND_D

For VCCO_3

2V5_VDD

33uF10VTANT-B

C2847nF16V0603

C331000pF50V0603

C341000pF50V0603

C351000pF50V0603

C36

GND_D

For 1V2_VCCINT1V2_VCCINT

47nF16V0603

C41000pF50V0603

C51000pF50V0603

C61000pF50V0603

C7

GND_D

100uF6.3VTANT-B

C3

For VCCA

3V3_VDD

33u10VTAN

C1

GND_D

1000pF50V0603

C81000pF50V0603

C9

For XCF

3V3_VDD

33u10VTAN

C2

GND_D

HV

7321 Ultraso

un

d T

X P

ulser E

valuatio

n B

oard

User’s G

uid

e

DS

20005656B

-page 56

2016 M

icrochip Technolo

gy Inc.

CLK3_PCLK3_N

A1B1BG1A2B2BG2A3B3BG3A4B4BG5A5B5BG4A6B6BG6A7B7BG7A8B8BG8A9B9BG9A10B10BG10

C1D1

DG1C2D2

DG2C3D3

DG3C4D4

DG4C5D5

DG5C6D6

DG6C7D7

DG7C8D8

DG8C9D9

DG9C10D10

DG10

J2

CONN-1469028

_D GND_D

IO_2V5_15_PIO_2V5_15_N

IO_2V5_17_PIO_2V5_17_N

IO_2V5_19_PIO_2V5_19_N

IO_2V5_21_PIO_2V5_21_N



IO_3V3_11_PIO_3V3_11_N

IO_3V3_13_NIO_3V3_13_P

IO_3V3_16IO_3V3_15

A.15 ADM00679 – SCHEMATIC (CONNECTORS)

A1B1BG1A2B2BG2A3B3BG3A4B4BG5A5B5BG4A6B6BG6A7B7BG7A8B8BG8A9B9BG9A10B10BG10

C1D1

DG1C2D2

DG2C3D3

DG3C4D4

DG4C5D5

DG5C6D6

DG6C7D7

DG7C8D8

DG8C9D9

DG9C10D10

DG10

J1

CONN-1469028

GND_D GND_D

D5V








IO_2V5_11_PIO_2V5_11_N

IO_2V5_13_PIO_2V5_13_N




IO_2V5_10_PIO_2V5_10_N

IO_2V5_12_PIO_2V5_12_N

IO_2V5_14_NIO_2V5_14_P

IO_3V3_1IO_3V3_2

IO_3V3_3IO_3V3_4

IO_3V3_5CLK4

CLK2_PCLK2_N

33uF10VTANT-B

C10.1uF25V0603

C2

GND_D

PWR5V0

CLK5

GND

D5V

GND_D

PWR5V0

IO_2V5_16_PIO_2V5_16_N

IO_2V5_18_PIO_2V5_18_N

IO_2V5_20_PIO_2V5_20_N



IO_3V3_10_PIO_3V3_10_N

IO_3V3_12_PIO_3V3_12_N

IO_3V3_14_NIO_3V3_14_P

IO_3V3_17

33uF10VTANT-B

C900.1uF25V0603

C89


A.16 ADM00679 – TOP SILK

A.17 ADM00679 – TOP COPPER AND SILK



A.18 ADM00679 – TOP COPPER

A.19 ADM00679 – INNER 1



A.20 ADM00679 – INNER 2

A.21 ADM00679 – INNER 3



A.22 ADM00679 – INNER 4

A.23 ADM00679 – BOTTOM COPPER



A.24 ADM00679 – BOTTOM COPPER AND SILK

A.25 ADM00679 – BOTTOM SILK



NOTES:




Appendix B. Bill of Materials (BOM)

TABLE B-1: HV7321 ULTRASOUND TX PULSER EVALUATION BOARD (ADM00659) BILL OF MATERIALS (BOM) (Note 1)

Qty. Reference Description Manufacturer Part Number

28

C1, C2, C8, C9, C12-18, C22, C23, C25, C26, C30-36, C44-46, C55-57

1 µF 16V Ceramic Capacitor X7R 0603 (1608 Metric) 0.063" L x 0.031" W (1.60 mm x 0.80 mm)

TDK Corporation C1608X7R1C105M

8C3-6, C37-40

1 µF 100V Ceramic Capacitor X7S 0805 (2012 Metric) 0.079" L x 0.049" W (2.00 mm x 1.25 mm)

TDK Corporation CGA4J3X7S2A105K125AB

2 C7, C290.22 µF 16V Ceramic Capacitor X7R 0603 (1608 Metric) 0.063" L x 0.031" W (1.60 mm x 0.80 mm)

TDK Corporation C1608X7R1C224K

8C10, C24, C27, C28, C47-50

2.2 µF 16V Ceramic Capacitor X5R 0603 (1608 Metric) 0.063" L x 0.031" W (1.60 mm x 0.80 mm)

TDK Corporation C1608X5R1C225K080AB

4C11, C19, C20, C21

220 pF 200V Ceramic Capacitor C0G, NP0 0805 (2012 Metric) 0.079" L x 0.049" W (2.00 mm x 1.25 mm)

Panasonic® - ECG ECJ-2YC2D221J

3C41, C42, C52

10000 pF 16V Ceramic Capacitor X7R 0603 (1608 Metric) 0.063" L x 0.031" W (1.60 mm x 0.80 mm)

TDK Corporation C1608X7R1C103K

1 C432 pF 50V Ceramic Capacitor C0G, NP0 0603 (1608 Metric) 0.063" L x 0.031" W (1.60 mm x 0.80 mm)

TDK Corporation CGJ3E2C0G1H020C080AA

1 C511000 pF 16V Ceramic Capacitor X7R 0603 (1608 Metric) 0.063" L x 0.032" W (1.60 mm x 0.81 mm)

AVX Corporation 0603YC102KAT2A

3C53, C54, C112


TDK Corporation C1005X7R1A104K050BB

3 D1, D5, D6Red LED Indication - Discrete 2V 0805 (2012 Metric)

Lumex® Inc. SML-LXT0805IW-TR

1 D2Green LED Indication - Discrete 2V 0805 (2012 Metric)

Lumex Inc. SML-LXT0805GW-TR

3 D3, D4, D7Yellow LED Indication - Discrete 2.1V 0805 (2012 Metric)

Lumex Inc. SML-LXT0805YW-TR

5D8, D10, D11, D12, D17

Diode Array 2 Independent Schottky 30V 100 mA Surface Mount 6-TSSOP, SC-88, SOT-363

Diodes Incorporated® BAT54DW-7

Note 1: The components listed in this Bill of Materials are representative of the PCB assembly. The released BOM used in manufacturing uses all RoHS-compliant components.



2 D9, D18Diode Array 1 Pair Series Connec-tion Standard 70V 215 mA (DC) Sur-face Mount SC-70, SOT-323

ON Semiconductor® BAV99WT1G

6D13-16, D19, D20

Diode Schottky 100V 1A Surface Mount SMA

Diodes Incorporated B1100-13F

5J1, J2, J3 J4, J14

SMA Connector Jack, Female Socket 50 Board Edge, End Launch Solder

Cinch Connectivity Solutions

142-0711-821

2 J5, J23CONN HEADER 40POS R/A HM-ZD TIN

TE Connectivity, Ltd. 6469169-1

12J6-9J15-22

2 Positions Header, Unshrouded, Breakaway Connector 0.100" (2.54 mm) Through Hole Gold

Molex® 22-28-4023

5J6J19-22

2 (1 x 2) Position Shunt Connector Black Open Top 0.100" (2.54 mm) Gold


1 J106 Positions Header, Unshrouded Connector 0.100" (2.54mm) Through Hole Gold

TE Connectivity, Ltd. 3-641213-6

3 J11-J133 Positions Header, Unshrouded Connector 0.100" (2.54 mm) Through Hole Gold


4 MH1-MH4Hex Standoff Threaded #4-40 Alumi-num 0.250" (6.35mm) 1/4"

Keystone Electronics Corp.

1891

4 MH1-MH4 Machine Screw Pan Phillips 4-40 B&FTM Fasteners Supply NY PMS 440 0025 PH

1 PCBHV7321 Ultrasound TX Pulser Eval-uation Board – Printed Circuit Board

— 04-10398

4R1, R2R25, R26

RES SMD 0.1 OHM 5% 1/5W 0603Panasonic - ECG ERJ-L03KJ10CV

7

R3, R14 R17, R18 R20, R23 R33

RES SMD 49.9 OHM 1% 1/10W 0603

Panasonic - ECG ERJ-3EKF49R9V

8R5-11R38

RES SMD 200 OHM 5% 1/10W 0603

Panasonic - ECG ERJ-3GEYJ201V

2R12R44

RES SMD 0.0OHM JUMPER 1/10W 0603

Panasonic - ECG ERJ-3GEY0R00V

4R13, R16 R19, R22

RES SMD 49.9 OHM 1% 1/10W 0603

Panasonic - ECG ERJ-3EKF49R9V

2R24R29

RES SMD 499 OHM 1% 1/10W 0603

Panasonic - ECG ERJ-3EKF4990V

1 R27RES SMD 249 OHM 1% 1/10W 0603


3R28, R32 R39

RES SMD 1K OHM 1% 1/10W 0603Panasonic - ECG ERJ-3EKF1001V

2R30R34

RES SMD 100 OHM 1% 1/10W 0603


7 R31, R35-37 DO NOT POPULATE — —

TABLE B-1: HV7321 ULTRASOUND TX PULSER EVALUATION BOARD (ADM00659) BILL OF MATERIALS (BOM) (CONTINUED)(Note 1)




2 R40, R41RES SMD 100 OHM 1% 1/10W 0402

Panasonic - ECG ERJ-2RKF1000X

2 R42, R43RES SMD 0.0OHM JUMPER 1/10W 0402

Panasonic - ECG ERJ-2GE0R00X

3TP50, TP61 TP65

PC Pin Terminal Connector Free Hanging (In-Line) Gold 0.030" (0.76mm) Dia.

Mill-Max Mfg. Corporation

3132-0-00-15-00-00-08-0

1 U1High-Voltage Ultrasound Pulser with T/R Switches

Microchip Technology Inc.

HV7321K6-G

1 U2Ultra-Low Phase Noise Continuous Waveform Transmitter with Beamformer


MD1730-V/M2

1 U3Low-Voltage, Low-Quiescent Cur-rent LDO Regulator


MCP1727-2502E/SN

1 U4 Rail-to-Rail Output Op AmpMicrochip Technology Inc.

MCP661-E/SN

1 U6Voltage Feedback Amplifier 1 Circuit 8-SOIC-EP

Analog Devices Inc. AD8099ARDZ-REEL7

1 X1200 MHz LVDS XO (Standard) Oscil-lator Surface Mount 2.5V 34 mA Enable/Disable

Fox Electronics FXO-LC726R-200

TABLE B-2: MUPB001 MICROCHIP ULTRASOUND PLATFORM BOARD (ADM00679) BILL OF MATERIALS (BOM) (Note 1)


8

C1C10-C12 C27-C29 C90

33 µF Molded Tantalum Capacitors 10V 1411 (3528 Metric) 1.4 Ohm 0.138" L x 0.110" W (3.50 mm x 2.80 mm)

KEMET T494B336K010AT

4C2, C89 C104, C106


Murata Electronics North America, Inc.

GRM188R71E104KA01D

1 C3

100 µF Molded Tantalum Capaci-tors 6.3V 1210 (3528 Metric) 400 mOhm 0.138" L x 0.110" W (3.50 mm x 2.80 mm)

AVX Corporation TPSB107K006R0400

7

C4, C13 C17, C21 C30, C33 C37


Murata Electronics North America, Inc.

GRM188R71C473KA01D

24

C5-C9 C14-C16 C18-C20 C22-C26 C31, C32 C34-C36 C38-C40

1000 pF 50V 10% Ceramic Capaci-tor X7R MLCC 0603

NIC Components Corp. NMC0603X7R102K50TRPF


TABLE B-1: HV7321 ULTRASOUND TX PULSER EVALUATION BOARD (ADM00659) BILL OF MATERIALS (BOM) (CONTINUED)(Note 1)





1 C410.022 µF 50V Ceramic Capacitor X7R 0603 (1608 Metric) 0.063" L x 0.032" W (1.60 mm x 0.81 mm)

AVX Corporation 06035C223JAT2A

10

C42, C50 C52, C54 C56, C58 C60, C62 C64, C66


TDK Corporation C1608X7R1H104M080AA

3 C47-C4910 µF 35V Ceramic Capacitor X5R 1206 (3216 Metric) 0.126" L x 0.063" W (3.20 mm x 1.60 mm)

Taiyo Yuden Co., Ltd. GMK316BJ106KL-T

8C67, C68 C81, C82 C92-C95


Samsung Electro-Mechanics America, Inc.

CL10B104KO8NNNC

9

C69, C70 C83, C84 C96, C97 C107-C109


TDK Corporation C1608X5R1C475K080AC

3C71, C85 C98


Yageo Corporation CC0603KRX7R8BB103

3C72, C86 C99


KEMET C0603C472K5RACTU

12

C73-C78 C87, C88 C91 C100-C102


AVX Corporation 06035C103KAT2A

2 C103, C1054.7 µF 16V Ceramic Capacitor X7R 1206 (3216 Metric) 0.126" L x 0.063" W (3.20 mm x 1.60 mm)

KEMET C1206C475K4RACTU

1 D1Diode Schottky 30V 2A Surface Mount SMB

Vishay Intertechnology, Inc.

VS-20BQ030TRPBF

8 D2-D9Diode Schottky 30V 200 mA (DC) Surface Mount SOD-523

Micro Commercial Components

BAT54WX-TP

2J1J2

CONN RCPT 40 POS 2 ROW RT ANG T/H

TE Connectivity AMP Connectors

1469028-1

2J4J5

6 Positions Header, Unshrouded, Breakaway Connector 0.100" (2.54 mm) Through Hole Tin

Sullins Connector Solutions

PEC06SAAN

1 J6Power Barrel Connector Jack 2.50 mm ID (0.098"), 5.50 mm OD (0.217") Through Hole, Right Angle

CUI Inc. PJ-002B

1 J7USB - mini B USB 2.0 Receptacle Connector 5 Position Surface Mount, Right Angle, Horizontal

Hirose Electric Co., Ltd. UX60SC-MB-5ST(80)

2J8J9

SMA Connector Jack, Female Socket 50 Through Hole Solder

TE Connectivity, Ltd. 5-1814832-1

TABLE B-2: MUPB001 MICROCHIP ULTRASOUND PLATFORM BOARD (ADM00679) BILL OF MATERIALS (BOM) (CONTINUED)(Note 1)




4 J10-J13PC Pin Terminal Connector Free Hanging (In-Line) Gold 0.030" (0.76 mm) Dia

Mill-Max Mfg. Corporation

3132-0-00-15-00-00-08-0

1 L1Fixed Inductors XAL6060 High Cur-rent 4.7 µH 20% 11A

Coilcraft XAL6060-472MEB

3LD1, LD2 LD4

Green 568 nm LED Indication - Dis-crete 2.2V 0603 (1608 Metric)

Kingbright Electronics Co., Ltd.

APT1608SGC

1 LD5Red 633 nm LED Indication - Dis-crete 2V 0603 (1608 Metric)

OSRAM Opto Semicon-ductors GmbH.

LS Q976-NR-1

1 Q1MOSFET N-CH 100V 170 mA SOT23-3

Diodes Incorporated® BSS123-7-F

1 PCB MUPB001 – Printed Circuit Board — 04-10438

6R1, R2, R4 R11, R13 R14

RES SMD 4.7K OHM 5% 1/10W 0603


2R3R8

RES SMD 51 OHM 5% 1/10W 0603Panasonic - ECG ERJ-3GEYJ510V

3R5, R10 R15

RES TKF 0R 1/10W SMD 0603NIC Components Corp. NRC06Z0TRF

6R5, R10 R34, R35 R39, R41

DO NOT POPULATE— —

2R6R7

RES SMD 100 OHM 5% 1/10W 0603

Vishay/Dale CRCW0603100RJNEA

1 R9 RES SMD 22 OHM 5% 1/10W 0603 Panasonic - ECG ERJ-3GEYJ220V

1 R12

330 ±5% 0.063W, 1/16W Tem-perature Sensitive Specialized Resistor Metal Film 3300 ppm/°C Surface Mount

Panasonic - ECG ERA-V33J331V

1 R16RES SMD 39K OHM 1% 1/10W 0603


1 R17RES SMD 19.1K OHM 1% 1/10W 0603


1 R18 RES SMD 1K OHM 5% 1/10W 0603 Panasonic - ECG ERJ-3GEYJ102V

2 R19, R27RES SMD 390 OHM 5% 1/10W 0603


3R20, R37 R40

RES SMD 100 OHM 1% 1/10W 0603


1 R21RES SMD 8.66K OHM 1% 1/10W 0603

Yageo Corporation RC0603FR-078K66L

6R22, R28 R29, R33 R38, R42

RES SMD 10K OHM 1% 1/8W 0603Vishay Beyschlag MCT06030C1002FP500

1 R25RES SMD 51K OHM 1% 1/10W 0603


1 R26RES SMD 69.8K OHM 1% 1/10W 0603







4R23, R24 R30, R50

RES SMD 10K OHM 5% 1/10W 0603


1 R31RES SMD 82K OHM 1% 1/10W 0603


1 R32RES SMD 10.7K OHM 1% 1/10W 0603


4R34, R35 R39, R41

RES SMD 150 OHM 1% 1/10W 0603

Stackpole Electronics, Inc.

RMCF0603FT150R

1 R36RES SMD 75K OHM 1% 1/10W 0603


3R43, R45R47

RES SMD 100K OHM 1% 1/10W 0603


3R44, R46 R48

RES SMD 78.7K OHM 1% 1/10W 0603

Yageo Corporation RC0603FR-0778K7L

2R49R52

RES SMD 0.0OHM JUMPER 1/10W 0603

Panasonic - ECG ERJ-3GEY0R00V

1 R51RES SMD 150 OHM 5% 1/10W 0603


1 SW1Switch Slide Min. Single Pole Dou-ble Throw On-On PCB Mount 50 Volt DC @ 0.5 Amps Lead 4 mm

Jameco Valuepro SS-12F56-4

1 SW2Tactile Switch SPST-NO Top Actu-ated Surface Mount

E-Switch®, Inc. TL3301NF260QG

1 U1 IC FPGA 102 I/O 144TQFP Xilinx Inc. XC6SLX9-2TQG144C

1 U2IC PROM SRL FOR 4M GATE 20-TSSOP

Xilinx Inc. XCF04SVOG20C

1 U3Buck Switching Regulator IC Posi-tive Adjustable 0.9V 1 Output 3A 16-VFQFN Exposed Pad


MCP16323T-ADJE/NG

4 U4-U7Microchip Analog LDO 0.8V-5V MCP1727T-ADJE/MF DFN-8


MCP1727-ADJE/MF

3U8, U11U12

Linear Voltage Regulator IC Positive Adjustable 1 Output 1.2V ~ 3.4V 500 mA 6-TDFN (1.6x1.6)


MIC94325YMT-TR

1 U9USB Bridge, USB to SPI USB 2.0 SPI Interface 20-SSOP


MCP2210T-I/SS

1 U10Flexible Ultra-low Jitter Clock Gener-ator


SM803234UMG

1 X1Resonators 12 MHz 0.1% SMD CSTCE-G

Murata Electronics CSTCE12M0G15L99-R0

1 X240 MHz ±30 ppm Crystal 12 pF 40 -20°C ~ +70°C Surface Mount 4-SMD

TXC CORPORATION 7B-40.000MAAE-T






EVALUATION BOARD
USER’S GUIDE
Appendix C. HV7321 Ultrasound TX Pulser Evaluation Board Typical Waveforms

C.1 BOARD TYPICAL WAVEFORMS

C.1.1 5 MHz VPP0/VNN0 = ±80V, VPP1/VNN1 = ±60V, 220 pF//1K Load


TX0

TX0 ±80V ±60V

POS0

NEG0

SEL0




C.1.4 Fall Time of VPP0/VNN0 = ±80V, with 220 pF//1K Load

TX0 ±80V ±60V

POS0

NEG0

SEL0

TX0


HV7321 Ultrasound TX Pulser Evaluation Board Typical Waveforms

C.1.5 Rise Time of VPP1/VNN1 = ±80V, with 220 pF//1K Load

TX0



NOTES:


DS20005656B-page 73 2014-2016 Microchip Technology Inc.

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Worldwide Sales and Service

11/07/16

http://support.microchip.com

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