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THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS Issue 43 Summer 2002 R Xcell journal Xcell journal THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS ISSUE 43, SUMMER 2002 XCELL JOURNAL XILINX, INC. ANALYSIS Total Cost Management TECHNOLOGY How to Build Efficient FIR Filters Xyron Inc. Makes RTOS Breakthrough PERSPECTIVE Using DSP in Real-Time Video Processing NEWS IBM ASICs Incorporate Xilinx Technology Virtex-II Pro – New Products, Reduced Pricing Cover Story Xilinx CEO Wim Roelandts Reveals How to Survive a Recession and Gain Market Leadership ANALYSIS Total Cost Management TECHNOLOGY How to Build Efficient FIR Filters Xyron Inc. Makes RTOS Breakthrough PERSPECTIVE Using DSP in Real-Time Video Processing NEWS IBM ASICs Incorporate Xilinx Technology Virtex-II Pro – New Products, Reduced Pricing Cover Story Xilinx CEO Wim Roelandts Reveals How to Survive a Recession and Gain Market Leadership

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  • T H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

    Issue 43Summer 2002


    Xcell journalXcell journalT H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

    ISSUE 43, SUMM




    Total Cost Management


    How to Build Efficient FIR Filters

    Xyron Inc. Makes RTOS Breakthrough


    Using DSP in Real-TimeVideo Processing


    IBM ASICs Incorporate Xilinx Technology

    Virtex-II Pro New Products,Reduced Pricing

    Cover Story Xilinx CEO Wim Roelandts RevealsHow to Survive a Recession and Gain Market Leadership


    Total Cost Management


    How to Build Efficient FIR Filters

    Xyron Inc. Makes RTOS Breakthrough


    Using DSP in Real-TimeVideo Processing


    IBM ASICs Incorporate Xilinx Technology

    Virtex-II Pro New Products,Reduced Pricing

    Cover Story Xilinx CEO Wim Roelandts RevealsHow to Survive a Recession and Gain Market Leadership

  • ast year, Xilinx debuted at #14 on the FORTUNE 100 Best Companies to Work Forannual list. This year, we broke into the Top 10 with a ranking of #6 the only Silicon

    Valley/San Francisco Bay Area company to make the Top 10.

    To help determine the new rankings, FORTUNE weighed how companies reacted to the economicdownturn of 2001. Although revenue at Xilinx declined by 50 percent over the course of 2001, thecompany decided employee layoffs would come only as a last resort. As a result of significant cost-cutting measures including tiered salary cuts for everyone except the lowest paid employees Xilinxmanaged to avoid layoffs, continued to bring remarkable new products to market, and became largerthan all other public programmable logic companies combined.

    We believe the FORTUNE magazine ranking reflects the strong values we hold at Xilinx:

    Customer focus






    Very open communication

    Enjoying our work.

    These CREATIVE values are a vital part of our culture, and they make a positive difference for ouremployees and our customers. Our values make Xilinx a great company to work for and a greatcompany to work with. Our technology, our service, and our customer satisfaction continue to leadthe industry. We are always seeking new ways to make a real difference in our world. And, thoughtechnology drives our business, weve built our success on the strong partnerships weve created withour customers, our suppliers, and other technology leaders in our industry.

    To learn more about the FORTUNE magazines top 100 companies to work for, go to: www.fortune.com/lists/bestcompanies/.

    L E T T E R F R O M T H E E D I T O R

    EDITOR IN CHIEF Carlis [email protected]

    MANAGING EDITOR Tom [email protected]

    CONTRIBUTING EDITORS Jane BratunBrendan BridgfordLeRoy MillerRyan Wilson

    DESIGN & ILLUSTRATION Scott BlairDan Teie

    Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124-3400Phone: 408-559-7778FAX: 408-879-47802002 Xilinx Inc.All rights reserved.

    Xcell is published quarterly. XILINX, the Xilinx logo,CoolRunner, Spartan, and Virtex are registered trade-marks of Xilinx Inc. Alliance Series, Xilinx FoundationSeries, AllianceCORE, Foundation, IRL, LogiCORE,SelectI/O, WebPACK, WebPOWERED, WebFITTER,QPro, XPERTS, XtremeDSP, CORE Generator, RocketI/O, Fast Zero Power, SelectRAM, IP-Immersion,System ACE, ChipScope, and all XC-prefix products aretrademarks, and The Programmable Logic Company isa service mark of Xilinx Inc. Other brand or productnames are trademarks or registered trademarks oftheir respective owners.

    The articles, information, and other materials includ-ed in this issue are provided solely for the conven-ience of our readers. Xilinx makes no warranties,express, implied, statutory, or otherwise, and acceptsno liability with respect to any such articles, informa-tion, or other materials or their use, and any usethereof is solely at the risk of the user. Any person orentity using such information in any way releases andwaives any claim it might have against Xilinx for anyloss, damage, or expense caused thereby.

    We Did It Again Only Better This TimeL

    Xcell journalXcell journal

    Many Xilinx employees have told me how proud they are to

    receive this recognition. It speaks as much about the great

    culture we have created at Xilinx as is does about the quality

    of people who work here.

    Wim Roelandts, CEO, Xilinx Inc.

    Tom DurkinManaging Editor

  • How to Survive a Recession and Gain Market LeadershipI said from the beginning that we wanted to emerge from the recession a greater company and I think we have achieved that.

    Contents Summer 2002Cover Story Page 4


    Customize Virtual Private Networks with Spartan-IIE FPGA Solutions Spartan-IIE FPGA solutions can help you to customize your virtual private network for highest performance, greatest security, and lowest cost.

    When Total Cost Management Counts, Xilinx PLDs Pay OffCoolRunner-II CPLDs, Spartan-IIE FPGAs, and Virtex-II EasyPath Platform FPGAs can give you total system cost solutions superior to those of traditional ASICs.

    Software Page 24

    Exploring Hardware/Software Co-Design with Virtex-II Pro FPGAsTo explore the possibilities of hardware/software co-design, the Xilinx Design Services team created a reference design for a real-time operating system for telecommunications.

    Applications Page 55

    Page 8

    Xcell journalXcell journal

    Technology Focus Page 42

    How to Survive a Recession and Gain Market Leadership ...........4

    IBM ASICs Incorporate Xilinx Technology..................................7

    Total Cost Management.........................................................8

    New Virtex-II Pro Devices Lower Cost.................................12

    Virtex-II FPGAs Deliver Advanced Data Security .......................15

    CoolRunner-II CPLDs Go All Digital .........................................18

    If Disaster Strikes, Xilinx Is Prepared .....................................21

    Xilinx Software Improves Your Productivity.............................22

    Hardware/Software Co-Design with Virtex-II Pro FPGAs ...........24

    Virtex-II Pro Platform FPGA Drives Convergence ......................27

    Xilinx Offers End-to-End Solutions .........................................30

    FPGAs Enabling DSP in Real-Time Video Processing..............32

    FPGAs Provide Flexibility in Digital TV Development.................36

    Xilinx Technology Can Disable Stolen Cell Phones....................39

    Customize Virtual Private Networks.......................................42

    Build Secure and Robust Wireless Communications .................44

    Leading Technologies for Wired Home Networking ..................48

    You Can Take It With You: On the Road with Xilinx.................52

    Build an Efficient FIR Filter Using System Generator ................55

    Xilinx Software Tools to Reduce Line Echoes...........................58

    SystemIO Solution Expands with Bandwidth Demands.............59

    Develop MicroBlaze Applications...........................................62

    Xyron Semiconductors RTOS Breakthrough ............................64

    Power Supply Solutions for Virtex-II Pro Platform FPGAs ..........66

    Nallatechs DIME-II Architecture Goes Pro ...............................68

    Platform FPGAs Take on ASIC SOCs ......................................70

    CoolRunner-II Data Sheet.....................................................74

    Reference Pages ................................................................86

    How to Build an Efficient FIR FilterUsing System Generator Xilinx System Generator 2.2 software enables high-level modeling and implementation of DSP systems in Xilinx Platform FPGAs to outperform traditional DSP processors.

    Develop MicroBlaze Applications with ThreeFlexible Hardware Evaluation PlatformsMicroBlaze Development Kits from Memec Design demonstrate the versatility of the MicroBlaze soft processor core in a variety of Xilinx FPGAs.

    New Products Page 62

    Reference Page 74

    CoolRunner-II Data SheetRealDigital CPLDs consume only microwatts of power, yet provide very high performance take a look at whats under the hood.

    Subscribe to the Xilinx Xcell Journal at: www.xilinx.com/forms/literature.htm.

    Visit Xcell Online for the latest news and information, as soon as it arrives at: www.xilinx.com/publications/xcellonline/.

  • How to Survive a Recession and Gain Market Leadership

    4 Xcell Journal Summer 2002

    Cover StoryView from the Top

    I said from the beginningthat we wanted to emergefrom the recession a greatercompany and I think wehave achieved that.

  • by Wim RoelandtsCEO, Xilinx, Inc.

    Last year was avery difficult yearfor the semicon-ductor industry.In fact, it was theworst recession

    ever in the history of semiconductors. In1985, the industry decreased in a year-over-year basis by 17% to 18%. In 2001,the decline was 32% to 33% almosttwice as bad as 1985.

    Nevertheless, I believe that its in therecessions that the good companies dis-tance themselves from the not so goodcompanies. Even though our business wasvery weak, we gained market share duringthis recession in quite a dramatic way.Last quarter, for the first time in our his-tory, we became larger than all the otherpublic programmable logic device compa-nies combined.

    From a strategic point of view, we want towin through product leadership. Thatmeans we have to have the best products always from the customers point of view which means the highest densities, thefastest performance, and the software andservice to support them.

    When you are an industry that is new and that is still changing very rapidly, you have to continue to innovate. Youhave to continue to bring new productsinto the market.

    Despite the recession, the last part of2001 and the early part of 2002 was oneof our most productive periods for newproduct introductions. In about fivemonths time, we introduced a new family in every one of our product cate-gories Spartan, CoolRunner, andVirtex. Each, in its own way, is uniquein its capabilities. In fact, two of thesenew products the CoolRunner-IIRealDigital CPLD and the Virtex-IIPro Platform FPGA have no compe-tition. Literally, there are no comparableproducts on the market that can competedirectly with them.

    Whenever you lay off employees, some ofthe accumulated knowledge of the com-pany its intellectual capital is goingto walk out the door. Especially in thehigh-tech industry, the value of the com-pany is in the heads of its engineers andsupport staff. At Xilinx, 70% or 80 % ofour employees are highly educated peopleworking in engineering and marketingand supply-chain management. They areall experts and specialists in their ownway and thats why its so important tokeep these people happy at Xilinx. Oncepeople like that leave, that intellectualcapital goes out the door with them, andthats a lot of value for a cutting-edgecompany to lose.

    Several compelling studies have proved thatif you go back two years later, the compa-nies that laid off employees are generally inworse shape than companies that didnt.Layoffs have a very profound impact on themorale and the trust between managementand employees. Furthermore, a lot ofknow-how has left the company. And ittakes a long time to get it back.

    For these reasons, and more, I decided totry to avoid layoffs.

    Pay Cuts An Innovative Approach

    The reality of economics is that when busi-ness drops, you have to bring your laborcosts in line. With layoffs not being anoption, the way we cut our labor costs wasby a very innovative program where we hada tiered salary reduction that was propor-tional to the size of each workers salary.The lowest paid people had no reductions,and the highest paid people had the biggestreductions (myself included).

    In implementing this policy, we discov-ered that we should give people somechoices and make sure they get somethingin return. People had the choice to eithertake the salary reduction or to take vaca-tion time or take stock options. Stockoptions arent money, but it is compensa-tion for the work people put in. We cantask the employees to sacrifice unless wecan compensate them for the extra flexi-bility were asking from them.

    Total Solutions

    Im very excited about the programmablelogic industry. Its an industry thats still inthe early phases, but over time, it willbecome the dominant way to implementintegrated circuit designs.

    The inherent flexibility of programmablelogic allows you to gain time to market, tointroduce new products very quickly, andto upgrade your product, even after thesale, through field-upgradeable technology.

    Were not just focusing on the chips, how-ever. Our chips must also have the soft-ware, the intellectual property cores, thetraining, and the support to deliver totalsolutions to our customers.

    And we have to continue to be innovativein all these areas of IC technology. Mywhole belief is that Xilinx must excel in acontinuous push to innovation through-out the company, be it in chip design, soft-ware development, or marketing.Innovation is absolutely critical especiallyin times of recession.

    No Layoffs Not Just a Nice Thing to Do

    This recession has put a tremendous strainon the industry. When I saw this declinecoming, I concluded that it would be bestfor us if we could avoid layoffs eventhough the economic consequences wouldbe very difficult. I wanted to avoid layoffs,because once you start layoffs, people getworried and if people are worried, theycannot innovate.

    Innovation means that you have to take risksthat some things are not going to work, andtherefore, if you are worried about your job,the mantra becomes, Dont rock the boat.Dont push yourself or make yourself toovisible which is totally opposite fromwhat we want to see happening.

    If people are worried about their jobs,clearly, theyre not going to be as produc-tive. Layoffs affect not only the people whoget laid off. Very often the people who arestill there go through trauma, because theysee their friends disappear and theyalways have this fear: Maybe next time itwill be me.

    Cover Story View from the Top

    Summer 2002 Xcell Journal 5

  • Cover Story View from the Top

    The tiered salary reduction was extremelywell received in the company. The vastmajority and Im talking about close to100% of the employees felt this was theright thing to do.

    People even volunteered for the plan, whichwas important in Europe, because inEurope, companies cannot mandate salaryreductions. It must be done on a voluntarybasis. If people hadnt volunteered, we couldnot have done it, but pretty much all of ourEuropean employees volunteered for thesalary reduction, because they felt solidaritywith the company.

    With an acceptance of fair pay cuts and apromise of no layoffs, our employees feltsafe to continue to risk and innovate. Theyhave kept their attention full-time on theirjobs. The net result has been that we havebeen able to maintain our aggressive sched-ule of new product rollouts and this in aperiod when our business was off by 50%in three quarters.

    Moreover, we were not only able to remainin the black from a profit point of view, butduring all this period, we were also able toremain cash-flow positive for the company.

    The Importance of Being Fabless

    One of the reasons we could afford to stayin the black is because Xilinx is a fablesssemiconductor company. We dont ownfabs [fabrication plants]. We dont have thisbig problem of having a fab that we need tokeep busy. For us, if business goes down,we just buy fewer wafers.

    The same thing is true for our sales force.We dont have a Xilinx sales force. Wework through distribution and sales reps,which again means that our sales costs areby and large variable. Sales people getpaid a commission. If they dont sell,theres no commission.

    These two factors helped us tremendous-ly in remaining in the black and remain-ing cash-flow positive, because a lot ofour expenses go up and down with thebusiness climate.

    The good news is that we reached ourlowest quarter in September of 2001.

    Since then, business has been starting toimprove. We were able to eliminate salaryreductions early in 2002, and as of thismoment, all salary reductions have beeneliminated. The company continues to dovery well from both a new product gener-ation point of view, as well as a businesspoint of view.

    Innovation Not Just for Engineers

    Innovation is not just the engineeringdepartment. Even in the way we managethe company, we are very innovative and it really has paid off for us. Morale isvery high, and the attrition rate isextremely low. People have kept theirattention on their jobs of designing greatnew products and marketing them andsupporting them.

    In general, I think Xilinx is very much anadmired company in our industry. I thinkwe are perceived as a leader in our industry not just from a product point of view ora financial point of new, but also from amanagement point of view.

    I want to stress, however, that all of this ispossible because we are a fabless company.If we had our own fabs, I dont know if wecould have done this.

    Nevertheless, as a fabless company, ourbusiness model lends itself very well to gothough these economic cycles that areinfamous in the semiconductor industry.This last recession was the worst, but italso served to prove that our businessmodel is a very, very solid model thatallows us to go through these ups anddowns without too much hurt.


    In high technology, things change very,very rapidly. And companies often get introuble because they dont change quicklyenough. One of the reasons they dontchange quickly is that the people who seethe change happen dont act on it, and thepeople who can act on it dont even knowthe change is happening.

    Therefore, what we are creating at Xilinxis an environment where everybody says:Hey, if it changes, lets change with it.Lets anticipate change. Lets make thechange happen ourselves. Lets be incharge of the change not the victim ofthe change.

    It is this kind of thinking that got us throughthe recession, and now that we are emergingfrom the recession, there is a tremendoussense of pride in the company. People aresaying: Hey, this is unique. We have donesomething that very few other companieshave done. Even companies that didnt laypeople off didnt do it the way we did.

    There is absolutely no doubt in my mindthat there is a much, much higher spirit ofbelonging, of community within theXilinx people than there was before. Whenyou go through a tough time together, itcreates solid bonds.

    And it shows that, indeed, if you can man-age a company during a recession in a cor-rect way, you can really differentiate your-self from the competition. You can gainmarket share and emerge a stronger com-pany with a creative, dedicated and intact workforce at the end of recession.

    6 Xcell Journal Summer 2002

  • by Xilinx Staff

    IBM and Xilinx recently signed an agree-ment that could help you shave hundreds ofthousands of dollars off the cost of creatingcustom chips. Under the agreement, IBMhas licensed FPGA technology from Xilinxfor integration into IBMs recentlyannounced Cu-08 application-specific inte-grated circuits (ASICs). Cu-08 will supportcircuits as small as 90 nanometers less than1/1,000th the width of a human hair.

    This news underscores our joint commit-ment to a technology relationship aimed atbringing innovative and flexible newhybrid chips to market, combining thebest attributes of standard ASIC and flexi-ble FPGA technology for use in communi-cations, storage, and consumer applications.

    Engineers working on complex chip designshave been clamoring for ways to achieve highlevels of integration, yet still have the abilityto change on the fly late in the design cycle.By combining FPGAs (circuits that can beconfigured to perform a wide variety of digi-tal electronic circuit functions) with standardASICs, you get the flexibility of the FPGA,with the density, performance, and overallcost advantages of an ASIC all on one chip.

    Savings here could be dramatic, saidMichel Mayer, general manager, IBMMicroelectronics Division. When anASIC takes on more function, you canreduce cost by eliminating one, two, oreven more separate chips. With this tech-nology, customers would be able to tweakdesigns and integrate new changes imme-diately, eliminating the need to restart awhole new design cycle, bringing tremen-dous time-to-market advantages.

    Mayer said changes that force an addition-al chip prototype can easily cost hundredsof thousands of extra dollars and canstretch design cycles out for several addi-tional months. This approach is expectedto change the landscape entirely, he said.

    Cu-08, with as many as eight layers ofcopper wiring separated by an advancedlow-k insulation, will support up to 72million gates for high-complexity ICsolutions. As many as 400,000 ASICgates may be dedicated to one or more ofthe FPGA cores on the ASIC.

    Weve improved upon our delivery of pro-grammable hardware by allowing reconfigu-ration using the same chip. Flexibility is thebeauty of combining ASIC and FPGA tech-nology, said Wim Roelandts, president andCEO of Xilinx. Our latest agreement withIBM is a natural extension of and a signifi-cant milestone in our existing relationshipthat allows us to address new opportunitiesin the high-end ASIC market.

    Even after this new custom chip is builtinto a product, you can add to its func-tionality, simply, easily, and effectively. A

    good example would be in the communica-tion industry, where various protocol andinterface specifications are constantly evolv-ing. Cell phones, printers, set top boxes,and other consumer electronic productsalso are well suited for this new approach.

    IBM is the number one ASIC manufacturerworldwide. Xilinx is the number one PLDmanufacturer worldwide, with more than15 years experience in FPGA design tools.

    IBM and Xilinx already have a productivebusiness relationship. IBM suppliesembedded PowerPC processors forXilinx Virtex-II Pro FPGAs. In Marchof this year, Xilinx signed a high-volume,multi-million dollar manufacturing agree-ment with IBM to manufacture theseFPGAs using IBMs advanced 130nanometer and 90 nanometer copper-based chip-making technology.

    The new FPGA cores for the Cu-80ASICS are now in development. They areexpected to be available from IBM,embedded in an ASIC, in early 2004, fol-lowing IBMs full release of its standard-setting Cu-08 technology.

    News IBM Partnership

    New ASICs from IBM will contain Xilinx programmable logic technology.

    IBM ASICs Will Incorporate Xilinx FPGAs

    Summer 2002 Xcell Journal 7

  • by Eric ThackerManager, Product Solutions MarketingXilinx, [email protected]

    Rapidly changing markets and new tech-nologies are subverting traditional systemdesign paradigms. Historically, in electronicsystems development, the standard designprocedure was to prototype a system using

    programmable logic devices (PLDs), andthen redesign the system using ASICs assoon as possible for cost reduction. Theidea was to leverage the flexibility anddevelopment time advantage of program-mable logic until the design stabilized andthen to convert the design to a lower-unit-cost ASIC to reduce overall system cost.

    In the past, programmable logic was lowerdensity, lower performance, and morelimited in capabilities. When systems fol-lowed traditional product life cycle behav-ior, the PLD-to-ASIC design strategyworked quite well. In fact, in some marketsegments, characterized by relativelymature technologies, established stan-dards, and a stable competitive environ-ment, this strategy is still optimal today.

    In dynamic, rapidly changing markets,however, this strategy becomes question-able. For many advanced electronic prod-ucts such as plasma televisions, homenetworking hardware, and digitalaudio/video equipment the market isanything but stable. Baseline standardsfor advanced products are ever-changing,features demanded by customers shiftconstantly, new technological capabilitiesare continually being introduced, andcompetitors are always trying to gain abetter market position resulting inmany short-lived products.

    These volatile market pressures give a sig-nificant competitive advantage to flexibleand first-to-market products. In thesemarkets, ASICs with their long leadtimes, high initial costs, high minimumorder quantities, higher risks, and inflexi-bility are not a compelling solution.

    Therefore, many designers are tappinginto programmable logics benefits ofinstant reprogrammability, short leadtimes, greatly improved performance,expanded densities, and overall flexibility.Indeed, todays programmable logicdevices offer many of the same featuresfound in ASICs. Clock management,embedded processors, high-performanceDSP, advanced interfacing, and a pletho-ra of intellectual property (IP) cores allmake todays PLDs strong candidates fora systems core logic.

    With their emphasis on cost-optimiza-tion, the CoolRunner-II CPLDs,Spartan-IIE FPGAs, and Virtex-IIEasyPath Solutions families fromXilinx bring these advanced benefits toyour high volume applications.

    Perspective Cost Management

    CoolRunner-II CPLDs, Spartan-IIE FPGAs, and Virtex-II EasyPathPlatform FPGAs can give you total system cost solutions superior to those of traditional ASICs.

    When Total Cost Management Counts, Xilinx PLDs Pay Off

    8 Xcell Journal Summer 2002

    When Total Cost Management Counts, Xilinx PLDs Pay Off

  • Total Cost Solution

    In the past, the primary motivation in con-verting a PLD design to one based on anASIC was unit cost. ASICs, in general, areavailable at lower unit cost than PLDs. Butlooking at unit costs alone could actuallylead to an overall higher cost solution. Thatis because unit costs are only one of the fac-tors that contribute to total system cost.Total system costs can be broken down intothree broad categories design and develop-ment, production, and life cycle.

    Design and Development

    Design costs are primarily worker-hour andnon-recurring engineering (NRE) costs.PLD designs require fewer worker hours,because design/debug changes can be madeinstantly, hardware and software can bedeveloped concurrently, test vector genera-tion is unnecessary, and product lead timesare practically zero compared to ASICs.PLDs have no NRE costs, which can be avery important consideration as productionvolumes per design revision are much lowerin rapidly evolving markets. In many cases,Xilinx offers free PLD design tools, thusincreasing the PLD cost advantage.

    There are also lost opportunity costs associat-ed with ASICs. Systems using ASICS losemarket penetration due to long developmenttimes. Furthermore, the inflexibility of ASIC-based systems prevents upgrading products tomeet changing market needs. Overall, PLDdesign cost advantages alone can often out-weigh any ASIC unit cost advantage.

    Finally, long-lived legacy products usingASICs can face the need for boardredesign should the ASIC product orprocess be discontinued. PLD reprogram-mability avoids this problem. Thus, lega-cy products with PLDs do not siphondesign resources from next-generationproducts, and this presents a significantmarket cost savings.

    As illustrated in the discussion of thesethree cost categories, we must look beyondunit cost when deciding on logic solutionsbased on cost. In many applications, theunit cost savings of ASICs are more thanoffset by the lower risks, design, produc-tion, and life cycle costs of PLDs.

    Xilinx Solutions for Total Cost Management

    Xilinx has taken the lead among PLDsuppliers in providing low risk, low cost,high performance logic solutions fortodays rapidly changing and highly com-petitive markets.

    Low Power, Low Density: CoolRunner-II CPLDs

    CoolRunner-II RealDigital CPLDs com-bine high performance, ultra low power,low cost, and integration of specializedcapabilities to bring you a new class ofprogrammable logic devices. The versatil-ity and low cost of CoolRunner-IICPLDs allow them to serve a multitudeof logic, interface, and control functions.See Figure 2.


    Unit cost is the mostobvious cost in this cat-egory. ASICs usuallydo hold the unit costadvantage over PLDs,but this cost differen-tial is shrinking.

    Todays PLDs haveaggressively drivendown both die size andpackage costs to providea persuasive ASIC alter-native. The advancedsystem capabilities ofmodern PLDs allow

    designers to integrate discrete componentfunctions into the PLD reducing boardand total component costs.

    Finally, unlike an inflexible ASIC, one lineof PLDs can be inventoried to supply mul-tiple applications. You can reprogram andredeploy PLDs as needed. Combined withmuch lower minimum order quantities,PLDs reduce inventory costs, as well as therisk of obsolescence, further offsettingPLDs unit cost disadvantage. See Figure 1.

    Life Cycle

    Life cycle costs are probably the least consid-ered costs when designing an electronic sys-tem, but they can have a significant impacton the total return from a given design.Using PLDs instead of ASICs means practi-cally no risk of obsolete inventory, becausestandard-product PLDs canbe redeployed to differentapplications as needed.Unlike ASICs, PLDs do nothave to be scrapped if a spe-cific product is cancelled.

    In addition, because PLDscan be reprogrammed, it ispossible to upgrade prod-ucts in the field simply bydownloading a new hard-ware configuration file tothe PLD. Bug fixes and fea-ture upgrades can be per-formed remotely withoutchanging any hardware.

    Summer 2002 Xcell Journal 9

    Figure 2 - CoolRunner-II CPLDs deliver high performance at low cost.

    Figure 1 - Cost comparison of ASICs and FPGAs

    Perspective Cost Management

  • Perspective Cost Management

    The 0.18-micron CoolRunner-II familyutilizes second-generation Fast ZeroPower technology for low power, highperformance operation. These RealDigitalCPLDs feature an all-digital core that elim-inates power-hungry analog sense ampli-fiers. The CPLDs also offer increased capa-bilities, higher performance, and lower cost with no performance penalty.

    Available in densities from 32 to 512macrocells, the CoolRunner-II family pro-vides performance over 330 MHz, withstandby power consumption of less than100 A. CoolRunner-II devices also deliveradvanced system features that enable theintegration of costly discrete system func-tions into a single reprogrammable device.This integration results in lower costs, fur-ther power reduction, increased reliability,faster time to market, and smaller designs.These system features include superiorI/Os, advanced clocking features, and fourlevels of design security.

    The in-system reprogrammable nature ofCoolRunner-II CPLDs allows designers tochange designs on the fly, correct designs,and test out alternate designs withoutchanging any hardware. This saves signifi-cant engineering change orders (ECOs) andNRE charges compared to ASIC solutions.

    The CoolRunner-II CPLDs advanced I/Ointerface capabilities include DataGATE, aprogrammable on/off switch for power man-agement; advanced interfaces such as HSTL,and SSTL; and Schmitt trigger inputs for

    input signal conditioning. All of these fea-tures reduce the need for external compo-nents, reducing part costs and board space.

    To further reduce system costs and the needfor additional components, theCoolRunner-II family provides a unique fea-ture called CoolCLOCK. CoolCLOCK is acombination of a clock doubler and clockdivider. The incoming clock is divided bytwo and then doubled at the output to main-tain the same performance, while reducingthe internal power consumption.

    To increase your cost management advantage, Xilinx provides a free Internet-based ISE WebPACK design tool suiteand a free WebFITTER design fittingtool to give you a complete, pushbuttondesign solution.

    The combination of advanced interfacing,integrated system features, and free designtools makes CoolRunner-II CPLDs a com-pelling choice for logic functions in cost-sensitive applications. For more informa-tion, visit www.xilinx.com/coolrunner2.

    Moderate Density, System Integration:Spartan-IIE FPGAs

    Cutting-edge consumer electronics marketsdemand products that provide performanceand flexibility in a cost-optimized format forhome networking equipment, home theatersystems, and other high-end personal elec-tronic devices. These consumer productsmust accommodate rapidly evolving stan-dards, shifting demand patterns, highly fluid

    competitive positioning, and the continuousintroduction of new capabilities. Logicrequirements for these designs include mod-erate density, advanced system features, pre-designed and verified IP blocks, and high-quality design tools. Spartan-IIE FPGAsmeet all of these requirements and more.

    Xilinx designed its next-generation Spartan-IIE consumer FPGA with total cost man-agement in mind. Spartan-IIE FPGAsrange in density from 50,000 system gatesto 300,000 system gates. To reduce FPGAcomponent costs, Spartan-IIE FPGAs areproduced by the industrys most advancedfoundry process on 300 mm wafers. Thisprocess lowers die cost and enablesadvanced, low-cost packaging.

    To reduce board cost and improve systemperformance, Spartan-IIE FPGAs have anumber of built-in advanced system fea-tures that allow you to eliminate costly dis-crete translators and commodity chipsfrom your boards, as shown in Figure 3.

    Advanced interfacing including LVDS,LVPECL, HSTL, and SSTL remove theneed for specialized interface componentson the board. Furthermore, Spartan-IIEFPGAs offer four delay-locked loops(DLLs) for advanced clock management.Spartan-IIE FPGAs also contain both para-meterizable block RAM (single or dualport) and distributed RAM (scalable andadjacent to logic). All these features canspeed the design process, provide designflexibility, reduce design worker hours,deliver very high levels of performance, andaccelerate time to market.

    As consumer products increase their digitalcapabilities, digital signal processing (DSP)capability has become a critical performancefactor. The Xilinx XtremeDSP initiativeenables nearly one billion DSP multiply-and-accumulates (MACs) per second perdollar of performance in Spartan-IIE devices delivering advanced DSP without theneed for specialized board components.

    Xilinx offers more than 200 Spartan-familyIP cores to speed logic design and reduceengineering resources needed to completethe system. These IP cores are also opti-

    10 Xcell Journal Summer 2002

    Figure 3 - Spartan-IIE FPGAs save board space and money.

  • Perspective Cost Management

    mized for die area, which may permit theuse of smaller density Spartan-IIE parts,resulting in further cost savings.

    Additionally, the free ISE WebPACK soft-ware provides the industrys most advanceddesign tool platform to support the entireSpartan series.

    Die and packaging, advanced system fea-tures, extensive IP offerings, enhanced flex-ibility all these Spartan-IIE cost controlfeatures give you the performance, features,and time to market advantage necessary tocompete in todays rapidly evolving elec-tronics markets. For more information, visitwww.xilinx.com/spartan.

    High Performance, High Density: Virtex-II EasyPath FPGAs

    The Virtex-II FPGA is the first embodi-ment of the Platform FPGA concept.Virtex-II devices deliver SystemIO inter-faces to bridge emerging standards,XtremeDSP performance up to 100X con-ventional DSP solutions, multi-gigabittransceivers, and Empower! embeddedprocessor technology. Together with theindustrys most advanced design tools,Virtex-II Platform FPGAs offer a feature setthat is unparalleled in the industry.

    Virtex-II EasyPath FPGAs bring theunprecedented capabilities of the Virtex-IIfamily to cost-sensitive applications byreducing the cost of high-density FPGAdesigns. Virtex-II EasyPath Solutions usethe exact same FPGA silicon as the Virtex-II FPGA family, but Virtex-II EasyPathSolutions make use of a specialized testingprogram to verify the FPGAs for a specificcustomer application, resulting in higheryields and significantly lower costs.

    Virtex-II EasyPath solutions provide anFPGA volume conversion strategy with norisk, no investment of customer engineeringresources, and the fastest conversion time ofany competing high-volume strategy forhigh-density FPGA designs. The main ben-efits of Virtex-II EasyPath solutions are:

    Lower unit costs: Customers can expect a30-90% price reduction compared tostandard FPGAs.

    Lower up-front costs: These costs can beas low as 30% of the NRE costs of anASIC or gate array.

    No added engineering resources: Unlikeother FPGA conversion strategies, Virtex-II EasyPath FPGAs require no additionalengineering resources or tools. Customersare not required to contribute anyresources for conversion, verification,qualification, or board redesign.

    No risk: Virtex-II EasyPath Solutionshave none of the performance, timing,functionality, or architecture match risksof alternative FPGA conversion strategies,because the conversion FPGA fabric is thesame as the standard Virtex-II FPGA.

    Minimal lead times: With Virtex-IIEasyPath FPGAs, initial orders are filledwithin six weeks and restocking orders arefilled within days of being placed.Compare that to lead times of multiplemonths for both initial and follow-onorders for alternative conversion strategies.

    Because Virtex-II EasyPath FPGAs are testedfor a specific design configuration, testingthroughput and yields are significantly high-er, thus driving down the unit costs of theFPGA, as shown in Figure 4. You can initial-ly design your system using standard Virtex-II FPGAs. Once the design has stabilized,you can use Virtex-II EasyPath Solutions toconvert to a lower-cost platform with none

    of the risk, lower NRE costs, and none of theadditional engineering resources required byconversion to ASICs. For more information,visit www.xilinx.com/virtex2.


    From low density, ultra low powerCoolRunner-II CPLDs to mid-range, lowcost Spartan-IIE FPGAs to high densityVirtex-II EasyPath Platform FPGASolutions, Xilinx presents a portfolio ofproducts that can play a critical role in yourtotal cost management of system design.These advantages include:

    Cost-optimized silicon and packaging tominimize unit costs

    Advanced system features to reduce coststhrough system integration

    Reprogrammability to streamline designand debug

    No-cost system upgrade capabilities

    Reduced risk of obsolete inventory

    An extensive IP library to improve designefficiency and reduce system components

    Free design tools that maximize designefficiency.

    Together, Xilinx CPLDs and FPGAs giveyou a cost-optimized solution for managingsystem costs while maximizing system per-formance, functionality, and flexibility.

    Summer 2002 Xcell Journal 11

    Figure 4 - Virtex-II EasyPath Solutions are design-specific and cost-effective.

  • by Anil Telikepalli, Marketing Manager Virtex Solutions, Worldwide MarketingXilinx, [email protected]

    In a significant move, Xilinx recentlyexpanded the Virtex-II Pro PlatformFPGA family two ways:

    Five new devices offering increased capability

    Lower cost versions for the entire family in a new reduced-speed series.

    With this, the new Virtex-II Pro familyexpands to ten devices, and sets industryrecords in every conceivable category, pro-viding the advanced system-level featuresand high performance you need, atremarkably low prices.

    The new Virtex-II Pro FPGA solution,illustrated in Figure 1, provides every-thing you need, on a single, reprogram-mable device, including:

    The worlds highest logic and memory density

    The worlds highest I/O capacity

    The worlds fastest DSP capability

    The worlds fastest multi-gigabit serialI/O connectivity

    The worlds most flexible parallel I/O connectivity

    The worlds only embedded processingFPGA solution using IBM PowerPCprocessor cores.

    New Products FPGAs

    Now you get programmable system features at programmable logic prices.

    New Virtex-II Pro Devices Increased Capability, Lower Cost

    12 Xcell Journal Summer 2002

    New Virtex-II Pro Devices Increased Capability, Lower Cost Now you get programmable system features at programmable logic prices.

  • New Products FPGAs

    Your demands, both for increased capabili-ty as well as lower cost versions of ourVirtex-II Pro devices, were made clear atour Programmable World 2002 event. Andnow, we can deliver the performance andthe pricing you need due to the success ofour initial devices and development tools,as well as advances in our process technol-ogy which includes 300-mm wafers.

    These new, lower cost devices not only deliv-er tremendous cost savings over comparablecompeting programmable device offerings,but they also bring Virtex-II Pro capabilitieswithin the reach of a much wider range ofapplications. With the Virtex-II Pro familyyou now get multiple IBM PowerPC proces-sors and multi-gigabit serial transceivers atabout the same cost as our Virtex-IIFPGAs (which dont offer these features),effectively providing programmable systemfeatures at programmable logic prices.

    The Highest Performance and the Lowest Cost

    The new Virtex-II Pro XC2VP125 FPGA,shown in Table 1, is the worlds highestcapacity, highest performance, and high-est capability programmable logic device,delivering unique system performancesuch as one trillion MACs/sec DSP per-formance and 120 Gb/s aggregate payloadbandwidth. There is no programmable

    age, digital broadcast, networking, andwireless networking. For example, in net-working, as you move from the core of thenetwork to the edge, the line rate and pro-cessing speed of the equipment decreaseswhile the need for intelligent processingincreases. In addition, price pressureincreases, because the edge equipment ismore price sensitive than the core equip-ment. This analogy can be applied toalmost any application and market seg-ment. Xilinx is providing -5 devices specif-ically to address such price-sensitive appli-cations that benefit from system featuresthat include embedded processors andmulti-gigabit transceivers.

    Virtex-II Pro FPGA Architecture Review

    The Virtex-II Pro family, shipping sinceFebruary of this year, is the worlds first 130nm, 9-layer copper, FPGA family and thefirst and only one to offer integrated IBMPowerPC microprocessor technology and3.125 Gb/s serial transceivers. Its architec-ture is built upon the award-winningVirtex-II FPGA fabric, which already hasthousands of satisfied users.

    With 10 devices, multiple packages, andmultiple speed grades to choose from, theVirtex-II Pro FPGAs give you the rightfeatures and performance to meet yourspecific needs. The family, as shown inTable 1, includes:

    Immersed IBM PowerPC processors (0 to 4)

    Integrated 3.125 Gb/s Rocket I/Otransceivers (0 to 24)

    The award-winning Virtex-II FPGA fabric.

    device in the world that competes with itin features, performance, or cost. Withsuch unparalleled leadership advantage,the Virtex-II Pro Platform FPGAs put youon a platform of success, closer to yourdesign goals.

    Expanding the Market and Target Applications

    The new -5 speed grade delivers cost-effective 2Gb/s transceiver performance,with over 266 MHz embedded PowerPCprocessor performance. In comparison,our fastest devices (-7 speed grade) provide up to 3.125 Gb/s transceiver per-formance, with over 300 MHz embeddedPowerPC processor performance. The -5speed grade is therefore ideal for mediumto high-speed applications including stor-

    Summer 2002 Xcell Journal 13

    Figure 1 - Virtex-II Pro Platform FPGA

    The Virtex brand has been the number one choice of designers worldwide, based on its industry-leadingcapacity, performance, capabilities, and cost-effectiveness. In each generation of families, our mission is to deliver significantly enhanced functionality while driving down prices. We continuethis strategy in the Virtex-II Pro family by including state-of-the-art multi-gigabit serial trans-ceivers and high-performance PowerPC RISC CPUs, in the standard feature set, at no charge. Thus, we enable the creation of next-generation systems designs at previously unattainable price points.

    Erich Goetting Vice President and General Manager of the Xilinx Advanced Products Division

  • New Products FPGAs

    IBM PowerPC Processors

    Each immersed IBM PowerPC processorruns at up to 300+ MHz and 420+Dhrystone MIPS providing high-perform-ance embedded processing. The PowerPCprocessor is supported by the IBMCoreConnect bus technology. A com-plete set of embedded software tools areavailable to help you quickly develop anddebug your PowerPC designs through anOEM agreement, Xilinx provides softwaretools from Wind River Systems, cus-tomized for Virtex-II Pro FPGAs.

    Rocket I/O Multi-gigabit Transceivers

    The Rocket I/O multi-gigabit trans-ceivers (MGTs) are based on theMindspeed SkyRail CMOS technology.Each transceiver runs at rates ranging from622 Mb/s to 3.125 Gb/s, and includes theentire transceiver support circuitry. EachRocket I/O transceiver consists of both adigital Physical Coding Sublayer (PCS), aswell as an analog Physical MediaAttachment (PMA), to provide an integrat-ed SerDes (serializer/deserializer) function.

    Award-winning Virtex-II Fabric

    The Virtex-II FPGA fabric provides fea-tures for high-performance system design

    that has made it a platform of choice for users. These features include:

    High-performance logic with a widechoice of densities

    Embedded block RAM

    XtremeDSP embedded hardware multiply circuitry

    Advanced digital clock management circuitry

    XCITE technology for digitally con-trolled impedance matching on I/Os

    Bitstream encryption technology fordesign protection

    Flexible Select I/O-Ultra technologyfor supporting over 20 single-ended anddifferential I/O signaling standards.


    The expanded Virtex-II Pro family pro-vides a broad choice of 10 devices in scala-ble features and speed grades. It marksleadership in every facet, providing morecapability than any other competing pro-grammable logic device. In addition, thenew pricing delivers programmable systemfeatures at programmable logic prices,making embedded PowerPC processorsand multi-gigabit transceivers standard fea-tures in high-performance programmabledevices. For more information on Virtex-IIPro Platform FPGAs and design resources,go to www.xilinx.com/virtex2pro.

    14 Xcell Journal Summer 2002

    With the immersion of PowerPC cores, Xilinxhas developed the optimal platform to imple-ment our storage network designs. Virtex-II Prodevices provide the critical elements of system-level design, including high-speed serial I/O,making it an ideal combination for our nextgeneration products. Moreover, the uniquearchitectural synthesis design environmentallows us to make hardware and softwaretradeoffs throughout the design cycle.

    Sandy Helton Executive VP and CTO, SAN Valley

    Device XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100 XC2VP125

    Logic Cells 3,168 6,768 11,088 20,880 30,816 43,632 53,136 74,448 99,216 125,136Block RAM (Kbits) 216 504 792 1,584 2,448 3,456 4,176 5,904 7,992 10,00818x18 Multipliers 12 28 44 88 136 192 232 328 444 556

    Digital Clock Management Blocks 4 4 4 8 8 8 8 8 12 12Configuration Memory (Mbits) 1.31 3.01 4.49 8.21 11.36 15.56 19.02 25.6 33.65 42.78

    IBM PowerPC Processors 0 1 1 2 2 2 2 2 2 4Multi-Gigabit Transceivers 4 4 8 8 8 12* 16* 20 20* 24*

    Max Available User I/O 204 348 396 564 692 804 852 996 1164 1200


    FG256 140 140FG456 156 248 248FF672 204 348 396FF896 396 556 556

    FF1152 564 692 692 692FF1148* 804 812FF1517 804 852 964FF1704 996 1040 1040

    FF1696* 1164 1200

    *Note: FF1148 and FF1696 packages support higher user I/O and zero Rocket I/O multi-gigabit transceivers

    Table 1- Virtex-II Pro Platform FPGAs Power of Choice (new -5 devices shown in red)

    Figure 2 - Expanding the market from ultra-high speed to medium-high speed applications

  • by Simon CockingDesign ConsultantHelion Technology [email protected]

    As secure communication data ratesincrease, software implementations of thekey data encryption algorithms present amajor system bottleneck. To make mattersworse, standard off-the-shelf CPUs andDSPs have failed to keep pace with thecomputational demands of data encryptionalgorithms. Besides, CPUs and DSPs justhave too many other tasks to perform.

    The magnitude of the software perform-ance gap for high-speed data encryption isillustrated by the benchmark results shownin Table 1. These figures are for imple-mentations of the new 128-bit AdvancedEncryption Standard (AES) algorithm run-ning on standard CPU and DSP architec-tures as compared to how a Virtex-IIPlatform FPGA solution based on a FastAES core from Helion Technology Ltd. canprovide the multi-gigabit encryption datathroughput required by high-speed inter-connect technologies.

    Technology Focus Virtex-II Platform FPGA

    How to Use Virtex-II FPGAs to Deliver Gigabit Advanced Data Security with HelionEncryption Cores

    Summer 2002 Xcell Journal 15

    How to Use Virtex-II FPGAs to Deliver Gigabit Advanced Data Security with HelionEncryption Cores Virtex-II Platform FPGAs enabled Helion Technology Ltd. not only to deliver on time but to exceed the clients requirements.

  • Technology Focus Virtex-II Platform FPGA

    The Design Brief

    Last year, we at Helion were asked by oneof our clients to provide a flexible, highperformance FPGA-based data securityengine to handle encryption of InternetProtocol (IP) packet-based data for theirnext-generation network security products.Even though their product was based on ahigh-performance dual 64-bit MIPS net-work processor, benchmarking had showna software encryption solution to be some-what short of achieving the minimum 600Mbps throughput our client required.

    The system requirement was for a PCI-based engine that could accommodatemultiple encryption algorithms: AES anda proprietary algorithm for legacy purpos-es. The solution had to be low cost, capa-ble of supporting gigabit data rates, andflexible enough to allow for future algo-rithm changes.

    After evaluating the available options, theonly solution that met all of the require-ments was a PCI card containing the onemillion-gate Virtex-II XC2V1000 PlatformFPGA. The device incorporated a XilinxLogiCORE 32-bit/66-MHz PCI coreand Helion-designed encryption cores.

    Why Use a Virtex-II FPGA?

    From our many years of design experiencewith leading edge technology, we werewell aware of the potential pitfalls, such asinadequate design tool support andunavailable parts. Fortunately, Virtex-IIPlatform FPGAs use the same EDAtoolset as earlier technologies, and theXC2V1000 device was already in produc-tion. The reasons for choosing theXC2V1000 instead of the more estab-lished Virtex-E family were compelling:

    Costs The Virtex-II XC2V1000 costless than half the nearest equivalentVirtex-E(-8) device.

    Performance Benchmarking with theHelion AES core showed the Virtex-II(-4)FPGA to be 30% faster than the nearestequivalent Virtex-E(-8) device.

    controller. This configuration allows theencryption keys to be easily changed bysoftware an important security feature.

    The DMA read-and-write buffers useblock RAM to support the long PCI burstread-and-write transfers needed to achieveoptimum performance. Checksum calcu-lation and buffering is also provided forthe encrypted data (ciphertext) to off-loadthis task from the system software, whichreads the checksum(s) at the end of eachDMA transfer.

    The main data path between the DMAbuffers is through the encryption cores. TheHelion 128-bit fast AES encryption core hadalready been developed, so it was simply acase of dropping it into the design. However,it was still necessary to develop a high-per-formance core for the proprietary algorithm.

    Encryption Engine Operation

    While the encryption engine is inactive (noDMA encrypt transfer in progress), thePCI interface defaults to target mode andwaits for the system CPU to initiate aDMA transfer. Once a DMA operation isrequested, the PCI interface is switched tomaster mode, and the DMA controllerinitiates the required bus transfers.

    Upon completion, the encryption engineasserts the PCI interrupt request andreturns the interface to target mode sothat the system CPU can read the check-sums and/or start the next transfer.

    Bigger and wider block RAM We found32-bit wide data buffers were more effi-ciently implemented in Virtex-II blockRAM. For example, a 512x32 bufferrequired only a single Virtex-II block RAMrather than four in Virtex-E technology.

    Enhanced CLBs The MUXF7 andMUXF8 primitives allowed up to fourslices to be combined for fast imple-mentations of any logic function up toeight inputs wide. This led to fewerlogic levels and faster critical paths forthe very wide logic functions typical ofencryption algorithms.

    Digital Clock Manager (DCM) Trueclock frequency synthesis allowed theencryption data clock to be tuned toclosely match worst-case PAR (place-and-route) timing, optimizing encryp-tion throughput.

    Easier Design Implementation The rawspeed of Virtex-II devices meant no PARguide file was required for theLogiCORE 66-MHz PCI bus logic.

    Encryption Engine Overview

    A block diagram of the encryption engineis shown in Figure 1. The only externalinterface is the LogiCORE 32-bit/66-MHzPCI bus.

    All encryption key information and data tobe encrypted (plaintext) are stored in PCIsystem memory and transferred into theFPGA by the direct memory access (DMA)

    16 Xcell Journal Summer 2002

    Solution Clock (MHz) Encryption Data Rate Comments

    TMS320C62XX 32-bit 200 112 Mbpsfixed-point DSP

    MIPS-based 64-bit 250 392 Mbps Assumes fully primed cache and RISC processor CPU fully dedicated to encryption

    Pentium III 1,000 464 Mbps Assumes fully primed cache and CPU fully dedicated to encryption

    Helion Fast AES Core 132 1536 Mbps Virtex-II XC2V1000-4 target

    Table 1 - Typical achievable data rates for 128-bit Advanced Encryption Standard solutions

  • Technology Focus Virtex-II Platform FPGA

    Because the plaintext data stream writteninto PCI system memory can be frag-mented into multiple IP packets, the sys-tem software is responsible for creating acontrol data structure that details the size,location, and number of fragments, aswell as the encryption type to use. Thisstructure is transferred from memory intoa block RAM in the DMA controller atthe start of each encrypt transfer.

    The encryption engine can then read inall plaintext fragments, encrypt themusing the selected algorithm, and re-assemble the ciphertext fragments inmemory. In the process of writing cipher-text back to memory, a checksum is cal-culated for each encrypted fragment, andthis value is added to a total checksum ofall fragments. These checksums are storedin a small distributed RAM in the FPGA,and then read back by the system CPU atthe end of each transfer.

    Encryption Engine Performance

    Our client was delighted to learn that notonly was the final encryption enginedesign delivered on time, but that it alsoexceeded the required data throughput forboth encryption algorithms by a signifi-cant margin.

    The proprietary algorithm core isclocked at 66 MHz to achieve a rawencryption throughput of 990Mbps. The AES core is clockedat 132 MHz to yield a rawencryption throughput of1.536 Gbps.

    However, these rawthroughput figures aredegraded somewhat inthe final system due tobus arbitration over-head in the PCI bridge.In fact, the data throughput of theHelion fast AES core is so high that themaximum available bandwidth on the 32-bit/66-MHz PCI bus acts as a ceiling onits performance.

    Frequent changing of the encryption keyswill also lead to a reduction in overall dataencryption throughput due to theincreased transfer load on the PCI bus.


    The encryption engine project wevedescribed is a great example of how acombination of third-party intellectualproperty cores and Virtex-II PlatformFPGA technology can yield flexible,high-performance security products inrecord time.

    A large reduction in the effort required toimplement such a design relies on theready availability of intellectual propertylike the Xilinx LogiCORE PCI productsand the range of advanced encryptioncores we have developed at Helion. Designblocks like these enable a single engineer toattack a million-gate design and achieveresults in a matter of weeks.

    Future plans for our encryption engineinclude the use of a higher bandwidth businterface, such as HyperTransport tech-nology in place of PCI. We also plan theaddition of multiple AES cores to provide afull-duplex (encrypt and decrypt), higherperformance solution.

    The Helion encryption cores allow for evenhigher throughput: Eight similar Fast AEScores in a larger Virtex-II Platform FPGAcould provide encryption at rates in excess of12 Gbps. This is fast enough to supportemerging high-speed interconnect standards,such as OC-192, 10 Gigabit Ethernet, POS-PHY L4, and RapidIO Phy.

    For more detailed information on Helion andour products and services, please visit theHelion website at www.heliontech.com.

    Summer 2002 Xcell Journal 17

    Figure 1 - DMA encryption

    engine block diagram

  • by Steve ProkoschCPLD Product Marketing Xilinx, [email protected]

    When Xilinx asked design engineers whatthey expected from the new generation ofcomplex programmable logic devices(CPLDs), their responses showed theypretty much wanted it all:

    Advantages derived from state-of-the-artfabrication processes

    More industry standard I/O features

    System security

    Lower power operation

    Higher performance.

    Designers required the next generation ofCPLDs to increase performance of bat-tery-powered devices. And, they stipulat-ed that the next generation of CPLDsmust improve performance withoutpower penalties and with the featuresand functions that would meet the expec-tations of todays discriminating designersand cost-conscious consumers.

    In response to the high expectations of topdesign engineers, Xilinx has created theCoolRunner-II RealDigital CPLD. TheCoolRunner-II CPLD architecture intro-duces, for the first time, the advantage ofboth high performance and low poweroperation. The CoolRunner-II RealDigitalCPLD reprogrammable logic solution justmay be the defining element of a new eraof CPLD-based applications small formfactor, high performance, power sensitiveproducts that are feature rich and protectedby multiple levels of security.

    New Product CPLD

    Xilinx CoolRunner-II RealDigital CPLDs consume less powerand offer reprogrammable flexibility with unprecedenteddesign security without a price premium.

    CoolRunner-II CPLDsGo All Digital

    18 Xcell Journal Summer 2002

    CoolRunner-II CPLDsGo All Digital

    Xilinx CoolRunner-II RealDigital CPLDs consume less powerand offer reprogrammable flexibility with unprecedenteddesign security without a price premium.

  • New Product CPLD

    CoolRunner-II RealDigital CPLDs

    Evolutions of the XPLA (extended pro-grammable logic array) CPLD architecturehave led to this ultra low power, ultra highspeed, reprogrammable CMOS logic thatoffers significant improvements over earliergenerations. (See sidebar The Evolution ofLow-Power CPLDs.) These capabilitiesare aiding in dramatic device size reduc-tions and performance increases that areenhancing the look and feel of both hand-held and high performance products.

    The CoolRunner-II RealDigital CPLDdelivers on several design fronts: low power,high performance, design flexibility, andsecurity. Today, designers can choose highperformance devices that do not requireextra power for speed.

    Process Technology

    The CoolRunner-II family of CPLDs hasbenefited from the leading edge of XilinxFPGA (field programmable gate array)process technology. The originalCoolRunner CPLD architecture began ona 0.5-micron process and then migrated to0.35 micron.

    Today, the CoolRunner-II CPLD family ismanufactured using a 0.18-micron processtechnology the same as the high-endXilinx Virtex-II FPGAs. With this ultrahigh density process technology, and scala-ble CMOS architecture, it is now possibleto lower power consumption even furtherthan before.

    Multiple I/O Features

    To facilitate its use in multiple systemarchitectures, various input/output (I/O)standards have been incorporated in theCoolRunner-II interface. These include:


    LVCMOS 33, 25, 18

    SSTL2-1, SSTL3-1


    1.5V I/O.

    High-speed transceiver logic (HSTL) I/Ostandards are common in high-speed mem-ory interfaces. Stub-series terminated logic

    DataGATE makes it possible to reducepower consumption by reducing unneces-sary toggling of inputs when they are not inuse. A prime example of this would be abus interface. These input signals wouldbecome active only when information ispassed to the CPLD. This eliminates theunnecessary switching from high tolow/low to high. As bus interfaces grow, sowill the power demand from needlessswitching of input signals.

    CoolCLOCK, another CoolRunner-II lowpower enhancement, is implemented bydividing, then doubling, a clock signal.Using Global Clock 2 (GCK2) clock inputand dividing by 2, then doubling the clockat the macrocell, performance can be main-tained while lowering power consumption.The CoolCLOCK method is easily synthe-sized and is available on 128 macrocell andlarger devices.

    Schmitt Trigger

    When communicating with CPLD designengineers, we discovered they were lookingfor an easy method to interface to noisyanalog components. Thus, CoolRunner-IICPLDs incorporate Schmitt trigger inputs,which are helpful by delaying the switchingtime on slow rising or falling signals.Schmitt trigger inputs also help eliminate

    (SSTL) is associated with circuit designswhere buses must be isolated from relative-ly large stubs. With these added I/O stan-dards, CoolRunner-II CPLDs can easilyadapt to a variety of interfaces that otherlow power processors might not be able tohandle. This makes CoolRunner-II CPLDsa great system integration solution formicroprocessor-based applications.

    100% Digital Core

    CoolRunner-II RealDigital CPLDs do notuse traditional sense amplifier technology and that means the historical tradeoffbetween speed and power has been elimi-nated. RealDigital technology has enabledXilinx to offer the industrys lowest powerconsumption and highest performance ona single device with no price premium.

    Low Power Enhancements

    Learning that designers of portable prod-ucts wanted even lower power thanCoolRunner XPLA3 CPLDs, Xilinx addedarchitectural features to accommodate tightpower budgets. Even with FZP (Fast ZeroPower) technology and voltage reduc-tion, we still had to add two new architec-tural features to lower overall power con-sumption in designs for power sensitiveapplications. Those features are DataGATEand CoolCLOCK.

    Summer 2002 Xcell Journal 19

    Figure 1 - Xilinx CoolRunner-II CPLD product family

  • New Product CPLD

    false switching due to noise spikes. The pos-sibility also exists to form a simple oscillatorcircuit from these inputs. You must exercisecare to assure reliability, but it can savecomponent costs on simple circuit designs.


    The loss of intellectual property is always aconcern for electronic equipment manufac-turers. With CoolRunner-II RealDigitalCPLDs, security was enhanced to eliminatethe possibility of code theft. The securitybits are scattered and affect different modesof operation. If any tampering of the securi-ty chain is detected, the device automatical-ly locks down and is erased. Even if thedevice is de-capped, buried interconnectsmake it almost impossible to trace securityconnections without destroying the device.Security details cannot be discussed evenunder non-disclosure agreements, thusensuring ultimate protection.

    User-Defined Grounds

    As voltage levels decrease, noise andground bounce become larger factors insignal integrity. Now, a few hundred mil-livolts is the difference between on andoff, versus a few volts in legacy devices.We had to take extra care in design andlayout to shorten signal paths and mini-mize potential interference.

    Differential signaling (SSTL and HSTL)serves as a good method to reduce noiseand increase signal integrity with the pro-vision that extra pins are available for dif-ferential I/O and reference voltage sources.

    To simplify the elimination of noise andground bounce, CoolRunner-II CPLDs alsoemploy software-definable ground pins.These programmable ground pins are anideal way to reduce noise and ground bounceeffects. By using neighboring I/Os as groundpins, CoolRunner-II devices can tolerate alarger amount of potential signal noise.

    Voltage Translator Clearinghouse

    Due to the availability of various specialtyelectronic devices, it may be necessary tointerface with multiple component voltagelevels. With CoolRunner-II RealDigitalCPLDs, I/O banking is an easy way to elim-

    inate voltage level translators. Banking isthe ability to separate function blocks withinthe CPLD so that these blocks can operateindependently at different voltage levels.

    For instance, one function block could beI/O compatible with 3.3V devices, andanother function block could interfacewith 1.8V devices. This saves board spaceand eases voltage level design issues.


    From process technology to a 100% digitalcore to added power reduction features,

    CoolRunner-II RealDigital devices markthe beginning of a new era for CPLDapplications. Many system design concerns including speed, power, I/O interfaces,clock management, and security havebeen consolidated into one reprogramma-ble logic solution: CoolRunner-IIRealDigital CPLDS from Xilinx.

    For more information, please visit www.xilinx.com > Products > CPLDs > IntroducingCoolRunner-II RealDigital CPLDs, orwww.xilinx.com/xlnx/xil_prodcat_product.jsp?title=coolrunner2_page.

    20 Xcell Journal Summer 2002

    A Short History of Low Power CPLDs

    The first reprogrammable logic devices have their roots in bipolar PROM (programmable read-only memory) technology, with added logic capacity and fea-tures. The first company to generate customer interest was Signetics, with theirintroduction of the 82S100 FPLA (field programmable logic array).

    Monolithic Memories Inc. attempted to be a second source supplier to the 82S100,but failed due to a process technology mismatch. They instead developed the nowfamous PAL (programmable array logic). This development by MMI led to aggres-sive process technology shrinks and increased speeds as logic designers pushed forfaster state machine operation.

    Philips Semiconductors purchased Signetics, and in 1977, acquired a second sourcelicense for the PAL from MMI. Philips continued to work on different architec-tural enhancements and migrated to a BiCMOS (bipolar CMOS) process. Whenthe first 22V10 PAL from AMD hit the market, it was a greater success than any-one anticipated. From this beginning, devices matured into what are now knownas CPLDs. Xilinx entered the CPLD market in the early 1990s by acquiring PlusLogic and introduced the 7200 family of CPLDs.

    CMOS CPLD products use power for speed improvements by partially turning on(biasing) transistors and by using sense amp technology. In the past, this was aneasy way to promote devices and claim a speed advantage. The by-product, how-ever, was heat.

    In 1994, Philips Semiconductors made the move to CMOS CPLDs. With thisdecision, CPLDs broke away from their BiCMOS PROM roots and entered intothe scalable process technology arena. These products reflected innovativeapproaches in circuit design with an awareness of power consumption by removingthe old bipolar style sense amplifier from the circuitry.

    Xilinx purchased the CoolRunner line of CPLDs from Philips Semiconductors in1999 to penetrate the low power CPLD market segment. Today, ultra high densityCMOS processes (0.18 micron) make possible reduced size and lower power con-sumption, which directly reduces heat dissipation.

    Consumers demands for smaller, faster, cheaper, better products are the drivingforces in todays competitive markets and the state-of-the-art CoolRunner-IIRealDigital CPLDs meet these demands.

  • by Alicia TrippManager, Business Continuity ProgramXilinx, [email protected]

    Our customers depend on us and youexpect us to provide reliable product andconsistent service, even in the event of adisaster or interruption to our business. Forthese reasons and for the benefit of ourstakeholders, we incorporated the BusinessContinuity Program (BCP) into the Xilinxculture in June 2000. The BCP is a corpo-ration-wide initiative that is supported byour Board of Directors and throughout ouremployee population.

    We began the program by conducting abusiness impact analysis (BIA) and a threatand risk assessment (TRA) to determinethe critical business processes within thecompany. In addition, the BIA and TRAprovided an understanding of the impactof the loss of one or more of the criticalfunctions. Once the analyses were complet-ed, more than 80 departmental recoveryplans were developed. The recovery plansare the road maps that will allow us to con-tinue providing products and services toour customers during a major disruption.

    Incident management teams (IMTs) areone of the most vital parts of the BusinessContinuity Program. We have locatedIMTs strategically throughout the Xilinxenterprise. Each team consists of membersof functional business units within thecompany such as Human Resources, Legal,Purchasing, Security, Facilities, RiskManagement, Accounting, and Safety. TheIMTs are responsible for handling theevent, from the time of a disaster throughrecovery and restoration activities. The pur-pose of the IMTs is to protect the healthand safety of our employees, to guide thecompany through a crisis, and to provide astructured organization for overseeing theresponse. These teams will conveneduring a major business interrup-tion to assess the situation anddetermine if a disaster shouldbe declared and whether ornot to launch departmen-tal recovery plans.

    Incident management teams convenedfour times in less than 48 hours after theSeptember 11, 2001, terrorist attacks tomake plans to assist our employees. Wewere able to have counselors on site, and

    travel representatives helped employeestraveling on business to schedule returnflights home.

    The Business Continuity Program has beensuccessfully integrated into our businessculture in large part, because of the top-level support from executive management.From the very beginning, our executivestaff has been onboard to make sure theprogram goals and objectives are achieved.

    The BCP includes an executive awarenessand ongoing plan development that helpsour executive officers to continue to beinvolved and ready to respond. This execu-tive awareness plan will allow Xilinx to prop-

    erly manage any incident from the timea disaster is declared through recov-ery and restoration activities.

    Recovery plans and IMTs are exer-cised on a regular basis. By devel-oping and actively maintaining

    the Business Continuity Program, weare prepared to limit the effect a long-termbusiness interruption might have on Xilinx and to mitigate the impact on our customers.

    Please contact your local sales representa-tive for additional information.

    Services Business Continuity

    War, natural disasters, terrorism, economic ruin, and other catastrophes cant be prevented, but their effects can be attenuated. Xilinx has in place a Business Continuity Program designed to minimize the impact on your business.

    If Disaster Strikes, Xilinx Is Prepared

    Summer 2002 Xcell Journal 21

  • by Lee HansenProduct Marketing ManagerXilinx, [email protected]

    Your Xilinx programmable logic deviceoffers you more capabilities than everbefore, and coming releases of the ISEdesign tools will help you to handle thepressure that comes from using thesecomplex new features. Come along for aglimpse into the future of ISE.

    ISE Delivers a Wealth of Device Features

    The most compelling pressure on thelogic design flow comes from the addedcomplexity of new capabilities and toolfeatures. Embedded systems, increasedclock speeds, verification of high-densitydesigns, new device capabilities, high-speed I/O, a variety of IP (intellectualproperty) sources, and design reuse all ofthese logic trends force more requirementsinto the design flow.

    New Products ISE Software

    Xilinx Integrated Software Environment (ISE) design tools promise to manage design complexity and, at the same time, ensure your logic design flow is easy to use.

    22 Xcell Journal Summer 2002

    Even as Designs Grow MoreComplex, Xilinx SoftwareImproves Your ProductivityXilinx Integrated Software Environment (ISE) design tools promise to manage design complexity and, at the same time, ensure your logic design flow is easy to use.

    Even as Designs Grow MoreComplex, Xilinx SoftwareImproves Your Productivity

  • New Products ISE Software

    In 2001, the Virtex-II FPGA intro-duced a revolution in clock capabilitieswith Digital Clock Manager (DCM),and this year, the Virtex-II ProPlatform FPGA broke new ground bydelivering 3.125-gigabit serial I/O trans-ceivers and embedded IBM PowerPCmicroprocessors. As the demand formore device features continues to grow,engineers must learn all the program-ming attributes for these new features and the learning curve escalateswith the introduction of each newdevice feature.

    To ease the learning curve, Xilinx ISE 5.1i will offer designers evenmore interactive architecture anddesign assistance. In addition toquick and easy dialogs, wizards willautomatically step you through con-figuring advanced device features andinserting those configurations direct-ly into your HDL source code.Upcoming releases of ISE will softenyour learning curve, helping to speeddesign completion.

    ISE Enables IP Capture and Design Reuse

    As design sizes grow, source manage-ment and methods to improve sourcecode productivity must keep pace. In amulti-million-gate design, source codecan come from multiple resources,including purchased IP, developed code,and design reuse modules of HDLdeveloped and proved in a prior design.

    In upcoming releases of ISE, it will bepossible to capture proven IP modules atthe floorplan level. This captured IP willnot be just a module of code, but it willalso have attached relative placement andfloorplanning area information that willhelp speed implementation in later uses.

    As time-to-market pressures increase,design change impacts late in the designcycle will become an even larger designchallenge. Enhancements to ISE willconfine late-cycle design changes to onlythat portion of the design that isrequired to change. The remainder of thedesign will be left intact, thus speeding

    A Higher Level of Abstraction Is Coming

    While high-level languages (HLLs) havebeen explored in logic and systems design,the pain of existing logic design method-ologies hasnt been great enough to force ahigh-level language or associated method-ology into common use.

    Verilog and VHDL have served the logicdesign space well for the last two decades,

    but now logic design sizes are routinelyexceeding one million gates. These mil-lion-gate-plus designs require large andcumbersome HDL source code and longperiods of debugging time. Emergingembedded processor methodologies arealso complicating the design process.Moreover, the need to serve two distinctlanguage-driven design flows (hardwareand software) is now making HLL designsupport imperative.

    Xilinx is investing time and technologyin the industry-wide HLL effortsthrough partner technologies such asSynopsys SystemC and CeloxicaHandel-C as well as through ForgeCompiler, which Xilinx acquired fromLavaLogic two years ago. The resultsare leading to optimized performancefor FPGA devices, and to better inte-

    gration of the co-design and co-verifica-tion phases of the embedded systemsdesign flow.

    Longer-term technology is also beingdefined to help you architect the poten-tial design at the HLL source code level,analyze what modules should be imple-mented in the logic design flow, anddetermine what modules are required inthe processor design flow to reach opti-mum system performance.


    New device capabilities will continue to pushdesign complexity. The good news is thatXilinx design tools are keeping pace. Newreleases of ISE software will help you keepyour design time down and your time tomarket fast. For more information on XilinxISE logic software, go to www.xilinx.com/ise and watch for the release of ISE 5.1i coming in late summer.

    overall design completion. This technolo-gy is enabled by new floorplanning capa-bilities along HDL hierarchy boundariesthat make it easier to define areas of logic.

    High-Speed Design Will Push Innovation

    High-speed design pressures will continueto push more innovation into logic designand into the board design flow.

    Timing analysis and timing constraintshave until now lived under two differ-ent analysis domains, separated at theFPGA pin. The logic designer has lookedto the specification and timing require-ments to define design closure, while theboard designer has picked up the signal atthe logic pin and attempted to lay out andanalyze the effects that the PCB trace willhave on that signal.

    Now, however, the line between logicdesigner and board designer functions willbegin to blur as timing constraint lan-guages become more uniform across thelogic tools and among the logic-level andboard-level tools. Trace analysis packagesalso will increasingly use more complex pinmodels provided by the logic tools, butthese complex analyses will also becomemuch faster, dumping slower general ana-log simulation in favor of specialized trans-mission line trace simulations.

    Summer 2002 Xcell Journal 23

  • by Jean-Louis Brelet, Manager APD Technical Market ResearchXilinx, [email protected]

    What is hardware/software co-design?

    Hardware/software co-design generallymeans that the hardware and software aredeveloped at the same time some softwarefunctions may be implemented in hardwarefor additional speed, and some hardwarefunctions may be implemented in softwareto free up logic resources.

    What does XDS do?

    Xilinx Design Services, located in Dublin,Ireland, is part of the Xilinx Global ServicesDivision (GSD). XDS has two functionalgroups: software engineers who provide cus-tom software solutions, and hardware engi-neers who provide custom hardware solu-tions. The combined team consists of morethan 50 engineers.

    Typically, we help customers with their fullproduct life cycle, from requirements cap-ture, through design implementation andtest, to final acceptance and delivery. Wework very closely with our customers, andform a team of experts who best match thejob requirements.

    Perspective Virtex-II Pro

    To explore the possibilities of hardware/software co-design, the Xilinx Design Services team created a reference designfor a real-time operating system (RTOS) for telecommunications here is an interview with the team.

    Exploring Hardware/Software Co-Design with Virtex-II Pro FPGAs

    24 Xcell Journal Summer 2002

    In this interview, Jean-Louis Brelet,manager of Technical Market Researchfor the Xilinx Advanced ProductsDivision, interviewed Xilinx DesignServices (XDS) software and hardwareengineers about their practical experiencewith an RTOS reference design project.Senior Project Engineer Matthew Rocheacted as spokesman for XDS.

  • Perspective Virtex-II Pro

    What are your previous experiences with embedded software?

    We have worked on technologies thatinclude:

    Digital video systems both set-top boxesand head-ends

    High speed digital network communica-tions systems

    Automotive applications

    Real time operating systems

    Board-level designs.

    Due to the nature of design services, we haveattained experience from many differentdevelopment environments and methodolo-gies. We have experience with a wide rangeof designs, for device-level to system-levelapplications.

    How would you describe the Virtex-II ProFPGA family from a software perspective?

    The introduction of PowerPC processorsinto the Virtex-II Pro Platfrom FPGAarchitecture creates many new possibilities.Now we can design custom co-processorswith innovative (and fast) interfaces. Due tothe flexibility of the embedded IBM proces-sors, and their surrounding programmablelogic, we can offload some parts of our soft-ware design into a dedicated hardwareimplementation that can run much faster.

    Previous hardware/software designs havebeen based around an inflexible hard-ware/software interface.

    When did you startto design for thenext-generationVirtex-II ProPlatform FPGA?

    As soon as the tech-nology becameavailable, it became

    apparent that we must evaluate the systemin a real project situation the RTOS ref-erence design. This way we could becomeaware of the new possibilities offered by theVirtex-II Pro device and be best placed tocontribute our knowledge of the advancedarchitectures used by our customers.

    and capabilities of thehardware.

    Likewise, the hard-ware team must havea good understand-ing of software andhow the applicationoperates. Both teams

    must have a common language or a goodunderstanding of each others languageand a willingness to adapt.


    What is your approach at the system level topartition embedded hardware and softwarefunctions?

    We designed and implemented the RTOSreference design project for telecommunica-tions with resource-constrained processors.We built it for state-based SDL (specifica-tion and design language) applications.

    The application for this RTOS was to bein systems with high numbers of processeswith large numbers of context switches. At this level, the overhead of the operatingsystem would be significant and thus,must be minimized.

    First, we analyzed the system and identifiedthe time-hungry elements. Our initial per-formance analysis indicated that processingof the state tables and managing the mostheavily used queues (signal queues) were theprocessor-intensive tasks. The first iterationsof the design placed these tasks into hard-ware with a clearly defined hardware/soft-ware interface. This did not completelyremove the bottlenecks, but it did have atendency to move them from the processinginto the interface.

    Further iterations of the design requiredmuch closer integration of the hardwareand software teams. This allowed thedesign of coherent and integrated tasks,which could be completely dealt with inhardware, and required minimal use ofthe interface.

    Having the processor embedded into theFPGA fabric allows a variety of interfacetechniques, which do not necessarily requirethe use of the IBM CoreConnect proces-

    Project Objectives

    What are the main objectives of this project?

    The overall and real objective was to gainexperience in developing a product in atightly coupled hardware/software environ-ment. The ability to shift functions fromsoftware to hardware, or vice versa, in a veryshort time frame, creates an environmentwhere the design teams need a much greaterknowledge of each others work.

    The smaller and more restricted objectivewas to identify the speed bottlenecks in theRTOS and remove the bottlenecksthrough the use of dedicated hardware effectively implementing large sections ofthe kernel in hardware.

    Before Virtex-II Pro FPGAs, how would youdevelop a system like this?

    The RTOS project is very suited to theVirtex-II-Pro architecture. Given thecosts, project time, cycle time, and riskrequired to develop this project with othertechnologies for example, an ASIC itis unlikely that it would even be under-taken. An ASIC design doesnt offer youthe benefit of reprogrammability and flex-ibility to change/improve or upgrade thesystem in the field.

    What is the expertise required to successfullyimplement these systems?

    Software people must understand the natureof hardware designs and the type of prob-lems encountered by the hardware team.They also must understand the possibilities

    Summer 2002 Xcell Journal 25

    Mathew Roche

    Jean-Louis Brelet

  • Perspective Virtex-II Pro

    sor local bus. This feature became an impor-tant design issue, as the speed of the systemwas capable of hogging the bus.

    In our experience, we have found that thereis no distinct division between functionsthat are suitable for hardware or software. Itbecomes a trade-off of how fast you want todo something and how many configurable

    logic blocks you want to spend on doing it.Greater complexity of the function orrequired speed of operation will bias thedesign towards software or hardware.

    How would you summarize your method forpartitioning the system?

    We simply integrated the design teams, toavoid a purely hardware- or software-ledsolution.

    How have you split the teamwork?

    Most of the software was designed first,because we needed to understand how thesystem would operate before transferringparts of it into hardware. This gave us theadvantage of having functioning proto-types before a full hardware implementa-tion significantly reducing our theoreti-cal time to market.

    At the system design level, the division oflabor became less important as the projectwent on. It was necessary for both sides tohave a good understanding of what theother team was doing. Design decisions hadto be made with knowledge of both hard-ware and software. This had some interest-ing implications for the language and termi-nology used by the teams.

    Virtex-II Pro Embedded Software

    Is it easier to create embedded software forthe Virtex-II Pro fabric?

    In the first applications, embedded softwaredevelopment techniques will not necessarilybe different for Virtex-II Pro devices theycan be viewed as conventional systems withperformance improvements and reducedchip count. However, as experience builds, itwill become apparent that traditional designmethods do not use the full potential of thedevice. System partitioning will become partof the architectural design process, and theboundary between hardware and softwarewill become less rigid.

    The RTOS project gave us an opportunityto examine the project with system co-design as the goal. Virtex-II-Pro PlatformFPGAs allow significantly more integrated

    designs with all the performance benefitsthat entails.

    What is the most innovative feature ofVirtex-II Pro for a software engineer?

    Using multiple processors (both IBMPowerPC 405 hard core and XilinxMicroBlaze soft core processors), on asingle chip, allow you to dedicate processesto particular processors for critical tasks.You can easily implement interfacesbetween the different processors, usinghardware-based FIFOs, reducing the com-munications bus overhead.

    How easy is it to partition a Virtex-II Pro design?

    Partitions are very flexible in the Virtexarchitecture. Changes were being made tothe interface all the way through the designand implementation of our RTOS system.This allowed us to reduce our design timeand minimize design roadblocks.


    Could you summarize your experience?