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THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS Issue 43 Summer 2002 R Xcell journal Xcell journal THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS ISSUE 43, SUMMER 2002 XCELL JOURNAL XILINX, INC. ANALYSIS Total Cost Management TECHNOLOGY How to Build Efficient FIR Filters Xyron Inc. Makes RTOS Breakthrough PERSPECTIVE Using DSP in Real-Time Video Processing NEWS IBM ASICs Incorporate Xilinx Technology Virtex-II Pro – New Products, Reduced Pricing Cover Story Xilinx CEO Wim Roelandts Reveals How to Survive a Recession and Gain Market Leadership ANALYSIS Total Cost Management TECHNOLOGY How to Build Efficient FIR Filters Xyron Inc. Makes RTOS Breakthrough PERSPECTIVE Using DSP in Real-Time Video Processing NEWS IBM ASICs Incorporate Xilinx Technology Virtex-II Pro – New Products, Reduced Pricing Cover Story Xilinx CEO Wim Roelandts Reveals How to Survive a Recession and Gain Market Leadership

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Page 1: Xcell Journal: Issue 43

T H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

Issue 43Summer 2002

R

Xcell journalXcell journalT H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

ISSUE 43, SUMM

ER 2002XCELL JOURNAL

XILINX, INC.

ANALYSIS

Total Cost Management

TECHNOLOGY

How to Build Efficient FIR Filters

Xyron Inc. Makes RTOS Breakthrough

PERSPECTIVE

Using DSP in Real-TimeVideo Processing

NEWS

IBM ASICs Incorporate Xilinx Technology

Virtex-II Pro – New Products,Reduced Pricing

Cover Story Xilinx CEO Wim Roelandts RevealsHow to Survive a Recession and Gain Market Leadership

ANALYSIS

Total Cost Management

TECHNOLOGY

How to Build Efficient FIR Filters

Xyron Inc. Makes RTOS Breakthrough

PERSPECTIVE

Using DSP in Real-TimeVideo Processing

NEWS

IBM ASICs Incorporate Xilinx Technology

Virtex-II Pro – New Products,Reduced Pricing

Cover Story Xilinx CEO Wim Roelandts RevealsHow to Survive a Recession and Gain Market Leadership

Page 2: Xcell Journal: Issue 43

ast year, Xilinx debuted at #14 on the FORTUNE 100 Best Companies to Work For™annual list. This year, we broke into the Top 10 with a ranking of #6 – the only Silicon

Valley/San Francisco Bay Area company to make the Top 10.

To help determine the new rankings, FORTUNE weighed how companies reacted to the economicdownturn of 2001. Although revenue at Xilinx declined by 50 percent over the course of 2001, thecompany decided employee layoffs would come only as a last resort. As a result of significant cost-cutting measures – including tiered salary cuts for everyone except the lowest paid employees – Xilinxmanaged to avoid layoffs, continued to bring remarkable new products to market, and became largerthan all other public programmable logic companies combined.

We believe the FORTUNE magazine ranking reflects the strong values we hold at Xilinx:

• Customer focus

• Respect

• Excellence

• Accountability

• Teamwork

• Integrity

• Very open communication

• Enjoying our work.

These CREATIVE values are a vital part of our culture, and they make a positive difference for ouremployees and our customers. Our values make Xilinx a great company to work for – and a greatcompany to work with. Our technology, our service, and our customer satisfaction continue to leadthe industry. We are always seeking new ways to make a real difference in our world. And, thoughtechnology drives our business, we’ve built our success on the strong partnerships we’ve created withour customers, our suppliers, and other technology leaders in our industry.

To learn more about the FORTUNE magazine’s top 100 companies to work for, go to: www.fortune.com/lists/bestcompanies/.

L E T T E R F R O M T H E E D I T O R

EDITOR IN CHIEF Carlis [email protected]

MANAGING EDITOR Tom [email protected]

CONTRIBUTING EDITORS Jane BratunBrendan BridgfordLeRoy MillerRyan Wilson

DESIGN & ILLUSTRATION Scott BlairDan Teie

Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124-3400Phone: 408-559-7778FAX: 408-879-4780©2002 Xilinx Inc.All rights reserved.

Xcell is published quarterly. XILINX, the Xilinx logo,CoolRunner, Spartan, and Virtex are registered trade-marks of Xilinx Inc. Alliance Series, Xilinx FoundationSeries, AllianceCORE, Foundation, IRL, LogiCORE,SelectI/O, WebPACK, WebPOWERED, WebFITTER,QPro, XPERTS, XtremeDSP, CORE Generator, RocketI/O, Fast Zero Power, SelectRAM, IP-Immersion,System ACE, ChipScope, and all XC-prefix products aretrademarks, and The Programmable Logic Company isa service mark of Xilinx Inc. Other brand or productnames are trademarks or registered trademarks oftheir respective owners.

The articles, information, and other materials includ-ed in this issue are provided solely for the conven-ience of our readers. Xilinx makes no warranties,express, implied, statutory, or otherwise, and acceptsno liability with respect to any such articles, informa-tion, or other materials or their use, and any usethereof is solely at the risk of the user. Any person orentity using such information in any way releases andwaives any claim it might have against Xilinx for anyloss, damage, or expense caused thereby.

We Did It Again – Only Better This TimeL

Xcell journalXcell journal

“Many Xilinx employees have told me how proud they are to

receive this recognition. It speaks as much about the great

culture we have created at Xilinx as is does about the quality

of people who work here.”

– Wim Roelandts, CEO, Xilinx Inc.

Tom DurkinManaging Editor

Page 3: Xcell Journal: Issue 43

How to Survive a Recession and Gain Market Leadership“I said from the beginning that we wanted to emerge from the recession a greater company – and I think we have achieved that.”

Contents Summer 2002Cover Story Page 4

Perspective

Customize Virtual Private Networks with Spartan-IIE FPGA Solutions Spartan-IIE FPGA solutions can help you to customize your virtual private network for highest performance, greatest security, and lowest cost.

When Total Cost Management Counts, Xilinx PLDs Pay OffCoolRunner-II CPLDs, Spartan-IIE FPGAs, and Virtex-II EasyPath Platform FPGAs can give you total system cost solutions superior to those of traditional ASICs.

Software Page 24

Exploring Hardware/Software Co-Design with Virtex-II Pro FPGAsTo explore the possibilities of hardware/software co-design, the Xilinx Design Services team created a reference design for a real-time operating system for telecommunications.

Applications Page 55

Page 8

Xcell journalXcell journal

Technology Focus Page 42

How to Survive a Recession and Gain Market Leadership ...........4

IBM ASICs Incorporate Xilinx Technology..................................7

Total Cost Management.........................................................8

New Virtex-II Pro Devices – Lower Cost.................................12

Virtex-II FPGAs Deliver Advanced Data Security .......................15

CoolRunner-II CPLDs Go All Digital .........................................18

If Disaster Strikes, Xilinx Is Prepared .....................................21

Xilinx Software Improves Your Productivity.............................22

Hardware/Software Co-Design with Virtex-II Pro FPGAs ...........24

Virtex-II Pro Platform FPGA Drives Convergence ......................27

Xilinx Offers End-to-End Solutions .........................................30

FPGAs – Enabling DSP in Real-Time Video Processing..............32

FPGAs Provide Flexibility in Digital TV Development.................36

Xilinx Technology Can Disable Stolen Cell Phones....................39

Customize Virtual Private Networks.......................................42

Build Secure and Robust Wireless Communications .................44

Leading Technologies for Wired Home Networking ..................48

You Can Take It With You: On the Road with Xilinx.................52

Build an Efficient FIR Filter Using System Generator ................55

Xilinx Software Tools to Reduce Line Echoes...........................58

SystemIO Solution Expands with Bandwidth Demands.............59

Develop MicroBlaze Applications...........................................62

Xyron Semiconductor’s RTOS Breakthrough ............................64

Power Supply Solutions for Virtex-II Pro Platform FPGAs ..........66

Nallatech’s DIME-II Architecture Goes Pro ...............................68

Platform FPGAs Take on ASIC SOCs ......................................70

CoolRunner-II Data Sheet.....................................................74

Reference Pages ................................................................86

How to Build an Efficient FIR FilterUsing System Generator Xilinx System Generator 2.2 software enables high-level modeling and implementation of DSP systems in Xilinx Platform FPGAs to outperform traditional DSP processors.

Develop MicroBlaze Applications with ThreeFlexible Hardware Evaluation PlatformsMicroBlaze Development Kits from Memec Design demonstrate the versatility of the MicroBlaze soft processor core in a variety of Xilinx FPGAs.

New Products Page 62

Reference Page 74

CoolRunner-II Data SheetRealDigital CPLDs consume only microwatts of power, yet provide very high performance – take a look at what’s “under the hood.”

Subscribe to the Xilinx Xcell Journal at: www.xilinx.com/forms/literature.htm.

Visit Xcell Online for the latest news and information, as soon as it arrives at: www.xilinx.com/publications/xcellonline/.

Page 4: Xcell Journal: Issue 43

How to Survive a Recession and Gain Market Leadership

4 Xcell Journal Summer 2002

Cover StoryView from the Top

”I said from the beginningthat we wanted to emergefrom the recession a greatercompany – and I think wehave achieved that.“

Page 5: Xcell Journal: Issue 43

by Wim RoelandtsCEO, Xilinx, Inc.

Last year was avery difficult yearfor the semicon-ductor industry.In fact, it was theworst recession

ever in the history of semiconductors. In1985, the industry decreased in a year-over-year basis by 17% to 18%. In 2001,the decline was 32% to 33% – almosttwice as bad as 1985.

Nevertheless, I believe that it’s in therecessions that the good companies dis-tance themselves from the not so goodcompanies. Even though our business wasvery weak, we gained market share duringthis recession in quite a dramatic way.Last quarter, for the first time in our his-tory, we became larger than all the otherpublic programmable logic device compa-nies combined.

From a strategic point of view, we want towin through product leadership. Thatmeans we have to have the best products –always from the customer’s point of view –which means the highest densities, thefastest performance, and the software andservice to support them.

When you are an industry that is new and that is still changing very rapidly, you have to continue to innovate. Youhave to continue to bring new productsinto the market.

Despite the recession, the last part of2001 and the early part of 2002 was oneof our most productive periods for newproduct introductions. In about fivemonths’ time, we introduced a new family in every one of our product cate-gories – Spartan™, CoolRunner™, andVirtex™. Each, in its own way, is uniquein its capabilities. In fact, two of thesenew products – the CoolRunner-IIRealDigital CPLD and the Virtex-IIPro™ Platform FPGA – have no compe-tition. Literally, there are no comparableproducts on the market that can competedirectly with them.

Whenever you lay off employees, some ofthe accumulated knowledge of the com-pany – its “intellectual capital” – is goingto walk out the door. Especially in thehigh-tech industry, the value of the com-pany is in the heads of its engineers andsupport staff. At Xilinx, 70% or 80 % ofour employees are highly educated peopleworking in engineering and marketingand supply-chain management. They areall experts and specialists in their ownway – and that’s why it’s so important tokeep these people happy at Xilinx. Oncepeople like that leave, that intellectualcapital goes out the door with them, andthat’s a lot of value for a cutting-edgecompany to lose.

Several compelling studies have proved thatif you go back two years later, the compa-nies that laid off employees are generally inworse shape than companies that didn’t.Layoffs have a very profound impact on themorale and the trust between managementand employees. Furthermore, a lot ofknow-how has left the company. And ittakes a long time to get it back.

For these reasons, and more, I decided totry to avoid layoffs.

Pay Cuts – An Innovative Approach

The reality of economics is that when busi-ness drops, you have to bring your laborcosts in line. With layoffs not being anoption, the way we cut our labor costs wasby a very innovative program where we hada tiered salary reduction that was propor-tional to the size of each worker’s salary.The lowest paid people had no reductions,and the highest paid people had the biggestreductions (myself included).

In implementing this policy, we discov-ered that we should give people somechoices and make sure they get somethingin return. People had the choice to eithertake the salary reduction or to take vaca-tion time – or take stock options. Stockoptions aren’t money, but it is compensa-tion for the work people put in. We can’task the employees to sacrifice unless wecan compensate them for the extra flexi-bility we’re asking from them.

Total Solutions

I’m very excited about the programmablelogic industry. It’s an industry that’s still inthe early phases, but over time, it willbecome the dominant way to implementintegrated circuit designs.

The inherent flexibility of programmablelogic allows you to gain time to market, tointroduce new products very quickly, andto upgrade your product, even after thesale, through field-upgradeable technology.

We’re not just focusing on the chips, how-ever. Our chips must also have the soft-ware, the intellectual property cores, thetraining, and the support to deliver totalsolutions to our customers.

And we have to continue to be innovativein all these areas of IC technology. Mywhole belief is that Xilinx must excel in acontinuous push to innovation – through-out the company, be it in chip design, soft-ware development, or marketing.Innovation is absolutely critical – especiallyin times of recession.

No Layoffs – Not Just a Nice Thing to Do

This recession has put a tremendous strainon the industry. When I saw this declinecoming, I concluded that it would be bestfor us if we could avoid layoffs – eventhough the economic consequences wouldbe very difficult. I wanted to avoid layoffs,because once you start layoffs, people getworried – and if people are worried, theycannot innovate.

Innovation means that you have to take risksthat some things are not going to work, andtherefore, if you are worried about your job,the mantra becomes, “Don’t rock the boat.Don’t push yourself or make yourself toovisible” – which is totally opposite fromwhat we want to see happening.

If people are worried about their jobs,clearly, they’re not going to be as produc-tive. Layoffs affect not only the people whoget laid off. Very often the people who arestill there go through trauma, because theysee their friends disappear – and theyalways have this fear: “Maybe next time itwill be me.”

Cover Story View from the Top

Summer 2002 Xcell Journal 5

Page 6: Xcell Journal: Issue 43

Cover Story View from the Top

The tiered salary reduction was extremelywell received in the company. The vastmajority – and I’m talking about close to100% of the employees – felt this was theright thing to do.

People even volunteered for the plan, whichwas important in Europe, because inEurope, companies cannot mandate salaryreductions. It must be done on a voluntarybasis. If people hadn’t volunteered, we couldnot have done it, but pretty much all of ourEuropean employees volunteered for thesalary reduction, because they felt solidaritywith the company.

With an acceptance of fair pay cuts and apromise of no layoffs, our employees feltsafe to continue to risk and innovate. Theyhave kept their attention full-time on theirjobs. The net result has been that we havebeen able to maintain our aggressive sched-ule of new product rollouts – and this in aperiod when our business was off by 50%in three quarters.

Moreover, we were not only able to remainin the black from a profit point of view, butduring all this period, we were also able toremain cash-flow positive for the company.

The Importance of Being “Fabless”

One of the reasons we could afford to stayin the black is because Xilinx is a “fabless”semiconductor company. We don’t ownfabs [fabrication plants]. We don’t have thisbig problem of having a fab that we need tokeep busy. For us, if business goes down,we just buy fewer wafers.

The same thing is true for our sales force.We don’t have a Xilinx sales force. Wework through distribution and sales reps,which again means that our sales costs areby and large variable. Sales people getpaid a commission. If they don’t sell,there’s no commission.

These two factors helped us tremendous-ly in remaining in the black and remain-ing cash-flow positive, because a lot ofour expenses go up and down with thebusiness climate.

The good news is that we reached ourlowest quarter in September of 2001.

Since then, business has been starting toimprove. We were able to eliminate salaryreductions early in 2002, and as of thismoment, all salary reductions have beeneliminated. The company continues to dovery well from both a new product gener-ation point of view, as well as a businesspoint of view.

Innovation – Not Just for Engineers

Innovation is not just the engineeringdepartment. Even in the way we managethe company, we are very innovative –and it really has paid off for us. Morale isvery high, and the attrition rate isextremely low. People have kept theirattention on their jobs of designing greatnew products and marketing them andsupporting them.

In general, I think Xilinx is very much anadmired company in our industry. I thinkwe are perceived as a leader in our industry– not just from a product point of view ora financial point of new, but also from amanagement point of view.

I want to stress, however, that all of this ispossible because we are a fabless company.If we had our own fabs, I don’t know if wecould have done this.

Nevertheless, as a fabless company, ourbusiness model lends itself very well to gothough these economic cycles that areinfamous in the semiconductor industry.This last recession was the worst, but italso served to prove that our businessmodel is a very, very solid model thatallows us to go through these ups anddowns without too much hurt.

Conclusion

In high technology, things change very,very rapidly. And companies often get introuble because they don’t change quicklyenough. One of the reasons they don’tchange quickly is that the people who seethe change happen don’t act on it, and thepeople who can act on it don’t even knowthe change is happening.

Therefore, what we are creating at Xilinxis an environment where everybody says:“Hey, if it changes, let’s change with it.Let’s anticipate change. Let’s make thechange happen ourselves. Let’s be incharge of the change – not the victim ofthe change.”

It is this kind of thinking that got us throughthe recession, and now that we are emergingfrom the recession, there is a tremendoussense of pride in the company. People aresaying: “Hey, this is unique. We have donesomething that very few other companieshave done. Even companies that didn’t laypeople off didn’t do it the way we did.”

There is absolutely no doubt in my mindthat there is a much, much higher spirit ofbelonging, of community within theXilinx people than there was before. Whenyou go through a tough time together, itcreates solid bonds.

And it shows that, indeed, if you can man-age a company during a recession in a cor-rect way, you can really differentiate your-self from the competition. You can gainmarket share and emerge a stronger com-pany with a creative, dedicated – and intact– workforce at the end of recession.

6 Xcell Journal Summer 2002

Page 7: Xcell Journal: Issue 43

by Xilinx Staff

IBM and Xilinx recently signed an agree-ment that could help you shave hundreds ofthousands of dollars off the cost of creatingcustom chips. Under the agreement, IBMhas licensed FPGA technology from Xilinxfor integration into IBM’s recentlyannounced Cu-08 application-specific inte-grated circuits (ASICs). Cu-08 will supportcircuits as small as 90 nanometers – less than1/1,000th the width of a human hair.

This news underscores our joint commit-ment to a technology relationship aimed atbringing innovative and flexible new“hybrid” chips to market, combining thebest attributes of standard ASIC and flexi-ble FPGA technology for use in communi-cations, storage, and consumer applications.

Engineers working on complex chip designshave been clamoring for ways to achieve highlevels of integration, yet still have the abilityto change “on the fly” late in the design cycle.By combining FPGAs (circuits that can beconfigured to perform a wide variety of digi-tal electronic circuit functions) with standardASICs, you get the flexibility of the FPGA,with the density, performance, and overallcost advantages of an ASIC – all on one chip.

“Savings here could be dramatic,” saidMichel Mayer, general manager, IBMMicroelectronics Division. “When anASIC takes on more function, you canreduce cost by eliminating one, two, oreven more separate chips. With this tech-nology, customers would be able to tweakdesigns and integrate new changes imme-diately, eliminating the need to restart awhole new design cycle, bringing tremen-dous time-to-market advantages.”

Mayer said changes that force an addition-al chip prototype can easily cost hundredsof thousands of extra dollars and canstretch design cycles out for several addi-tional months. “This approach is expectedto change the landscape entirely,” he said.

Cu-08, with as many as eight layers ofcopper wiring separated by an advancedlow-k insulation, will support up to 72million gates for high-complexity ICsolutions. As many as 400,000 ASICgates may be dedicated to one or more ofthe FPGA cores on the ASIC.

“We’ve improved upon our delivery of pro-grammable hardware by allowing reconfigu-ration using the same chip. Flexibility is thebeauty of combining ASIC and FPGA tech-nology,” said Wim Roelandts, president andCEO of Xilinx. “Our latest agreement withIBM is a natural extension of and a signifi-cant milestone in our existing relationshipthat allows us to address new opportunitiesin the high-end ASIC market.”

Even after this new custom chip is builtinto a product, you can add to its func-tionality, simply, easily, and effectively. A

good example would be in the communica-tion industry, where various protocol andinterface specifications are constantly evolv-ing. Cell phones, printers, set top boxes,and other consumer electronic productsalso are well suited for this new approach.

IBM is the number one ASIC manufacturerworldwide. Xilinx is the number one PLDmanufacturer worldwide, with more than15 years experience in FPGA design tools.

IBM and Xilinx already have a productivebusiness relationship. IBM suppliesembedded PowerPC™ processors forXilinx Virtex-II Pro™ FPGAs. In Marchof this year, Xilinx signed a high-volume,multi-million dollar manufacturing agree-ment with IBM to manufacture theseFPGAs using IBM’s advanced 130nanometer and 90 nanometer copper-based chip-making technology.

The new FPGA cores for the Cu-80ASICS are now in development. They areexpected to be available from IBM,embedded in an ASIC, in early 2004, fol-lowing IBM’s full release of its standard-setting Cu-08 technology.

News IBM Partnership

New ASICs from IBM will contain Xilinx programmable logic technology.

IBM ASICs Will Incorporate Xilinx FPGAs

Summer 2002 Xcell Journal 7

Page 8: Xcell Journal: Issue 43

by Eric ThackerManager, Product Solutions MarketingXilinx, [email protected]

Rapidly changing markets and new tech-nologies are subverting traditional systemdesign paradigms. Historically, in electronicsystems development, the standard designprocedure was to prototype a system using

programmable logic devices (PLDs), andthen redesign the system using ASICs assoon as possible for cost reduction. Theidea was to leverage the flexibility anddevelopment time advantage of program-mable logic until the design stabilized andthen to convert the design to a lower-unit-cost ASIC to reduce overall system cost.

In the past, programmable logic was lowerdensity, lower performance, and morelimited in capabilities. When systems fol-lowed traditional product life cycle behav-ior, the PLD-to-ASIC design strategyworked quite well. In fact, in some marketsegments, characterized by relativelymature technologies, established stan-dards, and a stable competitive environ-ment, this strategy is still optimal today.

In dynamic, rapidly changing markets,however, this strategy becomes question-able. For many advanced electronic prod-ucts – such as plasma televisions, homenetworking hardware, and digitalaudio/video equipment – the market isanything but stable. Baseline standardsfor advanced products are ever-changing,features demanded by customers shiftconstantly, new technological capabilitiesare continually being introduced, andcompetitors are always trying to gain abetter market position – resulting inmany short-lived products.

These volatile market pressures give a sig-nificant competitive advantage to flexibleand first-to-market products. In thesemarkets, ASICs – with their long leadtimes, high initial costs, high minimumorder quantities, higher risks, and inflexi-bility – are not a compelling solution.

Therefore, many designers are tappinginto programmable logic’s benefits ofinstant reprogrammability, short leadtimes, greatly improved performance,expanded densities, and overall flexibility.Indeed, today’s programmable logicdevices offer many of the same featuresfound in ASICs. Clock management,embedded processors, high-performanceDSP, advanced interfacing, and a pletho-ra of intellectual property (IP) cores allmake today’s PLDs strong candidates fora system’s core logic.

With their emphasis on cost-optimiza-tion, the CoolRunner™-II CPLDs,Spartan™-IIE FPGAs, and Virtex-IIEasyPath™ Solutions families fromXilinx bring these advanced benefits toyour high volume applications.

Perspective Cost Management

CoolRunner-II CPLDs, Spartan-IIE FPGAs, and Virtex-II EasyPathPlatform FPGAs can give you total system cost solutions superior to those of traditional ASICs.

When Total Cost Management Counts, Xilinx PLDs Pay Off

8 Xcell Journal Summer 2002

When Total Cost Management Counts, Xilinx PLDs Pay Off

Page 9: Xcell Journal: Issue 43

Total Cost Solution

In the past, the primary motivation in con-verting a PLD design to one based on anASIC was unit cost. ASICs, in general, areavailable at lower unit cost than PLDs. Butlooking at unit costs alone could actuallylead to an overall higher cost solution. Thatis because unit costs are only one of the fac-tors that contribute to total system cost.Total system costs can be broken down intothree broad categories – design and develop-ment, production, and life cycle.

Design and Development

Design costs are primarily worker-hour andnon-recurring engineering (NRE) costs.PLD designs require fewer worker hours,because design/debug changes can be madeinstantly, hardware and software can bedeveloped concurrently, test vector genera-tion is unnecessary, and product lead timesare practically zero compared to ASICs.PLDs have no NRE costs, which can be avery important consideration as productionvolumes per design revision are much lowerin rapidly evolving markets. In many cases,Xilinx offers free PLD design tools, thusincreasing the PLD cost advantage.

There are also lost opportunity costs associat-ed with ASICs. Systems using ASICS losemarket penetration due to long developmenttimes. Furthermore, the inflexibility of ASIC-based systems prevents upgrading products tomeet changing market needs. Overall, PLDdesign cost advantages alone can often out-weigh any ASIC unit cost advantage.

Finally, long-lived legacy products usingASICs can face the need for boardredesign should the ASIC product orprocess be discontinued. PLD reprogram-mability avoids this problem. Thus, lega-cy products with PLDs do not siphondesign resources from next-generationproducts, and this presents a significantmarket cost savings.

As illustrated in the discussion of thesethree cost categories, we must look beyondunit cost when deciding on logic solutionsbased on cost. In many applications, theunit cost savings of ASICs are more thanoffset by the lower risks, design, produc-tion, and life cycle costs of PLDs.

Xilinx Solutions for Total Cost Management

Xilinx has taken the lead among PLDsuppliers in providing low risk, low cost,high performance logic solutions fortoday’s rapidly changing and highly com-petitive markets.

Low Power, Low Density: CoolRunner-II CPLDs

CoolRunner-II RealDigital CPLDs com-bine high performance, ultra low power,low cost, and integration of specializedcapabilities to bring you a new class ofprogrammable logic devices. The versatil-ity and low cost of CoolRunner-IICPLDs allow them to serve a multitudeof logic, interface, and control functions.See Figure 2.

Production

Unit cost is the mostobvious cost in this cat-egory. ASICs usuallydo hold the unit costadvantage over PLDs,but this cost differen-tial is shrinking.

Today’s PLDs haveaggressively drivendown both die size andpackage costs to providea persuasive ASIC alter-native. The advancedsystem capabilities ofmodern PLDs allow

designers to integrate discrete componentfunctions into the PLD – reducing boardand total component costs.

Finally, unlike an inflexible ASIC, one lineof PLDs can be inventoried to supply mul-tiple applications. You can reprogram andredeploy PLDs as needed. Combined withmuch lower minimum order quantities,PLDs reduce inventory costs, as well as therisk of obsolescence, further offsettingPLDs’ unit cost disadvantage. See Figure 1.

Life Cycle

Life cycle costs are probably the least consid-ered costs when designing an electronic sys-tem, but they can have a significant impacton the total return from a given design.Using PLDs instead of ASICs means practi-cally no risk of obsolete inventory, becausestandard-product PLDs canbe redeployed to differentapplications as needed.Unlike ASICs, PLDs do nothave to be scrapped if a spe-cific product is cancelled.

In addition, because PLDscan be reprogrammed, it ispossible to upgrade prod-ucts in the field simply bydownloading a new hard-ware configuration file tothe PLD. Bug fixes and fea-ture upgrades can be per-formed remotely withoutchanging any hardware.

Summer 2002 Xcell Journal 9

Figure 2 - CoolRunner-II CPLDs deliver high performance at low cost.

Figure 1 - Cost comparison of ASICs and FPGAs

Perspective Cost Management

Page 10: Xcell Journal: Issue 43

Perspective Cost Management

The 0.18-micron CoolRunner-II familyutilizes second-generation Fast ZeroPower™ technology for low power, highperformance operation. These RealDigitalCPLDs feature an all-digital core that elim-inates power-hungry analog sense ampli-fiers. The CPLDs also offer increased capa-bilities, higher performance, and lower cost– with no performance penalty.

Available in densities from 32 to 512macrocells, the CoolRunner-II family pro-vides performance over 330 MHz, withstandby power consumption of less than100 µA. CoolRunner-II devices also deliveradvanced system features that enable theintegration of costly discrete system func-tions into a single reprogrammable device.This integration results in lower costs, fur-ther power reduction, increased reliability,faster time to market, and smaller designs.These system features include superiorI/Os, advanced clocking features, and fourlevels of design security.

The in-system reprogrammable nature ofCoolRunner-II CPLDs allows designers tochange designs on the fly, correct designs,and test out alternate designs withoutchanging any hardware. This saves signifi-cant engineering change orders (ECOs) andNRE charges compared to ASIC solutions.

The CoolRunner-II CPLDs’ advanced I/Ointerface capabilities include DataGATE, aprogrammable on/off switch for power man-agement; advanced interfaces such as HSTL,and SSTL; and Schmitt trigger inputs for

input signal conditioning. All of these fea-tures reduce the need for external compo-nents, reducing part costs and board space.

To further reduce system costs and the needfor additional components, theCoolRunner-II family provides a unique fea-ture called CoolCLOCK. CoolCLOCK is acombination of a clock doubler and clockdivider. The incoming clock is divided bytwo and then doubled at the output to main-tain the same performance, while reducingthe internal power consumption.

To increase your cost management advantage, Xilinx provides a free Internet-based ISE WebPACK™ design tool suiteand a free WebFITTER™ design fittingtool to give you a complete, pushbuttondesign solution.

The combination of advanced interfacing,integrated system features, and free designtools makes CoolRunner-II CPLDs a com-pelling choice for logic functions in cost-sensitive applications. For more informa-tion, visit www.xilinx.com/coolrunner2.

Moderate Density, System Integration:Spartan-IIE FPGAs

Cutting-edge consumer electronics marketsdemand products that provide performanceand flexibility in a cost-optimized format forhome networking equipment, home theatersystems, and other high-end personal elec-tronic devices. These consumer productsmust accommodate rapidly evolving stan-dards, shifting demand patterns, highly fluid

competitive positioning, and the continuousintroduction of new capabilities. Logicrequirements for these designs include mod-erate density, advanced system features, pre-designed and verified IP blocks, and high-quality design tools. Spartan-IIE FPGAsmeet all of these requirements and more.

Xilinx designed its next-generation Spartan-IIE consumer FPGA with total cost man-agement in mind. Spartan-IIE FPGAsrange in density from 50,000 system gatesto 300,000 system gates. To reduce FPGAcomponent costs, Spartan-IIE FPGAs areproduced by the industry’s most advancedfoundry process on 300 mm wafers. Thisprocess lowers die cost and enablesadvanced, low-cost packaging.

To reduce board cost and improve systemperformance, Spartan-IIE FPGAs have anumber of built-in advanced system fea-tures that allow you to eliminate costly dis-crete translators and commodity chipsfrom your boards, as shown in Figure 3.

Advanced interfacing – including LVDS,LVPECL, HSTL, and SSTL – remove theneed for specialized interface componentson the board. Furthermore, Spartan-IIEFPGAs offer four delay-locked loops(DLLs) for advanced clock management.Spartan-IIE FPGAs also contain both para-meterizable block RAM (single or dualport) and distributed RAM (scalable andadjacent to logic). All these features canspeed the design process, provide designflexibility, reduce design worker hours,deliver very high levels of performance, andaccelerate time to market.

As consumer products increase their digitalcapabilities, digital signal processing (DSP)capability has become a critical performancefactor. The Xilinx XtremeDSP™ initiativeenables nearly one billion DSP multiply-and-accumulates (MACs) per second perdollar of performance in Spartan-IIE devices– delivering advanced DSP without theneed for specialized board components.

Xilinx offers more than 200 Spartan-familyIP cores to speed logic design and reduceengineering resources needed to completethe system. These IP cores are also opti-

10 Xcell Journal Summer 2002

Figure 3 - Spartan-IIE FPGAs save board space – and money.

Page 11: Xcell Journal: Issue 43

Perspective Cost Management

mized for die area, which may permit theuse of smaller density Spartan-IIE parts,resulting in further cost savings.

Additionally, the free ISE WebPACK soft-ware provides the industry’s most advanceddesign tool platform to support the entireSpartan series.

Die and packaging, advanced system fea-tures, extensive IP offerings, enhanced flex-ibility – all these Spartan-IIE cost controlfeatures give you the performance, features,and time to market advantage necessary tocompete in today’s rapidly evolving elec-tronics markets. For more information, visitwww.xilinx.com/spartan.

High Performance, High Density: Virtex-II EasyPath FPGAs

The Virtex-II™ FPGA is the first embodi-ment of the Platform FPGA concept.Virtex-II devices deliver SystemIO inter-faces to bridge emerging standards,XtremeDSP performance up to 100X con-ventional DSP solutions, multi-gigabittransceivers, and Empower! embeddedprocessor technology. Together with theindustry’s most advanced design tools,Virtex-II Platform FPGAs offer a feature setthat is unparalleled in the industry.

Virtex-II EasyPath FPGAs bring theunprecedented capabilities of the Virtex-IIfamily to cost-sensitive applications byreducing the cost of high-density FPGAdesigns. Virtex-II EasyPath Solutions usethe exact same FPGA silicon as the Virtex-II FPGA family, but Virtex-II EasyPathSolutions make use of a specialized testingprogram to verify the FPGAs for a specificcustomer application, resulting in higheryields and significantly lower costs.

Virtex-II EasyPath solutions provide anFPGA volume conversion strategy with norisk, no investment of customer engineeringresources, and the fastest conversion time ofany competing high-volume strategy forhigh-density FPGA designs. The main ben-efits of Virtex-II EasyPath solutions are:

• Lower unit costs: Customers can expect a30-90% price reduction compared tostandard FPGAs.

• Lower up-front costs: These costs can beas low as 30% of the NRE costs of anASIC or gate array.

• No added engineering resources: Unlikeother FPGA conversion strategies, Virtex-II EasyPath FPGAs require no additionalengineering resources or tools. Customersare not required to contribute anyresources for conversion, verification,qualification, or board redesign.

• No risk: Virtex-II EasyPath Solutionshave none of the performance, timing,functionality, or architecture match risksof alternative FPGA conversion strategies,because the conversion FPGA fabric is thesame as the standard Virtex-II FPGA.

• Minimal lead times: With Virtex-IIEasyPath FPGAs, initial orders are filledwithin six weeks and restocking orders arefilled within days of being placed.Compare that to lead times of multiplemonths for both initial and follow-onorders for alternative conversion strategies.

Because Virtex-II EasyPath FPGAs are testedfor a specific design configuration, testingthroughput and yields are significantly high-er, thus driving down the unit costs of theFPGA, as shown in Figure 4. You can initial-ly design your system using standard Virtex-II FPGAs. Once the design has stabilized,you can use Virtex-II EasyPath Solutions toconvert to a lower-cost platform with none

of the risk, lower NRE costs, and none of theadditional engineering resources required byconversion to ASICs. For more information,visit www.xilinx.com/virtex2.

Conclusion

From low density, ultra low powerCoolRunner-II CPLDs to mid-range, lowcost Spartan-IIE FPGAs to high densityVirtex-II EasyPath Platform FPGASolutions, Xilinx presents a portfolio ofproducts that can play a critical role in yourtotal cost management of system design.These advantages include:

• Cost-optimized silicon and packaging tominimize unit costs

• Advanced system features to reduce coststhrough system integration

• Reprogrammability to streamline designand debug

• No-cost system upgrade capabilities

• Reduced risk of obsolete inventory

• An extensive IP library to improve designefficiency and reduce system components

• Free design tools that maximize designefficiency.

Together, Xilinx CPLDs and FPGAs giveyou a cost-optimized solution for managingsystem costs while maximizing system per-formance, functionality, and flexibility.

Summer 2002 Xcell Journal 11

Figure 4 - Virtex-II EasyPath Solutions are design-specific and cost-effective.

Page 12: Xcell Journal: Issue 43

by Anil Telikepalli, Marketing Manager Virtex Solutions, Worldwide MarketingXilinx, [email protected]

In a significant move, Xilinx recentlyexpanded the Virtex-II Pro™ PlatformFPGA family two ways:

• Five new devices offering increased capability

• Lower cost versions for the entire family in a new reduced-speed series.

With this, the new Virtex-II Pro familyexpands to ten devices, and sets industryrecords in every conceivable category, pro-viding the advanced system-level featuresand high performance you need, atremarkably low prices.

The new Virtex-II Pro FPGA solution,illustrated in Figure 1, provides every-thing you need, on a single, reprogram-mable device, including:

• The world’s highest logic and memory density

• The world’s highest I/O capacity

• The world’s fastest DSP capability

• The world’s fastest multi-gigabit serialI/O connectivity

• The world’s most flexible parallel I/O connectivity

• The world’s only embedded processingFPGA solution using IBM® PowerPC™processor cores.

New Products FPGAs

Now you get programmable system features at programmable logic prices.

New Virtex-II Pro Devices – Increased Capability, Lower Cost

12 Xcell Journal Summer 2002

New Virtex-II Pro Devices – Increased Capability, Lower Cost Now you get programmable system features at programmable logic prices.

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New Products FPGAs

Your demands, both for increased capabili-ty as well as lower cost versions of ourVirtex-II Pro devices, were made clear atour Programmable World 2002 event. Andnow, we can deliver the performance andthe pricing you need due to the success ofour initial devices and development tools,as well as advances in our process technol-ogy which includes 300-mm wafers.

These new, lower cost devices not only deliv-er tremendous cost savings over comparablecompeting programmable device offerings,but they also bring Virtex-II Pro capabilitieswithin the reach of a much wider range ofapplications. With the Virtex-II Pro familyyou now get multiple IBM PowerPC proces-sors and multi-gigabit serial transceivers atabout the same cost as our Virtex-II™FPGAs (which don’t offer these features),effectively providing programmable systemfeatures at programmable logic prices.

The Highest Performance and the Lowest Cost

The new Virtex-II Pro XC2VP125 FPGA,shown in Table 1, is the world’s highestcapacity, highest performance, and high-est capability programmable logic device,delivering unique system performancesuch as one trillion MACs/sec DSP per-formance and 120 Gb/s aggregate payloadbandwidth. There is no programmable

age, digital broadcast, networking, andwireless networking. For example, in net-working, as you move from the core of thenetwork to the edge, the line rate and pro-cessing speed of the equipment decreaseswhile the need for intelligent processingincreases. In addition, price pressureincreases, because the edge equipment ismore price sensitive than the core equip-ment. This analogy can be applied toalmost any application and market seg-ment. Xilinx is providing -5 devices specif-ically to address such price-sensitive appli-cations that benefit from system featuresthat include embedded processors andmulti-gigabit transceivers.

Virtex-II Pro FPGA Architecture Review

The Virtex-II Pro family, shipping sinceFebruary of this year, is the world’s first 130nm, 9-layer copper, FPGA family and thefirst and only one to offer integrated IBMPowerPC microprocessor technology and3.125 Gb/s serial transceivers. Its architec-ture is built upon the award-winningVirtex-II FPGA fabric, which already hasthousands of satisfied users.

With 10 devices, multiple packages, andmultiple speed grades to choose from, theVirtex-II Pro FPGAs give you the rightfeatures and performance to meet yourspecific needs. The family, as shown inTable 1, includes:

• Immersed IBM PowerPC processors (0 to 4)

• Integrated 3.125 Gb/s Rocket I/O™transceivers (0 to 24)

• The award-winning Virtex-II FPGA fabric.

device in the world that competes with itin features, performance, or cost. Withsuch unparalleled leadership advantage,the Virtex-II Pro Platform FPGAs put youon a platform of success, closer to yourdesign goals.

Expanding the Market and Target Applications

The new -5 speed grade delivers cost-effective 2Gb/s transceiver performance,with over 266 MHz embedded PowerPCprocessor performance. In comparison,our fastest devices (-7 speed grade) provide up to 3.125 Gb/s transceiver per-formance, with over 300 MHz embeddedPowerPC processor performance. The -5speed grade is therefore ideal for mediumto high-speed applications including stor-

Summer 2002 Xcell Journal 13

Figure 1 - Virtex-II Pro Platform FPGA

“The Virtex brand has been the number one choice of designers worldwide, based on its industry-leadingcapacity, performance, capabilities, and cost-effectiveness. In each generation of families, our mission is to deliver significantly enhanced functionality while driving down prices. We continuethis strategy in the Virtex-II Pro family by including state-of-the-art multi-gigabit serial trans-ceivers and high-performance PowerPC RISC CPUs, in the standard feature set, at no charge. Thus, we enable the creation of next-generation systems designs at previously unattainable price points.”

Erich Goetting – Vice President and General Manager of the Xilinx Advanced Products Division

Page 14: Xcell Journal: Issue 43

New Products FPGAs

IBM PowerPC Processors

Each immersed IBM PowerPC processorruns at up to 300+ MHz and 420+Dhrystone MIPS providing high-perform-ance embedded processing. The PowerPCprocessor is supported by the IBMCoreConnect™ bus technology. A com-plete set of embedded software tools areavailable to help you quickly develop anddebug your PowerPC designs – through anOEM agreement, Xilinx provides softwaretools from Wind River Systems, cus-tomized for Virtex-II Pro FPGAs.

Rocket I/O Multi-gigabit Transceivers

The Rocket I/O™ multi-gigabit trans-ceivers (MGTs) are based on theMindspeed SkyRail™ CMOS technology.Each transceiver runs at rates ranging from622 Mb/s to 3.125 Gb/s, and includes theentire transceiver support circuitry. EachRocket I/O transceiver consists of both adigital Physical Coding Sublayer (PCS), aswell as an analog Physical MediaAttachment (PMA), to provide an integrat-ed SerDes (serializer/deserializer) function.

Award-winning Virtex-II Fabric

The Virtex-II FPGA fabric provides fea-tures for high-performance system design

that has made it a platform of choice for users. These features include:

• High-performance logic with a widechoice of densities

• Embedded block RAM

• XtremeDSP embedded hardware multiply circuitry

• Advanced digital clock management circuitry

• XCITE technology for digitally con-trolled impedance matching on I/Os

• Bitstream encryption technology fordesign protection

• Flexible Select I/O™-Ultra technologyfor supporting over 20 single-ended anddifferential I/O signaling standards.

Conclusion

The expanded Virtex-II Pro family pro-vides a broad choice of 10 devices in scala-ble features and speed grades. It marksleadership in every facet, providing morecapability than any other competing pro-grammable logic device. In addition, thenew pricing delivers programmable systemfeatures at programmable logic prices,making embedded PowerPC processorsand multi-gigabit transceivers standard fea-tures in high-performance programmabledevices. For more information on Virtex-IIPro Platform FPGAs and design resources,go to www.xilinx.com/virtex2pro.

14 Xcell Journal Summer 2002

“With the immersion of PowerPC cores, Xilinxhas developed the optimal platform to imple-ment our storage network designs. Virtex-II Prodevices provide the critical elements of system-level design, including high-speed serial I/O,making it an ideal combination for our nextgeneration products. Moreover, the uniquearchitectural synthesis design environmentallows us to make hardware and softwaretradeoffs throughout the design cycle.”

Sandy Helton – Executive VP and CTO, SAN Valley

Device XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100 XC2VP125

Logic Cells 3,168 6,768 11,088 20,880 30,816 43,632 53,136 74,448 99,216 125,136Block RAM (Kbits) 216 504 792 1,584 2,448 3,456 4,176 5,904 7,992 10,00818x18 Multipliers 12 28 44 88 136 192 232 328 444 556

Digital Clock Management Blocks 4 4 4 8 8 8 8 8 12 12Configuration Memory (Mbits) 1.31 3.01 4.49 8.21 11.36 15.56 19.02 25.6 33.65 42.78

IBM PowerPC Processors 0 1 1 2 2 2 2 2 2 4Multi-Gigabit Transceivers 4 4 8 8 8 12* 16* 20 20* 24*

Max Available User I/O 204 348 396 564 692 804 852 996 1164 1200

Package

FG256 140 140FG456 156 248 248FF672 204 348 396FF896 396 556 556

FF1152 564 692 692 692FF1148* 804 812FF1517 804 852 964FF1704 996 1040 1040

FF1696* 1164 1200

*Note: FF1148 and FF1696 packages support higher user I/O and zero Rocket I/O multi-gigabit transceivers

Table 1- Virtex-II Pro Platform FPGAs Power of Choice (new -5 devices shown in red)

Figure 2 - Expanding the market from ultra-high speed to medium-high speed applications

Page 15: Xcell Journal: Issue 43

by Simon CockingDesign ConsultantHelion Technology [email protected]

As secure communication data ratesincrease, software implementations of thekey data encryption algorithms present amajor system bottleneck. To make mattersworse, standard off-the-shelf CPUs andDSPs have failed to keep pace with thecomputational demands of data encryptionalgorithms. Besides, CPUs and DSPs justhave too many other tasks to perform.

The magnitude of the software perform-ance gap for high-speed data encryption isillustrated by the benchmark results shownin Table 1. These figures are for imple-mentations of the new 128-bit AdvancedEncryption Standard (AES) algorithm run-ning on standard CPU and DSP architec-tures – as compared to how a Virtex™-IIPlatform FPGA solution based on a FastAES core from Helion Technology Ltd. canprovide the multi-gigabit encryption datathroughput required by high-speed inter-connect technologies.

Technology Focus Virtex-II Platform FPGA

How to Use Virtex-II FPGAs to Deliver Gigabit Advanced Data Security with HelionEncryption Cores

Summer 2002 Xcell Journal 15

How to Use Virtex-II FPGAs to Deliver Gigabit Advanced Data Security with HelionEncryption Cores Virtex-II Platform FPGAs enabled Helion Technology Ltd. not only to deliver on time but to exceed the client’s requirements.

Page 16: Xcell Journal: Issue 43

Technology Focus Virtex-II Platform FPGA

The Design Brief

Last year, we at Helion were asked by oneof our clients to provide a flexible, highperformance FPGA-based data securityengine to handle encryption of InternetProtocol (IP) packet-based data for theirnext-generation network security products.Even though their product was based on ahigh-performance dual 64-bit MIPS net-work processor, benchmarking had showna software encryption solution to be some-what short of achieving the minimum 600Mbps throughput our client required.

The system requirement was for a PCI-based engine that could accommodatemultiple encryption algorithms: AES anda proprietary algorithm for legacy purpos-es. The solution had to be low cost, capa-ble of supporting gigabit data rates, andflexible enough to allow for future algo-rithm changes.

After evaluating the available options, theonly solution that met all of the require-ments was a PCI card containing the onemillion-gate Virtex-II XC2V1000 PlatformFPGA. The device incorporated a XilinxLogiCORE™ 32-bit/66-MHz PCI coreand Helion-designed encryption cores.

Why Use a Virtex-II FPGA?

From our many years of design experiencewith leading edge technology, we werewell aware of the potential pitfalls, such asinadequate design tool support andunavailable parts. Fortunately, Virtex-IIPlatform FPGAs use the same EDAtoolset as earlier technologies, and theXC2V1000 device was already in produc-tion. The reasons for choosing theXC2V1000 instead of the more estab-lished Virtex-E family were compelling:

• Costs – The Virtex-II XC2V1000 costless than half the nearest equivalentVirtex-E(-8) device.

• Performance – Benchmarking with theHelion AES core showed the Virtex-II(-4)FPGA to be 30% faster than the nearestequivalent Virtex-E(-8) device.

controller. This configuration allows theencryption keys to be easily changed bysoftware – an important security feature.

The DMA read-and-write buffers useblock RAM to support the long PCI burstread-and-write transfers needed to achieveoptimum performance. Checksum calcu-lation and buffering is also provided forthe encrypted data (ciphertext) to off-loadthis task from the system software, whichreads the checksum(s) at the end of eachDMA transfer.

The main data path between the DMAbuffers is through the encryption cores. TheHelion 128-bit fast AES encryption core hadalready been developed, so it was simply acase of dropping it into the design. However,it was still necessary to develop a high-per-formance core for the proprietary algorithm.

Encryption Engine Operation

While the encryption engine is inactive (noDMA encrypt transfer in progress), thePCI interface defaults to “target” mode andwaits for the system CPU to initiate aDMA transfer. Once a DMA operation isrequested, the PCI interface is switched to“master” mode, and the DMA controllerinitiates the required bus transfers.

Upon completion, the encryption engineasserts the PCI interrupt request andreturns the interface to “target” mode sothat the system CPU can read the check-sums and/or start the next transfer.

• Bigger and wider block RAM – We found32-bit wide data buffers were more effi-ciently implemented in Virtex-II blockRAM. For example, a 512x32 bufferrequired only a single Virtex-II block RAMrather than four in Virtex-E technology.

• Enhanced CLBs – The MUXF7 andMUXF8 primitives allowed up to fourslices to be combined for fast imple-mentations of any logic function up toeight inputs wide. This led to fewerlogic levels and faster critical paths forthe very wide logic functions typical ofencryption algorithms.

• Digital Clock Manager (DCM) – Trueclock frequency synthesis allowed theencryption data clock to be tuned toclosely match worst-case PAR (place-and-route) timing, optimizing encryp-tion throughput.

• Easier Design Implementation – The rawspeed of Virtex-II devices meant no PARguide file was required for theLogiCORE 66-MHz PCI bus logic.

Encryption Engine Overview

A block diagram of the encryption engineis shown in Figure 1. The only externalinterface is the LogiCORE 32-bit/66-MHzPCI bus.

All encryption key information and data tobe encrypted (plaintext) are stored in PCIsystem memory and transferred into theFPGA by the direct memory access (DMA)

16 Xcell Journal Summer 2002

Solution Clock (MHz) Encryption Data Rate Comments

TMS320C62XX 32-bit 200 112 Mbpsfixed-point DSP

MIPS-based 64-bit 250 392 Mbps Assumes fully primed cache and RISC processor CPU fully dedicated to encryption

Pentium III 1,000 464 Mbps Assumes fully primed cache and CPU fully dedicated to encryption

Helion Fast AES Core 132 1536 Mbps Virtex-II XC2V1000-4 target

Table 1 - Typical achievable data rates for 128-bit Advanced Encryption Standard solutions

Page 17: Xcell Journal: Issue 43

Technology Focus Virtex-II Platform FPGA

Because the plaintext data stream writteninto PCI system memory can be frag-mented into multiple IP packets, the sys-tem software is responsible for creating acontrol data structure that details the size,location, and number of fragments, aswell as the encryption type to use. Thisstructure is transferred from memory intoa block RAM in the DMA controller atthe start of each encrypt transfer.

The encryption engine can then read inall plaintext fragments, encrypt themusing the selected algorithm, and re-assemble the ciphertext fragments inmemory. In the process of writing cipher-text back to memory, a checksum is cal-culated for each encrypted fragment, andthis value is added to a total checksum ofall fragments. These checksums are storedin a small distributed RAM in the FPGA,and then read back by the system CPU atthe end of each transfer.

Encryption Engine Performance

Our client was delighted to learn that notonly was the final encryption enginedesign delivered on time, but that it alsoexceeded the required data throughput forboth encryption algorithms by a signifi-cant margin.

The proprietary algorithm core isclocked at 66 MHz to achieve a rawencryption throughput of 990Mbps. The AES core is clockedat 132 MHz to yield a rawencryption throughput of1.536 Gbps.

However, these rawthroughput figures aredegraded somewhat inthe final system due tobus arbitration over-head in the PCI bridge.In fact, the data throughput of theHelion fast AES core is so high that themaximum available bandwidth on the 32-bit/66-MHz PCI bus acts as a ceiling onits performance.

Frequent changing of the encryption keyswill also lead to a reduction in overall dataencryption throughput due to theincreased transfer load on the PCI bus.

Conclusion

The encryption engine project we’vedescribed is a great example of how acombination of third-party intellectualproperty cores and Virtex-II PlatformFPGA technology can yield flexible,high-performance security products inrecord time.

A large reduction in the effort required toimplement such a design relies on theready availability of intellectual propertylike the Xilinx LogiCORE PCI productsand the range of advanced encryptioncores we have developed at Helion. Designblocks like these enable a single engineer toattack a million-gate design and achieveresults in a matter of weeks.

Future plans for our encryption engineinclude the use of a higher bandwidth businterface, such as HyperTransport™ tech-nology in place of PCI. We also plan theaddition of multiple AES cores to provide afull-duplex (encrypt and decrypt), higherperformance solution.

The Helion encryption cores allow for evenhigher throughput: Eight similar Fast AEScores in a larger Virtex-II Platform FPGAcould provide encryption at rates in excess of12 Gbps. This is fast enough to supportemerging high-speed interconnect standards,such as OC-192, 10 Gigabit Ethernet, POS-PHY L4, and RapidIO™ Phy.

For more detailed information on Helion andour products and services, please visit theHelion website at www.heliontech.com.

Summer 2002 Xcell Journal 17

Figure 1 - DMA encryption

engine block diagram

Page 18: Xcell Journal: Issue 43

by Steve ProkoschCPLD Product Marketing Xilinx, [email protected]

When Xilinx asked design engineers whatthey expected from the new generation ofcomplex programmable logic devices(CPLDs), their responses showed theypretty much wanted it all:

• Advantages derived from state-of-the-artfabrication processes

• More industry standard I/O features

• System security

• Lower power operation

• Higher performance.

Designers required the next generation ofCPLDs to increase performance of bat-tery-powered devices. And, they stipulat-ed that the next generation of CPLDsmust improve performance withoutpower penalties – and with the featuresand functions that would meet the expec-tations of today’s discriminating designersand cost-conscious consumers.

In response to the high expectations of topdesign engineers, Xilinx has created theCoolRunner™-II RealDigital CPLD. TheCoolRunner-II CPLD architecture intro-duces, for the first time, the advantage ofboth high performance and low poweroperation. The CoolRunner-II RealDigitalCPLD reprogrammable logic solution justmay be the defining element of a new eraof CPLD-based applications – small formfactor, high performance, power sensitiveproducts that are feature rich and protectedby multiple levels of security.

New Product CPLD

Xilinx CoolRunner-II RealDigital CPLDs consume less powerand offer reprogrammable flexibility with unprecedenteddesign security – without a price premium.

CoolRunner-II CPLDsGo All Digital

18 Xcell Journal Summer 2002

CoolRunner-II CPLDsGo All Digital

Xilinx CoolRunner-II RealDigital CPLDs consume less powerand offer reprogrammable flexibility with unprecedenteddesign security – without a price premium.

Page 19: Xcell Journal: Issue 43

New Product CPLD

CoolRunner-II RealDigital CPLDs

Evolutions of the XPLA (extended pro-grammable logic array) CPLD architecturehave led to this ultra low power, ultra highspeed, reprogrammable CMOS logic thatoffers significant improvements over earliergenerations. (See sidebar “The Evolution ofLow-Power CPLDs.”) These capabilitiesare aiding in dramatic device size reduc-tions and performance increases that areenhancing the look and feel of both hand-held and high performance products.

The CoolRunner-II RealDigital CPLDdelivers on several design fronts: low power,high performance, design flexibility, andsecurity. Today, designers can choose highperformance devices that do not requireextra power for speed.

Process Technology

The CoolRunner-II family of CPLDs hasbenefited from the leading edge of XilinxFPGA (field programmable gate array)process technology. The originalCoolRunner CPLD architecture began ona 0.5-micron process and then migrated to0.35 micron.

Today, the CoolRunner-II CPLD family ismanufactured using a 0.18-micron processtechnology – the same as the high-endXilinx Virtex™-II FPGAs. With this ultrahigh density process technology, and scala-ble CMOS architecture, it is now possibleto lower power consumption even furtherthan before.

Multiple I/O Features

To facilitate its use in multiple systemarchitectures, various input/output (I/O)standards have been incorporated in theCoolRunner-II interface. These include:

• LVTTL

• LVCMOS 33, 25, 18

• SSTL2-1, SSTL3-1

• HSTL-1

• 1.5V I/O.

High-speed transceiver logic (HSTL) I/Ostandards are common in high-speed mem-ory interfaces. Stub-series terminated logic

DataGATE makes it possible to reducepower consumption by reducing unneces-sary toggling of inputs when they are not inuse. A prime example of this would be abus interface. These input signals wouldbecome active only when information ispassed to the CPLD. This eliminates theunnecessary switching from high tolow/low to high. As bus interfaces grow, sowill the power demand from needlessswitching of input signals.

CoolCLOCK, another CoolRunner-II lowpower enhancement, is implemented bydividing, then doubling, a clock signal.Using Global Clock 2 (GCK2) clock inputand dividing by 2, then doubling the clockat the macrocell, performance can be main-tained while lowering power consumption.The CoolCLOCK method is easily synthe-sized and is available on 128 macrocell andlarger devices.

Schmitt Trigger

When communicating with CPLD designengineers, we discovered they were lookingfor an easy method to interface to noisyanalog components. Thus, CoolRunner-IICPLDs incorporate Schmitt trigger inputs,which are helpful by delaying the switchingtime on slow rising or falling signals.Schmitt trigger inputs also help eliminate

(SSTL) is associated with circuit designswhere buses must be isolated from relative-ly large stubs. With these added I/O stan-dards, CoolRunner-II CPLDs can easilyadapt to a variety of interfaces that otherlow power processors might not be able tohandle. This makes CoolRunner-II CPLDsa great system integration solution formicroprocessor-based applications.

100% Digital Core

CoolRunner-II RealDigital CPLDs do notuse traditional sense amplifier technology –and that means the historical tradeoffbetween speed and power has been elimi-nated. RealDigital technology has enabledXilinx to offer the industry’s lowest powerconsumption and highest performance ona single device with no price premium.

Low Power Enhancements

Learning that designers of portable prod-ucts wanted even lower power thanCoolRunner XPLA3 CPLDs, Xilinx addedarchitectural features to accommodate tightpower budgets. Even with FZP (Fast ZeroPower™) technology and voltage reduc-tion, we still had to add two new architec-tural features to lower overall power con-sumption in designs for power sensitiveapplications. Those features are DataGATEand CoolCLOCK.

Summer 2002 Xcell Journal 19

Figure 1 - Xilinx CoolRunner-II CPLD product family

Page 20: Xcell Journal: Issue 43

New Product CPLD

false switching due to noise spikes. The pos-sibility also exists to form a simple oscillatorcircuit from these inputs. You must exercisecare to assure reliability, but it can savecomponent costs on simple circuit designs.

Security

The loss of intellectual property is always aconcern for electronic equipment manufac-turers. With CoolRunner-II RealDigitalCPLDs, security was enhanced to eliminatethe possibility of code theft. The securitybits are scattered and affect different modesof operation. If any tampering of the securi-ty chain is detected, the device automatical-ly locks down and is erased. Even if thedevice is de-capped, buried interconnectsmake it almost impossible to trace securityconnections without destroying the device.Security details cannot be discussed evenunder non-disclosure agreements, thusensuring ultimate protection.

User-Defined Grounds

As voltage levels decrease, noise andground bounce become larger factors insignal integrity. Now, a few hundred mil-livolts is the difference between on andoff, versus a few volts in legacy devices.We had to take extra care in design andlayout to shorten signal paths and mini-mize potential interference.

Differential signaling (SSTL and HSTL)serves as a good method to reduce noiseand increase signal integrity – with the pro-vision that extra pins are available for dif-ferential I/O and reference voltage sources.

To simplify the elimination of noise andground bounce, CoolRunner-II CPLDs alsoemploy software-definable ground pins.These programmable ground pins are anideal way to reduce noise and ground bounceeffects. By using neighboring I/Os as groundpins, CoolRunner-II devices can tolerate alarger amount of potential signal noise.

Voltage Translator Clearinghouse

Due to the availability of various specialtyelectronic devices, it may be necessary tointerface with multiple component voltagelevels. With CoolRunner-II RealDigitalCPLDs, I/O banking is an easy way to elim-

inate voltage level translators. “Banking” isthe ability to separate function blocks withinthe CPLD so that these blocks can operateindependently at different voltage levels.

For instance, one function block could beI/O compatible with 3.3V devices, andanother function block could interfacewith 1.8V devices. This saves board spaceand eases voltage level design issues.

Conclusion

From process technology to a 100% digitalcore to added power reduction features,

CoolRunner-II RealDigital devices markthe beginning of a new era for CPLDapplications. Many system design concerns– including speed, power, I/O interfaces,clock management, and security – havebeen consolidated into one reprogramma-ble logic solution: CoolRunner-IIRealDigital CPLDS from Xilinx.

For more information, please visit www.xilinx.com > Products > CPLDs > IntroducingCoolRunner-II RealDigital CPLDs, orwww.xilinx.com/xlnx/xil_prodcat_product.jsp?title=coolrunner2_page.

20 Xcell Journal Summer 2002

A Short History of Low Power CPLDs

The first reprogrammable logic devices have their roots in bipolar PROM (programmable read-only memory) technology, with added logic capacity and fea-tures. The first company to generate customer interest was Signetics, with theirintroduction of the 82S100 FPLA (field programmable logic array).

Monolithic Memories Inc. attempted to be a second source supplier to the 82S100,but failed due to a process technology mismatch. They instead developed the nowfamous PAL (programmable array logic). This development by MMI led to aggres-sive process technology shrinks and increased speeds as logic designers pushed forfaster state machine operation.

Philips Semiconductors purchased Signetics, and in 1977, acquired a second sourcelicense for the PAL from MMI. Philips continued to work on different architec-tural enhancements and migrated to a BiCMOS (bipolar CMOS) process. Whenthe first 22V10 PAL from AMD hit the market, it was a greater success than any-one anticipated. From this beginning, devices matured into what are now knownas CPLDs. Xilinx entered the CPLD market in the early 1990s by acquiring PlusLogic and introduced the 7200 family of CPLDs.

CMOS CPLD products use power for speed improvements by partially turning on(biasing) transistors and by using sense amp technology. In the past, this was aneasy way to promote devices and claim a speed advantage. The by-product, how-ever, was heat.

In 1994, Philips Semiconductors made the move to CMOS CPLDs. With thisdecision, CPLDs broke away from their BiCMOS PROM roots and entered intothe scalable process technology arena. These products reflected innovativeapproaches in circuit design with an awareness of power consumption by removingthe old bipolar style sense amplifier from the circuitry.

Xilinx purchased the CoolRunner line of CPLDs from Philips Semiconductors in1999 to penetrate the low power CPLD market segment. Today, ultra high densityCMOS processes (0.18 micron) make possible reduced size and lower power con-sumption, which directly reduces heat dissipation.

Consumers’ demands for smaller, faster, cheaper, better products are the drivingforces in today’s competitive markets – and the state-of-the-art CoolRunner-IIRealDigital CPLDs meet these demands.

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by Alicia TrippManager, Business Continuity ProgramXilinx, [email protected]

Our customers depend on us – and youexpect us to provide reliable product andconsistent service, even in the event of adisaster or interruption to our business. Forthese reasons and for the benefit of ourstakeholders, we incorporated the BusinessContinuity Program (BCP) into the Xilinxculture in June 2000. The BCP is a corpo-ration-wide initiative that is supported byour Board of Directors and throughout ouremployee population.

We began the program by conducting abusiness impact analysis (BIA) and a threatand risk assessment (TRA) to determinethe critical business processes within thecompany. In addition, the BIA and TRAprovided an understanding of the impactof the loss of one or more of the criticalfunctions. Once the analyses were complet-ed, more than 80 departmental recoveryplans were developed. The recovery plansare the road maps that will allow us to con-tinue providing products and services toour customers during a major disruption.

Incident management teams (IMTs) areone of the most vital parts of the BusinessContinuity Program. We have locatedIMTs strategically throughout the Xilinxenterprise. Each team consists of membersof functional business units within thecompany such as Human Resources, Legal,Purchasing, Security, Facilities, RiskManagement, Accounting, and Safety. TheIMTs are responsible for handling theevent, from the time of a disaster throughrecovery and restoration activities. The pur-pose of the IMTs is to protect the healthand safety of our employees, to guide thecompany through a crisis, and to provide astructured organization for overseeing theresponse. These teams will conveneduring a major business interrup-tion to assess the situation anddetermine if a disaster shouldbe declared and whether ornot to launch departmen-tal recovery plans.

Incident management teams convenedfour times in less than 48 hours after theSeptember 11, 2001, terrorist attacks tomake plans to assist our employees. Wewere able to have counselors on site, and

travel representatives helped employeestraveling on business to schedule returnflights home.

The Business Continuity Program has beensuccessfully integrated into our businessculture – in large part, because of the top-level support from executive management.From the very beginning, our executivestaff has been onboard to make sure theprogram goals and objectives are achieved.

The BCP includes an executive awarenessand ongoing plan development that helpsour executive officers to continue to beinvolved and ready to respond. This execu-tive awareness plan will allow Xilinx to prop-

erly manage any incident from the timea disaster is declared through recov-ery and restoration activities.

Recovery plans and IMTs are exer-cised on a regular basis. By devel-oping and actively maintaining

the Business Continuity Program, weare prepared to limit the effect a long-termbusiness interruption might have on Xilinx –and to mitigate the impact on our customers.

Please contact your local sales representa-tive for additional information.

Services Business Continuity

War, natural disasters, terrorism, economic ruin, and other catastrophes can’t be prevented, but their effects can be attenuated. Xilinx has in place a Business Continuity Program designed to minimize the impact on your business.

If Disaster Strikes, Xilinx Is Prepared

Summer 2002 Xcell Journal 21

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by Lee HansenProduct Marketing ManagerXilinx, [email protected]

Your Xilinx programmable logic deviceoffers you more capabilities than everbefore, and coming releases of the ISEdesign tools will help you to handle thepressure that comes from using thesecomplex new features. Come along for aglimpse into the future of ISE.

ISE Delivers a Wealth of Device Features

The most compelling pressure on thelogic design flow comes from the addedcomplexity of new capabilities and toolfeatures. Embedded systems, increasedclock speeds, verification of high-densitydesigns, new device capabilities, high-speed I/O, a variety of IP (intellectualproperty) sources, and design reuse – all ofthese logic trends force more requirementsinto the design flow.

New Products ISE Software

Xilinx Integrated Software Environment (ISE) design tools promise to manage design complexity and, at the same time, ensure your logic design flow is easy to use.

22 Xcell Journal Summer 2002

Even as Designs Grow MoreComplex, Xilinx SoftwareImproves Your ProductivityXilinx Integrated Software Environment (ISE) design tools promise to manage design complexity and, at the same time, ensure your logic design flow is easy to use.

Even as Designs Grow MoreComplex, Xilinx SoftwareImproves Your Productivity

Page 23: Xcell Journal: Issue 43

New Products ISE Software

In 2001, the Virtex™-II FPGA intro-duced a revolution in clock capabilitieswith Digital Clock Manager (DCM),and this year, the Virtex-II Pro™Platform FPGA broke new ground bydelivering 3.125-gigabit serial I/O trans-ceivers and embedded IBM PowerPC™microprocessors. As the demand formore device features continues to grow,engineers must learn all the program-ming attributes for these new features– and the learning curve escalateswith the introduction of each newdevice feature.

To ease the learning curve, Xilinx ISE 5.1i will offer designers evenmore interactive architecture anddesign assistance. In addition toquick and easy dialogs, wizards willautomatically step you through con-figuring advanced device features andinserting those configurations direct-ly into your HDL source code.Upcoming releases of ISE will softenyour learning curve, helping to speeddesign completion.

ISE Enables IP Capture and Design Reuse

As design sizes grow, source manage-ment and methods to improve sourcecode productivity must keep pace. In amulti-million-gate design, source codecan come from multiple resources,including purchased IP, developed code,and “design reuse” – modules of HDLdeveloped and proved in a prior design.

In upcoming releases of ISE, it will bepossible to capture proven IP modules atthe floorplan level. This captured IP willnot be just a module of code, but it willalso have attached relative placement andfloorplanning area information that willhelp speed implementation in later uses.

As time-to-market pressures increase,design change impacts late in the designcycle will become an even larger designchallenge. Enhancements to ISE willconfine late-cycle design changes to onlythat portion of the design that isrequired to change. The remainder of thedesign will be left intact, thus speeding

A Higher Level of Abstraction Is Coming

While high-level languages (HLLs) havebeen explored in logic and systems design,the pain of existing logic design method-ologies hasn’t been great enough to force ahigh-level language or associated method-ology into common use.

Verilog and VHDL have served the logicdesign space well for the last two decades,

but now logic design sizes are routinelyexceeding one million gates. These mil-lion-gate-plus designs require large andcumbersome HDL source code and longperiods of debugging time. Emergingembedded processor methodologies arealso complicating the design process.Moreover, the need to serve two distinctlanguage-driven design flows (hardwareand software) is now making HLL designsupport imperative.

Xilinx is investing time and technologyin the industry-wide HLL effortsthrough partner technologies such asSynopsys® SystemC™ and CeloxicaHandel-C – as well as through ForgeCompiler, which Xilinx acquired fromLavaLogic™ two years ago. The resultsare leading to optimized performancefor FPGA devices, and to better inte-

gration of the co-design and co-verifica-tion phases of the embedded systemsdesign flow.

Longer-term technology is also beingdefined to help you “architect” the poten-tial design at the HLL source code level,analyze what modules should be imple-mented in the logic design flow, anddetermine what modules are required inthe processor design flow to reach opti-mum system performance.

Conclusion

New device capabilities will continue to pushdesign complexity. The good news is thatXilinx design tools are keeping pace. Newreleases of ISE software will help you keepyour design time down and your time tomarket fast. For more information on XilinxISE logic software, go to www.xilinx.com/ise– and watch for the release of ISE 5.1i coming in late summer.

overall design completion. This technolo-gy is enabled by new floorplanning capa-bilities along HDL hierarchy boundariesthat make it easier to define areas of logic.

High-Speed Design Will Push Innovation

High-speed design pressures will continueto push more innovation into logic designand into the board design flow.

Timing analysis and timing constraintshave – until now – lived under two differ-ent analysis domains, separated at theFPGA pin. The logic designer has lookedto the specification and timing require-ments to define design closure, while theboard designer has picked up the signal atthe logic pin and attempted to lay out andanalyze the effects that the PCB trace willhave on that signal.

Now, however, the line between logicdesigner and board designer functions willbegin to blur as timing constraint lan-guages become more uniform across thelogic tools and among the logic-level andboard-level tools. Trace analysis packagesalso will increasingly use more complex pinmodels provided by the logic tools, butthese complex analyses will also becomemuch faster, dumping slower general ana-log simulation in favor of specialized trans-mission line trace simulations.

Summer 2002 Xcell Journal 23

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by Jean-Louis Brelet, Manager APD Technical Market ResearchXilinx, [email protected]

What is hardware/software co-design?

Hardware/software co-design generallymeans that the hardware and software aredeveloped at the same time – some softwarefunctions may be implemented in hardwarefor additional speed, and some hardwarefunctions may be implemented in softwareto free up logic resources.

What does XDS do?

Xilinx Design Services, located in Dublin,Ireland, is part of the Xilinx Global ServicesDivision (GSD). XDS has two functionalgroups: software engineers who provide cus-tom software solutions, and hardware engi-neers who provide custom hardware solu-tions. The combined team consists of morethan 50 engineers.

Typically, we help customers with their fullproduct life cycle, from requirements cap-ture, through design implementation andtest, to final acceptance and delivery. Wework very closely with our customers, andform a team of experts who best match thejob requirements.

Perspective Virtex-II Pro

To explore the possibilities of hardware/software co-design, the Xilinx Design Services team created a reference designfor a real-time operating system (RTOS) for telecommunications – here is an interview with the team.

Exploring Hardware/Software Co-Design with Virtex-II Pro FPGAs

24 Xcell Journal Summer 2002

In this interview, Jean-Louis Brelet,manager of Technical Market Researchfor the Xilinx Advanced ProductsDivision, interviewed Xilinx DesignServices (XDS) software and hardwareengineers about their practical experiencewith an RTOS reference design project.Senior Project Engineer Matthew Rocheacted as spokesman for XDS.

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Perspective Virtex-II Pro

What are your previous experiences with embedded software?

We have worked on technologies thatinclude:

• Digital video systems – both set-top boxesand head-ends

• High speed digital network communica-tions systems

• Automotive applications

• Real time operating systems

• Board-level designs.

Due to the nature of design services, we haveattained experience from many differentdevelopment environments and methodolo-gies. We have experience with a wide rangeof designs, for device-level to system-levelapplications.

How would you describe the Virtex-II ProFPGA family from a software perspective?

The introduction of PowerPC™ processorsinto the Virtex-II Pro™ Platfrom FPGAarchitecture creates many new possibilities.Now we can design custom co-processorswith innovative (and fast) interfaces. Due tothe flexibility of the embedded IBM proces-sors, and their surrounding programmablelogic, we can offload some parts of our soft-ware design into a dedicated hardwareimplementation that can run much faster.

Previous hardware/software designs havebeen based around an inflexible hard-ware/software interface.

When did you startto design for thenext-generationVirtex-II ProPlatform FPGA?

As soon as the tech-nology becameavailable, it became

apparent that we must evaluate the systemin a real project situation – the RTOS ref-erence design. This way we could becomeaware of the new possibilities offered by theVirtex-II Pro device – and be best placed tocontribute our knowledge of the advancedarchitectures used by our customers.

and capabilities of thehardware.

Likewise, the hard-ware team must havea good understand-ing of software andhow the applicationoperates. Both teams

must have a common language – or a goodunderstanding of each other’s languageand a willingness to adapt.

Partitioning

What is your approach at the system level topartition embedded hardware and softwarefunctions?

We designed and implemented the RTOSreference design project for telecommunica-tions with resource-constrained processors.We built it for state-based SDL (specifica-tion and design language) applications.

The application for this RTOS was to bein systems with high numbers of processeswith large numbers of context switches. At this level, the overhead of the operatingsystem would be significant and thus,must be minimized.

First, we analyzed the system and identifiedthe time-hungry elements. Our initial per-formance analysis indicated that processingof the state tables and managing the mostheavily used queues (signal queues) were theprocessor-intensive tasks. The first iterationsof the design placed these tasks into hard-ware with a clearly defined hardware/soft-ware interface. This did not completelyremove the bottlenecks, but it did have atendency to move them from the processinginto the interface.

Further iterations of the design requiredmuch closer integration of the hardwareand software teams. This allowed thedesign of coherent and integrated tasks,which could be completely dealt with inhardware, and required minimal use ofthe interface.

Having the processor embedded into theFPGA fabric allows a variety of interfacetechniques, which do not necessarily requirethe use of the IBM CoreConnect™ proces-

Project Objectives

What are the main objectives of this project?

The overall and real objective was to gainexperience in developing a product in atightly coupled hardware/software environ-ment. The ability to shift functions fromsoftware to hardware, or vice versa, in a veryshort time frame, creates an environmentwhere the design teams need a much greaterknowledge of each other’s work.

The smaller and more restricted objectivewas to identify the speed bottlenecks in theRTOS and remove the bottlenecksthrough the use of dedicated hardware –effectively implementing large sections ofthe kernel in hardware.

Before Virtex-II Pro FPGAs, how would youdevelop a system like this?

The RTOS project is very suited to theVirtex-II-Pro architecture. Given thecosts, project time, cycle time, and riskrequired to develop this project with othertechnologies – for example, an ASIC – itis unlikely that it would even be under-taken. An ASIC design doesn’t offer youthe benefit of reprogrammability and flex-ibility to change/improve or upgrade thesystem in the field.

What is the expertise required to successfullyimplement these systems?

Software people must understand the natureof hardware designs and the type of prob-lems encountered by the hardware team.They also must understand the possibilities

Summer 2002 Xcell Journal 25

Mathew Roche

Jean-Louis Brelet

Page 26: Xcell Journal: Issue 43

Perspective Virtex-II Pro

sor local bus. This feature became an impor-tant design issue, as the speed of the systemwas capable of hogging the bus.

In our experience, we have found that thereis no distinct division between functionsthat are suitable for hardware or software. Itbecomes a trade-off of how fast you want todo something and how many configurable

logic blocks you want to spend on doing it.Greater complexity of the function orrequired speed of operation will bias thedesign towards software or hardware.

How would you summarize your method forpartitioning the system?

We simply integrated the design teams, toavoid a purely hardware- or software-ledsolution.

How have you split the teamwork?

Most of the software was designed first,because we needed to understand how thesystem would operate before transferringparts of it into hardware. This gave us theadvantage of having functioning proto-types before a full hardware implementa-tion – significantly reducing our theoreti-cal time to market.

At the system design level, the division oflabor became less important as the projectwent on. It was necessary for both sides tohave a good understanding of what theother team was doing. Design decisions hadto be made with knowledge of both hard-ware and software. This had some interest-ing implications for the language and termi-nology used by the teams.

Virtex-II Pro Embedded Software

Is it easier to create embedded software forthe Virtex-II Pro fabric?

In the first applications, embedded softwaredevelopment techniques will not necessarilybe different for Virtex-II Pro devices – theycan be viewed as conventional systems withperformance improvements and reducedchip count. However, as experience builds, itwill become apparent that traditional designmethods do not use the full potential of thedevice. System partitioning will become partof the architectural design process, and theboundary between hardware and softwarewill become less rigid.

The RTOS project gave us an opportunityto examine the project with system co-design as the goal. Virtex-II-Pro PlatformFPGAs allow significantly more integrated

designs with all the performance benefitsthat entails.

What is the most innovative feature ofVirtex-II Pro for a software engineer?

Using multiple processors (both IBMPowerPC 405 hard core and XilinxMicroBlaze™ soft core processors), on asingle chip, allow you to dedicate processesto particular processors for critical tasks.You can easily implement interfacesbetween the different processors, usinghardware-based FIFOs, reducing the com-munications bus overhead.

How easy is it to partition a Virtex-II Pro design?

Partitions are very flexible in the Virtexarchitecture. Changes were being made tothe interface all the way through the designand implementation of our RTOS system.This allowed us to reduce our design timeand minimize design roadblocks.

Conclusion

Could you summarize your experience?

Close cooperation between hardware andsoftware teams is critical.

Is this project an example of making the impossible possible?

No. This project does not do anythingthat has been impossible before. What itdoes do is make it faster, cheaper, andwith reduced risk.

How can Xilinx customers benefit from your expertise?

It is part of our culture to maintain high lev-els of expertise in advanced and state-of-the-art technological systems and methodolo-gies. As project managers, we are constantlyimproving our service and quality in dealingwith our customers’ projects. Increasingcompetitiveness in the marketplace meansthat there is a higher emphasis on time tomarket and quality. XDS continues toimprove its skills in order to help our cus-tomers achieve these challenging targets.

XDS can be contacted by e-mail at [email protected] or by visitinghttp://support.xilinx.com/xds/.

26 Xcell Journal Summer 2002

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Perspective Convergence

The breakthrough technologies embedded and immersedwithin the Virtex-II Pro logic fabric deliver the integratedfunctionality demanded by top digital design engineers.

Virtex-II Pro Platform FPGADrives Convergence ofProgrammable Logic andEmbedded Systems

Summer 2002 Xcell Journal 27

Virtex-II Pro Platform FPGADrives Convergence ofProgrammable Logic andEmbedded SystemsThe breakthrough technologies embedded and immersedwithin the Virtex-II Pro logic fabric deliver the integratedfunctionality demanded by top digital design engineers.

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Perspectives Convergence

by Michael WorryCEO, Nuvation Engineering [email protected]

Time to market pressures have ruled outdesigning an ASIC from scratch, butwithout a custom ASIC, the discreteFPGA, microprocessor, and off-boardhigh-speed serial I/Os will never fit lastyear’s form factor. You just can’t fit 16channels this year on a board designed forfour channels last year.

As a Xilinx XPERTS partner andan engineering services compa-ny working in the cross disci-plines of FPGAs, printed cir-cuit boards, and firmware, weat Nuvation Engineering oftenencounter these problems ofform, fit, and function. Weneed an onboard industry stan-dard microprocessor, integratedhigh speed I/Os, off-the-shelfIP blocks, and double last year’sgate count.

Xilinx has delivered on all thisand more with their introductionof the revolutionary Virtex-II Pro™Platform FPGA. It starts with the techno-logically advanced Virtex™-II infrastruc-ture, supporting up to 8 million gates andI/O serial speeds of 3.125 Gbps. Nestledinto this digital workshop is the IBMPowerPC™ 405 microprocessor – thenumber one embedded CPU for network-ing and telecom infrastructure. The contin-ued convergence of programmable logicwith embedded systems has created a newdigital workbench with a wealth of integrat-ed platform standards and rapid co-devel-opment tools. The Virtex-II Pro PlatformFPGA is in a class by itself in the explodingprogrammable embedded market.

FPGAs and Microprocessors: A Symbiotic Relationship

Fundamentally, microprocessors andFPGAs fulfill different tasks (see Table 1).Programmable logic is needed for wirespeed, high bandwidth, custom digital pro-cessing, and hardware acceleration.However, that speed and customization

Virtex-II Pro Features

The Virtex-II Pro Platform FPGA bringstogether market-leading Xilinx program-mable logic with the industry standardPowerPC (PPC) microprocessors and high-speed I/Os. Truly this is the digital sandboxfor the 21st century engineer.

Integrate Off-the-Shelf IP

The Virtex-II Pro device offers as many as 8million system gates. This allows easy and

rapid SoC (system-on-chip)integration of existing IP coreswithout having to painstaking-ly code a custom implementa-tion of a standard interface tosave a few gates.

The Virtex-II Pro FPGA allowsyou to choose up to four PPCbuilt-in cores. No longer doyou have to meticulously calcu-late how many clock cycleseach firmware operation willtake to determine the processorinfrastructure. If the first PPCbecomes overloaded, justchange the part number and

add another PPC to the Virtex-II ProFPGA. You don’t have to respin the boardor, worse yet, you don’t have to deal with anincrease in the form factor rippling tomechanical changes.

The off-the-shelf features of Virtex-II Prodevices are matched with on-chip memoryof up to 4.5 MB. With this onboard mem-ory, you can get high-speed, on-chip busconnects without being bottlenecked by amemory arbiter to off-chip memory.

Flexible Clocking Infrastructure

Any first year student learns the first ruleof digital synchronous logic: never gate theclock. Well, Xilinx has packed that up withthe vacuum tubes and created an architec-ture that allows you to switch – glitch-free– among as many as 16 global clocks. Thisis a huge benefit for sharing systemresources among different clock domains.The Xilinx Digital Clock Manager alsoprovides on-chip frequency and phase con-trol, meaning that an off-chip, phase-locked loop is no longer needed.

comes at a price, both in parts and non-recurring engineering (NRE) costs.

For monitoring and control tasks, it is farcheaper and easier to use a microprocessor.Furthermore, microprocessors have existedlonger and have a larger base of engineer-ing familiarity. Thus, many product archi-tectures naturally marry an FPGA with amicroprocessor. At Nuvation, our complexdesigns often start with an FPGA and

microprocessor architecture, then wedetermine which system functions are bestimplemented in each. Xilinx takes this tothe next level by integrating these func-tions into a single chip.

A more traditional design would be amicroprocessor integrated with dedicatedhardwired logic in an ASIC. However, timeto market pressures are demanding plat-forms with full product cycles in monthsand integration cycles in hours. Comparedto the time for ASIC development andpotential respins, FPGAs present a highlyappealing alternative.

Because the FPGA is reprogrammableafter release, using technologies such asthe Blue Iguana™ System, a whole newmarket of revenue streams and businessmodels is opened. Xilinx has risen tothese market pressures by systematicallydriving down the cost of customizedhardware acceleration while producingcontinued innovation in size, speed, andintegrated features.

28 Xcell Journal Summer 2002

MicroprocessorFPGA

• Configurable and programmabledigital logic

• Instantiate multiple processing units to run tasks in parallel

• Hardware accelerate high speed tasks

• Scalable

• Coded in HDL

• Fixed processing units accessed bypredefined commands

• Greater knowledge, tools, installationbase and engineering familiarity

• Faster development time

• Lower parts costs

• Coded in firmware such as C

Table 1 - Hardware accelerates high speed tasks

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Perspectives Convergence

XCITE On-Chip Impedance Control

After drawing a thousand-pin FPGA, thelast thing a design engineer wants to dealwith is adding a few hundred terminationresistors. Xilinx Controlled ImpedanceTEchnology (XCITE) eliminates thoseresistors with dynamic, on-chip, digitallycontrolled impedance. The savings inboard space, schematic time, and layouttime are significant.

Integrated High Speed I/O

It seemed not too long agothat it was cutting-edge tosupport 64-bit, 66 MHzPCIs. Now we are up toPCI-X speeds at 133MHz. We have supportfor RapidIO™, POS-PHY4 and SPI-4 inter-connect technologies, toname a few. Pick almostany kind of memory youlike – ZBT™ SRAM,DDR SDRAM, or QDRSDRAM, for instance –and they can be imple-mented in the Virtex-IIPro logic fabric. Then wejump into serial I/Ospace, and the Virtex-IIPro platform can accom-modate as many as 16Rocket I/O™ multi-gigabit transceiversat a whopping 3.125 Gbps. This meansapplications like OC-48 can integrateSERDES (serializer/deserializers) rightinto the FPGA – once again, saving boardspace, cost, and valuable time.

Integrating Customer Hard IP

Hard IP is when digital logic is implement-ed in hard coded gates, removing the pro-gramming capability, but also using muchless silicon. Once a design or IP block isstable, it can be converted to hard IP. ThePPC 405 microprocessor is currentlyimplemented in the Virtex-II Pro device ashard IP, but Xilinx actually allows cus-tomers of sufficient volume to embed theirown hard IP. For example, if you wanted toroll out an existing ASIC to provide addi-tional capacity and integrate the micro-

processor, the Virtex-II Pro could embedthat ASIC as hard IP and provide program-mable gates for new functionality.

Integrated Bitstream Security

The Virtex-II Pro device has on-chip stor-age capacity for a 3DES key, either with abattery or constant power supply. Thestored or delivered bitstream is encrypted,and can only be unlocked with the on-chip key. The on-chip key allows Virtex-II

Pro devices to be designed into militaryapplications that traditionally haverequired OTP (one time programmable)solutions to remove any chance of codebecoming compromised.

Reconfigurability

The Virtex-II Pro Platform FPGA can bemade even more powerful by enablingremote configuration capabilities. XilinxIRL™ (Internet reconfigurable logic) tech-nology includes a partnership with WindRiver Systems Inc. to produce the PAVEFramework – PLD API for VxWorks™Embedded System Integration Framework.The framework enables Xilinx FPGAsusing Wind River’s VxWorks real-timeoperating systems and Tornado™ integrat-ed development environments to be recon-

figured during development and afterdeployment in the field.

Additionally, Xilinx is in partnership withBlue Iguana Networks Inc., a semicon-ductor company that provides secure,remote, hardware management. Theirpatented technology enables secure soft-ware and hardware upgrades to in-serviceequipment over the Internet and withoutdowntime. The Virtex-II Pro Platform

FPGA is an excellent matchfor Blue Iguana’s technology,as the embedded micro-processor could upgrade theFPGA, or vice versa.

Conclusion

Because microprocessor andFPGA functionalities differ, asapplications become morecomplex and diverse, it isoften insufficient to utilizejust one or the other. Thedevelopment of the XilinxVirtex-II Pro Platform FPGAresulted from the natural inte-gration of FPGAs and micro-processors. In the past, theonly solution would have beento utilize multiple, discreteASICs. However, because ofthe time to market require-ments – in addition to the

potential expenses associated with an error– reconfigurable processing has become anideal alternative.

With digital design engineers facing thepressures of increased flexibility, shortertime to market, and higher clock speeds,they will continue to drive the demand forintegrated standard platforms. The Virtex-II Pro Platform FPGA does a masterful jobof combining a highly technologicallyadvanced FPGA architecture with theindustry standard IBM PowerPC micro-processor. As a member of the Xilinx EarlyAdopters Program, as well as a XilinxXPERTS partner, we at Nuvation look for-ward to implementing this breakthroughtechnology for the benefits of our clients.For more information, please visit us atwww.nuvation.com.

Summer 2002 Xcell Journal 29

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Robert Bielby, Senior Director Strategic Solutions Marketing Xilinx, [email protected]

With the recently introduced Virtex-IIPro™ product family, the much awaitedand highly debated immersion of a micro-processor into a programmable logic fabrichas finally occurred. With up to four IBM®

PowerPC™ 405 microprocessors in thehighest density family members, Virtex-IIPro Platform FPGAs deliver more than2,000 Dhrystone MIPS, a number that isunchallenged in the industry.

Complemented by the integration of multi-gigabit serial I/O signaling tech-nology capable of supporting more than 3Gbps per I/O pin pair, the Virtex-II Profamily delivers the industry’s first trulyhigh-performance Platform FPGAs.These advanced programmable logicdevices are unparalleled in their capabili-ties not only to address a wide range ofthe most demanding applications – but also to adapt and adopt emerging I/O standards and protocols as theybecome available.

Advances in semiconductor and program-mable logic fabrication have not onlymade families like the high-end Virtex-IIPro Platform FPGAs possible, but on theother end of the spectrum, technologyadvances have also enabled the recentdelivery of Spartan™-IIE FPGAs andCoolRunner™-II RealDigital CPLDs.The Spartan-IIE family sets a new stan-dard for low cost within the programmablelogic industry, and the CoolRunner-IIseries sets an equivalent benchmark in theindustry for ultra low power consumption.

This premiere portfolio of programmablelogic solutions gives Xilinx the power toaddress a wide range of new markets andapplications, including consumer electronicsand handheld devices. In this issue of XcellJournal, we discuss some of the marketswe’ve opened and applications we’ve enabled.

Perspective Market Analysis

For anyone who has been following the history of programmable logic, it’s pretty clear that the industry has seen more changes in the course of the past yearthan it has perhaps in its entire 19 years of its existence.

Xilinx Offers End-to-End Solutions

30 Xcell Journal Summer 2002

Xilinx Offers End-to-End Solutions

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Perspective Market Analysis

Metropolitan Area Networks

The hottest areas in networking today aremetropolitan area networks (MANs) and“edge access” markets. Driven by the explo-sive growth of data traffic in metropolitanregions, this networking market segment isexpanding at a 34% CAGR (compoundannual growth rate).

New products and technologies based uponstandards proposals that leverage the com-bined benefits of Ethernet and SONET arenow being rushed to market to address thisrapidly growing demand for data services.However, the uncertainty surrounding theoverall acceptance of these new standards –and the rigorous requirements of supportingline rates in excess of 10 Gbps – have givenrise to the need for solutions like Virtex-IIPro Platform FPGAs that offer both flexibil-ity and high performance.

In addition to articles discussing the chal-lenges of developing solutions for theMAN, we are also pleased to present – inconjunction with Avnet Design Services,Avnet Cilicon, and Reed Electronics Group– an industry-wide event: the Metro-Optical Networking Forum to be held July25 at the Santa Clara Convention Center inCalifornia. This free one-day event (whichwill be simulcast to more than 40 NorthAmerican venues) is focused entirely on thelatest developments in metropolitan andedge access networking. For more informa-tion, see the article and ad in this issue ofXcell Journal. To register for this event, visitwww.xilinx.com/metro.

Consumer Electronics

Consumer electronics continue to grow at avery healthy pace, fueled by the trendtowards digitization. Consumers perceivethat anything digital is better. This con-sumer perception started with the introduc-tion of the digital clock. The digital clockwas more accurate than the analog clockand over time, more desirable.

Miniaturization drove the development of thedigital watch, handheld calculator, and a myr-iad of other consumer products based upondigital technologies. Naturally, a plethora ofnew standards and protocols have emerged.

consumer electronics products in history.According to International Data Corp,DVD had penetrated 23% of US house-holds by end of 2001.

The success of the DVD is attributed to sev-eral factors: the significant improvement inimage quality, the industry-wide standardiza-tion that reduced consumer confusion, andhigh-volume sales, which led to acceleratedcost reductions. Another key factor in thewidespread acceptance of DVDs was that theycan be viewed on existing analog televisions.

Now, as digital video has grown in popular-ity, it is spawning a host of new digital prod-ucts – and formats – including plasma dis-plays, personal video recorders, read/writeDVDs, and set-top boxes.

DTV has also spawned a widespread con-cern in the “infotainment” industry overvideo piracy. This concern is giving rise to asuite of new encryption standards, including5C, 4C, CPTWG, and TCPA (to mention afew) that are being proposed by a wide rangeof interested parties, including the motionpicture industry.

Conclusion

In this issue of Xcell, we discuss some of theexciting Xilinx solutions for consumer elec-tronics, with a special emphasis on digitalvideo applications, such as video image pro-cessing, navigating changing standards, andaddressing encryption challenges. We hopeyou enjoy these articles.

Multiple standards, changing protocols,high-performance processing, low powerrequirements at cost-conscious consumerprices – these are the challenges where thelow cost Spartan™ series of FPGAs andthe ultra low power CoolRunner™CPLDs shine.

Digital TV

With a heightened awareness and demon-strated demand for digitized electronics, thetelevision industry logically went aboutdefining a new television format based

entirely upon digital technology. The resultsof high-definition digital TV (DTV) wereastounding, but the price tag was prohibi-tively expensive, and consequently, con-sumer interest was low. Until just recently, itwas hard to pinpoint exactly why consumerinterest in DTV languished – was it becauseof price, or did consumers just think thatdigital video was not interesting?

Actually, it has only been in the past fiveyears that the story has slowly unraveled.Consumers have, in fact, voted strongly infavor of digital video – but this has come,not in the form of an end-to-end digitalsystem, but rather in the form of a singlevideo component: the digital video disc, orDVD. Never, in the history of any con-sumer electronics product, has there beensuch a wide and rapid acceptance of anynew medium or format as there has beenwith the introduction of the DVD. TheDVD represents one of the most successful

Summer 2002 Xcell Journal 31

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by David Nicklin, Senior ManagerStrategic Solutions, WirelessXilinx, [email protected]

Real-time video processing makes enor-mous demands on system-level perform-ance requirements and, except for the sim-plest of functions, is well beyond the capa-bilities of any general purpose DSPdevice. Therefore, DSP-based videodesigns often require several DSP devicesto get the necessary throughput, alongwith the overhead of multiple programand data memory resources. However,designing with programmable logic allowsyou to implement video signal processingalgorithms using parallel processing tech-niques, giving you the performance youneed within a single, highly flexible pro-grammable logic device. By performingvideo processing functions in real time,you can minimize the need for framestores and data buffering.

Technology Focus Real-Time Video Processing

With Xilinx FPGAs you can create DSPs that are much faster than any off-the-shelf stand-alone DSP device.

FPGAs – Enabling DSP inReal-Time Video Processing

32 Xcell Journal Summer 2002

FPGAs – Enabling DSP inReal-Time Video Processing

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Technology Focus Real-Time Video Processing

With the industry pushing for higher levelsof video quality, and the development ofimproved compression schemes, systemprocessing rates have increased dramatically.At the same time, we have introduced newprogrammable logic devices, such as theXilinx Spartan™-IIE FPGAs, which drawon the architectural heritage of the FPGAdevices that are commonly used in profes-sional broadcast equip-ment today. As FPGAprocess development fol-lows Moore’s Law, ournew products can performthe same functionality astheir predecessors, witheven higher performanceand a much lower cost.

By developing systemsusing our latest cost-effec-tive FPGAs, you canbring unprecedented lev-els of professional, broad-cast quality, video pro-cessing into areas of digi-tal video technology suchas high-end consumerproducts, security sys-tems, industrial andmachine vision applica-tions, and frame-grabbers.

One driver of this trend, isthe combination of net-working, broadcast, pro-cessing and display technology, in what theindustry has termed “digital convergence.”The need to send high bandwidth videodata over extremely difficult transmissionchannels, such as wireless, while still main-taining an acceptable quality-of-service(QoS), is extremely difficult. This has leadto wide ranging research in how to improveerror correction, compression and imageprocessing technology, much of it based onadvanced FPGA technology.

Image Compression/Decompression –DCT/IDCT

The main video compression schemeused in digital video systems today isMPEG2. It can be found at the heart of

blocks that are left undefined. It is withinthese undefined sections of the standardthat a company can truly differentiate itsproduct from its competition and developits own proprietary algorithms. Many pro-fessional MPEG encoders use FPGAs inthese sections, such as the motion estima-tion block, as shown in Figure 1. BecauseFPGAs are reconfigurable, the equipment

can be easily updated to incorporate newalgorithms at all stages of development,including in the field after deployment.Companies that rely totally on standardASSP solutions are limited in their abilityto produce products that can make themstand out from the competition, and theytherefore run the risk of being seen as justone of a number of similarly specifiedsolutions in the market.

Color Space Conversion

Another important part of a video systemis the requirement for color space conver-sion, a process that defines how an imagespecified in one color format can be con-verted into a different color format.

digital television, set-top boxes, digitalsatellite systems, high-definition televi-sion (HDTV) decoders, DVD players,video conferencing equipment, and Webphones, to name just a few. Raw digitalvideo information invariably has to becompressed so it can be either sent over asuitable transmission channel, or storedonto a suitable medium such as a disc.

There are also a number of emerging stan-dards, including most notably MPEG4.Most products based around this technolo-gy are still in development, although ramp-up to production is expected shortly. At theheart of the MPEG2 and MPEG4 algo-rithms is a function called the discretecosine transform (DCT). The aim of theDCT is to take a square of pixel blocks andremove redundant information that isimperceptible to the viewer. To decompressthe data, the inverse discrete cosine trans-form (IDCT) function is required.

While the DCT section of the MPEGalgorithms is standardized and can beimplemented very efficiently withinFPGAs, MPEG encoding has a lot of

Summer 2002 Xcell Journal 33

Preprocessor• Downsize I/P• Temporal Noise Reduction

Motion Estimation & Compensation• Search Patterns • Evaluate Modes/Options

Bitstream Encoder• Picture/Block Type• Error Resilience• Resynchronization

Rate Control• Scalability• Constant Rate• Variable Rate

Switch

Switch

DCT/Quantizer

Implementation undefined in standard

Defined in the standard

+

Figure 1 - Simplified video encoder diagram

Page 34: Xcell Journal: Issue 43

Technology Focus Real-Time Video Processing

Receptors in the human eye are only capableof detecting light wavelengths from 400 nmto 700 nm. These receptors are called conesand there are three different types, one forred light, one for green, and one for blue. Ifa single wavelength of light is observed, therelative responses of these three sensorsallow us to discern what we call the color ofthe light. This phenomenon is extremelyuseful because it means we can generate arange of colors by simply adding togethervarious proportions of light from just threedifferent wavelengths. The process is knownas additive color matching, and is used incolor television systems.

It’s possible to represent colors of light byplotting the red, green and blue (RGB)components proportions on a 3-dimen-sional cube, with black at the origin andwhile at the diagonally opposite corner.The resulting cube is known as the “RGBcolor space,” as shown in Figure 2.

Whether the final display medium is paper,LED, CRT, or plasma displays, the image isalways broken down into an array of pic-ture elements or pixels (HDTV, for exam-ple, can have 1920 x 1080 pixels). Whilethe mechanics change slightly for eachmedium, the basic concept is that each

pixel displays a proportion of red, green, orblue depending on the voltage signals driv-en to the display.

Processing an image in RGB format, whereeach pixel is defined by three 8-bit or 10-bit words corresponding to each primarycolor, is certainly not the most efficientmethod. With such a format, every actionon a pixel has to be performed on all thered, green, and blue channels. This invari-ably requires more storage and data band-width than other alternative color formats.

To address such issues many broadcaststandards, such as the European PAL andNorth American NTSC television sys-tems, use luminance and color differencevideo signals. A requirement thereforeexists for a mechanism to convert betweenthe different formats, and this is called“color space conversion.”

Realizing these circuits in hardware is a rel-atively simple task, once the coefficients tomap from one plane to another are known.One common format conversion is RGB toYCbCr (and conversely YCbCr to RGB).See Figure 3. It has been found thatbetween 60% and 70% of the luminanceinformation (Y) a human eye can detectcomes from the green color. The red and

blue channels in effect duplicate much ofthe luminance information, and hence, thisduplicate information can be safelyremoved. The end result is that the imagecan be represented as signals representingchrominance and luminance. In this for-mat, the luminance is defined as having arange of 16 to 235 in an 8-bit system, andthe Cb and Cr signals have a range of 16 to240, with 128 being equal to 0.

A color in the YCrCb space is converted tothe RGB color space using the equations:

R’ = 1.164 (Y – 16) + 1.596 (Cr – 128)

G’ = 1.164 (Y – 16) – 0.813 (Cr – 128) – 0.392 (Cb – 128)

B’ = 1.164 (Y – 16) + 1.596 (Cr – 128)

R’G’B’ are gamma corrected RGB values.A CRT display has a non-linear relation-ship between signal amplitude and outputintensity. By gamma correcting signalsbefore the display, the relationship betweenreceived signal amplitude and outputintensity can be made linear. The outputgain is also limited below certain thresholdsto reduce transmission-induced noise inthe darker parts of an image.

There are a number of possible implemen-tations – memory, logic, or embedded multipliers – to perform the necessary mul-tiplication functions. It is certainly possibleto meet and exceed the 74.25 MHz datarate required for HDTV systems. It is alsopossible to try different design trade-offs,such as that between system accuracy anddesign area. For example, for a 3% error inluminance, the design size of a YCrCb-to-RGB color-space-converter can be morethan halved. This may be unacceptable inmost display products but could be accept-able in other applications such as machinevision or security systems. By using anFPGA, you can tailor the algorithm for theapplication, thereby maximizing perform-ance, efficiency, or both.

Real-Time Image and Video Processing Functions

Limitations in the performance obtainablewith standard DSPs has led to the develop-ment of specially designed chips, such as

34 Xcell Journal Summer 2002

Red

Blue

White

GreenBlack

Figure 2 - Color space cube

Page 35: Xcell Journal: Issue 43

Technology Focus Real-Time Video Processing

media processors. However, these deviceshave often proved to be too inflexible in allbut a narrow range of applications, and cansuffer from performance bottlenecks. Thelimitations of a processor-based approachbecome especially apparent in high-resolu-tion systems, such as HDTV and medicalimaging. Fundamentally, a processor solu-tion is restricted in how many cycles can beallocated to each tap of a filter, or each stageof a transform. Once the performance lim-its have been reached there is often no otherway around the problem than to add extraDSP parts.

An FPGA, however, can be custom tailoredto provide the maximum efficiency of utiliza-tion and performance. It’s possible for you totrade off area against speed, and invariablyperform a given function at a much lowerclock rate than a DSP would require.

For example, Visicom Inc. found that fora median filter application a DSP proces-sor would require 67 cycles to perform thealgorithm. An FPGA needed to run atonly 25 MHz, because it could realize thefunction in parallel. For the DSP tomatch the same performance, it wouldhave to run at over 1.5 GHz. In this par-ticular application, the FPGA solution is

some 17 times more powerful than a100 MHz DSP processor.

There are a wide number of real-time imageand video processing functions that are wellfitted for implementation in FPGA devices– these include real-time functions such as:

• Image rotation

• Scaling

• Color and hue correction

• Shadow enhancement

• Edge detection

• Histogram functions

• Sharpening

• Median filters

• Blob analysis.

Many of these functions are both applica-tion specific and system specific, and arebased around core structures such as 2D-FIR filters. Such functions can be imple-mented quickly using HDL languagedesign or by exploiting the DSP buildingblocks found in high-level core design toolssuch as the Xilinx CORE Generator™software. It’s also possible to reduce bothdesign and simulation time by employing a

system-level design approach, using prod-ucts such as The MathWorks’ MATLAB™and Simulink™ software, as well as XilinxSystem Generator.

Conclusion

With digital convergence, you need tointegrate various standards and require-ments into one homogeneous product –this demands flexibility in design andimplementation.

FPGA technology is addressing the systemrequirements of new and emerging videoapplications, bringing with it the featuresand signal processing performance that havemade it the preferred solution for video andimage processing in the professional broad-cast equipment market for a number ofyears. The latest generation of FPGAs canprovide the same level of performance andfunctionality, at a fraction of the cost of theFPGAs that were designed into professionalequipment just a few years before.

In comparison to ASSP and chipset solu-tions, FPGAs offer levels of flexibilitythat designers demand in today’s prod-ucts, while at the same time maintaininga distinct performance advantage overconventional DSPs.

+

+ +

+

++

Limit R'

Limit

Limit

Y[7:0]

Cr[7:0]

Cb[7:0]

-128

-128

-16 1.164

1.596

-0.813

2.017

-0.392

CE

CLK

G'

B'

Figure 3 - YCrCb-to-RGB color space converter

Summer 2002 Xcell Journal 35

Page 36: Xcell Journal: Issue 43

by Robert Green, ManagerStrategic Solutions, Digital Audio-VideoXilinx, [email protected]

Broadcasters are very interested in creat-ing new revenue from digital televisionservices. However, a vast range of evolvingdigital television (DTV) standards intransmission, image processing, intercon-nectivity, and display interfaces can createconsiderable barriers to speedy implemen-tation. Yet, the industry promotes digitalbroadcasting, highlighting better videoand sound quality to attract new sub-scribers from the analog world. Consumeradoption of digital TV is important ifbroadcasters are to adhere to the scheduleof analog switch-off.

Bandwidth is precious; to make the most ofit, compression schemes have steadilyimproved and new algorithms are in devel-opment to push the envelope even further.As such, system-processing rates haveincreased over time, and real-time imageprocessing is now an ideal way of meetingthese requirements while removing memo-ry overhead. At the same time, Moore’s Lawhas resulted in low cost programmable logicdevices, such as the new Spartan™-IIEFPGAs, that provide the same functionalityand performance previously only found inexpensive professional broadcast products.

Which Standard Do I Use?

The transition from analog to digital tech-nology is providing opportunities forbroadcasters to offer new services, andcompetition is fierce between OEMs toproduce cost-effective systems that areattractive to consumers. As with manytechnology shifts, this introduces manynew proposed standards as companies viefor market leadership. It’s possible that thefirst company to market becomes a de factostandard regardless of the efforts of stan-dards bodies to ensure interoperability andfair competition. Even when standardsbodies successfully produce internationallyrecognized specifications, there are oftenmany versions of a standard that can beadhered to as they try to address manymember companies’ needs. Add to this the

Perspective Digital TV

FPGAs Provide Flexibility in Digital TV Development

36 Xcell Journal Summer 2002

Cost sensitive consumer applications, such as digital TVs, can now benefit from the many advantages of Spartan series programmable logic devices.

FPGAs Provide Flexibility in Digital TV DevelopmentCost sensitive consumer applications, such as digital TVs, can now benefit from the many advantages of Spartan series programmable logic devices.

Page 37: Xcell Journal: Issue 43

inevitable revisions to standards duringdevelopment, and it is easy to see why theflexibility of a fully reprogrammable solu-tion is so compelling.

For example, your return on investmentwould be much greater if you were able toreprogram your system so that it complieswith the latest revision of an emerging for-ward error correction algorithm. Replacingan aging encryption scheme such as DESwith a new, more robust version (AES) isanother example.

Table 1 shows a summary of broadcast for-mats defined by the Advanced TelevisionStandards Committee, and is referred to inthe broadcast industry as “Table 3” (fromthe ATSC A53 specification). There are 36options that equipment manufacturersneed to support in this table alone. Thereare also regional variations to broadcaststandards, with DVB, ISDB, and the pro-posed DMB used in different parts of theworld. Although ASSPs (ApplicationSpecific Standard Products) are available, itfrequently means that different chips arerequired for each format.

An FPGA solution, easily supporting datarates exceeding those required by HDTV,would enable all the formats to be support-

ed with one device that is reprogrammeddepending on the equipment or operationalmode it is used in. Such flexibility in a stan-dard, off-the-shelf component reduces yourbill of materials and removes any risk ofsupply problems from an ASSP provider.

Pixels and Performance

With the advent of high-definition broad-casts in many parts of the world, video sig-nal processing requirements have increased

integrated, allowing it to receive digitalbroadcasts. FPGAs can have many areas ofresponsibility within digital TV sets, asshown in Figure 1. Interfacing betweenstandard chipsets, as “glue logic,” hasalways been a strong application of FPGAs,but many more image processing tasks(such as color space conversion) and sup-port for network interfaces (such as IEEE1394) are now possible in low cost pro-grammable devices.

One driver of the trend to offload image-processing tasks to FPGAs is the result ofthe industry-coined phrase “digital conver-gence.” This arises from the need to sendhigh bandwidth video data over new andextremely difficult transmission channels,such as wireless networks, while still main-taining an acceptable quality-of-service(QoS). This has lead to wide rangingresearch in how to improve error-correc-tion, compression and image processingtechnology, much of it based aroundimplementation in an FPGA.

Product Differentiation

By using FPGAs, it is possible for you todifferentiate your standard-compliant sys-tems from your competitor’s products.With the MPEG-2 compression scheme,

for example, it’spossible to offloadthe IDCT (inversediscrete cosinetransform) portionof the algorithmfrom an MPEGprocessor, to anFPGA, to increasethe bandwidth.IDCT (and DCT

at the encoder) can be implementedextremely efficiently using FPGAs, andoptimized IP cores are readily available toinclude in MPEG based designs.

By integrating proprietary techniques forother image processing functions alongsidedefined blocks such as DCT, it’s possible toproduce a low cost, single chip solutionthat increases processing bandwidth andgives higher quality images than your com-petitor. By avoiding systems that rely just

dramatically. For example, an HDTV dis-play of 1920 x 1080 resolution, 24-bit pix-els, and 30 progressive frames per second,requires a total uncompressed bandwidthof around 1.5 Gbps. Even in areas wherehigh-definition images aren’t actuallybroadcast, HD pictures are still used in allpost production stages .

The latest low cost programmable logicdevices (the Spartan series) now have mul-tiple I/Os with LVDS (low voltage differ-ential signaling) that support these sortsof data rates. Therefore, even uncom-pressed video data can be brought on- andoff-chip and processed in real time.Performing real-time video processing,even at HDTV rates, allows you to reduceexternal memory requirements.

Multiple frame stores and data buffers areoften used in current digital TV systemsbecause the video signal processor portionof the design becomes a bottleneck. Usingthe parallel signal processing capabilities ofFPGAs means that smaller, or even single,frame stores can be used, and data bufferscan be eliminated. The limitations of stan-dard DSPs for real-time image processinghas led to the development of speciallydesigned devices. Although performance is

greatly improved, these devices have oftenproved to be too inflexible in all but a nar-row range of applications and can still suf-fer from performance bottlenecks.

FPGAs in Consumer Digital TVs

FPGAs have historically only been foundin expensive professional broadcast sys-tems. However, due to low costs, Spartanseries FPGAs can be used in high volumeconsumer products such as digital TVswhere set-top box functionality is fully

Summer 2002 Xcell Journal 37

Definition Lines/Frame Pixels/Line Aspect Ratios Frame Rates

High (HD) 1080 1920 16:9 23.976p, 24p, 29.97p, 29.97i, 30p, 30i

High (HD) 720 1280 16:9 23.976p, 24p, 29.97p, 30p, 59.94p, 60p

Standard (SD) 480 704 4:3, 16:9 23.976p, 24p, 29.97p, 29.97i, 30p, 30i, 59.94p, 60p

Standard (SD) 480 640 16:9 23.976p, 24p, 29.97p, 29.97i, 30p, 30i, 59.94p, 60p

Table 1 - ATSC broadcast formats

Perspective Digital TV

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Perspective Digital TV

on standard ASSP solutions, you no longerneed to be perceived as providing justanother product in a number of similarlyspecified products in the market. Plus, withFPGAs you can easily modify your designat any time to meet new standards or fixbugs – even after your product is in yourcustomers’ hands.

Time to Market and Time in Market

As well as enhancing DTV systems andincreasing processing performance, FPGAsalso get your products to market quickerand keep them generating more revenueonce they are in the field. Xilinx FPGAsare based on SRAM technology, whichallows you to easily reprogram the deviceduring the development phase. This allowssimple debugging of your system, but alsoenables last minute changes to be made tothe product if needed.

Because FPGAs are reprogrammable,there’s no waiting for development of anew ASSP chipset to support the latestrevision, or a costly and time consumingASIC re-spin if chip development is donein-house. New ways of programmingdevices in the field are giving the addedbenefit of being able to transmit hardwareupdates via the Internet or some othercommunications channel. For example,Xilinx IRL™ (Internet ReconfigurableLogic) technology allows you to auto-matically reconfigure your product,remotely, at any time. The power of thisfeature is highlighted in situations wherefirst-to-market is key, such as in con-sumer set-top boxes. It means that boxescan be shipped to customers without necessarily having a complete design –features can be added later.

Conclusion

FPGAs provide both professional and con-sumer digital broadcast OEMs with real-timeimage processing capabilities that address thesystem requirements of new and emergingvideo applications. Compared to other tech-nologies, FPGAs offer an unrivalled flexibili-ty that enables you to get your products tomarket quickly. Remote field upgradeabilitymeans that systems can be shipped now andfeatures, upgrades, or design fixes added later.

FPGAs also have significant performanceadvantages over conventional digital sig-nal processors and have the added benefitof allowing you to differentiate yourproducts from the many solutions on themarket. Programmable logic is the idealbalance between the flexibility of DSPsand the performance of ASSPs for digitalTV development.

38 Xcell Journal Summer 2002

ADC

SPDIF toI2C

CODEC

Tuner

NTSCVideo

DecoderVSB

ALT

1394PHY

1394MAC

QPSK

QAM

FEC

FEC PIDProcessor

RS 232CInterface

ParallelInterface

SerialInterface

Keyboard/MouseInterface

I/O ControlDescrambler

CPU

MemoryController

GraphicsController

MPEG-2Decoder

AudioMUX

ColorMUX

YUV toRGB

AudioCODEC

AudioCODEC

I2Cto SPDIFCODEC

DAC

DVI(TMDS)

SDRAM

MUX

AudioDecoder

PCI Bridge

MUXSPDIF Audio

RF in

HomeNetwork

Satellite

Cable

Display

Figure 1: System diagram of high-end digital TV set

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by Karen ParnellProduct Marketing Manager, AutomotiveXilinx [email protected]

Researchers at the University of Californiaat San Diego have found a way to “blowup” silicon chips with an electrical signal,according to a recent article, “ExplodingChips Could Foil Laptop Thieves,” inNewScientist.com.

The practical application of self-destroyingchips would be the ability to remotelydisable stolen laptops, cell phones, PDAs, and other devices using wirelesscommunication and containing confiden-tial information.

According to the NewScientist.com articleby Duncan Graham-Rowe, when a deviceis stolen, the victim or service providercould call the device and transmit a self-destruct order to “detonate” a small quanti-ty of gadolinium nitrate. The resultingexplosion would destroy the critical chips,rendering the stolen device useless – andirreparable. Unfortunately, information inthe device memory might remain intact –and that data could sometimes be moreuseful than the device itself.

At Xilinx, we have a better idea. WithIRL™ (Internet Reconfigurable Logic)technology, Comprehensive DesignSecurity, and CoolRunner™-II CPLDs,we can remotely disable up to four differ-ent functions of a stolen device, renderingit inoperable, and with locked-down, tam-perproof data. The beauty of the Xilinx

Technology Focus Comprehensive Security Design

Mobile phone theft is on the rise, but cell phonesequipped with CoolRunner-II CPLDs, InternetReconfigurable Logic, and Comprehensive DesignSecurity could remove the incentive to steal.

Xilinx Technology Can Disable Stolen Cell Phones – and Restore Them When Recovered

Summer 2002 Xcell Journal 39

Xilinx Technology Can Disable Stolen Cell Phones – and Restore Them When RecoveredMobile phone theft is on the rise, but cell phonesequipped with CoolRunner-II CPLDs, InternetReconfigurable Logic, and Comprehensive DesignSecurity could remove the incentive to steal.

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Technology Focus Comprehensive Security Design

solution is the unit is not damaged in anyway – full functionality and data can beeasily restored if the device is recovered.

Whose Problem Is It?

Every three minutes in the UK, a mobilephone is stolen, sometimes at knifepoint.This phenomenon is not just confined tothe UK. It is a global issue and continu-ing to rise. For example, in New SouthWales, in Australia, nearly 40,000 phoneswere stolen between October 1999 andSeptember 2000, a 100% rise over theprevious year.

But what if the phone hardware could bedisabled and effectively rendered useless,then surely the need to steal this much-cov-eted possession would decline. Wouldn’t it?Not necessarily ...

When a mobile phone is stolen, it is rela-tively easy for the phone operator to disablethe Subscriber Identity Module (SIM) cardinside the phone so that calls can not bemade using that particular number. This isof great benefit to the bill player, but this isnot usually why the phone has been stolen.Hackers can install a modified SIM cardthat fools the phone into believing it is aprepaid, “pay-as-you-go” phone withunlimited credits. This allows the phone tobe used indefinitely, free of charge.

What Are Today’s Solutions?

In March 2001, the then-UK HomeSecretary Jack Straw said that he wouldmeet with the world’s mobile phone manu-facturers and police to try to stop the grow-ing threat of street robberies that targetmobile phones. Among the measures con-sidered were the need for general vigilance,discrete usage, knowledge of security codesto lock the phone, and the use of anInternational Mobile Equipment Identifier(IMEI) number.

In addition to the SIM card, digital mobilephones connected to the GSM (GlobalSystem for Mobile Communications) net-work possess an IMEI identifier that isassociated with the handset itself. (GSM isthe dominant cellular system used inEurope and Asia.)

To maintain growth and even sustain currentincome and profits, cellular providers mustintroduce new services that will be attractiveand beneficial to users, who will then neednew types of technically sophisticated hand-sets from the providers’ manufacturers.

In order to capture the market for replace-ment cellular handsets, the next wave ofmobile phone handsets must be smarter,lighter, and last longer on one charge.These new smart phones are reinvigoratingthe flagging mobile market by providingmust-have functionality. The cell phonehas now moved from being just a humblevoice communications device to a com-bined PDA, Internet access device, MP3player, and games console.

For instance, Nokia recently unveiled itslatest “lifestyle” function phone, the 5510.The phone includes an integrated digitalmusic player (with 64 MB memory) forACC (Advanced Audio Coding) and MP3files, a full keyboard to facilitate bettermessaging functionality, and a handful ofembedded games.

Contrary to recent times, the full cost ofsmart phone will be borne by the customer– not subsidized as a free loss leader by awireless service provider, who intends torecover the cost of the hardware with inflat-ed air-time rates.

These smart phones are more costly for theowner and/or network operator to replaceif stolen. This cost risk has made themobile phone companies rethink how theirproducts are designed. The hardware ofhandset must have the built-in capability tobe remotely disabled if stolen – but stilltraceable via GPS (global positioning sys-tem) or similar geographic locator systems.

Once recovered, the phones must be ableto be reactivated to full functionality whenreturned to their owners. A phone withblown-up chips isn’t worth recovering. Tobe a viable consumer product, the disablingcomponent of a stolen cellular phone mustbe small, lightweight, low cost, low power –and capable of fully restoring the function-ality of the phone upon recovery.

Mobile phone owners are encouraged tonote down this number so that if thehandset is stolen, then the operator canbar that specific phone from working ontheir network.

But what about the other networks? Thehandset can theoretically still be used onother networks if a suitable SIM can befound on the black market.

The need, therefore, is to find a way tocompletely disable the handset hardwareon any cellular system – without blowingup the phone itself. Thus, the phone is use-less to the thief, but it can be reactivatedand restored if the phone recovered andreturned to its rightful owner.

This message was again reinforced inJanuary this year with UK ministers consid-ering whether to introduce legislation thatwill force networks to introduce the afore-mentioned anti-theft measures, but, theystipulated, this would be “a last resort.”

What Is Tomorrow’s Solution?

The average mobile phone thief is becom-ing more discerning, because in the blackmarket, the newer “smart phones” arebecoming the target of choice. To date, thegrowth of mobile communications hasbeen fuelled by voice calls, but voice isbecoming a saturated market, with increas-ing competition forcing a decline in aver-age revenue per user.

40 Xcell Journal Summer 2002

Page 41: Xcell Journal: Issue 43

Technology Focus Comprehensive Security Design

The Xilinx Solution

With typical forwardthinking, Xilinx hasalready developed thetools to combat phonetheft – IRL technology,Comprehensive SecurityDesign, and theCoolRunner-II CPLD.

If a CoolRunner-IICPLD were used to perform the keypadinterfacing in a handset,then if it were stolen, thekeypad could be dis-abled remotely by themobile phone operatorusing Xilinx IRL technology (Figure 1).When returned to itsowner, the handsetcould then be repro-grammed again via anIRL bitstream to enablethe keypad again. (IRL technology enablesthe remote upgrading or programmingprocess of CPLD or FPGA hardware overany kind of network, including wireless.)

It is virtually impossible for theCoolRunner-II device (Figure 2) to bereactivated or for data to be retrievedfrom the handset by the thief or hacker.Xilinx Comprehensive Design Securityprovides an unprecedented four aspects ofdesign security:

• Prevention of accidental/purposeful over-writing or read back of the configurationpattern

• Blocking visual or electrical detection ofthe configuration pattern

• Automatic device lockdown in responseto electrical or laser tampering

• Physical implementation of the protec-tion scheme that is virtually undetectable.

These design security aspects are not onlyburied within the layers of the device, butthey are also scattered throughout the die

to make their detection impossible.Designers can now design with the knowl-edge they are using the best design securityavailable on any CPLD in the industry.

The enhanced features of CoolRunner-IIalso elevate the CPLD from an ASIC fix to

that of an ASIC replacement. New featuresinclude clock doubling and clock divisionfor lower power consumption, various I/Ostandards support for level translation,selectable Schmitt trigger inputs to solvesignal integrity challenges, and bus hold.

Conclusion

By utilizing a combination of IRL technol-ogy, Comprehensive Security Design, andultra-low power CoolRunner-II CPLDs toremotely disable the hardware within astolen mobile phone, phone operators andmanufacturers can remove the incentive fortheft – and improve the odds of recoverywith geographic locator technology.

Furthermore, the triple-threat securitytechnology of Xilinx-protected productscan be extended to any consumer appli-ance, including laptops, set-top boxes forcable TV, PDAs, and other devices withwireless or wired network connectivity. Asthe word gets out, consumers will look forthe Xilinx brand in the products they buy– and thieves will look the other way.

Summer 2002 Xcell Journal 41

RFQPSK

Modulator

BluetoothModule

LCDModule

KeyMatrix

Keyboard& DisplayInterface

FLASHMemory

Xilinx CPU Non-XilinxMemory Mixed signal

FLASHAdapter I/OA Controller

PowerManagement

CPU Core(ARM Processor)

HCIBridge

DSP Voice CodecSpeaker

Amp

PowerSupply

I/OAModule

RFCodec

Multiple security mechanisms

Can be enabled and disabled remotelyif the handset is reported stolen

Remote deactivation and reactivation over wireless

and wired networks

Legend

• Different mechanisms disabled• Buried interconnects

• Multiple security signals• Scattered and layered

Figure 1 - Mobile phone block diagram with Xilinx Comprehensive Design Security

Figure 2 - Multiple security functions embedded in

CoolRunner-II CPLD

Page 42: Xcell Journal: Issue 43

by Amit DhirManager, Strategic SolutionsOptical/Wired NetworksXilinx, [email protected]

The worldwide VPN (virtual private network) market will reach $32 billion by2003, up from $3 billion in 2000, accord-ing to Infonetics Research. VPNs providehighly secure, temporary, point-to-point“tunnels” through the public Internet.These tunnels are created on demand andare removed when a session ends. VPNsoffer you the following advantages:

• Lower operating costs

• Extendable networks to respond tochanging business demands

• Anywhere, anytime access to e-mail,intranet, and other shared applications.

Essentially, VPNs are private networksdeployed over public networks that providesimilar levels of privacy, security, quality ofservice (QoS), reliability, prioritization,end-to-end management, and manageabili-ty as local area networks (LANs).

With Spartan™-IIE FPGAs, the right soft-ware, and Internet gateways, you get securedata encryption and packet authenticationeven over the wide-open public Internet.

Furthermore, compared to leased line net-works, Xilinx-enabled VPNs are:

• Simpler to set up and easier to administer

• More dynamic and extendable

• Less expensive to create and deploy

• More accessible anywhere, anytime.

Technology Focus Networking

42 Xcell Journal Summer 2002

Spartan-IIE FPGA solutions can help you to customize your virtual private network for highest performance, greatest security, and lowest cost.

Customize VirtualPrivate Networkswith Spartan-IIE FPGA Solutions

Page 43: Xcell Journal: Issue 43

Technology Focus Networking

How Do VPNs Work?

VPNs use the band-width of public, packet-routed networks – typi-cally the Internet or aservice provider’s back-bone network (InternetProtocol, frame relay, or ATM). Corporationshave company head-quarters, remote offices,mobile workers, inde-pendent contractors,and business partnersconnected to a networkservice provider’s localpoints of presence(POP). Remote usersand the company’sLAN(s) connect to theprovider’s networkusing dial-up, DSL,cable, ISDN, T1/T3,and wireless.

The key to VPNs is “tunneling” – the practiceof repackaging data from one network toanother. At the originating end of a tunneledtransmission, a data packet is “wrapped” orencapsulated with new header informationthat allows an intermediary network to reor-ganize and deliver the packet. At the termi-nating end, the terminal protocol “wrapper”is removed, and the original packet is deliv-ered to the destination.

Tunneling does not ensure privacy or securi-ty – just delivery. To secure a tunneled trans-mission against interception and tampering,all traffic must be encrypted. Therefore,VPNs must include additional functionalfeatures to enhance transmission security,ensure quality of service (QoS), and protectthe VPN perimeter with a firewall.

Security and privacy features include tunnel-ing itself, data encryption, packet authenti-cation, firewalls, and user identification.Tunneling uses IPSec (Internet ProtocolSecurity), and encryption uses DES (DataEncryption Standard), Triple DES, andDiffie-Hellman cryptographic algorithms.

VPN QoS and bandwidth managementmake possible delivery of high transmission

cores provide flexibilitywithout compromisingcost or performance –and reducing time tomarket.

Implementing encryp-tion in programmablehardware significantlyimproves performanceover software solutions.By using parallel com-puting, FPGAs encodeand decode larger trans-mission blocks moreeffectively. The encrypt-ed key can be changedwithin the FPGA fabric,and if a key is ever broken, the XilinxSpartan-IIE solution canbe reconfigured instantlywith new algorithms.

Spartan-IIE FPGAs give you the power toto choose and optimize just the right fea-ture set and intellectual property cores youneed to implement your designs. You canintegrate functionality, such as PCI, mem-ory controllers, and other components,within the Spartan-IIE device to customizeyour product and reduce costs. This flexi-bility comes at a significantly lower costcompared to ASSPs (application specificstandard products).

Conclusion

VPNs improve the productivity of remoteworkers and hence, their organizations.VPNs promote flexible work styles,extend workplaces beyond office walls,connect remote offices with the headquar-ters, and foster competitive advantageswith strategic partners – all at reducedcosts, compared to other options.

Using the Internet and/or service providerbackbones to transfer confidential datarequires state-of-the-art encryption andprivacy solutions. Spartan-IIE FPGA-based encryption and security give you thescalability and flexibility you need toimplement the perfect virtual private net-work for your enterprise.

quality, mission-critical applications (suchas financial reporting and order process-ing), and real-time voice/video applications(such as distance learning and videoconfer-encing). Packets are tagged with priorityand time sensitivity markers to allow trafficto be routed based on delivery priorities.Tagged packets take precedence over bandwidth-consuming applications (suchas Web surfing).

Network management features simplifythe addition, deletion, or changing ofusers; software upgrades; and policy management for security and QoS assur-ance. These features make scalability andinteroperability possible.

Xilinx Spartan-IIE FPGAs – ProvidingEncryption with Flexibility

VPN gateways secure Internet-based com-munication, perform user identification,authenticate data integrity and confidentiali-ty, and reject all non-tunneled IPSec traffic.Encryption and authentication lie at theheart of VPN products, and speeding up theprocessing of encryption algorithms booststhe performance and scale of VPN solutions.

Spartan-IIE FPGAs programmed withproprietary and/or standard encryption

Summer 2002 Xcell Journal 43

Page 44: Xcell Journal: Issue 43

by Mamoon Hamid, ManagerStrategic Solutions, Consumer/Home NetworkingXilinx, [email protected]

Although Bluetooth™ wireless technologypromises to be a ubiquitous, low cost solu-tion – perfect for a very wide range of datacommunication – there are two majorareas that further need to be addressed:data security and data integrity. These twoareas will serve to limit range of applica-tions where Bluetooth can be deployed.

Bluetooth Data Security

The Bluetooth specification has defined aset of security mechanisms to provide a verybasic level of protection for short-rangewireless communication. Each Bluetoothdevice is required to implement key man-agement, authentication, and encryption.The Bluetooth Generic Access Profile(GAP) divides security into three differentmodes. In addition, Bluetooth technologyimplements a frequency-hopping schemethat also serves as an additional securitymeasure against eavesdroppers.

Perspective Bluetooth Security

Programmable logic is used to design wireless products that address the needs of data security and integrity.

Leveraging Bluetooth Technology to Build Secure and Robust Wireless Communications

44 Xcell Journal Summer 2002

Leveraging Bluetooth Technology to Build Secure and Robust Wireless Communications

Page 45: Xcell Journal: Issue 43

Perspective Bluetooth Security

Key Management

Bluetooth security uses several differentkeys in higher layer software to ensuresecure transmissions. Figure 1 shows ablock diagram for key management.

Device Authentication

Authentication is a critical security com-ponent of Bluetooth systems, allowing adomain of trust between an ad-hoc net-work of Bluetooth devices. Bluetoothauthentication is based on a challenge-response scheme that secures the connec-tion between two devices. When a deviceis not authenticated, a period of time mustpass before a new attempt for authentica-tion can be made.

Encryption

Bluetooth Encryption is used to ensurethe privacy of a connection. Prior toencryption, an authenticated link mustbe in place. Encryption scrambles thedata payload of Bluetooth packets usingan 8-bit to 128-bit key, however, theBluetooth access code and the packetheader are never encrypted. Payloadencryption depends on the strength ofencryption desired and geographical reg-ulations in the countries in which theproduct is being deployed.

Physical Layer Data Security – FrequencyHopping Spread Spectrum

In addition to the other security featuresbuilt into Bluetooth equipment, the fre-quency-hopping scheme employed forBluetooth communication (FrequencyHopping Spread Spectrum or FHSS) alsoserves as mechanism to make eavesdrop-ping extremely difficult.

The Bluetooth radio operates in the 2.4 GHzISM band. In North America and most ofEurope, Bluetooth radio uses a frequencyrange from 2.402 GHz to 2.480 GHz, with this band divided into 79, 1-MHz subchannels. In frequency hopping, adata signal is modulated with a narrow-band carrier signal that hops from fre-quency to frequency as a function of time.

Summer 2002 Xcell Journal 45

Figure 1 - Bluetooth key management

• Automatic Repeat reQuest (ARQ) –Used to transmit and retransmit datapackets, among other things, until thereception of those packets is acknowl-edged from the recipient. The recipientreturns the acknowledgement in theheader sent back to the sender of theinitial packet.

Data Whitening

All the header and payload information isscrambled with data whitening bits beforetransmission occurs, so that redundant 0’sor 1’s are eliminated from the transmis-sions. This can be a problem with analogdata signals received by the basebandprocessor because they need to be classifiedas 0 or 1. Because there is no referencepoint such as DC for these signals, youmust rely on the last few signal transmis-sions for calibration purposes. Any longsequential string of 0’s or 1’s may cause cal-ibration to fail. Hence data whitening isused to scramble these signals so that theprobability of long strings of 0’s or 1’s issignificantly reduced.

Bluetooth radio employs a hoppingsequence of 1600 hops per second.

FHSS relies on frequency diversity to com-bat interference. If the radio encountersinterference on one frequency, the radiowill retransmit the signal on a subsequenthop on another frequency. The aggregateinterference will be very low, resulting inlittle or no bit errors.

Bluetooth Data Integrity – ForwardError Correction (FEC)

Forward error correction reduces the num-ber of retransmissions for a data payload.However, the drawback is that it cantremendously reduce the achievablethroughput. There are three types of for-ward error correction that are implementedby Bluetooth technology:

• 1/3 rate FEC – Each header bit is repeat-ed three times. It is primarily used formasking errors in the header, which con-tains vital link information.

• 2/3 rate FEC – Every ten informationbits are encoded into a 15-bit code word.This type of error correction is primarilyused for sending data packets in the leastvulnerable way.

Page 46: Xcell Journal: Issue 43

Perspective Bluetooth Security

Programmable Solutions for Advanced Data Security

Bluetooth data security is inadequate formost applications where a high level of con-fidentiality is of the utmost importance. Itseems to be adequate for smaller applica-tions, but any sensitive or otherwise prob-lematic data should not be transmitted viaBluetooth. For example, the encryptionscheme used in Bluetooth shows someweaknesses. In one possible scenario, anattacker can obtain the encryption key thatsecures communication between two devicesand can then eavesdrop on their messages.The attacker also could claim to be one ofthe devices and insert false messages. Oneway to avoid this, Lucent Technologies says,is for the users to employ lengthy personalidentification numbers to increase the diffi-culty of discovering the encryption keys.

This again involves manually entering per-sonal identification numbers (PINs). Thiscan quickly become a nuisance; it is a tediousprocess to secure the connection.

Another way to overcome these security issueswould be to use a more robust encryptionalgorithm, such as Data Encryption Standard(DES), or even Triple DES, or AdvancedEncryption Standard (AES), instead of thestream cipher E0 algorithm. DES is a blockcipher, which essentially means that thecipher encrypts blocks of data all at once andthen proceeds to the next block. In DES, theoriginal message is divided into fixed lengthblocks of 64 bits, enciphered using a 56-bitsecret key into a 64-bit encrypted message bymeans of permutation and substitution. Ablock diagram of DES is shown in Figure 2.

Unlike the Bluetooth stream cipher algo-rithm, it has been mathematically proved

that the block ciphers are completelysecure. The DES block cipher is highlyrandom, nonlinear, and produces encrypt-ed text that functionally depends on everybit of the original message and the key.The DES has more than 72 quadrillion(72 x 1015) possible encryption keys thatcan be used. For each given message, thekey is chosen at random, from among thisenormous number of keys. The DES algo-rithm is widely used and is considered verydependable, however, an even more securevariant, Triple DES, which applies DESthree times with different keys, in succes-sion is also available.

Both of these encryption algorithms –DES and Triple DES – can be imple-mented using low-cost programmablelogic devices and readily available intel-lectual property (IP) for a higher level ofencryption. Today, you can buy 100,000system gate Spartan™ FPGAs in volume,off the shelf, and ready to go, for just $10per unit. These FPGAs also allow addi-tional functionality, such as advancederror correction, to be added to a designas well. Hence, these devices enable dras-tic system-level cost reductions.

Another encryption algorithm that is gain-ing rapid acceptance (due its superiorrobustness and optimal implementation inhardware and software) is AES, also calledRijndael. AES is a 128-bit block cipherwith selectable 128, 192, or 256-bit keylengths. AES encryption and decryptionblocks can be implemented individuallyor as a whole in programmable logic. Inaddition, the key generator can be para-meterized based on key length. A pro-grammable logic-based implementation ismodular and also allows you to choose ahardware implementation based on thelevel of security desired. Shown in Figure3 is a block diagram of AES. The cost ona silicon basis for this encryption corewith a 128-bit key generator is less than $2 today. Variations can be imple-mented depending on the end applicationsecurity requirements.

46 Xcell Journal Summer 2002

ExpansionPermutation

P Permutation

Final Permutation

Final Permutation

Left reg Right reg

S Boxes

DOUT [63:0]

KEY [63:0]

DIN [63:0]

KeyProcessor

ControllingState

Machine

GO

RES_IN

CLK

E_DREADY

Figure 2 - X_DES cryptoprocessor block

diagram (courtesy of: InSilicon Corp.)

Page 47: Xcell Journal: Issue 43

Perspective Bluetooth Security

Software-based encryption solutions offerhigh flexibility, but low performance.Hardware-based encryption solutions pro-vide high performance, yet provide verylittle flexibility once designed. An encryp-tion solution based on programmablelogic provides the best of both worlds –you get high levels of flexibility as well ashigh performance.

A more robust encryption algorithm willallow Bluetooth technology to be safelydeployed in a wide range of applicationswhere security is of the utmost importance.This includes:

• Electronic financial transactions such as ATM or Smart Cards

• Secure e-commerce transactions

• Secure office communications

• Secure video surveillance system

• Digital set-top boxes

• HDTV

• Other consumer electronics devices.

Programmable Solutions for Advanced Data Integrity

The Bluetooth specification defines meas-ures that are effective for preventing unin-tentional errors from being transmittedusing data whitening and error checking.However, a particular stream of data, whichwould consistently cause transmissionerrors, is theoretically possible, but highlyunlikely in normal transactions.

There is still a risk of error-prone transmis-sions in more hostile environments, such as industrial locations, office buildings, airports, and metropolitan public trans-portation. In locations like these, noise andinterference from other multiple Bluetoothdevices, wireless networks, phone systems,or other electronic devices operating on thesame frequency band can cause problems.Again, programmable logic and advancederror-correction IP can be used to facilitateerror-free communication. A robust for-ward error correction technique, such asturbo convolution coding, is an alternativefor a hostile communications environment.

Turbo coding is an advanced forwarderror correction algorithm. It is a stan-dard component in third-generation(3G) wireless communication systems,like those employing wideband codedivision multiple access. The principle ofturbo coding is that the encoder gener-ates a data stream consisting of two inde-pendently encoded data streams and asingle un-encoded data stream. The twoparity streams are weakly correlated dueto the interleaving. In the turbo decoder,the two parity streams are separatelydecoded with soft decision outputs,referred to as “extrinsic” information.

The strength of the turbo decodingresults from the sharing of the extrinsicinformation during a number of itera-tions. The extrinsic information is passedfrom one parity decoding step to theother, from one iteration to the other. IPfor such a turbo convolutional codec isreadily available and is easily implement-ed on low cost programmable logicdevices such as the Xilinx Spartan series.This solution can ensure the integrity ofBluetooth data transmissions in hostileand error-prone environments.

Conclusion

Bluetooth wireless technology is chang-ing the way we communicate. However,it still faces challenges on the level of datasecurity and integrity for secure applica-tions. Low-cost programmable logicdevices are ideally suited for advanceddata security and integrity implementa-tion. This will be a necessity for thosewho wish to implement higher levels ofsecurity into applications where securityis of the utmost importance. Also, appli-cations that will be in operation in hos-tile environments will benefit from a cus-tomizable programmable logic imple-mentation. Programmable logic is anexcellent solution for integrating customBluetooth implementations, such asthese, into embedded systems.

Summer 2002 Xcell Journal 47

Helion AES Core

Helion AES Roundkey Core

encrypt request

plaintext in

key-size select encrypt status

asynch reset

master clock

various controland status

round keys

master clock

128-bits

cyphertext out

128-bits

key in

128/192/256-bits

Figure 3 - AES encryption core (Courtesy of: Helion Technology)

Page 48: Xcell Journal: Issue 43

by Amit Dhir, Manager Strategic Solutions, Optical/Wired NetworksXilinx, [email protected]

The consumer world is buzzing with newsand standards to network home appliances,PCs, peripherals, and other consumerdevices. A number of technologies arevying to be the next technology to networkall appliances in the home. Some of these22 technologies include HomeRF™,Bluetooth™, HiperLAN2, IEEE 802.11,Ethernet, HomePNA™, USB 2.0, andIEEE 1394.

Although each technology presents uniquepros and cons, the technologies that requirewires do provide one critical capability –the ability to deliver reliable high-speedvoice, data, and video transfer. Home net-working is incomplete without the abilityto transfer voice, data, and video together.

Ethernet, USB 1.1/2.0, and IEEE 1394 topthe list of these “new wires” technologies:

• Ethernet is a low-cost technology, whichuses a protocol ideal for data traffic.

• USB 1.1 and its more recent specificationUSB 2.0 are primarily PC-centric – net-working PCs and PC peripherals.

• IEEE 1394 is the technology that holdsthe most promise to be the perfect homenetworking technology that will networkaudio, video, and PC equipment.

IEEE 1394 Backgrounder

The move from analog to digital technologyhas enabled the sharing of video, Internet,data, and audio. Consumers are constantlysearching for faster, cheaper, more reli-able, and easier ways of transferring andsharing information. While informationsharing has been happening at the enter-prise level for the last few years, the homeis just seeing its introduction. This phe-nomenon, known as home networking,allows the interconnection of PCs, con-sumer equipment, and communications,and the distribution of infotainmentamong these appliances.

Technology Focus Home Networking

Home networking promises to be one of the hottest new markets in consumer electronics – and the combination of IEEE 1394 and HAVi technologies show the most promise to become the standard for home networking.

IEEE 1394 and HAVi Are the LeadingTechnologies for WiredHome Networking

48 Xcell Journal Summer 2002

Page 49: Xcell Journal: Issue 43

Technology Focus Home Networking

The convergence of voice, data, and videoin the home will happen only when seam-less, high-speed communication becomesreadily available. IEEE 1394 is one suchinterconnection technology that willenable connection of these devicesthroughout the home. IEEE 1394, alsoknown as 1394, FireWire™ or iLink™, isa versatile, high-speed, and inexpensivemethod of interconnecting a variety of con-sumer electronic devices (such as digitalTV, set-top boxes, and home theater equip-ment), PCs, and PC peripherals (such asscanners and printers).

The FireWire bus standard, originally cre-ated by Apple Computer, was born out ofthe need for a low cost, consumer-orientedconnection between digital-videorecorders and PCs. FireWire technologygrew into a standard – called IEEE 1394 –for low cost, high data rate connections. In1994, the 1394 Trade Association (1394ta)was formed to support and promote theadoption of the IEEE 1394 standard. In1995, the 1394ta formally released the

have fair access to the bus. As its physicalmedia, 1394 requires optical fiber or high-grade copper wiring between the appli-ances. The 1394 physical layer is physicallypoint-to-point and logically a bus (eachnode is a repeater).

The physical layer transmits the unstruc-tured, raw, bit stream over a physical medi-um, and describes the electrical, mechani-cal, and functional interface to the carrier.It provides the linking to the upper sessionsvia signaling and the initialization and arbi-tration services necessary to assure thatonly one node at a time is sending data.The physical layer of the 1394 protocolincludes electrical signaling, mechanicalconnectors and cabling, arbitration mecha-nisms, serial coding and decoding of thedata being transferred or received, andtransfer speed detection.

Link Layer

The link layer takes the raw data from thephysical layer and formats it into twotypes of recognizable 1394 packets –asynchronous and isochronous.

Asynchronous data transfer is the conven-tional transmit-acknowledgment protocoland puts the emphasis on guaranteeddelivery of data, with less emphasis onguaranteed timing.

Isochronous data transfer is a real-timeguaranteed-bandwidth protocol for just-in-time delivery of information. It puts theemphasis on the guaranteed timing of thedata and less emphasis on delivery.Isochronous transfers are always broadcastin a one-to-one or one-to-many fashion.No error correction or retransmission isavailable for isochronous transfers.

Transaction Layer

The third layer in the IEEE 1394 protocolis called the transaction layer and is respon-sible for managing the commands that areexecuted across the home network. It sup-ports the asynchronous protocol write,read, and lock commands. A write sendsdata from the originator to the receiver, anda read returns the data to the originator.

1394 specification. Further revisions like1394a in 1998 and 1394b in 1999, wereintroduced. The 1394b standard is fullybackward compatible with the current1394 and 1394a specifications. Each revi-sion of 1394 has added features, perform-ance, and capabilities.

IEEE 1394 Architecture

The components that form a 1394-basedhome network include the actual protocolitself, the cabling system, and the architec-tural design of the network. Similar toother high-speed networking systems,IEEE 1394 adopts a layered approach totransmitting data across a physical medi-um. The four layers used by the IEEE 1394protocol are shown in Figure 1.

Physical Layer

The physical layer provides the electricaland mechanical connection between the1394 appliance (connector) and the cableitself. Besides the actual data transmissionand reception tasks, the physical layer alsoprovides arbitration to insure all devices

Summer 2002 Xcell Journal 49

Serial BusManagement

Serial Soft API

Transaction Layer

Link Layer (Cycle control, packettransmitter, packet receiver)

Physical Layer (Encode/Decode,Arbitration, Media Interface)

IEEE 1394Physical Interface

Configuration &Error Control

Read, Write, Lock

Packets

Symbols

Electrical Signal &Mechanical Interface

IsochronousChannels

Figure 1 - IEEE 1394 protocol stack

Page 50: Xcell Journal: Issue 43

Technology Focus Home Networking

Serial Bus Management

The fourth and final logical grouping offunctions is responsible for the overall con-figuration control of the serial bus. It con-trols the serial bus in the form of optimiz-ing arbitration timing, guarantee of ade-quate electrical power for all devices on thebus, assignment of which 1394 device isthe cycle master, assignment of isochronouschannel ID, and basic notification oferrors. The bus management is built uponIEEE 1212 standard register architecture.

Benefits of IEEE 1394

• Broad industry and standards bodies sup-port

• Low cost

• High and scalable speeds

• Plug and play

• Nonproprietary.

IEEE 1394 is an enabling technology forconnecting multimedia devices, such as:

• Digital camcorders and VCRs

• Satellite modems

• Set-top boxes

• Digital TV

• PCs

• DVD players

• Gaming consoles

• Home theater

• Musical synthesizers/samplers with digi-tal audio capabilities

– Digital audio tape (DAT) recorders

– Mixers

– Hard-disk recorders

• Video editors.

HAVi Backgrounder

HAVi (Home Audio/Video interoperability)is an industry initiative started by Sony andPhilips in 1996. Since then six other com-panies have joined – Thomson, Hitachi,Toshiba, Matsushita, Sharp, and Grundig.

HAVi adopted the IEEE 1394 bus stan-dard as the underlying network technologyfor the HAVi protocols and for the trans-port of real-time audio/video (A/V)streams. Using 1394 as the bus standard(shown in Figure 2) provides benefits, such

as high-speed, flexible connectivity, and theability to link up to 63 appliances together.No other interconnection technologies,such as wireless, HomePlug™, HomePNA,and USB, are capable of distributing high-speed video applications.

The HAVi middleware architecture is anopen (nonproprietary), lightweight, andplatform-independent specification thatallows development of home networkingapplications. It does not, however, addresshome networking functions such as con-trolling the lights or monitoring the cli-mate within the house. HAVi specificallyfocuses on the transfer of digital A/V con-tent between in-home digital appliances,as well as the processing (rendering,recording, and playback) of this contentby HAVi-enabled appliances.

The HAVi middleware system is independ-ent of any particular operating system orCPU and can be implemented on a range ofhardware platforms, including digital prod-ucts such as cable modems, set-top boxes,integrated TVs, Internet TVs, or intelligentstorage appliances for A/V content.

Today in the world of analog consumerelectronic appliances, there exist a numberof proprietary solutions for interoperabilityamong appliances from one brand or ven-

dor. In the upcoming world of digital tech-nologies, HAVi extends this networkingmodel by allowing communication amongconsumer electronic appliances from mul-tiple brands in the home. The HAVi mid-dleware architecture specifies a set of APIs

(application programming interfaces) thatallow consumer electronic manufacturersand software engineering companies todevelop applications for IEEE 1394-basedhome networks.

One of the main reasons HAVi selectedIEEE 1394 over other transmission proto-cols is because of its support for isochro-nous communications. HAVi comprisessoftware elements that facilitate the interop-erability among different brands of enter-tainment appliances within the house.Interoperability is an industry term thatrefers to the ability of an application run-ning on an in-home appliance to detect anduse the functionality of other appliancesthat are connected to the home network.

The underlying structure for a home net-work based on HAVi technologies is apeer-to-peer network, where all appliancescan talk to and interact with each other.HAVi has been designed to allow theincremental addition of new appliances,which will most likely result in a numberof interconnected clusters of appliances.Typically, there will be several clusters ofnetworks in the home, with one per flooror per room. Over time these clusters willbe connected with technologies such as1394 long or wireless 1394.

50 Xcell Journal Summer 2002

HAVi

IEEE 1394 Link Layer Controller

IEEE 1394 PHY

Figure 2 - Simplistic figure showing HAVi using IEEE 1394 bus standard

Page 51: Xcell Journal: Issue 43

Technology Focus Home Networking

Benefits of HAVi

A HAVi-compliant appliance offers a num-ber of advantages, which include:

• Automatic detection

• Automatic registration of added appliance to the HAVi network

• Automatic software upgrades

• Manageability

• Brand independence

• Hot plug-and-play

• Legacy appliance support.

Xilinx Programmable Solutions Enable IEEE 1394/HAVi Products

The IEEE 1394 technology consists of aphysical layer for encoding-decoding,arbitration, a medium interface, and pro-vides an electrical signal and mechanicalinterface. The link layer provides cyclecontrol, packet transmits, packet receives,CRC, and provides the host and applica-tion interface.

As shown in Figure 3, programmable logicsolutions provide complete link layer func-tionality with the ability to connect to mul-tiple interfaces such as PCI, USB, and pro-prietary audio-video buses. The advantageof programmability is realized when thereis a proprietary application interface.However, in an IEEE 1394 system, theSpartan™-II FPGA provides system inter-face and other ASSP functionalities.

With the 1394 specification still continu-ing to evolve, having the link layer con-troller programmed in a FPGA providesthe ability to reprogram the FPGA with thelatest 1394 revision.

Supporting different products requires thesupport and interface to different interfaces.For example, using 1394 in a PC requiresan interface to PCI, PCMCIA, and otherproprietary interfaces. Programmable solu-tions are ideal for providing this interface,because developing ASSPs for these applica-tions is relatively expensive. Also, thedecreasing cost of programmable logic solu-tions makes them ideal for IEEE 1394 andHAVi-based products.

Conclusion

The digital home continues to evolve andsmarter appliances continue to populatethe home. These smarter appliances andthe need for sharing broadband data,voice, and video are pushing the need forhome networking. Although several tech-nologies exist, the technology that pro-vides high-speed and reliable delivery ofvoice, data, and video will win.

IEEE 1394 is one such home networkingtechnology that provides both high-speedand reliable delivery. The proliferation of1394 as the A/V standard will be acceler-ated through the use of HAVi as its mid-dleware solution to connect disparatedevices, thus providing a complete solu-tion to the consumer.

However, the specification continues toevolve and 1394 products need to coexistwith other home networking and systeminterface technologies, thus requiring prod-ucts that interface between these technolo-gies. With the continuing reduction in pricesof programmable logic solutions, these areideal solutions to provide interfaces between1394 and other technologies such as PCI,USB, PCI-X, SCSI, and HomePNA.

Summer 2002 Xcell Journal 51

Figure 3 - The IEEE 1394 physical layer

and link layer controller with a host interface

Page 52: Xcell Journal: Issue 43

by Karen Parnell, ManagerAutomotive Product Marketing Xilinx, [email protected]

Today’s consumers demand the comforts ofhome and the productivity of the officewhen they drive. They also want the latest ininformation and safety systems for their cars.The resulting convergence requires interfacestandards and protocols to interconnect andinteroperate. These standards and protocolsare still emerging, and will get even morecomplicated before being standardized. Theresult is a manufacturing dilemma. Shouldmanufacturers make an educated guess nowas to which standard will prevail, and riskmaking the wrong choice? Or should theywait for the standards to be fixed, and riskgetting left behind?

Xilinx has the answer. With Xilinx IQ pro-grammable logic solutions for automotiveapplications, manufacturers can win thetime-to-market battle risk free by using theability to reconfigure their products toaccommodate any standard – past, present,or future. Reconfigurable logic in produc-tion allows manufacturers to reconfigurethe units in-car to implement new hard-ware-based features. Xilinx high-volumeIQ FPGA and CPLD devices are cost-effective solutions that retain the tradition-al PLD time to market advantage. As aresult, many leading telematics and info-tainment product manufacturers useXilinx programmable logic devices. Thesemanufacturers recognize the added flexi-bility and time to market benefits that pro-grammable logic solutions provide.

Driving Your Office

Information Age professionals need to beable to work from wherever they happen tobe – from home, from hotel rooms, fromairports, from 36,000 feet over the Atlantic.They need to take their offices with them.

The laptop computer was a critical step inthe development of offices-on-the-go, butnow workers are demanding even more.One result has been the in-car office. Theautomobile is no longer just a way to getfrom Point A to Point B. Now it can includeGPS navigation with intelligent route find-ing, integrated PDA functions, built-inmobile communications, entertainment sys-tems, and even in-dash personal computers.

Automotive electronic designers face thesame challenges as designers of consumer

Technology Focus Automotive

Xilinx products and technology are putting office technology and functionality into next-generation automobiles.

You Can Take It with You: On the Road with Xilinx

52 Xcell Journal Summer 2002

Page 53: Xcell Journal: Issue 43

Technology Focus Automotive

equipment. They must grapple with time tomarket pressures, cost restrictions, and aprofusion of new standards and protocols.They also face added challenges like a con-strained design area, and the need for a sim-ple user interface so drivers can keep theireyes on the road.

As one example of the new technology,the latest BMW 7 Series automobilesallow the driver to operate the car’s heat-ing and air conditioning, entertainmentsystems, wireless communicationsdevices, navigation instruments, and PCapplications, all on a single display, bymeans of a joy-stick type of device.

Xilinx programmable logic devices enableautomotive designers to provide their cus-tomers with a more informative, productive,safe, and entertaining in-car environment.By using the flexibility, time to marketadvantage, and after-sale reconfigurability ofXilinx devices, manufacturers can be first tomarket and best in class long after the sale.

The Automotive Multimedia Platform

As more information and entertainmentsystems are added to automobiles, there’san inevitable conflict among the bewilder-ing array of standards and protocols beingtested, including Bluetooth™, BlueCAN,MOST (media-oriented system transport),FireWire™, CAN (controller area net-

PDAs, portable PCs, MP3 players, and otherpersonal portable electronic equipment.

As in-car and consumer functions converge –and new automotive and consumer stan-dards and protocols emerge – designers havebegun to prototype multimedia platformsthat can provide as much, or as little, func-tionality as required. The best way to createsuch multimedia platforms is to designreconfigurable hardware. Engineers can pro-gram reconfigurable hardware late in theproduction flow to provide custom function-ality on a standard hardware platform. At thesame time, they can configure the hardwareto accommodate new standards.

Figure 1 shows the automotive multimediaplatform design approach. This conceptallows upgrades throughout the life of thecar. Designers can implement theseupgrades remotely by means of wirelesscommunications and Internet connectivity.Xilinx Internet Reconfigurable Logic(IRL™) technology makes this remoteupgrading process possible.

With Xilinx IRL technology, designers canupgrade, modify, and fix systems long afterthe car leaves the dealership. For example, anengineer could remotely add a new MP3player to an in-car multimedia system, orupgrade the system with the latest protocol.This same technology can even disable themultimedia unit if it is stolen, then re-enableit when it is returned to the rightful owner.

Multimedia System Design Flow Using FPGAs

The multimedia platform should ideally bebased on one Human Machine Interface(HMI). This HMI allows the user to accessall functions by means of a touch screen. Ifthe functions are implemented in softwareand reconfigurable hardware, the manufac-turer or dealer can upgrade the system evenafter the buyer has driven the car away.

The new way of developing in-car systems isto prototype with FPGAs in a generic devel-opment environment. The designer can develop the elements quickly and easily with-out fixing specifications. This initial prototyp-ing phase can be realized using Virtex™-IIPlatform FPGAs. At this early stage, thedesigner can try, test, and debug the differentstandards, protocols, and functions by usingthe headroom provided by a large FPGA.

work), TTP (time triggered protocol), andFlex Ray™ technologies.

Designers of in-car multimedia systemsmay soon have to provide for traffic infor-mation systems, Internet and Web access,electronic game consoles, MPEG musicdownload capability, digital radio recep-tion, and mobile commerce services.

Designers must ensure that the car’s multi-media system can communicate with theautomobile’s other devices. For example, thecar should automatically detect a new mobilephone and connect it seamlessly to the car’scommunications network. This demand forautomatic connectivity may soon extend to

Summer 2002 Xcell Journal 53

Multimedia Platform Design Approach

Prototyping• Architecture choice

• Components

• Prototyping

• Technology evaluation

• Pretesting

• Generic software services

• Changing specifications and protocols

Production• Freeze specifications

• Single platform, multiplemanufacturing variations

• Design customer-specificservices

• Printed circuit boards

• Configuration

• Mechanics

Application• Flexible and

field-upgradeable after the sale

• Customizable look and feel

• Add new features and functions

Figure 1 - Automotive multimedia platform design approach

Figure 2 - Acunia automotive development platform with Xilinx Spartan-II FPGA and

CoolRunner™ CPLD onboard

Page 54: Xcell Journal: Issue 43

Technology Focus Automotive

54 Xcell Journal Summer 2002

As the design firms up, the specifications arefrozen. The designer can then select the spe-cific standard, protocol, or function from themany tested. This move from prototype toproduction enables the designer to optimizethe design and fit it into smaller, lower costFPGAs, such as Spartan™-IIE programmablelogic devices. This migration from Virtex-II™to Spartan-IIE FPGAs still allows for futuresystem upgradability via IRL connectivity.

Once the device is in production, the engi-neer can use the FPGA as an aid in totalprinted circuit board testing with JTAGtechniques. If necessary, the engineer can

also tweak and enhance the design even atthis late stage.

Recognizing the need for intelligent proto-typing platforms for use by in-car multi-media designers, leading next-generationtelematics technology providers such asAcunia have produced the Xingu™ tele-matics platform shown in Figure 2.

Conclusion

The final stage is the look and feel of theproduct. Each car manufacturer can cus-tomize the product to fit into a specificdashboard (or fascia). All of the produc-

tion multimedia units are built up aroundthe standard FPGA-based platform. Thedesigner can program this standard plat-form with its personality late in the pro-duction flow to accommodate last-minutedesign changes or end-user preferences.

For more information, visit these websites:

Xilinx Automotive IQ Solutions: www.xilinx.com/automotive/

Acunia: www.acunia.com

BMW 7 Series Sedan:www.bmw.com/bmwe/products/automobiles/7er/sedan/

Xilinx IQ Solutions – Creating Automotive Intelligence To address the needs of automotive telematics designers, Xilinx has created a new family of devices with an extended indus-trial temperature range option. This new “IQ” family consists of existing Xilinx industrial grade (I) FPGAs and CPLDs withthe addition of a new extended temperature grade (Q), available for selected devices. The new IQ product grade (-40°C to+125°C ambient for CPLDs and junctionfor FPGAs) is ideal for automotive andindustrial applications. See Table 1.

The wide range of device density and pack-age combinations enable you to deliver costeffective, high performance, flexible solu-tions to meet your most extreme applicationneeds. See Table 2.

With Xilinx IQ devices, you can design flexi-bility into your application and get your product to market faster thanever before. Because many new standards are evolving – such as theMOST (media-oriented system transport) and FlexRay™ in-carbussing protocols – you need the flexibility to quickly modify yourdesigns at any time. With our Internet Reconfigurable Logic (IRL™)capability, you can remotely and automatically modify your designs, inthe field, after your product has left the factory, and even after the sale.

By combining our latest IQ programmable logic deviceswith our solutions infrastructure of high productivitysoftware, IP cores, design services, and customer educa-tion, you can develop advanced, highly flexible prod-ucts, faster than ever before.

For more information, full product selector guide, data sheets, white paper, and more, go towww.xilinx.com/automotive/.

Temperature Grade/Range ˚C

Products Group C I Q

FPGA TJ = 0 to +85 TJ = -40 to +100 TJ = -40 to +125

CPLD TA = 0 to +70 TA = -40 to +85 TA = -40 to +125

Q Grade Ordering Information

XCxxxXL – 5yyyQ

XCR = CoolRunner XPLA3XC95 = XC9500 CPLDsXC2S = Spartan-IIXCS = Spartan-XL

XL = 3.3VXV = 2.5V

Package TypeVQ = VQFPTQ = TQFPPQ = PQFPFG = Fine Pitch BGAFT = Fine Pitch Thin BGA

XC9500XLCoolRunner XPLA3CoolRunner-II

Macrocell Count = Speed Grade(ns for CPLDs)

Temperature RangeQ = -40ºC to +125ºC(Ambient for CPLDs)(Junction for FPGAs)

Table 1 - IQ temperature range

Device Family Availability

Spartan-XL (3.3V)NOW - XCS05XL, XCS10XL, XCS20XL, XCS30XL, XCS40XL

XC9500XL (3.3V) NOW - XC9536XL, XC9572XL

CoolRunner XPLA3 (3.3V) Q3 - 02

Spartan-II (2.5V) Q3 - 02

CoolRunner-II (1.8V) Q1 - 03

Spartan-IIE (1.8V) Q1 - 03

Table 2 - Device availability schedule

Page 55: Xcell Journal: Issue 43

by Jim Hwang¸ Senior ManagerDSP Software and Design MethodologiesXilinx, [email protected]

Platform FPGAs have become key compo-nents for implementing high-performancedigital signal processing (DSP) systems,especially in digital communications,video, and image processing applications.FPGAs have memory bandwidth that farexceeds that of microprocessors and DSPprocessors running at clock rates two to tentimes faster, and unlike processors,Platform FPGAs possess the ability toimplement highly parallel custom signalprocessing architectures.

One of the main impediments to wideradoption of FPGAs for signal processinghas been the relative unfamiliarity withFPGA technology within the DSP com-munity. What is needed are tools that speakthe language of signal processing engineers– for example, MATLAB™ language andSimulink™ design tools from TheMathWorks, Inc. – while also supportingFPGA designers who already know how toachieve the highest performance circuitusing the least number of FPGA resources.

The new Xilinx System Generator 2.2 soft-ware meets the needs of both DSP engineersand FPGA designers. System Generatorenables high-level modeling and implemen-tation of DSP systems in the Virtex-IIPro™, Virtex™-II, Virtex, and Spartan™-II families of FPGAs. New in the 2.2 releaseis an increased capability to generate hard-ware that approaches the efficiency of hand-crafted modules, both in terms of perform-ance and resource usage. In this article, wedescribe how System Generator can be usedto create a custom FIR (finite impulseresponse) filter, an operation that lies at theheart of most signal processing systems. Wedemonstrate that in addition to accessinghigh-level Xilinx LogiCORE™ modules,you can use your own FPGA knowledge toadvantage in customizing a filter data path tominimize resources while achieving high per-formance. You will see how SystemGenerator provides a wide range of optionsfor implementing signal processing systems.

Technology Focus Digital Signal Processing

Xilinx System Generator 2.2 software enables high-level modelingand implementation of DSP systems in Xilinx Platform FPGAs tooutperform traditional DSP processors.

How to Build an Efficient FIR Filter Using System Generator

Summer 2002 Xcell Journal 55

How to Build an Efficient FIR Filter Using System GeneratorXilinx System Generator 2.2 software enables high-level modelingand implementation of DSP systems in Xilinx Platform FPGAs tooutperform traditional DSP processors.

Page 56: Xcell Journal: Issue 43

Technology Focus Digital Signal Processing

Xilinx System Generator

The Xilinx System Generator is a state-of-the-art “on-ramp’’ that allows you to movea DSP algorithm into a Xilinx FPGAquickly and easily. System Generatorextends the capabilities of the Simulink sys-tem-level simulation environment with bitand cycle-true modeling of an FPGA cir-cuit. System Generator simultaneouslyprovides access to key features in the FPGAfabric, including SRL16E shift registerlogic, distributed and block memory, andembedded multipliers.

System Generator includes aSimulink library of functionalblocks for building DSP, arith-metic, and digital logic cir-cuits. These polymorphicblocks compute their outputtypes based on their inputs,although alternatively, you canspecify their quantized outputtypes explicitly. You can com-bine Xilinx blocks with MAT-LAB and Simulink blocks tocreate a realistic test bench andto analyze data computed byyour model. The high level ofabstraction provided bySystem Generator greatly sim-plifies algorithm developmentand verification.

In addition to a system-level modelinglibrary, System Generator includes a codegenerator that automatically generates asynthesizable VHDL netlist from yourSimulink model. This netlist includes IP(intellectual property) blocks that havebeen carefully designed for high perform-ance and density in Xilinx FPGAs. SystemGenerator also creates project and con-straint files to assist implementation usingthe Xilinx Foundation™ ISE 4.2i andsoon-to-be-released ISE 5.1i tools, as wellas the major synthesis tools.

Building an FIR Filter

As a simple but instructive example, let’sconsider how System Generator can beused to create a parametric finite impulseresponse (FIR) filter. An N-tap FIR filter

Mapping the Algorithm onto an FPGA

You can implement an FIR filter in anFPGA in many ways. A versatile approachthat maps well onto an FPGA employs amultiply-accumulate (MAC) engine tocompute the sum of products. As shownin Figure 1, a MAC unit is easily con-structed in System Generator using themultiplier and accumulator blocks. Themultiplier can be implemented either inthe logic fabric or, for Virtex-II familyFPGAs, using dedicated 18-bit x18-bitembedded multipliers. System Generatorensures the underlying IP core provides

an efficient implementation. Notethat upon reset, the accumulatorreinitializes to its current inputvalue rather than zero, to avoid aone-clock cycle stall.

Customizing the Data Path

Although Simulink provides agraphical block editor, SystemGenerator should not be mistakenfor a “schematic capture’’ tool.System Generator models are fullycustomizable and executable inSimulink without recompilation.(In fact, some blocks can be recon-figured during simulation.) Xilinxblocks support Simulink’s data typepropagation capability, and provideextensive error checking on their

parameters and usage. Because SystemGenerator is seamlessly integrated with theSimulink tool suite, you can customizeXilinx blocks in ways that are impossible inschematic and other visual tools.

For example, in our System Generatormodel we can specify the arithmetic pre-cision of the blocks in the data path usingMATLAB expressions, making it possibleto minimize the hardware used, and stillavoid the possibility of overflow. For a fil-ter with k-bit coefficients and m-bitinput, we know that the output

is defined by its impulse response, a lengthN sequence of filter coefficients:h0, h1,..., hN-1. If x0, x1, x2,..., is a sequenceof input values, where by convention, wedefine xi =0 for i < 0, the filter outputsequence y0, y1, y2,... is defined by the con-volution sum

That is, the filter output at time n is com-puted by accumulating a sum of productsof the filter coefficients with the N mostrecent input samples.

In practice, all numbers must be repre-sented with a finite number of bits. Witha traditional processor, numeric data aretypically represented as 8, 16, or 32-bitintegers, or in a floating-point representa-tion. In contrast, in an FPGA, we have nosuch word length limitations. We can cre-ate a custom data path processor havingan arithmetic precision tailored to theapplication. System Generator supportsthis capability by providing an arbitraryprecision fixed-point data type. Eachblock allows us to specify its output pre-cision and the policy for handling quanti-zation and overflow. We can model thesystem in the Simulink environmentunder a number of scenarios, and analyzethe data to ensure exactly the right preci-sion for the application.

56 Xcell Journal Summer 2002

yn =i = 0

N –1

hi xn–iΣ

| yn | = |

| = 2m

| <

<

i = 0

N –1

hi xn – iΣi = 0

N –1

| hi xn – i|

| hi |

Σ

i = 0

N –1

| hi 2mΣ

i = 0

N –1

Σ

Figure 1 - Multiply-accumulate engine

Page 57: Xcell Journal: Issue 43

Technology Focus Digital Signal Processing

so the accumulator requires no more thanm + log2 ∑ |hi | bits. This is in practice considerably fewer than them + k + log2N bits implied by the inputand coefficient precision. The desiredaccumulator width is, of course, readilyexpressed in the MATLAB language. (InFigure 1, the binary point in the fixed-point data is also taken into account.)When you know the input values havelimited dynamic range, it may be possibleto further tighten the bond. The accumu-lator width we just derived is a function ofthe input precision and theMATLAB array that stores thefilter coefficients, so if youwant to change the input pre-cision or change the filteritself, the same model will“right-size” the data pathwithout any modification.The implications of this abili-ty to use the MATLAB inter-preter to customize yourSystem Generator modelshould not be underestimated– it is unrivaled by any otherdesign flow.

Completing the FIR Filter Data Path

As shown in Figure 2, the input data bufferis implemented as an SRL16E-basedaddressable shift register, and the filtercoefficient buffer is implemented as a blockmemory. (Both are supplied as handcraftedXilinx LogiCORE™ algorithms.) By stor-ing the filter coefficients in reverse order inmemory, the same address counter can beused to drive both buffers.

Because there are N multiply-accumulateoperations per input sample, the filter mustrun internally at N times the data rate tosupply a continuous data stream. The cap-ture register on the output of the MAC isused to latch the accumulated sum of prod-ucts, and its output is down-sampled by Nto match the input data rate. This simplefilter architecture is quite compact and effi-cient. A 64-tap non-symmetric filter with

12-bit coefficients and data requires only110 slices in a Virtex-II XC2V250-6FPGA, and it runs at 195 MHz, or 3 Msps(ISE 4.2i, production speeds files 1.96).

System Generator provides many ways totailor the implementation of a design, andchanges are tracked automatically andtransparently. In the FIR filter, you mightchoose to use dedicated embedded multi-pliers for the MAC engine, coupled with ablock memory (BRAM) for the coefficientdata. (It is natural to do so, because theseresources are juxtaposed in the FPGA –

although both can also be implementedefficiently in the logic fabric.) Filterthroughput can be increased significantlyby employing additional MAC engines.System Generator makes this a straight-forward extension of our example. Whenyou switch the implementation strategy,latencies are automatically adjusted asnecessary in the System Generator modelto match the hardware behavior.

Other Implementation Options

Of course, you do not have to build filtersfrom scratch. There is an FIR filter blockin the System Generator library thatemploys distributed arithmetic (DA) tomap the computation into the FPGA.This is often the best way to implement afilter, because the underlying IP core sup-

ports many efficient architectures, includ-ing fully parallel DA, fully serial DA, halfband, polyphase interpolators and deci-mators, and more.

At the same time, there are occasions whenyou will want to design a custom filter, forexample, to exploit symmetries, takeadvantage of the embedded Virtex-II mul-tipliers, or to build adaptive filters. Whileproviding a high-level simulation andmodeling capability, System Generatoralso allows you to apply your knowledge ofthe FPGA to map your algorithm onto

specific resources. As we saw inour example, you can often para-meterize the design using MAT-LAB functions, so that changingparameters automatically givesyou an appropriately customizedimplementation.

Conclusion

With Virtex/Virtex-II familyFPGAs, handcrafted IPLogiCORE algorithms, andSystem Generator software,Xilinx is rapidly changing theway people think about DSP.Designing a custom DSP datapath processor in an FPGA hasnever been easier.

This article barely scratches the surface of thecapabilities of the Xilinx System Generator.The System Generator 2.2 release includes anumber of useful annotated demonstrationdesigns, including a QAM demodulator,concatenated codec for digital video broad-cast, discrete wavelet transform, and severalextensions of the FIR filter discussed in thisarticle, to name but a few. These demonstra-tion designs can be used as-is, or provide astarting point for you to create your ownapplications. A full-featured, free, 90-dayevaluation version of System Generator 2.2 isavailable for download from the Xilinx web-site at www.xilinx.com/systemgenerator_dsp.

For more information on MATLAB and Simulink software, visit www.mathworks.com.

Summer 2002 Xcell Journal 57

Figure 2 - A multiply-accumulate (MAC)-based FIR filter

Page 58: Xcell Journal: Issue 43

by Nilesh RanpuraProject Manager, ASIC GroupeInfochips ltd [email protected]

Line echoes occur in public switched tele-phone networks (PSTN) at so-called“hybrid” points, where 2-wire and 4-wirecopper lines are interconnected at the cen-tral office. Due to electric current leakagein the hybrid, a part of the signal energy isreflected back to the sourceof the signal, which causesan echo on the phone line.Likewise, in packet net-works, the delays associatedwith processing the voicestream can also produce anecho on the line.

At eInfochips Ltd., we havedeveloped an echo cancellerusing Virtex™ FPGAs. Wechose Virtex devices becausethey give us high-speed per-formance and an edge inarea-to-cost ratio over tradi-tional ASIC solutions.

Echo cancellers are advancedsignal processing algorithmsrunning on DSPs or fixed-function ASICs that removeline echoes in voice net-works. An adaptive FIR fil-ter is used to predict the echo from the his-tory of the transmitted signal.

Echo cancellers can be integrated into aphone system or packet network alongwith other voice-processing functions, suchas subtracter, double-talk detector, nonlin-ear processor, narrow band signal detector,PCM encoder/decoder, offset null filter,and controller/processor interface, asshown in Figure 1.

Virtex FPGAs: The Obvious Choice

We started our project with the goal of cre-ating a single-channel echo canceller capa-ble of handling an echo tail length of 128ms. We had the option of using a DSPchip for algorithm implementation, butduring the course of development, we dis-covered we could deploy a Virtex FPGA-based solution with DSP capabilities toachieve echo cancellation of up to 128 ms.

The choice was obvious. Not only doVirtex FPGAs have high-speed digital sig-nal processing functions, but they alsoinclude extensive flexibility in using blockRAM and LUTs as RAM and ROM.

We implemented the following majorblocks as a part of the data path design inthe FPGA:

• Adaptive FIR filter for estimating theecho signal

• Programmable double-talk detectionthreshold

• Nonlinear processor with adaptive sup-pression threshold for removing the resid-ual echo signals

• Offset null filtering of PCM channels

• Narrow band signal detector conformingto ITU-T G.165 requirements for preventing the divergence of the adaptive

filter coefficients

• Selectable µ/A law com-panding, PCM coding,and sign magnitude.

The core was verifiedusing Industry StandardVectors compliant withthe G.165 standard.

Conclusion

Xilinx Virtex FPGAs sup-port high density andspeed with extensive EDAtools support on a widespectrum of features. Thecombined solution ofVirtex hardware (in thiscase, the Virtex XCV800FPGA), associated XilinxFoundation™ Series soft-ware, and the XilinxChipScope™ integrated

logic analysis tool saved us invaluable timeto market.

As a result, of implementing a total XilinxVirtex solution, we were able to be amongthe first to bring our echo canceller solu-tion into the emerging areas of Internetgateway, ATM gateway, XDSL technology,cable modem, and wireless telephony. Formore information visit www.einfochips.comor write [email protected].

Applications DSP

By using Xilinx software and Virtex FPGAs with DSP capabilities, eInfochips Ltd. brought its line-echo canceller to market faster and better than a traditional DSP chip solution.

Use Virtex FPGAs and Xilinx Software Tools toReduce Line Echoes in PSTN and Packet Networks

58 Xcell Journal Summer 2002

S/P OffsetNull

NLP +CNG P/S

P/S

µ/ALaw

S/P

Sin

Signal Input Block Signal Input Block

Rin

Sout

Rout

StatusBus

Control Register

Serial DataOutput

External MemoryInterface

FIRFilter + Controller

HostInterface

MainController

Double TalkDetector

NBSD +Tone

Detection

Reg.

ADPController

µ/ALaw

OffsetNull

Figure 1 - Echo canceller logic block diagram

Page 59: Xcell Journal: Issue 43

by Peggy AbusaidiProduct Marketing ManagerXilinx, [email protected]

Traditional system interfaces, such as the existing PCI and VME parallel bus schemes, cannot keep up with today’s ever-growing bandwidth requirements. Therefore, RapidIO™,HyperTransport™, InfiniBand™, PCIExpress™ (aka 3GIO), and other high-speed bus interconnect technologies havebeen developed to open the I/O bottle-neck. Figure 1 illustrates the variety ofInternet applications that drive the needfor more bandwidth.

How do you choose the right I/O interfacestandards for your systems now – and howdo you keep current with the evolving I/Ostandards in the future? Moreover, how do

you meet your time-to-market and costgoals with minimal risk when the interfacestandards keep changing?

As shown in Figure 2, Xilinx provides acomprehensive list of Platform FPGASystemIO Solutions to help you solve theI/O bottleneck problem. SystemIO givesyou the ability to implement designs usingany of the latest I/O standards. By using aXilinx Platform FPGA with a SystemIOsolution, you can accelerate your time tomarket and be assured that your designs willremain current even as I/O standards evolveand specifications change. In addition,SystemIO solutions enable you to “future-proof” your products by allowing to you

update the code in the FPGA to bring yourproduct up to compliance – even after theproduct has been deployed in the field.

Solving the Bandwidth Problem

Today, most computer, embedded pro-cessing, and telecommunications equip-ment are parallel bus-oriented. However,as device performance increases, anddemand for bandwidth rises, these multi-drop bus structures are reaching their per-formance limits. In most cases, these busescan only process one module at a time.This results in idle time for the subsystemswaiting for bus access, thus decreasingoverall system performance.

Technology Focus High Speed Interfacing

SystemIO SolutionExpands with Bandwidth Demands

Summer 2002 Xcell Journal 59

The Xilinx Platform FPGA SystemIO solutions solve the emerging interface challenges for high-speed system interconnectivity.

Page 60: Xcell Journal: Issue 43

The industry’s response has beenthe development of a host ofnew interconnection schemes,some with data transfer ratesexceeding 10 Gbps. The newproposed standards have backerslike Intel, AMD, Microsoft,Hewlett-Packard (Compaq),Dell, Xilinx, and SunMicrosystems. In addition to theaforementioned RapidIO, PCIExpress, HyperTransport, andInfiniBand technologies, otherstandards already in use, orevolving toward higher levels ofperformance, include 10-gigabitattachment unit interface(XAUI), POS-PHY Level 4,Gigabit Ethernet, and variousoptical ATM formats like OC-12, OC-48, and OC-192. These new orevolving standards cover all architecturalenvironments, such as motherboards inchip-to-chip communication; backplanesfor communications between subsystems;and storage, local, and wide area networks(SANs, LANs, and WANs).

Parallel bus standards are divided into twogeneral categories:

• System-Synchronous Parallel – the vener-able PCI family of buses, including PCI-X and Compact PCI.

• Source-Synchronous Parallel – RapidIO,HyperTransport, Flexbus 4, POS-PHYLevel 3/4, and other protocols.

Because these standards are new and subjectto change, FPGAs are the ideal way to shipa product without fear of obsolescence.Plus, the ability to use Xilinx LogiCORE™intellectual property (IP) cores that imple-ment these complex and timing-criticalbuses gives you a fast, risk-free method toaddress a rapidly changing market.

Clearly, the challenges you face are greaterthan ever. Not only are product life cyclesshorter, simple evolutionary product stepsare no longer sufficient with the multitudeof standards hitting the market. When youconsider that most of these standards arenot final, the challenge to get your product

SelectI/O™-Ultra blocks to pro-vide the fastest and most flexibleelectrical interfaces available.Each user I/O pin is individuallyprogrammable for 19 single-ended I/O standards or six differ-ential I/O standards, includingLVDS, SSTL, HSTL, and GTL+.The SystemIO solution is capableof delivering 840 Mbps doubledata rate (DDR) and 644 MHzsingle data rate (SDR) LVDS per-formance. Furthermore, any twoI/O pins can be used as a differ-ential pair, providing maximumboard layout flexibility andreducing overall system cost bysaving both component andboard layer costs.

Using Virtex-II 840 Mbps LVDS perform-ance and an abundance of memory andlogic resources, you can easily createdesigns using 1GE (Gigabit Ethernet) and10GE MAC, PCI and PCI-X, POS-PHYLevels 3 and 4, RapidIO, HyperTransport,and Flexbus 4 protocols. Free referencedesigns for implementing interfaces, suchas SFI-4, XSBI, XGMII, and CSIX areavailable from the Xilinx website. Table 1shows the Platform FPGA SystemIOSolutions Summary, including both IPcores and reference designs.

right on the first iteration is daunting.That’s why the ability to rapidly changeyour design to meet changes in the stan-dards and markets is incredibly valuable.Further, the ability to leverage your designefforts with pre-engineered, pre-verified,and supported LogiCORE IP cores allowsyou to create more functionality in lesstime than ever before.

The SystemIO Solution

The Xilinx Platform FPGA SystemIO Solution uses the unique Virtex™-II

Internet BandwidthRequirements

Audio

Data

Graphics

Video

Interactive Video

ConsumersNeed...

Band

widt

h

Time

60 Xcell Journal Summer 2002

Figure 2 - Xilinx Platform FPGA SystemIO Solutions

Figure 1- Internet bandwidth trend

Technology Focus High Speed Interfacing

Page 61: Xcell Journal: Issue 43

FPGA10GE MAC10GE

PHYLAN/WAN

ASSP ASSP ASSPIntegrated

OpticsOC-192 POS

POS-PHY L4XGMII

NPU

Bridge toControl Plane

Bridge toControl Plane

PCI 64/66, PCI-X 66 & 100, RapidIO, HyperTransport*

PCI 64/66, PCI-X 66 & 100, RapidIO, HyperTransport*

*Available in Q3/02

FPGA

FPGAPL4 to XAUI

Bridge

Bac

kpla

ne

POS-PHY L4 XAUI

Figure 3 - 10 Gigabit Ethernet LAN/WAN line card application example

Technology Focus High Speed Interfacing

With the variety of interface reference designsand cores available in the SystemIO solution,you can easily customize your application.Figure 3 shows a 10 Gigabit EthernetLAN/WAN line card example in which sever-al Platform FPGA SystemIO solutions areused to provide seamless interfaces to externalPHYs and network processors. All of theseinterfaces are pre-engineered by Xilinx foreasy drop-in functionality, enabling you toreduce your design cycle time.

With our recent introduction of the Virtex-II Pro™ Platform FPGA, we have incorpo-rated Mindspeed’s SkyRail™ architectureto embed up to 16 Rocket I/O™ 3.125Gbps multi-gigabit transceivers (MGTs),the highest number of MGTs in a singleprogrammable device. This breakthroughtechnology supports all the popular emerg-ing serial I/O standards, including the PCIExpress, InfiniBand, XAUI, and FibreChannel protocols.

The combination of SkyRail architectureand SelectI/O-Ultra technology supplies acomprehensive list of popular parallel andserial interface IP cores in the overallSystemIO solution. Additionally, both 1GEand 10GE MAC IP cores are available withboth parallel and serial interface options.

Conclusion

Platform FPGA SystemIO solutions enableXilinx to provide you with the ultimateconnectivity platform to connect andbridge interface requirements for your next-generation data communication systems.

A terabit system can simultaneously containmultiple interface requirements, includingboth emerging serial I/O protocols, as well asestablished parallel I/O standards. The newVirtex-II Pro Platform FPGA is ideally suit-ed to help you address interface challengesby providing Rocket I/O MGTs for serialconnectivity and SelectI/O-Ultra technologyfor parallel connectivity.

Combining LogiCORE IP cores for proto-cols and data processing, along with designtools and third-party partnerships, Xilinxprovides the complete system connectivitysolution for today’s – and tomorrow’s –high speed designs.

Summer 2002 Xcell Journal 61

IP Core Standard Compliance Aggregate Bandwidth Performance SelectI/O Bus Availability

POS-PHY L3 OIF-SPI3-01.0 2.48 Gbps 104 MHz 32b 3.3V CMOS NowSaturn POS-PHY L3

POS-PHY L4 OIF-SPI4-02.0 12.8 Gbps 800 Mbps per pair 16b LVDS NowSaturn POS-PHY L4 400 MHz DDR

Flexbus 4 OIF-SPI4-01.0 12.8 Gbps 200 MHz 64b HSTL NowAMCC Flexbus 4

Flexbus 4 to OIF-SPI4-01.0 11.2 Gbps 200 MHz 64b HSTL NowPOS-PHY L4 AMCC Flexbus 4 (Flexbus 4 side) (Flexbus 4 side)

Bridge OIF-SPI4-02.0 350 MHz DDR 16b LVDSSaturn POS-PHY L4 (PL4 side) (PL4 side)

1GE MAC w/GMII IEEE 802.3-2000 1 Gbps 125 MHz 8b 3.3V GMII Now

1GE MAC IEEE 802.3-2000 1.25 Gbps 1.25 Gbps 1 channel of Noww/ PCS-PMA Rocket I/O

Transceiver

10GE MAC Designed to 10 Gbps 156.25 MHz DDR 32b XGMII HSTL Noww/ XGMII IEEE P802.3ae

draft 4.1

10GE MAC Designed to 12.5 Gbps 3.125 Gbps 4 channels of Noww/ XAUI IEEE P802.3ae per channel 3.125 Gbps

draft 4.1 Rocket I/OTransceivers

RapidIO PHY RapidIO Interconnect 8 Gbps 500 Mbps per pair 8b LVDS NowSpecification v1.1 250 MHz DDR

PCI64 PCI Spec V2.3 264 -528 MBps 33/66 MHz 64b 5/3.3V PCI Now

PCI32 PCI Spec V2.3 132 -264 MBps 33/66 MHz 32b 5/3.3V PCI Now

PCI-X 64/100 PCI-X Spec V1.0a 800 MBps 66/100 MHz 64b 3.3V PCI-X Now

HyperTransport HyperTransport V1.01a 6.4 Gbps 800 Mbps per pair 8b HT I/O Q3 ‘02Single-Ended 400 MHz DDR

Slave

CSIX Reference CSIX-L1 6.4 Gbps 200 MHz 32b HSTL NowDesign

XGMII Designed to 10 Gbps 156.25 MHz DDR 32b XGMII HSTL NowReference Design IEEE P802.3ae

draft 4.1

Table 1 - Summary of Platform FPGA SystemIO solutions

Page 62: Xcell Journal: Issue 43

by Jim BenekeDirector of Technical MarketingInsight [email protected]

Running at 125 MHz, the XilinxMicroBlaze™ 32-bit soft processor core isthe industry’s fastest soft processing solu-tion. The MicroBlaze processor delivers atrue 32-bit processor, critical for buildingcomplex systems for the networking,telecommunication, data communication,

embedded, and consumer markets. The soft processor fea-tures RISC architecture withHarvard-style separate 32-bit

instruction and data busses, which run atfull speed to execute programs and accessdata from both on-chip and external mem-ory. With 900 logic cells and 82 D-MIPS,the MicroBlaze processor meets the utiliza-tion, performance, and cost targets thatmost FPGA designers require.

To support the development ofMicroBlaze-based applications, MemecDesign has introduced three differentMicroBlaze Development Kits (MDKs) to

accelerate design, prototype, and evalua-tion cycles. The three MDKs allow you toquickly prototype your MicroBlaze proces-sor and peripherals in real-world hardwareenvironments. With functioning hardwareplatforms based on Xilinx FPGAs, you caneasily verify design concepts, system inter-faces, and real-time functionality.

Three Families – Three Kits

The Virtex™-II, Spartan™-IIE, andSpartan-II FPGA families are the logicaltargets for MicroBlaze applications.Therefore, Memec offers specially designedstandalone system boards for a device fromeach of these families.

Additionally, each MDK offers an expansionmodule that contains common processor

peripheral interfaces and memory, a pro-totype module for creating custom circuits,the Xilinx MicroBlaze processor license,software tools, and a power supply.

• The Virtex-II platform is based on the onemillion-gate XC2V1000 device (Figure 1).The system board includes 2M x 16 DDRSDRAM and a 16-bit LVDS Tx/Rx port.

• The Spartan-IIE system board is based on the 300K-gate XC2S300E device(Figure 2). This board offers a 10-bit LVDSTx/Rx port and 82 general purpose I/Os.

• The Spartan-II kit uses the 200K-gateXC2S200 device (Figure 3), which resideson a 32-bit PCI interface, along with 2Mx 32 SDRAM. The PCI interface presentsan interesting configuration by allowingthe MicroBlaze processor to sit on thebackend of the PCI bus.

All three platforms include the P160 expan-sion slot, an ISP PROM, on-board powerregulation, and other user support circuits.

New Products Development Kits

MicroBlaze Development Kits from Memec Designdemonstrate the versatility of the MicroBlaze soft processor core in a variety of Xilinx FPGAs.

62 Xcell Journal Summer 2002

Develop MicroBlaze Applications with Three Flexible HardwareEvaluation Platforms

Develop MicroBlaze Applications with Three Flexible HardwareEvaluation Platforms

Spartan-IIE MDK

Virtex-II MDK

Spartan-II MDK

Page 63: Xcell Journal: Issue 43

New Products Development Kits

P160 Expansion

The P160 expansion slot provides the flex-ibility you need in a processor and IP devel-opment environment. The expansion slotallows you to easily plug custom peripheralmodules into the system board and inter-face to the FPGA device.

The P160 slot supplies 110 user-definedI/O signals from the FPGA to the userapplication circuit on the expansion card.By adding a P160 module, you can tailoryour development environment and easehardware verification.

Two P160 modules are included in theMDKs:

• The P160 communication module(Figure 4) provides interfaces for 10/100Ethernet, RS-232, USB, PS/2 keyboard,LCD module, I2C, and SPI connec-tions. The communication module alsoincludes 2M x 32 flash and 256K x 32SRAM for off-chip memory expansionby way of the IBM CoreConnect™ on-chip peripheral bus architecture.

• The P160 prototype module (Figure 5)offers general purpose expansion headersfor all 110 user I/O signals, as well as a prototype area for building custom circuits.

Conclusion

As MicroBlaze implementations move intothe mainstream, you will need easy to use,flexible, low-cost hardware platforms toverify and validate your design concepts.Supporting Virtex-II, Spartan-IIE, andSpartan-II devices, each Memec DesignMDK bundles the essential tools you needto explore MicroBlaze-based designs.

The Virtex-II MDK is priced at $795. TheSpartan-IIE and Spartan-II MDKs are avail-able for $695. Call 888-488-4133, ext. 235,or go to www.insight-electronics.com/microblaze for more information or to ordera MicroBlaze Development Kit.

MemecCore Group and Memec Design

In addition to the MicroBlazeDevelopment Kit, Insight Electronics

and Impact Technologies offerMicroBlaze design service support

through Memec Design. Our Xilinx-dedicated design services

group can assist you in MicroBlaze andturnkey FPGA design, CoreConnect

peripheral design, customization, integration, and FPGA performance

optimization. Furthermore, theMemecCore Group focuses exclusively

on offering Memec customers the highest quality intellectual property fortomorrow’s designs. MemecCore offersseveral CoreConnect-enabled peripheral

functions for easy integration intoMicroBlaze applications.

Visit www.insight-electronics.comor www.impact.eu.memec.comfor more information on our

complete MicroBlaze offerings.

RS-232SelectMap

Slave Serial

7-SegmentDisplay

DIP Switches

Push ButtonSwitches

User LEDs

2M x 16DDR SDRAM

Voltage Regulators

1.5 Volts

I/O Connector

I/O Connector

2.5 Volts

3.3 Volts

ISP PROM

P160 Slot

16-Bit LVDS RX

16-Bit LVDS TX

Clocks (2)

Reset Circuit

Virtex-IIFPGA

XC2V1000(FG456)

JTAG Port

RS-232SelectMap

Slave Serial

7-SegmentDisplay

DIP Switches

Push ButtonSwitches

User LEDs

82 User I/OHeaders

Voltage Regulators

1.8 Volts

I/O Connector

I/O Connector

2.5 Volts

3.3 Volts

ISP PROM

P160 Slot

10-Bit LVDS RX

10-Bit LVDS TX

Clocks (2)

Reset Circuit

Spartan-IIEFPGA

XC2S300E(FG456)

JTAG Port

RS-232SelectMap

Port

7-SegmentDisplay

DIP Switches

Push ButtonSwitches

User LEDs

PCI32Interface

Voltage Regulators

I/O Connector

I/O Connector

2.5 Volts

3.3 Volts

ISP PROM

P160 Slot

SDRAM 2M x 32

Clocks (2)

Reset Circuit

Spartan-IIFPGA

XC2S200(FG456)

JTAG Port

RS-232

10/100 PHY

USB

PS/2

LCD I/F

I2C

Flash2M x 32

SRAM256K x 32

SPI

I/O C

onne

ctor

s

I/O C

onne

ctor

s

2 x 20Headers

2 x 20Headers

User LED

PrototypeArea

2 x 20Headers

2 x 20Headers

Power LEDsI/O C

onne

ctor

s

I/O C

onne

ctor

s

Figure 1 - Virtex-II system board block diagram Figure 2 - Spartan-IIE system board block diagram Figure 3 - Spartan-II system board block diagram

Figure 4 - P160 communications module block diagram

Figure 5 - P160 prototype module block diagram

Summer 2002 Xcell Journal 63

Page 64: Xcell Journal: Issue 43

New Technology Development Board

Xyron Semiconductor’s zero overhead task switchtechnology gives a 40 MHzFPGA the real-time video rendering power of a GHzdesktop microprocessor.

Xyron ZOTS IP Core UsesVirtex-II FPGA to Demonstrate RTOS Breakthrough

64 Xcell Journal Summer 2002

Page 65: Xcell Journal: Issue 43

New Technology Development Board

by William DressDirector of Strategic DevelopmentXyron [email protected]

Xyron Semiconductor’s patented “zero over-head task switch” (ZOTS™) technologypromises to revolutionize both hard-ware and software design for embed-ded systems applications. Essentially,we remove the task-switching andinterrupt control decision-makingoff the core microprocessor – whichdramatically improves microproces-sor efficiency and provides endresults similar to increasing a micro-processor’s clock speed by severalorders of magnitude.

Our technological breakthrough isnovel and radical. Never before hasRTOS task management been imple-mented in hardware in such a manner.We knew we could attract customersif we could just effectively demon-strate the technology. Fortunately, thefunctionality of the Xilinx Virtex™-IIFPGA gave us the solution.

Show and Tell

We chose to demonstrate our tech-nology by building on a publicdomain 32-bit RISC architecture. Byintroducing a simple, seven-tasksimultaneous environment contain-ing real-time video, stored video, andreal-time audio, we have been able todemonstrate a fully functional multi-media microprocessor that handlesinterrupts on a pixel-by-pixel basis.With Xyronium™ technologyembedded into a 32-bit RISCprocessor as a firm IP core in a XilinxVirtex-II XC2V1000 FPGA, ourdemonstration board runs at only 40 MHz.Nevertheless, the board processes full-motion, full-frame video and stereo CD-quality audio – with enough performancepower remaining to manipulate video inreal time in a moving picture-in-picturesynchronized with the audio amplitude(Figure 1). To see an interactiveMacromedia® Flash™ demonstration, goto www.xyronsemi.com/xdemo.shtml.

Therefore, we created a powerful stand-alone, single-board computer that show-cased our technology so users could see forthemselves (Figure 2). Multiple video,audio, and user interfaces allow our cus-tomers the flexibility to design for any

application in a familiar XilinxFPGA environment.

Using a Virtex-II XC2V1000 FPGA,the development board is an ideal envi-ronment to not only illustrate thepower of the ZOTS innovation, butalso to implement these powerful newtechnologies in real-world applications.Once the Xyron ZOTS firm IP micro-processor core is inserted into the fab-ric of a Virtex-II device, there is ampleroom to create custom circuitry to sup-port specific design requirements.

Conclusion

The path from demonstrating a radicalnew microprocessor technology to pro-viding a practical development environ-ment was optimized with the Virtex-IIproduct family. The process only took afew months with a small design team.

In all fairness, we explored otheroptions, but they were not nearly asefficient. Without the functionality ofthe Virtex-II FPGA, it would not havebeen possible to construct such a robustdevelopment board as the Edison™DevelopmentBoard. That’swhy XyronSemiconductor has become a partner inthe Xilinx AllianceCORE™ program.

In a classic win-win situation, com-bining Xyron technology with Xilinxproducts has given us the ability torealize standard-cell, dedicated IC

performance in a flexible FPGA environ-ment. The Virtex-II product offering hasenabled Xyron Semiconductor to take itsfirst steps toward becoming a full-fledgedmicroprocessor company.

For more information on Xyron technolo-gy, please visit www.xyronsemi.com. To pur-chase a development board, go towww.xyronsemi.net.

A similarly burdened standalone desktopmicroprocessor programmed with the sameRTOS capability and without video, audio,or memory support architecture wouldneed to run at over 1.0 GHz to accomplishthe same real-time tasks.

Show and Sell

The Xyron ZOTS approach is so revolu-tionary that we anticipated the initial mar-ket acceptance might be difficult. Potentialcustomers might have difficulty believingyou can implement traditional RTOS soft-ware task management functions in hard-ware – and realize significant microproces-sor performance improvements as a result.

Summer 2002 Xcell Journal 65

Figure 2 - Xyron Semiconductor Edison development board

incorporates a Xilinx Virtex-II XC2V1000 FPGA.

Figure 1 - Special effects in real-time video

Page 66: Xcell Journal: Issue 43

by Art StryerSenior Field Applications EngineerElantec Semiconductor, [email protected]

Virtex-II Pro™ series Platform FPGAs useseparate supply voltages for the core circuitryand I/O interface power supplies. Typically,the I/O interface requires 2.5V and the corecircuitry requires 1.8V. As a designer, youneed to minimize board space and maximizethe reliability of the power supplies.

Elantec Semiconductor Inc. has highly inte-grated solutions to fulfill your local powerneeds. Elantec’s family of integrated FETDC:DC converters provides optimal solu-tions for Virtex-II Pro designs. These powerproducts are unique synchronous buck con-verters with integrated FETs and internalcurrent sensing. These features, as well asother embedded functions, enable high effi-ciency and higher frequencies, which lead tosmaller inductors. These features and func-tions require fewer external components,giving you the advantage of minimum boardspace. Additionally, higher reliability isachieved through lower die temperature.

Product Focus DC:DC Converters

High efficiency and fewer components give you high reliability while reducing printed circuit board real estate.

Elantec Semiconductor Has Power Supply Solutions for Virtex-II Pro Platform FPGAs

66 Xcell Journal Summer 2002

Elantec Semiconductor Has Power Supply Solutions for Virtex-II Pro Platform FPGAs

Page 67: Xcell Journal: Issue 43

Product Focus DC:DC Converters

Integrated FET DC:DC Converters

When you are designing a local power sup-ply for a Virtex-II Pro system, several factorsallow you to achieve a small PC board area.Elantec power products include the follow-ing features:

• Synchronous DC:DC switching regula-tors running at higher frequencies

– Up to 1 MHz switching frequency

• Higher frequencies, allowing use of small-er external capacitors and inductors

– Steady peak-to-peak ripple voltage withfewer external parts

• Higher integration, resulting in fewerexternal components

– No external FETs

• Reduced parts count.

Embedded Functions Reduce ICs

When designing a local power supply for aVirtex-II Pro system, you need certain fea-tures for a complete solution. To achievethese complete solutions usually requiresadditional ICs. Elantec parts, however, fea-ture embedded functions, including:

• Current mode control

– On-chip current sensing feedback forinternal PWM controller

• Over-current protection

– Cycle-by-cycle current sensing andlimiting

• Over-temperature protection

– Junction temperature monitor circuiton die

– Control circuits with hysteresis forautomatic supply restart

• Adjustable switching frequency

– User-selectable frequency to avoidswitching interference

• Soft start

– Internal power-up control

• Power sequencing

– Sequential activation of multiple powersupplies without additional control ICs

• Simultaneous power tracking with con-trolled voltage out.

Complete DC:DC Converter Family

Different designs will have varyingrequirements for voltage and current,switching frequency, and available boardspace. The Elantec family of DC:DCproducts meets Virtex-II Pro local systemneeds by providing:

• Continuous output currents

– Products to choose from with currentsup to 1A, 2A, 4A, 6A, and 8A

• Flexible output voltages

– Adjustable voltages from 1.0V to 3.3Vavailable from each product

• Multiple package types

– HTSSOP, QSOP, MSOP, HSOP, andSOL available.

Table 1 shows a comprehensive summaryof Elantec power products. Figure 1 showspackages and board area space for 4A and8A products.

Conclusion

Design engineers engaged in Virtex-II Proboard designs need to have power suppliesthat provide a complete solution for localpower in their systems. Elantec DC:DCconverters have all of the features andembedded functions to get the job done.For data sheets, application briefs, andadditional information, visit Elantec onlineat www.elantec.com, or send an e-mail [email protected].

High Reliability Components

The following list of functions in Elantecpower products improve the reliability ofyour power supply:

• Synchronous converter

– Both upper and lower power switcheson-chip

– Up to 95% efficiency

• Integrated Power FETs

– Reduced power dissipation versus exter-nal FETs with resistive connections

• Advanced packages

– Optional low die temperature, smallHTSSOP.

Summer 2002 Xcell Journal 67

Part No. Type Supply Voltage Output Voltage Output Current Package

EL7558BC Buck 4.5V to 5.5V 1.0V to 3.8V 8A HSOP28

EL7556BC Buck 4.5V to 5.5V 1.0V to 3.8V 6A SO28

EL7564C Buck 4.5V to 5.5V 1.0V to 3.8V 4A HTSSOP28

EL7563C Buck 3.0V to 3.6V 1.0V to 2.5V 4A HTSSOP28

EL7562C Buck 4.5V to 5.5V 1.0V to 3.8V 2A QSOP16

EL7551C Buck 4.5V to 5.5V 1.0V to 3.8V 1A QSOP16

EL7512C Boost 2.0V to 14V 5.0V to 16V 0.2A to 0.5A MSOP10

Table 1 - Elantec power products

Figure 1 - Integrated FET 4A and 8A DC:DC converter packages

Page 68: Xcell Journal: Issue 43

by Dr. Malachy Devlin Chief Technology OfficerNallatech [email protected]

Typical data handling and processing systems require a combination of high-performance capabilities. Until now, thesecapabilities could only be achieved throughcombining various programmable logicarchitectures and processor technologies tohandle complex control algorithms.

The release of the Xilinx Virtex-II Pro™Platform FPGAs, however, now gives us asingle, integrated package for manipulatingcomplex control algorithms. As many asfour IBM® PowerPC™ 405 processors canbe embedded deeply in the Virtex-II Proprogrammable logic fabric.

In order to create final systems based onVirtex-II Pro devices – and to harness maxi-mum power from these devices – appropri-ate hardware architecture is critical. TheDIME™ and DIME-II™ architectures areopen modular standards from Nallatech thatcreate the framework for scalable systems. Asmall, dedicated FPGA-based system can beeasily scaled to create high-end high-speedDSP applications through the DIME-IIplug-and-play capability. This architectureprovides support for processor integrationwithin FPGA-based systems, including the

New Products Scalable Systems

Nallatech’s second-generationmodular DIME-II architecture has been designed to maximizeVirtex-II Pro Platform FPGA performance and bandwidth.

Nallatech’s DIME-IIModular ArchitectureGoes Pro

68 Xcell Journal Summer 2002

DIME-IIVirtex-II Pro

DDRSDRAM

DDRSDRAM

ZBTSRAM

ZBTSRAM

ExternalRocket I/O

8 x 3.125 Gbit

InternalRocket I/O

8 x 3.125 Gbit

I/O

DIME-II

I/O

Figure 1 - BenPRO block diagram

Page 69: Xcell Journal: Issue 43

use of ICE (in-circuit emulation) debug-gers, remote booting, and configuration.

BenPRO Module

The BenPRO™ module from Nallatechprovides maximum scalability and maxi-mum communications bandwidth. TheBenPRO™ module will be available withall Virtex-II Pro devices that have embeddedPowerPC processors. In this configuration, asingle DIME-II module can have up to fourhard processors and up to four million sys-tem gates of logic for computational andinterfacing tasks.

By utilizing up to 16 Rocket I/O™ trans-ceivers on a single Virtex-II Pro, and stan-dard I/O interfaces offered by DIME-IItechnology, you can get an I/O bandwidthin the order of 100 gigabits per second

To support onboard data and program stor-age, four high-speed memory banks are builtinto the BenPRO module. As shown inFigure 1, DDR SDRAM and ZBT SRAMenable suitable memory architectures to bedesigned for tight integration with the algo-rithm or platform architecture required.

Controlling Virtex-II Pro Systems

Nallatech’s FUSE™ (field upgradeable sys-tems environment) software supplies thereconfigurable computing operating systemfor FPGA-based systems. The powerful API(application programming interface) enablesrapid development of systems and applica-tions based on FPGAs, either with or with-out, embedded processors. FUSE systemsoftware is portable and supports multipleoperating systems, such as Linux,VXWorks®, and Windows® systems.

Additionally, FUSE software supports awide range of languages, includingC/C++, Java™, MATLAB™ andDIMEscript™, Nallatech’s own dedicatedlanguage for controlling reconfigurablecomputing environments.

FUSE software also supports multipleembedded processors, including the IBMPowerPC hard processor and theMicroBlaze™ soft processor from Xilinx –both of which can be embedded in oneVirtex-II Pro Platform FPGA. The power of

Conclusion

Today, system designers require suitablesoftware tools, development platforms,and modular hardware to efficiently createcomplex high-performance systems. WithDIME-II hardware system architectureand the FUSE reconfigurable computingoperating system, you can not only harnessthe full power of Virtex-II Pro PlatformFPGAs, but you can also use Nallatech’sadvanced engineering to bundle multipledevices within a system – taking systemdesigns to unprecedented levels of com-plexity and functionality.

FUSE system software provides forhigh-speed booting and datacommunication, as well as sys-tem control. The FUSE capa-bility allows full integrationwith high-level designtools from Xilinx, indus-try-standard proto-cols, and user appli-cation software.Figure 2 showsthe relation-ship amongFUSE, DIME-II, and Virtex-IIPro components.

Distributed ParallelProcessing

Although a single Virtex-II Pro device canhave as many as four processors, DIME-IItechnology can scale systems far beyond this.For example, DIME-II interconnect tech-nology will enable you to tightly couple fourBenPRO modules on a BenERA™ cPCIcard, thus providing 16 PowerPC processorson a single card, as illustrated in Figure 3.With FUSE system control software, youcan expand connectivity to multiple cPCIcards, leading to a virtually unlimited arrayof processors within the overall system.

To benefit from this capability, the tools needto be in place for handling this distributedparallel processing sys-tem. Nallatech isenhancing its systemdesign products todeliver the tools andcommunications infra-structure to support dis-tributed parallel pro-cessing. Once in place,the combined DIME-IIand Virtex-II Pro tech-nologies will enable youto create a diverse rangeof system topologiesthat can take advantageof the high communi-cations bandwidthsnow available – and inthe future.

Summer 2002 Xcell Journal 69

Figure 2 - How FUSE software control works with Virtex-II Pro logic devices

Figure 3 - BenERA cPCI card with four Virtex-II Pro FPGAs on BenPRO modules

New Products Scalable Systems

Page 70: Xcell Journal: Issue 43

by Milan SainiTechnical Marketing Manager, Alliance Software MarketingXilinx, [email protected]

Perspective Industry Trend

Platform FPGAs Take on ASIC SOCs

70 Xcell Journal Summer 2002

Here are seven good reasons why Platform FPGAs provide a superior design environment and faster

time to market than ASIC SOCs.

Here are seven good reasons why Platform FPGAs provide a superior design environment and faster

time to market than ASIC SOCs.

Platform FPGAs Take on ASIC SOCs

Editor’s note: Due to a printing error, the last several paragraphs of this article were inadvertently cut off when it was published in the Spring 2002Edition of Xcell Journal. Therefore, we are reprinting this article in its entirety.

Page 71: Xcell Journal: Issue 43

Perspective Industry Trend

32

1

The system-on-a-chip (SOC) market hasexperienced steady and consistentgrowth. Dataquest estimates roughly halfof all ASIC design starts are SOC based.That percentage is projected to reach80% by 2005. There are several reasonsfor this clear shift in design methodology.Some of the obvious advantages includegreater component integration, increasedspeed (Logic <-> Processor), lowerpackaging and test costs, andincreased overall system reliability.All of these combined can potential-ly make significant contribu-tions to achieving the often elu-sive but always important goal ofaccelerated time to market.

Programmable logic device vendorshave entered the SOC solution spacewith the introduction of a new class ofdevices known as Platform FPGAs – with the most recent addition being theVirtex-II Pro™ Platform FPGA. Thesedevices offer the same level of integration asASIC SOCs, but in contrast, PlatformFPGAs facilitate the development of a widerange of applications on the same chip. Thisarticle focuses on seven of the key advan-tages of the Platform FPGA approach.

#1 – Pre-Engineered Platform

Platform FPGAs integrate several fixedand predetermined blocks of hard IP(intellectual property) components (sys-tem elements) within the programmablefabric. Notable among these are high-per-formance RISC CPUs, multi-gigabit andhigh speed I/Os, block RAM, systemclock management, and dedicated DSPprocessing hardware. This powerfulassembly and harmonious blend of com-ponents creates a cohesive system designenvironment. This environment offersunprecedented flexibility and perform-ance, thus enabling the deployment of awide range of applications.

The critical technological breakthrough isin the ability to tightly interface the vari-ous elements into the programmable fab-ric. Without this tight integration, much

ering the performance, capacity, and inte-gration that is necessary to challenge anddisplace the current established platformsof system design.

For instance, FPGAs now make it entirelyfeasible to build systems of up to 2M (ASIC)gates with CPU(s) running at 400 MHz,serial I/O channels at 3.125 Gbps CLB fab-ric-switching at 300 MHz, and the entiresystem clocking over 150 MHz. This sur-passes the projected sweet spot of ASICSOC designs.

Looking at it in pure economic terms,the costs for a typical mask set for a

130 nm ASIC run into the $700K+range. That raises the bar for entry intothe ASIC space, making the PlatformFPGA an even more attractive option for agrowing percentage of all SOC designs.

Summary: FPGA silicon is best-in-class inprocess and engineering, thereby deliver-ing best-in-class system performance.

#3 – Software Tools and Methodology

It is well known that EDA designer pro-ductivity for ASICs is lagging behindrecent silicon advances. The ability to cre-ate a productive design and debug environ-ment is absolutely essential to the success ofany silicon platform. Therefore, softwareplays a critical role in not only making theplatform easy to use and work with, butalso in extracting the most performanceand device utilization out of the silicon.

The goal is to insulate the user from hav-ing to learn extraneous details about theplatform, yet providing empowerment andcontrol when and where it is needed. Tothis end, FPGA vendors have created cus-tomized and user-friendly processor sys-tem generator tools that aid in instantia-tion, initialization, and configuration of allthe various system component blocks. Inaddition, these software tools automateotherwise manual and error-prone tasks,such as the interconnections among theprocessor, its peripherals, and buses.

Design entry is engineered to tightly cou-ple the HW/SW domains. Such engineer-

of the speed benefits could not be realized.The fact that the choice of system elementsis already made greatly simplifies thedesign and development process. A fixedarchitecture is particularly beneficial forsoftware tool and IP providers in allowingthem to deliver better value, customiza-tion, and architecture-optimized solutions.

The assembly of the various hybrid IPblocks in an ASIC adds substantial com-plexity and hardship to the users’ designand development environment, because ofa variety of issues relating to tool and IPinteroperability, physical layout, timing,and system verification. For PlatformFPGAs, on the other hand, it is much eas-ier to tailor and optimize components –such as silicon, software, support, and IP –because FPGAs represent a fixed and pre-engineered target.

Summary: A fixed, pre-engineered butprogrammable FPGA solution offers amore productive and efficient develop-ment environment from both the softwareand silicon perspective.

#2 – Process Technology

PLD vendors have been able to extractgreat value and benefits from Moore’s Lawand shrinking device geometries. Whilethe majority of ASIC design starts are at orhigher than 180 nm, FPGAs have racedahead to bring the cost and performanceadvantages of 130 nm to its customers.This ability to rapidly migrate to the lead-ing edge of technology is essential to deliv-

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Perspective Industry Trend

54ing leads to not only simplified and easy-to-use design flows, but it ensures reliabil-ity and robustness from the very start byperforming design rule and data consisten-cy checks across the two domains.

Two examples of the advantages of cross-domain HW/SW co-design include:

• Automatic generation of device driversand header files for SW engineers oncea particular block is instantiated by theHW designer

• Tools to automatically populate SWbinary code into appropriate FPGAmemory bitstreams.

Summary: Software sells silicon.

#4 – Advanced Debug

The importance of finding problems earlycannot be overstated. Yet, up-front ASICverification is extremely designer- andcomputer-resource intensive. Compared

to systems on a board, SOC limits visibil-ity into the internal nodes of the system,making the task of verification and debugmore challenging than ever.

The critical part includes the verificationof complex interactions between theapplication software and the custom-designed peripheral hardware. TraditionalHDL-centric verification and debug tech-niques can no longer deal with the risingcomplexity of system designs.

Consider a typical application, such asMPEG A/V decoding, where a largenumber of simulation cycles are requiredto complete a small sequence of frames.Co-verification tools in this case wouldeither take an impractically long time tocomplete or validate only a mere fractionof the software code, falling far short ofwhat it takes to find problems in theHW/SW interface.

FPGAs overcome this problem in largepart by being able to provide access to realor near real targets at a very early stage inthe design cycle. Among other things, thismeans that SW engineers using FPGAscan quickly and easily sort out logic anddesign flaws by targeting real silicon. Theengineers do not have to rely on ineffi-cient ASIC-centric techniques like co-ver-ification or writing stub code. Applicationsoftware can be debugged at system speedswith full hardware and software registeraccess and control.

Additionally, the FPGA fabric allows forconstruction of highly customized andvalue-added cores to enable powerful real-time, on-chip debug capability. Someexamples of such instrumentation include:

• Logic and bus analyzer functions

• Bus protocol compliance monitors

• Memory buffers for debug and traceport data

• Cross-domain triggers and breakpoints

• Hardware run control of the CPU

• HW/SW time synchronization logic.

Furthermore, a single cable is able to per-form multiple functions, like debugginghardware, debugging software, as well asprogramming the FPGAs. This greatlysimplifies the lab setup making it mucheasier to exploit the debug advantages.

Summary: Platform FPGAs offer a clear-er, more cohesive, and overall more effec-tive debug strategy. Specifically, PlatformFPGAs offer up-front silicon access alongwith unprecedented visibility and controlof the processor and its peripherals resid-ing in the programmable fabric.

#5 – Top Tier Partnerships and Vendor Tools Support

In extending the concept of traditionalprogrammable logic to Platform FPGAs,certain critical technologies have had tobe developed or acquired. One of mostexciting aspects brought forth by FPGAvendors has been to successfully forge

72 Xcell Journal Summer 2002

Figure 1 - Software makes use of idle processor time.

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Perspective Industry Trend

76

strategic partnerships with vendors hold-ing various system technology compo-nents. Driven largely by the successes ofthe FPGA business models, leading ven-dors have been eager to partner in fulfill-ing the vision of building powerful pro-grammable systems platforms.

Areas of cooperation include partnershipsin the form of cutting-edge process tech-nology, powerful mainstream processingelements – such as RISC CPU, high-speed I/O – and other componentsdeemed of significance to a system designplatform. IBM, Conexant Systems, Inc.,Wind River Systems, and other high pro-file vendors are currently engaged in suchstrategic partnerships. What this means toyou is there is no need for these partnersto negotiate licensing, royalty, and inte-gration issues with individual vendors,thereby greatly reducing your engineering,management, and accounting overhead.

The appeal and draw of FPGAs hascaught the attention of independent SWtool vendors. Increasing numbers of ven-dors are able to sustain business modelsselling to FPGA customers. Several newvendors are setting up shop to write cus-tom tools to help enhance and exploit theunique capabilities of Platform FPGAs.

Summary: The FPGA business model hasattracted top-tier silicon and IP vendors toforge strategic partnerships to create pow-erful system design platforms. Softwarevendors are able to financially justifyinvestment in research and developmentleading to a continuous stream of anincreasing number of innovative solutions.

#6 – Application Space: Co-Design Flexibility

Programmable HW combined withprocessors on a single chip softens theHW/SW design boundary. By usinghardware-assisted architectural explo-ration, designers can optimally search forthe right HW and SW partitioning,which leads to the increased probabilityof being able to meet performance andarea targets. Sequential computing,exception handling, and control func-

tions, for instance, programmed in HWcould be implemented in SW running onthe processor to save silicon.

On the other hand, SW structures andalgorithms – which can be broken intoparallel, non-blocking processes – canachieve significant speed and datathroughput improvements by implement-ing them in HW. In fact, software engi-neers represent a new and emerging mar-ket for Platform FPGAs. Aided by designtools, it is now easier than ever for SWengineers to explore concepts of softwareacceleration via HW. Both hardware andfirmware are reprogrammable and fieldupgradeable, which enables the develop-ment and deployment of several productgenerations from one base. This translatesinto a much broader applicability thanASICs and ASSPs.

In addition to being suitable for buildingcomplex embedded applications, HW engi-neers can utilize an otherwise idle processorto run relevant portions of their designalgorithms or control logic. As Figure 1shows, the CPU can serve as a simplemicrocontroller running a single-threadedapplication. PLD vendors add value byproviding software device drivers andlibrary functions for rapid implementationwithout requiring the HW engineer to havedetailed knowledge of SW practices.

Summary: The Platform FPGAs provide themost flexible co-design platform by enablingdynamic HW-SW design partitioning.

#7 – Risk Management

When compared to Platform FPGAs, ASICSOCs present a huge design risk. Withmore variables and issues to worry about,and with limited debug capabilitieswhen mistakes are found,ASIC designers are

forced to either resolve problems subopti-mally in software, or in the worst case sce-nario, they are forced to respin the silicon atgreat cost and loss of time to market.

Reprogrammability comes up big here.Programmable platforms allow earlyaccess to silicon. Engineers can validateperformance and functionality in real sil-icon, leading to greater confidence in thereliability of the completed system. Theprogrammability of the platform allowsitself to be debugged and upgraded evenafter the system has been deployed. Thishelps promote and protect the time-to-market advantage by alleviating a largepart of the risk.

Summary: Programmable PlatformFPGAs provide better control over thelife cycle management of products byminimizing the cost and time penalty fordesign errors and specification changes.

Conclusion

In an era when SOCs continue to domi-nate mainstream design, Platform FPGAsare emerging to take a share of the spot-light from ASICs. While ASIC SOCs haveand will continue to be strong in certainsegments – like low power, small form fac-tor, and high-volume, cost-sensitive con-sumer electronic gadgets – an increasingrange of other infrastructure applicationsin areas such as networking, telecommu-nications, industrial electronics, and datastorage have compelling reasons to moveto a programmable platform.

Summer 2002 Xcell Journal 73

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CoolRunner-II CPLD Family

Advance Product SpecificationDS090 (v1.0) January 3, 2002

Features• Optimized for 1.8V systems

- Industry’s fastest low power CPLD- Static Icc of less than 100 microamps at all times- Densities from 32 to 512 macrocells

• Industry’s best 0.18 micron CMOS CPLD- Optimized architecture for effective logic synthesis- Multi-voltage I/O operation — 1.5V to 3.3V

• Advanced system features- Fastest in system programming

· 1.8V ISP using IEEE 1532 (JTAG) interface- IEEE1149.1 JTAG Boundary Scan Test- Optional Schmitt trigger input (per pin)- Unsurpassed low power management- FZP 100% CMOS product term generation- DataGATE external signal control- Flexible clocking modes

· Optional DualEDGE triggered registers· Clock divider (÷ 2,4,6,8,10,12,14,16)· CoolCLOCK

- Global signal options with macrocell control· Multiple global clocks with phase selection per

macrocell· Multiple global output enables· Global set/reset

- Abundant product term clocks, output enables andset/resets

- Efficient control term clocks, output enables andset/resets for each macrocell and shared acrossfunction blocks

- Advanced design security- Open-drain output option for Wired-OR and LED

drive- Optional bus-hold or weak pullup on selected I/O

pins- Optional configurable grounds on unused I/Os- Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and 3.3V logic levels on all parts

· SSTL2-1,SSTL3-1, and HSTL-1 on 128 macro-cell and denser devices

- PLA architecture· Superior pinout retention· 100% product term routability across function

block- Hot pluggable- Wide package availability including fine pitch:

· Chip Scale Package (CSP) BGA, Fine LineBGA, TQFP, PQFP, VQFP, and PLCC packages

- Design entry/verification using Xilinx and industrystandard CAE tools

- Free software support for all densities using XilinxWebPACK™ or WebFITTER™ tools

- Industry leading nonvolatile 0.18 micron CMOSprocess

- Guaranteed 1,000 program/erase cycles- Guaranteed 20 year data retention

Family OverviewXilinx CoolRunner™-II CPLDs deliver the high speed andease of use associated with the XC9500/XL/XV CPLD fam-ily with the extremely low power versatility of the XPLA3™family in a single CPLD. This means that the exact sameparts can be used for high-speed data communications/computing systems and leading edge portable products,with the added benefit of In System Programming. Lowpower consumption and high-speed operation are com-bined into a single family that is easy to use and cost effec-tive. Xilinx patented Fast Zero Power™ (FZP) architectureinherently delivers extremely low power performance with-out the need for any special design measures. Clockingtechniques and other power saving features extend theusers’ power budget. The design features are supportedstarting with Xilinx ISE 4.1i, WebFITTER, and ISE Web-PACK.

Table 1 shows the macrocell capacity and key timingparameters for the CoolRunner-II CPLD family.

R

©2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

74 Xcell Journal Summer 2002

Table 1: CoolRunner-II CPLD Family Parameters

XC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512

Macrocells 32 64 128 256 384 512

Max I/O 33 64 100 184 240 270

TPD (ns) 3.5 4.0 4.5 5.0 5.5 6.0

TSU (ns) 1.7 2.0 2.1 2.2 2.3 2.4

TCO (ns) 2.8 3.0 3.4 3.8 4.2 4.6

FSYSTEM (MHz) 303 270 244 204 189 222

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CoolRunner-II CPLD FamilyR

Table 2 shows the CoolRunner-II CPLD package offeringwith corresponding I/O count. All packages are surfacemount, with over half of them being ball-grid technologies.The ultra tiny packages permit maximum functional capacityin the smallest possible area. The CMOS technology used inCoolRunner-II CPLDs generates minimal heat, allowing theuse of tiny packages during high-speed operation.

There are at least two densities present in each packagewith three in the VQ100 (100-pin 1.0mm QFP) and TQ144(144-pin 1.4mm QFP), and in the FT256 (256-ball 1.0mmspacing FLBGA). The FT256 is particularly important forslim dimensioned portable products with mid- to high-den-sity logic requirements.

Table 2: CoolRunner-II CPLD Family Packages and I/O Count

XC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512

PC44 33 33 - - - -

VQ44 33 33 - - - -

CP56 33 45 - - - -

VQ100 - 64 80 80 - -

CP132 - - 100 106 - -

TQ144 - - 100 118 118 -

PQ208 - - - 173 173 173

FT256 - - - 184 212 212

FG324 - - - - 240 270

Table 3: CoolRunner-II CPLD Family Features

XC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512

IEEE 1532

I/O banks 1 1 2 2 4 4

Clock division - -

Clock doubling

DataGATE - -

LVTTL

LVCMOS33, 25, 18, and 1.5V I/O

SSTL2-1 - -

SSTL3-1 - -

HSTL-1 - -

Configurable ground

Quadruple data security

Open drain outputs

Hot plugging

Table 3 details the distribution of advanced features acrossthe CoolRunner-II CPLD family. The family has uniformbasic features with advanced features included in densitieswhere they are most useful. For example, it is very unlikelythat four I/O banks are needed on 32 and 64 macrocellparts, but very likely they are for 384 and 512 macrocellparts. The I/O banks are groupings of I/O pins using any one

of a subset of compatible voltage standards that share thesame VCCIO level. (See Table 4 for a summary ofCoolRunner-II I/O standards.) The clock division capabilityis less efficient on small parts, but more useful and likely tobe used on larger ones. DataGATE, an ability to block andlatch inputs to save power, is valuable in larger parts, butbrings marginal benefit to small parts.

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Architecture Description

CoolRunner-II CPLD is a highly uniform family of fast, lowpower CPLDs. The underlying architecture is a traditionalCPLD architecture combining macrocells into FunctionBlocks (FBs) interconnected with a global routing matrix, theXilinx Advanced Interconnect Matrix (AIM). The FunctionBlocks use a Programmable Logic Array (PLA) configurationwhich allows all product tems to be routed and sharedamong any of the macrocells of the FB. Design software canefficiently synthesize and optimize logic that is subsequent-ly fit to the FBs and connected with the ability to utilize avery high percentage of device resources. Design changesare easily and automatically managed by the software,which exploits the 100% routability of the ProgrammableLogic Array within each FB. This extremely robust buildingblock delivers the industry’s highest pinout retention, under

very broad design conditions. The architecture will beexplained by expanding the detail as we discuss theunderlying Function Blocks, logic and interconnect.

The design software automatically manages these deviceresources so that users can express their designs usingcompletely generic constructs without knowledge of thesearchitectural details. More advanced users can takeadvantage of these details to more thoroughly understandthe software’s choices and direct its results.

Figure 1 shows the high-level architecture wherebyFunction Blocks attach to pins and interconnect to eachother within the internal interconnect matrix. Each FB con-tains 16 macrocells. The BSC path is the JTAG BoundaryScan Control path. The BSC and ISP block has the JTAGcontroller and In-System Programming Circuits.

Figure 1: CoolRunner-II CPLD Architecture

FunctionBlock 1

FunctionBlock n

PLA PLA

I/O B

lock

s

I/O B

lock

s

16 16

40 40

16 FB 16 FB

16 16

I/O Pin MC1MC2

MC16

MC1MC2

MC16

DS090_01_121201

AIM

I/O Pin

I/O Pin

Fast Inputs

BSC and ISP

Clock and Control Signals

BSC Path

Fast Inputs

I/O PinI/O Pin

I/O Pin

JTAG

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Summer 2002 Xcell Journal 77

Function Block

The CoolRunner-II CPLD Function Blocks contain 16macrocells, with 40 entry sites for signals to arrive for logiccreation and connection. The internal logic engine is a 56product term PLA. All Function Blocks, regardless of thenumber contained in the device, are identical. For a high-level view of the Function Block, see Figure 2.

At the high level, it is seen that the product terms (p-terms)reside in a programmable logic array (PLA). This structure isextremely flexible, and very robust when compared to fixedor cascaded product term function blocks.

Classic CPLDs typically have a few product terms availablefor a high-speed path to a given macrocell. They rely oncapturing unused p-terms from neighboring macrocells toexpand their product term tally, when needed. The result ofthis architecture is a variable timing model and the possibil-ity of stranding unusable logic within the FB.

The PLA is different — and better. First, any product termcan be attached to any OR gate inside the FB macrocell(s).Second, any logic function can have as many p-terms asneeded attached to it within the FB, to an upper limit of 56.Third, product terms can be re-used at multiple macrocell

OR functions so that within a FB, a particular logical prod-uct need only be created once, but can be re-used up to16 times within the FB. Naturally, this plays well with thefitting software, which identifies product terms that can beshared.

The software places as many of those functions as it caninto FBs, so it happens for free. There is no need to forcemacrocell functions to be adjacent or any other restrictionsave residing in the same FB, which is handled by thesoftware. Functions need not share a common clock,common set/reset or common output enable to take fulladvantage of the PLA. Also, every product term arriveswith the same time delay incurred. There are no cascadetime adders for putting more product terms in the FB.When the FB product term budget is reached, there is asmall interconnect timing penalty to route signals to anoth-er FB to continue creating logic. Xilinx design softwarehandles all this automatically.

MacrocellThe CoolRunner-II CPLD macrocell is extremely efficientand streamlined for logic creation. Users can develop sumof product (SOP) logic expressions that comprise up to 40inputs and span 56 product terms within a single functionblock. The macrocell can further combine the SOP expres-sion into an XOR gate with another single p-term expres-sion. The resulting logic expression’s polarity is also selec-table. As well, the logic function can be pure combinatorialor registered, with the storage element operating selec-tably as a D or T flip-flop, or transparent latch. Available ateach macrocell are independent selections of global, func-tion block level or local p-term derived clocks, sets, resets,and output enables. Each macrocell flip-flop is config-urable for either single edge or DualEDGE clocking, pro-viding either double data rate capability or the ability to dis-tribute a slower clock (thereby saving power). For singleedge clocking or latching, either clock polarity may beselected per macrocell. CoolRunner-II macrocell detailsare shown in Figure 3. Note that in Figure 3, standard logicsymbols are used except the trapezoidal multiplexers haveinput selection from statically programmed configurationselect lines (not shown). Xilinx application note XAPP376gives a detailed explanation of how logic is created in theCoolRunner-II CPLD family.

Figure 2: CoolRunner-II CPLD Function Block

PLA 1640

3

MC1

Out

To AIM

GlobalClocks

GlobalSet/Reset

MC2

MC16

DS090_02_101001

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78 Xcell Journal Summer 2002

When configured as a D-type flip-flop, each macrocell hasan optional clock enable signal permitting state hold while aclock runs freely. Note that Control Terms (CT) are availableto be shared for key functions within the FB, and are gener-ally used whenever the exact same logic function would berepeatedly created at multiple macrocells. The CT productterms are available for FB clocking (CTC), FB asynchronousset (CTS), FB asynchronous reset (CTR), and FB outputenable (CTE).

Any macrocell flip-flop can be configured as an input regis-ter or latch, which takes in the signal from the macrocell’sI/O pin, and directly drives the AIM. The macrocell combina-tional functionality is retained for use as a buried logic nodeif needed.

Advanced Interconnect Matrix (AIM)The Advanced Interconnect Matrix is a highly connected lowpower rapid switch. The AIM is directed by the software todeliver up to a set of 40 signals to each FB for the creationof logic. Results from all FB macrocells, as well as, all pininputs circulate back through the AIM for additional connec-tion available to all other FBs as dictated by the designsoft-

ware. The AIM minimizes both propagation delay andpower as it makes attachments to the various FBs.

I/O BlockI/O blocks are primarily transceivers. However, each I/O iseither automatically compliant with standard voltage rangesor can be programmed to become so.

In addition to voltage levels, each input can selectivelyarrive through Schmitt-trigger inputs. This adds a small timedelay, but substantially reduces noise on that input pin.Hysteresis also allows easy generation of external clock cir-cuits. The Schmitt-trigger path is best seen in Figure 4.

Outputs can be directly driven, 3-stated or open-drain con-figured. A choice of slow or fast slew rate output signal isalso available. Table 4 summarizes various supported volt-age standards associated with specific part capacities. Allinputs and disabled outputs are voltage tolerant up to 3.3V.

Figure 4 details the I/O pin, where it is noted that the inputsrequiring comparison to an external reference voltage(SSTL2-1, SSTL3-1, HSTL-1) are available on the 128macrocell and denser parts.

Figure 3: CoolRunner-II CPLD Macrocell

GCK0GCK1GCK2CTC

PTC

PTC

DS090_03_121201

49 P-termsTo PTA, PTB, PTC of other macrocells

CTC, CTR,CTS, CTE

From AIM

4 P-terms

PTA

Fast Inputfrom

I/O BlockFeedback

to AIM

PTB

PTC

PLA OR Term

PTACTSGSRGND

GND

VCC

R

D/T

CE

CK

FIFLatchDualEDGE

QS

40

To I/O Block

PTACTRGSRGND

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Summer 2002 Xcell Journal 79

Table 4 summarizes the single ended I/O standard supportand shows which standards require VREF values and boardtermination. VREF detail is given in specific data sheets.

Output BankingCPLDs are widely used as voltage interface translators. Tothat end, the output pins are grouped in large banks. Thesmallest parts are not banked, so all signals will have thesame output swing for 32 and 64 macrocell parts. Themedium parts (128 and 256 macrocell) support two outputbanks. With two, the outputs will switch to one of two select-ed output voltage levels, unless both banks are set to thesame voltage. The larger parts (384 and 512 macrocell)support four output banks split evenly. They can supportgroupings of one, two, three or four separate output voltagelevels. This kind of flexibility permits easy interfacing to3.3V, 2.5V, 1.8V, and 1.5V in a single part.

DataGATELow power is the hallmark of CMOS technology. OtherCPLD families use a sense amplifier approach to creatingproduct terms, which always has a residual current com-ponent being drawn. This residual current can be severalhundred milliamps, making them unusable in portablesystems. CoolRunner-II CPLDs use standard CMOSmethods to create the CPLD architecture and deliver thecorresponding low current consumption, without doingany special tricks. However, sometimes designers wouldlike to reduce their system current even more by selec-tively disabling circuitry not being used.

The patented DataGATE technology was developed to per-mit a straightforward approach to additional power reduc-tion. Each I/O pin has a series switch that can block thearrival of free running signals that are not of interest.Signals that serve no use may increase power consump-tion, and can be disabled. Users are free to do their design,then choose sections to participate in the DataGATE func-tion. DataGATE is a logic function that drives an assertionrail threaded through the medium and high-densityCoolRunner-II CPLD parts. Designers can select inputs tobe blocked under the control of the DataGATE function,effectively blocking controlled switching signals so they donot drive internal chip capacitances. Output signals that donot switch, are held by the bus hold feature. Any set of inputpins can be chosen to participate in the DataGATE function.Figure 5 shows the familiar CMOS ICC versus switchingfrequency graph. With DataGATE, designers can approachzero power, should they choose to, in their designs

Figure 6 shows how DataGATE basically works. One I/Opin drives the DataGATE Assertion Rail. It can have anydesired logic function on it. It can be as simple as mappingan input pin to the DataGATE function or as complex as a

Figure 4: CoolRunner-II CPLD I/O Block Diagram

DS090_04_121201

VREF

Available on 128 MacrocellDevices and Larger

Hysteresis

BusHold

WeakPullup

From Macrocell

EnabledCTEPTB

GTS[0:3]CGND

Open DrainDisabled

VCCIO4

To AIM

To MacrocellFast Input

Table 4: CoolRunner-II CPLD I/O Standard Summary

I/O Standard VCCIO

Input VREF

Board Termination Voltage (VTT)

LVTTL 3.3 N/A N/A

LVCMOS33 3.3 N/A N/A

LVCMOS25 2.5 N/A N/A

LVCMOS18 1.8 N/A N/A

1.5V I/O 1.5 N/A N/A

HSTL-1 1.5 0.75 0.75

SSTL2-1 2.5 1.25 1.25

SSTL3-1 3.3 1.5 1.5

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80 Xcell Journal Summer 2002

counter or state machine output driving the DataGATE I/Opin through a macrocell. When the DataGATE rail isasserted low, any pass transistor switch attached to it isblocked. Note that each pin has the ability to attach to theAIM through a DataGATE pass transistor, and thus beblocked. A latch automatically captures the state of the pinwhen it becomes blocked. The DataGATE Assertion Railthreads throughout all possible I/Os, so each can partici-pate if chosen. Note that one macrocell is singled out todrive the rail, and that macrocell is exposed to the outside

world through a pin, for inspection. If DataGATE is notneeded, this pin is an ordinary I/O.

Figure 5: CMOS ICC vs. Switching Frequency Curve

DS090_05_101001

ICC

Frequency0

Figure 6: DataGATE Architecture (output drivers not shown)

PLA

MC1MC2

MC16

DS090_06_111201

PLA

PLA

DataGATE Assertion Rail

PLA

AIMMC1MC2

MC16

MC1MC2

MC16

MC1MC2

MC16

To AIM

Latch

To AIM

Latch

To AIMTo AIM

LatchLatch

To AIM

Latch

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CoolRunner-II CPLD FamilyR

Summer 2002 Xcell Journal 81

Global SignalsGlobal signals, clocks (GCK), sets/resets (GSR) and outputenables (GTS), are designed to strongly resemble eachother. This approach enables design software to make thebest utilization of their capabilities. Each global capability issupplemented by a corresponding product term version.Figure 7 shows the common structure of the global signaltrees. The pin input is buffered, then drives multiple internalglobal signal traces to deliver low skew and reduce loadingdelays. The DataGATE assertion rail is also a global signal.

Additional Clock Options: Division,DualEDGE, and CoolCLOCKDivision

Circuitry has been included in the CoolRunner-II CPLDarchitecture to divide one externally supplied global clockby standard values. Division by 2,4,6,8,10, 12, 14 and 16are the options (see Figure 8). This capability is suppliedon the GCK2 pin. The resulting clock produced will be50% duty cycle for all possible divisions. Note that aSynchronous Reset is included to guarantee no runtclocks can get through to the global clock nets. Note thatagain, the signal is buffered and driven to multiple traceswith minimal loading and skew.

DualEDGE

Each macrocell has the ability to double its input clockswitching frequency. Figure 9 shows the macrocell flip-flop with the DualEDGE option (doubled clock) at eachmacrocell. The source to double can be a control termclock, a product term clock or one of the available globalclocks. The ability to switch on both clock edges is vitalfor a number of synchronous memory interface applica-tions as well as certain double data rate I/O applications.

CoolCLOCK

In addition to the DualEDGE flip-flop, additional powersavings can be had by combining the clock division cir-cuitry with the DualEDGE circuitry. This capability iscalled CoolCLOCK and is designed to reduce clockingpower within the CPLD. Because the clock net can be anappreciable power drain, the clock power can be reducedby driving the net at half frequency, then doubling theclock rate using DualEDGE triggering at the macrocells.Figure 10 shows how CoolCLOCK is created by internalclock cascading with the divider and DualEDGE flip-flopworking together.

Figure 7: Global Clocks (GCK), Sets/Resets (GSR) and Output Enables (GTS)

DS090_07_101001

Figure 8: Clock Division Circuitry for GCK2

DS090_08_12120

ClockIn

2 4 6 8

10 12 14 16

GCK2

Synch Reset

Synch Rst

Page 82: Xcell Journal: Issue 43

CoolRunner-II CPLD FamilyR

82 Xcell Journal Summer 2002

Design SecurityDesigns can be secured during programming to preventeither accidental overwriting or pattern theft via readback.Four independent levels of security are provided on-chip,eliminating any electrical or visual detection of configurationpatterns. These security bits can be reset only by erasingthe entire device. Additional detail is omitted intentionally.

Timing ModelFigure 11 shows the CoolRunner-II CPLD timing model. Itrepresents one aspect of the overall architecture from a tim-

ing viewpoint. Each little block is a time delay that a signalwill incur if the signal passes through such a resource.Timing reports are created by tallying the incremental sig-nal delays as signals progress within the CPLD. Softwarecreates the timing reports after a design has beenmapped onto the specific part, and knows the specificdelay values for a given speed grade. Equations for thehigher level timing values (i.e., TPD and FSYSTEM) areavailable. Table 5 summarizes the individual parametersand provides a brief definition of their associated func-tions. Xilinx application note XAPP375 details theCoolRunner-II CPLD family timing with several examples.

Figure 9: Macrocell Clock Chain with DualEDGE Option Shown

Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option

GCK0GCK1GCK2CLK_CT

PTC

PTCDS090_09_121201

D/T

CE

CK

FIFLatchDualEDGE

Q

GCK0GCK1GCK2CTC

PTC

PTC

DS090_10_121201

D/T

CE

CK

FIFLatchDualEDGE

Q

ClockIn

2 4 6 8

10 12 14 16

GCK2

Synch Reset

Synch Rst

Page 83: Xcell Journal: Issue 43

CoolRunner-II CPLD FamilyR

Summer 2002 Xcell Journal 83

Figure 11: CoolRunner-II CPLD Timing Model

D/T

S/R

TF

TSUI THI

TCOI

TRAI

TAOI

TECSU

TECHO TOUT

TSLEW

TEN

DS090_11_12

TOEM

TPDITLOGI2

TLOGI1TIN

THYS

CE

TFIN

THYS TCT

TGCK

THYS TCDIV

TGSR

THYS

TGTS

THYS

Table 5: Timing Parameter Definitions

Symbol Parameter

Buffer Delays

TlN Input Buffer Delay

TFIN Fast data register input delay

TGCK Global clock (GCK) buffer delay

TGSR Global set/reset (GSR) buffer delay

TGTS Global output enable (GTS) buffer delay

TOUT Output buffer delay

TEN Output buffer enable/disable delay

TSLEW Output buffer slew rate control delay

P-term Delays

TCT Control Term delay (single PT or FB-CT)

TLOGI1 Single P-term logic delay

TLOGI2 Multiple P-term logic delay adder

Macrocell Delays

TPDI Macro cell input to output valid

TSUI Macro register setup before clock

THI Macro register hold after clock

TECSU Macro register enable clock setup time

TECHO Macro register enable clock hold time

TCOI Macro register clock to output valid

TRAI Macro register set/reset recovery before clock

TAOI Macro register set/reset to output valid

TCDIV Clock divider delay adder

THYS Hysteresis selection delay adder

Feedback Delays

TF Feedback delay

TOEM Macrocell to Global OE delay

Table 5: Timing Parameter Definitions (Continued)

Symbol Parameter

Page 84: Xcell Journal: Issue 43

CoolRunner-II CPLD FamilyR

84 Xcell Journal Summer 2002

In System ProgrammingAll CoolRunner-II CPLD parts are 1.8V in system program-mable. This means they derive their programming voltageand currents from the 1.8V VCC (internal supply voltage)pins on the part. The VCCIO pins do not participate in thisoperation, as they may assume another voltage ranging ashigh as 3.3V down to 1.5V. A 1.8V VCC is required to prop-erly operate the internal state machines and charge pumpsthat reside within the CPLD to do the nonvolatile program-ming operations. Xilinx software is provided to deliver thebit-stream to the CPLD and drive the appropriate IEEE 1532protocol. To that end, there is a set of IEEE 1532 commandsthat are supported in the CoolRunner-II CPLD parts.Programming times are less than one second for 32 to 256macrocell parts. Programming times are less than four sec-onds for 384 and 512 macrocell parts.

JTAG InstructionsTable 6 shows the commands available to users. Thesesame commands may be used by third party ATE products,as well. The internal controllers can operate as fast as 66MHz. The JTAG interface buffers are powered by a dedicat-ed power pin, VCCAUX , which is independent of all othersupply pins.

Power-Up CharacteristicsCoolRunner-II CPLD parts must operate under the demandsof both the high-speed and the portable market places,therefore, they must support hot plugging for the high-speedworld and tolerate most any power sequence to its variousvoltage pins. They must also not draw excessivecurrent dur-

ing power-up initialization. To those ends, the generalbehavior is summarized as follows:

1. I/O pins are disabled until the end of power-up.

2. As supply rises, configuration bits transfer from non-volatile memory to SRAM cells.

3. As power up completes, the outputs become as con-figured (input, output, or I/O).

4. The process takes less than 25 ms and draws lessthan 5 mA of current.

I/O BankingCoolRunner-II CPLD 32 and 64 macrocell parts support asingle VCCIO rail that can range from 3.3V down to 1.5Voperation. Two VCCIO rails are supported on the 128 and256 macrocell parts where outputs on each rail can inde-pendently range from 3.3V down to 1.5V operation. FourVCCIO rails are supported on the 384 and 512 macrocellparts with each rail independently supporting any voltagebetween 3.3V and 1.5V. The VCC (internal supply voltage)for a CoolRunner-II CPLD must be maintained within 1.8V±5% for correct speed operation and proper in systemprogramming.

Mixed Voltage, Power Sequencing,and Hot PluggingAs mentioned in I/O Banking, CoolRunner-II CPLD partssupport mixed voltage I/O signals where signals within thesame bank can range from 3.3V down to 1.5V. The powerapplied to the VCCIO and VCC pins can occur in any orderand the CoolRunner-II CPLD will not be damaged.CoolRunner-II CPLDs can reside on boards where theboard is inserted into a “live” connector (hot plugged) andthe parts will be well-behaved as if powering up in a stan-dard way.

Development System SupportXilinx CoolRunner-II CPLDs are supported by all configura-tions of Xilinx standard release development software aswell as the freely available WebFITTER and ISE WebPACKsoftware available from www.xilinx.com. Third party devel-opment tools include synthesis tools from Cadence,Exemplar, Mentor Graphics, Synplicity, and Synopsys.

ATE SupportThird party ATE development support is available for bothprogramming and board/chip level testing. Vendors pro-viding this support include Hewlett-Packard, GenRad, andTeradyne. Other third party providers are expected todeliver solutions in the future.

Table 6: JTAG Instructions

Code Instruction Description

00000000 EXTEST Force boundary scan data onto outputs

00000011 PRELOAD Latch macrocell data into boundary scan cells

11111111 BYPASS Insert bypass register between TDI and TDO

00000010 INTEST Force boundary scan data onto inputs and feedbacks

00000001 IDCODE Read IDCODE

11111101 USERCODE Read USERCODE

11111100 HIGHZ Force output into high impedance state

11111010 CLAMP Latch present output state

Page 85: Xcell Journal: Issue 43

CoolRunner-II CPLD FamilyR

Summer 2002 Xcell Journal 85

Absolute Maximum Ratings(1)

Quality and Reliability Parameters

Revision HistoryThe following table shows the revision history for this document.

Symbol Parameter Min. Max. Unit

VCC Supply voltage(2) relative to GND –0.5 2.0 V

VI Input voltage(3) relative to GND –0.5 4.0 V

TJ Maximum junction temperature –40 125 ˚C

TSTR Storage temperature –65 150 ˚C

Notes: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional

operation at these or any other condition above those indicated in the operational and programming specification is not implied.2. The chip supply voltage should rise monotonically.3. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the

device pins may undershoot to –2.0V or overshoot to 3.5 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. The I/O voltage may never exceed 4.0V.

Symbol Parameter Min Max Units

TDR Data retention 20 - Years

NPE Program/erase cycles (Endurance) 1,000 - Cycles

VESD Electrostatic discharge 2,000 - Volts

Date Version Revision

01/03/02 1.0 Initial Xilinx release.

Page 86: Xcell Journal: Issue 43

Reference FPGAs

Xilinx FPGA Product Selection Matrix

86 Xcell Journal Summer 2002

CLB Resources BLK RAM CLK Resources I/O Features Speed

Syst

em G

ates

(see

not

e 1)

CLB

Arra

y (R

ow X

Col

)

Num

ber o

f Slic

es

Logi

c Ce

lls (s

ee n

ote

2)

CLB

Flip

-Flo

ps

Max

.Dist

ribut

ed R

AM B

its

# Bl

ock

RAM

Blo

cks

Bloc

k RA

M B

its

# De

dica

ted

Mul

tiplie

rs

DLL

Freq

uenc

y (m

in/m

ax)

# DL

L's

Freq

uenc

y Sy

nthe

sis

Phas

e Sh

ift

Digit

ally C

ontro

lled

Impe

danc

e

Num

ber o

f Diffe

rent

ial I/

O Pa

irs

Max

.I/O

I/O S

tand

ards

Com

mer

cial S

peed

Gra

des

(slo

wes

t to

fast

est)

Indu

stria

l Spe

ed G

rade

s(s

low

est t

o fa

stes

t)

Seria

l PRO

M F

amily

Conf

ig.M

emor

y (B

its)

Virtex-II Family — 1.5 VoltXC2V40 40K 8 x 8 256 576 512 8K 4 72K 4 24/420 4 DCM DCM YES 44 88XC2V80 80K 16 x8 512 1,152 1,024 16K 8 144K 8 24/420 4 DCM DCM YES 60 120XC2V250 250K 24 x16 1,536 3,456 3,072 48K 24 432K 24 24/420 8 DCM DCM YES 100 200XC2V500 500K 32 x 24 3,072 6,912 6,144 96K 32 576K 32 24/420 8 DCM DCM YES 132 264XC2V1000 1M 40 x 32 5,120 11,520 10,240 160K 40 720K 40 24/420 8 DCM DCM YES 216 432XC2V1500 1.5M 48 x 40 7,680 17,280 15,360 240K 48 864K 48 24/420 8 DCM DCM YES 264 528XC2V2000 2M 56 x 48 10,752 24,192 21,504 336K 56 1008K 56 24/420 8 DCM DCM YES 312 624XC2V3000 3M 64 x 56 14,336 32,256 28,672 448K 96 1728K 96 24/420 12 DCM DCM YES 360 720XC2V4000 4M 80 x 72 23,040 51,840 46,080 720K 120 2160K 120 24/420 12 DCM DCM YES 456 912XC2V6000 6M 96 x 88 33,792 76,032 67,584 1056K 144 2592K 144 24/420 12 DCM DCM YES 552 1104XC2V8000 8M 112 x 104 46,592 104,832 93,184 1456K 168 3024K 168 24/420 12 DCM DCM YES 554 1108Virtex-E Family — 1.8 VoltXCV50E 72K 16 x 24 768 1,728 1,536 24K 16 64K NA 25/350 8 YES YES NA 88 176XCV100E 128K 20 x 30 1,200 2,700 2,400 37.5K 20 80K NA 25/350 8 YES YES NA 98 196XCV200E 306K 28 x 42 2,352 5,292 4,704 73.5K 28 112K NA 25/350 8 YES YES NA 142 284XCV300E 412K 32 x 48 3,072 6,912 6,144 96K 32 128K NA 25/350 8 YES YES NA 158 316XCV400E 570K 40 x 60 4,800 10,800 9,600 150K 40 160K NA 25/350 8 YES YES NA 202 404XCV600E 986K 48 x 72 6,912 15,552 13,824 216K 72 288K NA 25/350 8 YES YES NA 256 512XCV1000E 1,569K 64 x 96 12,288 27,648 24,576 384K 96 384K NA 25/350 8 YES YES NA 330 660XCV1600E 2,188K 72 x 180 25,920 34,992 51,840 486K 144 576K NA 25/350 8 YES YES NA 362 724XCV2000E 2,542K 80 x 120 19,200 43,200 38,400 600K 160 640K NA 25/350 8 YES YES NA 402 804XCV2600E 3,264K 92 x 138 25,392 57,132 50,784 793.5K 184 736K NA 25/350 8 YES YES NA 402 804XCV3200E 4,074K 104 x 156 32,448 73,008 64,896 1014K 208 832K NA 25/350 8 YES YES NA 402 804Virtex-EM Family — 1.8 VoltXCV405E 1.31M 40 x 60 4,800 10,800 9,600 150K 140 560K NA 25/350 8 YES YES NA 202 404XCV812E 2.54M 56 x 84 9,408 21,168 18,816 294K 280 1120K NA 25/350 8 YES YES NA 278 556Spartan-IIE Family — 1.8 VoltXC2S50E 50K 16 x 24 768 1,728 1,536 24K 8 32K NA 25/320 4 YES YES NA 84 182XC2S100E 100K 20 x 30 1,200 2,700 2,400 37.5K 10 40K NA 25/320 4 YES YES NA 86 202XC2S150E 150K 24 x 36 1,728 3,888 3,456 54K 12 48K NA 25/320 4 YES YES NA 114 263XC2S200E 200K 28 x 42 2,352 5,292 4,704 73.5K 14 56K NA 25/320 4 YES YES NA 120 289XC2S300E 300K 32 x 48 3,072 6,912 6,144 96K 16 64K NA 25/320 4 YES YES NA 120 329Spartan-II Family — 2.5 VoltXC2S15 15K 8 x 12 192 432 384 6K 4 16K NA 25/200 4 YES YES NA NA 86XC2S30 30K 12 x 18 432 972 864 13.5K 6 24K NA 25/200 4 YES YES NA NA 132XC2S50 50K 16 x 24 768 1,728 1,536 24K 8 32K NA 25/200 4 YES YES NA NA 176XC2S100 100K 20 x 30 1,200 2,700 2,400 37.5K 10 40K NA 25/200 4 YES YES NA NA 196XC2S150 150K 24 x 36 1,728 3,888 3,456 54K 12 48K NA 25/200 4 YES YES NA NA 260XC2S200 200K 28 x 42 2,352 5,292 4,704 73.5K 14 56K NA 25/200 4 YES YES NA NA 284

LDT-25, LVPECL-33,LVDS-33, LVDS-25,

LVDSEXT-33, LVDSEXT-25,BLVDS-25, ULVDS-25,

LVTTL, LVCMOS33,LVCMOS25, LVCMOS18,

LVCMOS15, PCI33, PCI66,PCI-X, GTL, GTL+, HSTL I,HSTL II, HSTL III, HSTL IV,

SSTL21, SSTL211,SSTL3 I, SSTL3 II

LVTTL, LVCMOS2,LVCMOS18, PCI33,PCI66, GTL, GTL+,

HSTL I, HSTL III, HSTL IV,SSTL3 I, SSTL3 II,

SSTL21, SSTL211, BLVDS,LVDS, LVPECL

Same AsVirtex-E

LVTTL,LVCMOS2,LVCMOS18,PCI33, PCI66, GTL, GTL+,

HSTL I,HSTL III,HSTL IV,SSTL3 I,SSTL3 II,SSTL2 I,SSTL2 II, AGP-2X,CTT, LVDS, BLVDS, LVPECL

LVTTL, LVCMOS2,PCI33 (3.3V & 5V),

PCI66 (3.3V), GTL, GTL+,HSTL I, HSTL III, HSTL IV,SSTL3 I, SSTL3 II, SSTL2 I,

SSTL2 II, AGP-2X, CTT

-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5

-4 -5 -4

-6 -7 -8 -6 -7-6 -7 -8 -6 -7-6 -7 -8 -6 -7-6 -7 -8 -6 -7-6 -7 -8 -6 -7-6 -7 -8 -6 -7-6 -7 -8 -6 -7-6 -7 -8 -6 -7-6 -7 -8 -6 -7-6 -7 -8 -6 -7-6 -7 -8 -6 -7

-6 -7 -8 -6 -7-6 -7 -8 -6 -7

-6 -7 -6 -6 -7 -6-6 -7 -6 -6 -7 -6 -6 -7 -6

-5 -6 -5-5 -6 -5-5 -6 -5-5 -6 -5-5 -6 -5-5 -6 -5

ISP

ISP

ISP

ISP

ISP

OTP

OTP

OTP

OTP

OTP

.15um Eight Layer Metal Process

.18um Six Layer Metal Process

.18um Six Layer Metal Process

.18um Six Layer Metal Process

.22/.18um Six Layer Metal Process

0.4M0.6M1.7M2.8M4.1M5.7M7.5M10.5M15.7M21.9M29.1M

0.6M0.9M1.45M1.88M2.7M3.97M6.6M8.4M10.2M13M

16.3M

3.43M6.52M

0.6M0.9M1.1M1.4M1.9M

0.2M0.4M0.6M0.8M1.1M1.4M

Note: 1. System Gates include 20-30% of CLBs used as RAM Important: Verify all Data with Device Data Sheet2. A Logic Cell is defined as a 4 input LUT and a registerDCM – Digital Clock Management

XC2VP2 4 0 16 x 22 1,408 44 12 12 216 4 204

XC2VP4 4 1 40 x 22 3,008 94 28 28 504 4 348

XC2VP7 8 1 40 x 34 4,928 154 44 44 792 4 396

XC2VP20 8 2 56 x 46 9,280 290 88 88 1,584 8 564

XC2VP50 16 4 88 x 70 22,592 706 216 216 3,888 8 852

Device

Rocket I/O™

TransceiverBlocks

PowerPC™

ProcessorBlocks

ArrayRow x Col Slices

MaximumDistributedRAM Kbits

18 x 18 BitMultiplier

Blocks18 KbitBlocks

MaxBlock RAM

Kbits DCMsMax

I/O Pads

CLB (1 CLB = 4 slices = Max 128 bits) Block SelectRAM

Page 87: Xcell Journal: Issue 43

CLB Resources BLK RAM CLK Resources I/O Features Speed

Syst

em G

ates

(see

not

e 1)

CLB

Arra

y (R

ow X

Col

)

Num

ber o

f Slic

es

Logi

c Ce

lls (s

ee n

ote

2)

CLB

Flip

-Flo

ps

Max

.Dist

ribut

ed R

AM B

its

# Bl

ock

RAM

Bloc

k RA

M (k

bits

)

# De

dica

ted

Mul

tiplie

rs

DLL

Freq

uenc

y (m

in/m

ax)

# DL

L's

Freq

uenc

y Sy

nthe

sis

Phas

e Sh

ift

Digit

ally C

ontro

lled

Impe

danc

e

Num

ber o

f Diffe

rent

ial I/

O Pa

irs

Max

.I/O

I/O S

tand

ards

Com

mer

cial S

peed

Gra

des

(slo

wes

t to

fast

est)

Indu

stria

l Spe

ed G

rade

s(s

low

est t

o fa

stes

t)

Seria

l PRO

M F

amily

Conf

ig.M

emor

y (B

its)

Spartan-IIE Family — 1.8 VoltXC2S50E 50K 16 x 24 768 1,728 1,536 24K 8 32K NA 25/320 4 YES YES NA 84 182XC2S100E 100K 20 x 30 1,200 2,700 2,400 37.5K 10 40K NA 25/320 4 YES YES NA 86 202XC2S150E 150K 24 x 36 1,728 3,888 3,456 54K 12 48K NA 25/320 4 YES YES NA 114 263XC2S200E 200K 28 x 42 2,352 5,292 4,704 73.5K 14 56K NA 25/320 4 YES YES NA 120 289XC2S300E 300K 32 x 48 3,072 6,912 6,144 96K 16 64K NA 25/320 4 YES YES NA 120 329Spartan-II Family — 2.5 VoltXC2S15 15K 8 x 12 192 432 384 6K 4 16K NA 25/200 4 YES YES NA NA 86XC2S30 30K 12 x 18 432 972 864 13.5K 6 24K NA 25/200 4 YES YES NA NA 132XC2S50 50K 16 x 24 768 1,728 1,536 24K 8 32K NA 25/200 4 YES YES NA NA 176XC2S100 100K 20 x 30 1,200 2,700 2,400 37.5K 10 40K NA 25/200 4 YES YES NA NA 196XC2S150 150K 24 x 36 1,728 3,888 3,456 54K 12 48K NA 25/200 4 YES YES NA NA 260XC2S200 200K 28 x 42 2,352 5,292 4,704 73.5K 14 56K NA 25/200 4 YES YES NA NA 284

LVTTL,LVCMOS2,LVCMOS18,PCI33, PCI66, GTL, GTL+,

HSTL I,HSTL III,HSTL IV,SSTL3 I,SSTL3 II,SSTL2 I,SSTL2 II, AGP-2X,CTT, LVDS, BLVDS, LVPECL

LVTTL, LVCMOS2,PCI33 (3.3V & 5V),

PCI66 (3.3V), GTL, GTL+,HSTL I, HSTL III, HSTL IV,SSTL3 I, SSTL3 II, SSTL2 I,

SSTL2 II, AGP-2X, CTT

-6 -7 -6 -6 -7 -6-6 -7 -6 -6 -7 -6 -6 -7 -6

-5 -6 -5-5 -6 -5-5 -6 -5-5 -6 -5-5 -6 -5-5 -6 -5

ISP

ISP

OTP

OTP

.18um Six Layer Metal Process

.22/.18um Six Layer Metal Process

0.6M0.9M1.1M1.4M1.9M

0.2M0.4M0.6M0.8M1.1M1.4M

Note: 1. System Gates include 20-30% of CLBs used as RAM2. A Logic Cell is defined as a 4 input LUT and a registerDCM – Digital Clock ManagementImportant: Verify all Data with Device Data Sheet

Numbers indicated in the matrix are the maximum number of user I/O’s forthat package and device combination.

XC2S

50E

XC2S

100E

XC2S

150E

XC2S

200E

XC2S

300E

XC2S

15

XC2S

30

XC2S

50

XC2S

100

XC2S

150

XC2S

200

Pins Body Size 182 202 263 289 329 86 132 176 196 260 284

PQFP Packages (PQ)

208 28 x 28 mm 146 146 146 146 146 132 140 140 140 140

VQFP Packages (VQ)

100 14 x 14 mm 60 60

TQFP Packages (TQ)

144 20 x 20 mm 102 102 86 92 92 92

Chip Scale Packages — wire-bond chip-scale BGA (0.8 mm ball spacing)

144 12 x 12 mm 86 92

FGA Packages (FT) — wire-bond fine-pitch thin BGA (1.0 mm ball spacing)

256 17 x 17 mm 182 182 182 182 182

FGA Packages (FG) — wire-bond fine-pitch BGA (1.0 mm ball spacing)

256 17 x 17 mm 176 176 176 176

456 23 x 23 mm 202 263 289 329 196 260 284

Spartan-IIE (1.8V) Spartan-II (2.5V)

I/O’s

PACKAGE OPTIONS AND USER I/O

Xilinx Spartan FPGAs

Reference FPGAs

Summer 2002 Xcell Journal 87

Page 88: Xcell Journal: Issue 43

Xilinx Configuration Storage Solutions

5 Xcell Journal Spring 2002

Xilinx Home Pagehttp://www.xilinx.com

Xilinx Online Support

http://www.xilinx.com/support/support.htm

Xilinx IP Centerhttp://www.xilinx.com/ipcenter/index.htm

System ACE CF up to8 Gbit 2 25cm2 No JTAGUnlimited Yes Yes

Yes 30 Mbit/secCompactFlash

System ACE

MPM

Mem

ory

Den

sity

Num

ber

of

Com

pone

nts

Min

boa

rd s

pace

Reference FPGAs

88 Xcell Journal Summer 2002

XCV5

0E

XCV1

00E

XCV2

00E

XCV3

00E

XCV4

00E

XCV6

00E

XCV1

000E

XCV1

600E

XCV2

000E

XCV2

600E

XCV3

200E

XCV4

05E

XCV8

12E

XC2V

40

XC2V

80

XC2V

250

XC2V

500

XC2V

1000

XC2V

1500

XC2V

2000

XC2V

3000

XC2V

4000

XC2V

6000

XC2V

8000

XC2S

50E

XC2S

100E

XC2S

150E

XC2S

200E

XC2S

300E

XC2S

15

XC2S

30

XC2S

50

XC2S

100

XC2S

150

XC2S

200

Pins Body Size 88 120 200 264 432 528 624 720 912 1104 1296 176 176 284 316 404 512 660 724 804 804 804 404 556 182 202 263 289 329 86 132 176 196 260 284

PQFP Packages (PQ)

208 28 x 28 mm 146 146 146 146 146 132 140 140 140 140

240 32 x 32 mm 158 158 158 158 158 158 158

HQFP Packages (HQ)

240 32 x 32 mm 158 158

VQFP Packages (VQ)

100 14 x 14 mm 60 60

TQFP Packages (TQ)

144 20 x 20 mm 102 102 86 92 92 92

Chip Scale Packages — wire-bond chip-scale BGA (0.8 mm ball spacing)

144 12 x 12 mm 88 92 92 94 94 94 86 92

BGA Packages (BG) — wire-bond standard BGA (1.27 mm ball spacing)

352 40 x 40 mm 196 260 260

432 40 x 40 mm 316 316 316

560 42.5 x 42.5 mm 404 404 404 404 404 404 404

575 31 x 31 mm 328 392 408

728 35 x 35 mm 456 516

FGA Packages (FT) — wire-bond fine-pitch thin BGA (1.0 mm ball spacing)

256 17 x 17 mm 182 182 182 182 182

FGA Packages (FG) — wire-bond fine-pitch BGA (1.0 mm ball spacing)

256 17 x 17 mm 88 120 172 172 172 176 176 176 176 176 176 176 176

456 23 x 23 mm 200 264 324 284 312 202 263 289 329 196 260 284

676 27 x 27 mm 392 456 484 404 444 404

680 40 x 40 mm 512 512 512 512

860 42.5 x 42.5 mm 660 660 660

900 31 x 31 mm 512 660 700 556

1156 35 x 35 mm 660 724 804 804 804

FFA Packages (FF) — flip-chip fine-pitch BGA (1.0 mm ball spacing)

896 31 x 31 mm 432 528 624

1152 35 x 35 mm 720 824 824 824

1517 40 x 40 mm 912 1104 1108

BFA Packages (BF) — flip-chip fine-pitch BGA (1.27 mm ball spacing)

957 40 x 40 mm 624 684 684 684 684

Virtex-II (1.5V) Virtex-E (1.8V) V-EM Spartan-IIE (1.8V) Spartan-II (2.5V)

Note: Virtex-II packages FG456 and FG676 are footprint compatible.Virtex-II packages FF896 and FF1152 are footprint compatible.Important: Verify all Data with Device Data Sheet

Numbers indicated in the matrix are the maximum number of userI/O’s for that package and device combination.

I/O’s

Xilinx FPGA Package Options and User I/O

Package Pitch (mm) Size (mm) XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP50

FG256 1.00 17 x 17 140 140

FG456 1.00 23 x 23 156 248 248

FF672 1.00 27 x 27 204 348 396

FF896 1.00 31 x 31 396 556

FF1152 1.00 35 x 35 564 692

FF1517 1.00 40 x 40 852

BF957 1.27 40 x 40 564 584

User Available I/Os

Page 89: Xcell Journal: Issue 43

Reference CPLDs

Summer 2002 Xcell Journal 89

Xilinx CPLD Product Selection MatrixPRODUCT SELECTION MATRIX

I/O Features Speed Clocking

Syst

em G

ates

Mac

roce

lls

Prod

uct t

erm

s pe

r Mac

roce

ll

Inpu

t Vol

tage

Com

patib

le

Outp

ut V

olta

ge C

ompa

tible

Max

.I/O

I/O B

anki

ng

Min.

Pin-to

-Pin

Logic

Dela

y (ns

)

Com

mer

cial S

peed

Gra

des

(fast

est t

o slo

wes

t)

Indu

stria

l Spe

ed G

rade

s(fa

stes

t to

slow

est)

Glo

bal C

lock

sPr

oduc

t Ter

m C

lock

s pe

rFu

nctio

n Bl

ock

CoolRunner-II Family — 1.8 Volt

XC2C32 750 32 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 33 1 3.5 -3 -4 -6 -6 3 17

XC2C64 1500 64 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 64 1 4 -4 -5 -7 -7 3 17

XC2C128 3000 128 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 100 2 4.5 -4 -6 -7 -7 3 17

XC2C256 6000 256 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 184 2 5 -5 -6 -7 -7 3 17

XC2C384 9000 384 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 240 4 6 -6 -7 -10 -10 3 17

XC2C512 12000 512 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 270 4 6 -6 -7 -10 -10 3 17

CoolRunner XPLA3 Family — 3.3 Volt

XCR3032XL 750 32 48 3.3/5 3.3 36 5 -5 -7 -10 -7 -10 4 16

XCR3064XL 1500 64 48 3.3/5 3.3 68 6 -6 -7 -10 -7 -10 4 16

XCR3128XL 3000 128 48 3.3/5 3.3 108 6 -6 -7 -10 -7 -10 4 16

XCR3256XL 6000 256 48 3.3/5 3.3 164 7.5 -7 -10 -12 -10 -12 4 16

XCR3384XL 9000 384 48 3.3/5 3.3 220 7.5 -7 -10 -12 -10 -12 4 16

XCR3512XL 12000 512 48 3.3/5 3.3 260 7.5 -7 -10 -12 -10 -12 4 16

XC9500XV Family — 2.5 Volt

XC9536XV 800 36 90 2.5/3.3 1.8/2.5/3.3 36 1 5 -5 -7 -7 3 18

XC9572XV 1600 72 90 2.5/3.3 1.8/2.5/3.3 72 1 5 -5 -7 -7 3 18

XC95144XV 3200 144 90 2.5/3.3 1.8/2.5/3.3 117 2 5 -5 -7 -7 3 18

XC95288XV 6400 288 90 2.5/3.3 1.8/2.5/3.3 192 4 6 -6 -7 -10 -7 -10 3 18

XC9500XL Family — 3.3 Volt

XC9536XL 800 36 90 2.5/3.3/5 2.5/3.3 36 5 -5 -7 -10 -7 -10 3 18

XC9572XL 1600 72 90 2.5/3.3/5 2.5/3.3 72 5 -5 -7 -10 -7 -10 3 18

XC95144XL 3200 144 90 2.5/3.3/5 2.5/3.3 117 5 -5 -7 -10 -7 -10 3 18

XC95288XL 6400 288 90 2.5/3.3/5 2.5/3.3 192 6 -6 -7 -10 -7 -10 3 18

XC2C

32

XC2C

64

XC2C

128

XC2C

256

XC2C

384

XC2C

512

CoolRunner-II

XCR3

032X

L

XCR3

064X

L

XCR3

128X

L

XCR3

256X

L

XCR3

384X

L

XCR3

512X

L

XC95

36XV

XC95

72XV

XC95

144X

V

XC95

288X

V

XC9500XV

XC95

36XL

XC95

72XL

XC95

144X

L

XC95

288X

L

XC9500XL

*JTAG pins and port enable are not pin compatible in this package for this member of the family.Important: Verify all Data with Device Data Sheet and Product Availability with your local Xilinx Rep

CoolRunner XPLA3

Body Size

PLCC Packages (PC)

44 17.5 x 17.5 mm 33 33 36 36 34 34 34 34

PQFP Packages (PQ)

208 28 x 28 mm 173 173 173 164 172 180 168 168

VQFP Packages (VQ)

44 12 x 12 mm 33 33 36 36 34 34 34 34

64 12 x 12 mm 36 52

100 16 x 16 mm 64 80 80 68 84

TQFP Packages (TQ)

100 14 x 14 mm 72 81 72 81

144 20 x 20 mm 100 118 118 108 120 118* 117 117 117 117

Chip Scale Packages (CP) — wire-bond chip-scale BGA (0.5 mm ball spacing)

56 6 X 6 mm 33 45 48

132 8 X 8 mm 100 106

Chip Scale Packages (CS) — wire-bond chip-scale BGA (0.8 mm ball spacing)

48 7 x 7mm 36 40 36 38 36 38

144 12 x 12 mm 108 117 117

280 16 x 16 mm 164 192 192

BGA Packages (BG) — wire-bond standard BGA (1.27 mm ball spacing)

256 27 x 27 mm 192

FGA Packages (FT) — wire-bond fine-pitch thin BGA (1.0 mm ball spacing)

256 17 x 17 mm 184 212 212 164 212 212

FBGA Packages (FG) — wire-bond Fineline BGA (1.0 mm ball spacing)

256 17 x 17 mm 192 192

324 23 x 23 mm 240 270 220 260

PACKAGE OPTIONS AND USER I/O

Page 90: Xcell Journal: Issue 43

Reference Development Tools

Xilinx Software

90 Xcell Journal Summer 2002

Feature ISE WebPACK ISE BaseX ISE Foundation ISE Alliance

Platform PC PC PC/UNIX PC/UNIX

Device Support Virtex™Series Up to 300K (Virtex-E and Virtex-II) Up to 300K ALL ALL

Spartan™ II/IIE Families ALL ALL ALL ALL

Spartan™ /XL Families No Implementation Only* Implementation Only* ALL

XC4000™ Series No Implementation Only* Implementation Only* ALL

CoolRunner XPLA3 / CoolRunner™-II Families ALL ALL ALL ALL

XC9500™ Series ALL ALL ALL ALL

Design Planning Modular Design No Sold as an Option Sold as an Option Sold as an Option

Educational Services Yes Yes Yes Yes

Design Services Sold as an Option Sold as an Option Sold as an Option Sold as an Option

Support Services Web Only Yes Yes Yes

Design Entry Schematic Editor (Gate & Block Level HDL) Yes Yes PC Only No

HDL Editor Yes Yes Yes Yes

State Diagram Editor Yes Yes PC Only No

CORE Generator No Yes Yes Yes

System Generator for DSP No Sold as an Option Sold as an Option Sold as an Option

Synthesis Xilinx Synthesis Technology (XST) Yes Yes Yes No

Synplicity Synplify/Pro No Integration Kit Integration Kit (PC Only) Integration Kit (PC Only)

Leonardo Spectrum Integration Kit Integration Kit Integration Kit Integration Kit

Synopsys FPGA Compiler II EDIF Only EDIF Only EDIF Only EDIF Only

ABEL CPLD CPLD CPLD (PC Only) No

Implementation Tools iMPACT Yes Yes Yes Yes

FloorPlanner Yes Yes Yes Yes

Xilinx Constraints Editor Yes Yes Yes Yes

Timing Driven Place & Route Yes Yes Yes Yes

Timing Improvement Wizard No Yes Yes Yes

Board Level Integration IBIS Models Yes Yes Yes Yes

STAMP Models Yes Yes Yes Yes

LMG SmartModels Yes Yes Yes Yes

HSPICE Models** Yes Yes Yes Yes

Verification HDL Bencher™ Yes Yes PC Only No

ModelSim Xilinx Edition (MXE II) ModelSim XE II Starter*** ModelSim XE II Starter*** ModelSim XE II Starter*** ModelSim XE II Starter***

Static Timing Analyzer Yes Yes Yes Yes

ChipScope No Sold as an Option Sold as an Option Sold as an Option

FPGA Editor with Probe No Yes Yes Yes

ChipViewer Yes Yes Yes Yes

XPower (Power Analysis) Yes Yes Yes Yes

3rd Party Simulator Support Yes Yes Yes Yes

IP/CORE For more information on the complete list of Xilinx IP products, visit the Xilinx IP Center at http://www.xilinx.com/ipcenter

* For Spartan, SpartanXL, and 4K device families, ISE supports the implementation by reading in gate-level EDIF netlist.

** HSPICE Models available at the Xilinx Design Tools Center at www.xilinx.com/ise.

*** MXE II supports the simulation of designs up to 1 million system gates and is sold as an option.

Page 91: Xcell Journal: Issue 43

Xilinx Configuration Storage Solutions

Reference Configuration

Summer 2002 Xcell Journal 91

Xilinx Home Pagehttp://www.xilinx.com

Xilinx Online Supporthttp://www.xilinx.com/support/support.htm

Xilinx IP Centerhttp://www.xilinx.com/ipcenter/index.htm

Xilinx Education Centerhttp://www.xilinx.com/support/education-home.htm

Xilinx Tutorial Centerhttp://www.xilinx.com/support/techsup/tutorials/index.htm

Xilinx WebPACKhttp://www.xilinx.com/sxpresso/webpack.htm

Dens

ity

PD8

VO8

SO20

PC20

PC44

VQ44

Core

Vol

tage

2.5V

3.3V

In-System Programming (ISP) Configuration PROMs

XC18V256 256Kb Y Y Y 3.3V Y Y

XC18V512 512Kb Y Y Y 3.3V Y Y

XC18V01 1Mb Y Y Y 3.3V Y Y

XC18V02 2Mb Y Y 3.3V Y Y

XC18V04 4Mb Y Y 3.3V Y Y

One-Time Programmable (OTP) Configuration PROMs

XC17V01 1.6Mb Y Y Y 3.3V Y Y

XC17V02 2Mb Y Y Y 3.3V Y Y

XC17V04 4Mb Y Y Y 3.3V Y Y

XC17V08 8Mb Y Y 3.3V Y Y

XC17V16 16Mb Y Y 3.3V Y Y

I/OVoltage

System ACE CF up to 8 Gbit 2 25 cm2 No JTAG Unlimited Yes Yes Yes 30 Mbit/sec CompactFlash

System ACE MPM 16 Mbit 1 12.25 cm2 Yes SelectMAP (up to 4 FPGA) Up to 8 No No Yes 152 Mbit/sec AMD Flash Memory32 Mbit Slave-Serial (up to 8 FPGA chains)64 Mbit

System ACE SC 16 Mbit 3 Custom Yes SelectMAP (up to 4 FPGA) Up to 8 No No Yes 152 Mbit/sec AMD Flash memory32 Mbit Slave-Serial (up to 8 FPGA chains)64 Mbit

Mem

ory

Den

sity

Num

ber

of C

ompo

nent

s

Min

boa

rd s

pace

Com

pres

sion

FPG

A C

onfig

.Mod

e

Mul

tipl

e D

esig

ns

Soft

war

e St

orag

e

Rem

ovab

le

IRL

Hoo

ks

Max

Con

fig.S

peed

Non

-Vol

atile

Med

ia

FPG

A

PD8

VO8

SO20

PC20

PC44

VQ44

Core

Vol

tage

2.5V

3.3V

OTP Configuration PROMs for Spartan-II/IIE

XC17S50A XC2S50E Y Y Y 3.3V Y Y

XC17S100A XC2S100E Y Y Y 3.3V Y Y

XC17S200A XC2S150E Y Y Y 3.3V Y Y

XC17S200A XC2S200E Y Y Y 3.3V Y Y

XC17S300A XC2S300E Y 3.3V Y Y

XC17S15A XC2S15 Y Y Y 3.3V Y Y

XC17S30A XC2S30 Y Y Y 3.3V Y Y

XC17S50A XC2S50 Y Y Y 3.3V Y Y

XC17S100A XC2S100 Y Y Y 3.3V Y Y

XC17S150A XC2S150 Y Y Y 3.3V Y Y

XC17S200A XC2S200 Y Y Y 3.3V Y Y

I/OVoltage

Page 92: Xcell Journal: Issue 43

Reference IP/Cores

92 Xcell Journal Summer 2002

Xilinx

IP S

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Virtex-II Pro

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Spartan-IIE

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Page 93: Xcell Journal: Issue 43

Reference IP/Cores

Summer 2002 Xcell Journal 93

Co

mm

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Ne

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h-sp

eed c

ompu

ter lin

ksTu

rbo

Conv

olut

iona

l Dec

oder

- 3G

PP C

ompl

iant

Xi

linx

Logi

CORE

V-II

V-E

V80

%40

XC2V

500

3GPP

spe

cs,2

Mbp

s,BE

R=10

-6 fo

r 1.5

dB S

NR

3G W

irele

ss In

frast

ruct

ure

Turb

o De

code

r,3G

PPSy

sOnC

hip,

Inc.

Allia

nceC

ORE

V-II

V66

XC2V

500-

53G

PP/U

MTS

com

plia

nt,I

MT-

2000

,2M

bps

data

rate

Erro

r cor

rect

ion,

wire

less

Turb

o De

code

r,DV

B-RC

S iCo

ding T

echno

logy,I

nc.

Allia

nceC

ORE

V-II

V-E

V44

%71

XC2V

2000

-5DV

B-RC

S com

plian

t,9M

bps,

data

rate,

switc

hable

code

rates

and

frame

size

sEr

ror c

orre

ctio

n,w

irele

ss,D

VB,S

atel

lite

data

link

Turb

o De

code

rTel

ecom

Italia

Lab S

.p.A.

Allia

nceC

ORE

V-II

V70

%65

XC2V

2000

-53G

PP/U

MTS

com

plia

nt,>

2Mbp

s da

ta ra

teEr

ror c

orre

ctio

n,w

irele

ssTu

rbo

Conv

olut

iona

l Enc

oder

- 3G

PP C

ompl

iant

Xilin

xLo

giCO

REV-

IIV-

EV

65%

60XC

2V25

0Co

mpl

iant

w/ 3

GPP

,pun

ctur

ing

3G W

irele

ss In

frast

ruct

ure

Turb

o En

code

r,DV

B-RC

S iCo

ding T

echno

logy,I

nc.

Allia

nceC

ORE

V-II

V-E

V2%

69XC

2V20

00-5

DVB-

RCS c

ompli

ant,

9Mbp

s,da

ta rat

e,sw

itcha

ble co

de ra

tes an

d fra

me si

zes

Erro

r cor

rect

ion,

wire

less

,DVB

,Sat

ellit

e da

ta li

nkTu

rbo

Enco

der

Teleco

m Ita

lia La

b S.p.

A.Al

lianc

eCO

REV-

IIV

S-II

48%

120

XC2V

80-5

3GPP

/UM

TS c

ompl

iant

,upt

o 4

inte

rleav

er la

ws

Erro

r cor

rect

ion,

wire

less

UTO

PIA

leve

l 2 s

lave

inte

face

Paxon

et Co

mmun

icatio

nsAl

lianc

eCO

RECe

ll han

dsha

ke in

SPHY

mod

e,8/1

6 bit o

perat

ion,in

terna

l FIFO

,dete

cts ru

nt ce

llsAT

M P

HY la

yer

UTO

PIA

Leve

l-2 P

HY S

ide

RX In

terfa

ceTel

ecom

Italia

Lab S

.p.A.

Allia

nceC

ORE

VS-

IIS

8%53

XCV5

0-6

Prot

ocol

conv

ersion

from

Pb

(RAC

E BLN

T) to

UTO

PIA L2

,8/1

6 bit

ope

ration

ATM

PHY

laye

rUT

OPI

A Le

vel-2

PHY

Sid

e TX

Inte

rface

Teleco

m Ita

lia La

b S.p.

A.Al

lianc

eCO

REV

S-II

S10

%61

XCV5

0-6

Prot

ocol

conv

ersio

n fro

m UT

OPIA

L2 P

b (R

ACE

BLNT

),8/

16 b

it op

eratio

nAT

M P

HY la

yer

UTO

PIA

Leve

l-3 A

TM R

ecei

ver

inSilic

on C

orpo

ration

Allia

nceC

ORE

VS-

IIS

UTO

PIA

Leve

l-3 A

TM Tr

ansm

itter

inSilic

on C

orpo

ration

Allia

nceC

ORE

VS-

IIS

UTO

PIA

Leve

l-3 P

HY R

ecei

ver

inSilic

on C

orpo

ration

Allia

nceC

ORE

VS-

IIS

UTO

PIA

Leve

l-3 P

HY Tr

ansm

itter

inSilic

on C

orpo

ration

Allia

nceC

ORE

VS-

IIS

UTO

PIA

Mas

ter

Paxon

et Co

mmun

icatio

nsAl

lianc

eCO

REV

S-II

SSP

HY,M

PHY,

HEC

proc

essin

g,ro

und

robin

poll

ing,in

d.tra

nsmi

tter r

eceiv

erAT

M P

HY la

yer

UTO

PIA

Slav

ePa

xonet

Comm

unica

tions

Allia

nceC

ORE

VS-

IIS

26%

79XC

V50-

4Ce

ll han

dshak

e in S

PHY m

ode,

8/16 b

it ope

ration

,32 b

it FIFO

inter

face,

detec

ts run

t cell

sAT

M P

HY la

yer

Vite

rbi D

ecod

er,I

EEE

802-

com

patib

leXi

linx

Logi

CORE

V-IIP

V-II

V-E

VS-

IIES-

II35

%15

7XC

2V50

0-5

Param

eteriza

ble so

urce c

ode w

ith co

nstrain

t leng

th(k)=

7,G0

=171

,G1=

133;

or G0

=133

,G1=

17,

L/M

MDS

,bro

adca

st e

quip

,wire

less

LAN

,cab

le m

odem

,inc

ludes

BestS

tate L

ogic,

ability

to ch

ange

code r

ate an

d trac

eback

depth

on th

e fly,

suppo

rtsxD

SL,s

at c

om,u

wav

e ne

tsTre

llis Co

ded M

odula

tion,

IEEE8

02.11

a/16a

comp

atible

,reach

es OC

3 (15

5Mbp

s) and

high

erVi

terb

i Dec

oder

,Gen

eral

Pur

pose

Xilin

xLo

giCO

REV-

IIPV-

IIV-

EV

S-IIE

S-II

38%

128

XC2V

500-

5Pun

cturing

,serial

& par

allel ar

chitec

ture,d

ynamic

rate c

hange,

param

terized

const

raint le

ngth,s

oft/ha

rd3G

bas

e st

atio

ns,b

road

cast

,wire

less

LAN

,cab

le m

odem

,dec

ision w

ith pro

gramm

able n

umber

of so

ft bits,

dual ra

te deco

der,er

asure p

ins fo

r exter

nal pu

ncturin

g,xD

SL,s

atel

lite

com

,uw

ave,

CDM

A200

0com

patible

with

standa

rds su

ch as

DVB E

TS,3G

PP2,IE

EE802.

16,Hip

erlan,I

ntelsa

t IESS-

308/30

9Vi

terb

i Dec

oder

Teleco

m Ita

lia La

b S.p.

A.Al

lianc

eCO

REV-

IIV-

ES-

II74

%91

XC2V

500-

5Ra

dix-2/

radix4

archi

tectur

es,BE

R,de

punct

uring

.Cod

e rate

,contr

aint le

ngth

param

eteriza

bleDa

ta tr

ansm

issio

n,w

irele

ssD

igit

al

Sig

na

l P

roce

ssin

g10

24-P

oint

Com

plex

FFT

/IFFT

Xilin

xLo

giCO

REV-

EV

1024

-Poi

nt C

ompl

ex F

FT/IF

FT fo

r Virt

ex-II

Xilin

xLo

giCO

REV-

II62

%41

us,1

00M

HzXC

2V50

016

bit

com

plex

dat

a,2'

s co

mp,

forw

ard

and

inve

rse

trans

form

16-P

oint

Com

plex

FFT

/IFFT

Xilin

xLo

giCO

REV-

IIV-

EV

16-P

oint

Com

plex

FFT

/IFFT

for V

irtex

-IIXi

linx

Logi

CORE

V-II

37%

123n

s 13

0MHz

XC2V

500

16 b

it co

mpl

ex d

ata,

2's

com

p,fo

rwar

d an

d in

vers

e tra

nsfo

rm25

6-Po

int C

ompl

ex F

FT/IF

FTXi

linx

Logi

CORE

V-II

V-E

V32

-Poi

nt C

ompl

ex F

FT/IF

FTXi

linx

Logi

CORE

V-IIP

V-II

V-E

VS-

IIES-

II29

%11

0XC

2V50

0-6

Comp

lex FF

T,Forw

ard an

d Inver

se tra

nsform

.Suppo

rts bit

precisi

ons fro

m 2-32

bits.E

mbedd

ed me

mory

64-,

256-

,102

4-Po

int C

ompl

ex F

FT/IF

FTXi

linx

Logi

CORE

V-IIP

V-II

32%

140

XC2V

1500

-664

-,256

-,102

4-po

int p

rogra

mmab

le po

int si

ze,fo

rward

and

invers

e tran

sform

,Er

ror c

orre

ctio

n16

-bit

comp

lex d

ata,1

8-bit

pha

se fa

ctors,

2's co

mplem

ent,

built-

in me

morie

s,pr

ogram

mable

data

scali

ng,1

40 M

Hz,1

024-

point

tran

sform

— 7

.31 u

s,25

6-po

int tr

ansfo

rm —

1.83

us,

64-p

oint t

ransfo

rm -

0.46

us64

-Poi

nt C

ompl

ex F

FT/IF

FTXi

linx

Logi

CORE

V-E

V64

-Poi

nt C

ompl

ex F

FT/IF

FT fo

r Virt

ex-II

Xilin

xLo

giCO

REV-

II38

%1.

9us,

100M

HzXC

2V50

016

bit

com

plex

dat

a,2'

s co

mp,

forw

ard

and

inve

rse

trans

form

Bit C

orre

lato

rXi

linx

Logi

CORE

V-IIP

V-II

V-E

VS-

IIES-

II40

96 ta

ps,s

eria

l/par

alle

l inp

ut,4

096

bits

wid

thCa

scad

ed In

tegr

ator

Com

b (C

IC) F

ilter

Xilin

xLo

giCO

REV-

IIPV-

IIV-

EV

S-IIE

S-II

32 b

its d

ata

wid

th,r

ate

chan

ge fr

om 8

to 1

6384

Com

b Fi

lter

Xilin

xLo

giCO

RES

Not re

comme

nded

for ne

w des

igns.S

ugges

ted re

placem

ent:C

ascad

ed Int

egrato

r Com

b Filte

rCO

RDIC

Xilin

xLo

giCO

REV-

IIPV-

IIV-

EV

S-IIE

S-II

Polar

to re

ctang

ular,r

ectan

gular

to po

lar,sin

& cos

,sinh

& cos

h,ata

n & at

anh,

square

root

Digi

tal r

ecei

vers

Digi

tal D

own

Conv

erte

r (DD

C)Xi

linx

Logi

CORE

V-IIP

V-II

V-E

VS-

IIES-

II47

%11

6XC

2V50

0-5

Conf

igur

able

dat

apat

h co

mpr

ising

mix

er,D

DS,o

ptio

nal

Wire

less &

wire

line c

ommu

nicati

on sy

stems

such

as so

ftware

defi

ned

radios

,CI

C fil

ter,

optio

nal p

olyp

hase

dec

imat

ors,

25 to

108

dbdig

ital r

eceiv

ers,c

able

mode

ms,B

PSK,

QPSK

,QAM

dem

odula

tors,

sprea

dDD

S sp

urio

us fr

ee d

ynam

ic ra

nge

spec

trum

comm

unica

tion

system

s,CD

MA2

000

& 3G

bas

estat

ions

Dire

ct D

igita

l Syn

thes

izer (

DDS)

Xilin

xLo

giCO

REV-

IIPV-

IIV-

EV

S-IIE

S-II

12%

245

XC2V

80-6

8-65

K sa

mpl

es,3

2-bi

ts o

utpu

t pre

cisio

n,ph

ase

dith

erin

g/of

fset

Dist

ribut

ed A

rithm

etic

(DA)

FIR

Filt

erXi

linx

Logi

CORE

V-IIP

V-II

V-E

VS-

IIES-

II32

-bit

input

/coeff

widt

h,10

24 ta

ps,1

-8 ch

an,p

olyph

ase,

onlin

e coe

ff rel

oad

Dual

-Cha

nnel

Num

erica

lly C

ontro

lled

Osc

illat

orXi

linx

Logi

CORE

V-E

VS-

IIES-

IIS

Not re

comm

ende

d for

new

desig

ns.Su

ggest

ed re

placem

ent:D

irect

Digita

l Syn

thesiz

erLF

SR,L

inea

r Fee

dbac

k Sh

ift R

egist

erXi

linx

Logi

CORE

V-IIP

V-II

V-E

VS-

IIES-

II16

8 in

put w

idth

s,SR

L16/

regi

ster

impl

emen

tatio

nM

AC F

IRXi

linx

Logi

CORE

V-IIP

V-II

V-E

VS-

IIES-

II16

%XC

2V25

0Si

ngle

rate

,Pol

ypha

se D

ecim

ator

,Pol

ypha

se I

nter

pola

tor

3G b

ase

stat

ions

,wire

less

com

mun

icatio

ns,i

mag

e fil

terin

gN

umer

ically

Con

trolle

d O

scill

ator

Xilin

xLo

giCO

REV-

EV

S-IIE

S-II

SNo

t reco

mmen

ded f

or ne

w de

signs.

Sugg

ested

repla

cemen

t:Dire

ct Dig

ital S

ynthe

sizer

Func

tion

Vend

or N

ame

IP Ty

peOc

cM

HzDe

vice

Key

Feat

ures

Appl

icatio

n Ex

ampl

es

Impl

emen

tatio

n Ex

ampl

e

Virtex-II Pro

Virtex-II

Virtex-E

Virtex

Spartan-IIE

Spartan-II

Spartan

Page 94: Xcell Journal: Issue 43

94 Xcell Journal Summer 2002

Reference IP/Cores

Dig

ita

l S

ign

al

Pro

cess

ing

(co

nti

nu

ed

)Pa

ralle

l Dist

ribut

ed A

rithm

etic

FIR

Filte

rXi

linx

Logi

CORE

SNo

t recom

mend

ed for

new

design

s.Sug

gested

repla

cement

:Distr

ibuted

Arith

metic

FIR Fil

terSe

rial D

istrib

uted

Arit

hmet

ic FI

R Fi

lter

Xilin

xLo

giCO

RES

Not re

comme

nded

for ne

w des

igns.S

ugges

ted re

placem

ent:D

istribu

ted Ar

ithme

tic FIR

Filter

Tim

e-Sk

ew B

uffe

r,N

onsy

mm

etric

16-

Deep

Xi

linx

Logi

CORE

SN

ot re

com

men

ded

for n

ew d

esig

ns.

Tim

e-Sk

ew B

uffe

r,N

onsy

mm

etric

32-

Deep

Xi

linx

Logi

CORE

SN

ot re

com

men

ded

for n

ew d

esig

ns.

Tim

e-Sk

ew B

uffe

r,Sy

mm

etric

16-

Deep

Xi

linx

Logi

CORE

STM

S320

25 D

SP P

roce

ssor

cor

eCA

ST,I

nc.

Allia

nceC

ORE

V-II

V-E

VS-

II66

%63

XC2V

500-

5M

ath

Fu

nct

ion

s1s

and

2s

Com

plem

ent

Xilin

xLo

giCO

RES

Not

reco

mm

ende

d fo

r new

des

igns

.Sug

gest

ed re

plac

emen

t:Bu

s G

ate

or T

wos

Com

plem

ente

rAc

cum

ulat

orXi

linx

Logi

CORE

V-IIP

V-II

V-E

VS-

IIES-

II1-

256s

bit

wid

eAd

der S

ubtra

cter

Xilin

xLo

giCO

REV-

IIPV-

IIV-

EV

S-IIE

S-II

1-25

6s b

it w

ide

Cons

tant

Coe

fficie

nt M

ultip

lier

Xilin

xLo

giCO

RES

Not r

ecom

men

ded

for n

ew d

esign

s.Su

gges

ted

repla

cem

ent:

Mult

iplier

Cons

tant

Coe

fficie

nt M

ultip

lier -

Pip

elin

edXi

linx

Logi

CORE

SNo

t rec

omm

ende

d fo

r new

des

igns.

Sugg

este

d re

place

men

t:M

ultipl

ierDy

nam

ic Co

nsta

nt C

oeffi

cient

Mul

tiplie

rXi

linx

Logi

CORE

V-E

VNo

t rec

omm

ende

d fo

r new

des

igns.

Sugg

este

d re

place

men

t:M

ultipl

ierFl

oatin

g Po

int A

dder

Digit

al Co

re D

esign

Allia

nceC

ORE

V-II

VS-

II66

XC2V

250-

5Fu

ll IEE

E-75

4 co

mplia

nce,

4 pip

eline

s,Sin

gle p

recisi

on re

al for

mat s

uppo

rtDS

P,M

ath,

Arith

met

ic ap

psFl

oatin

g Po

int D

ivid

erDi

gital

Core

Des

ignAl

lianc

eCO

REV-

IIV

S-II

53XC

2V25

0-5

Full I

EEE-

754

comp

lianc

e,15

pipe

lines

,Sing

le pr

ecisi

on re

al for

mat s

uppo

rtDS

P,M

ath,

Arith

met

ic ap

psFl

oatin

g Po

int M

ultip

lier

Digit

al Co

re D

esign

Allia

nceC

ORE

V-II

V-E

VS-

II74

XC2V

250-

5Fu

ll IEE

E-754

comp

lianc

e,7 p

ipelin

es,32

x32 m

ult,S

ingle

precis

ion re

al for

mat s

uppo

rtDS

P,M

ath,

Arith

met

ic ap

ps.

Floa

ting

Poin

t Squ

are

Com

para

tor

Digit

al Co

re D

esign

Allia

nceC

ORE

V-II

VS-

II91

XC2V

80-5

Full I

EEE-

754

comp

lianc

e,4

pipeli

nes,

Single

prec

ision

real

forma

t sup

port

DSP,

Mat

h,Ar

ithm

etic

apps

.Fl

oatin

g Po

int S

quar

e Ro

ot O

pera

tor

Digit

al Co

re D

esign

Allia

nceC

ORE

V-II

V-E

S-II

66XC

2V25

0-5

Full I

EEE-

754

comp

lianc

e,4

pipeli

nes,

Single

prec

ision

real

forma

t sup

port

DSP,

Mat

h,Ar

ithm

etic

apps

Floa

ting

Poin

t to

Inte

ger C

onve

rter

Digit

al Co

re D

esign

Allia

nceC

ORE

V-II

VS-

II66

XC2V

250-

5Fu

ll IEE

E-75

4 co

mplia

nce,

4 pip

eline

s,Sin

gle p

recisi

on re

al for

mat s

uppo

rtDS

P,M

ath,

Arith

met

ic ap

psIn

tege

r to

Floa

ting

Poin

t Con

verte

rDi

gital

Core

Des

ignAl

lianc

eCO

REV-

IIV

S-II

73XC

2V25

0-5

Full I

EEE-7

54 co

mplia

nce,

doub

le wo

rd inp

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lianc

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1 in

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ctio

n se

t,8

bit A

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R I/F

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Impl

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Virtex-II Pro

Virtex-II

Virtex-E

Virtex

Spartan-IIE

Spartan-II

Spartan

Page 95: Xcell Journal: Issue 43

Summer 2002 Xcell Journal 95

Reference IP/Cores

Mic

rop

roce

sso

rs,

Co

ntr

oll

ers

& P

eri

ph

era

ls (

con

tin

ue

d)

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re D

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ORE

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Page 96: Xcell Journal: Issue 43

96 Xcell Journal Summer 2002

Reference IP/Cores

Mic

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sso

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Co

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Page 97: Xcell Journal: Issue 43

Summer 2002 Xcell Journal 97

Reference IP/Cores

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Page 98: Xcell Journal: Issue 43

Reference Support

98 Xcell Journal Summer 2002

Xilinx Global Services

Part Number Product Description Duration Availability

Educational Services

FPGA13000-4-ILT Fundamentals of FPGA Design (v4.x) 8 Now

FPGA16000-4-ILT ISE Design Entry (v4.x) — Instructor-Led course 8 Now

FPGA23000-4-ILT Designing for Performance (v4.x) 16 Now

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ASIC1500-3-ILT FPGA Design for the ASIC User (v3.x) — Instructor-Led Course 24 Now

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DC-DES-SERV Design Services Contract

Xilinx Design Services

• Provide extensive FPGA hardware andembedded software design experience backed by industry recognized experts andresources to solve even the most complexdesign challenge.

• System Architecture Consulting — Provideengineering services to define system architectureand partitioning for design specification.

• Custom Design Solutions — Project designed,verified, and delivered to mutually agreedupon design specifications.

• IP Core Development, Optimization, Integration,Modification, and Verification — Modify, integrate, and optimize customer intellectualproperty or third party cores to work withXilinx technology. Develop customer-required special features to Xilinx IP cores or third party cores. Perform integration,optimization, and verification of IP cores in Xilinx technology.

• Embedded Software — Develop complexembedded software with real-time constraints,using hardware/software co-design tech-niques.

• Conversions — Convert ASIC designs andother FPGAs to Xilinx technology anddevices.

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Page 99: Xcell Journal: Issue 43

The new Spartan-IIE FPGAs deliver over 20 billion

MACs/s, giving you the DSP performance required

for high-resolution digital images. Together with

advanced signaling standards including LVDS,

HSTL and SSTL, you’ve got the speed you need

for digital video processing.

From Picture to Pixel, the Complete Solution

Through capture, process and display, Spartan-IIE FPGAs bring the total

solution into focus. Encryption IP, operating at high speed

video rates, offers a new level of security protecting every pixel.

And the desktop programmability of Spartan-IIE FPGAs

solves your time-to-market pressures as design cycles get shorter.

The eSP Web Portal . . . a Unique Designer’s Resource

The Xilinx eSP web portal gives you all the support you could wish for

as standards continue to rapidly change.

Simply log on to xilinx.com/esp and

you’ll get immediate access to reference

boards, system block diagrams, a full spectrum of technology & stan-

dards tutorials, and much more. You’ll soon see why eSP is one of the

most successful websites of its kind.

Visit www.xilinx.com/spartan2e/dvt today and find out

why Spartan-IIE FPGAs are the clear choice for digital

video design.

The Programmable Logic CompanySM

www.xilinx.com/spartan2e/dvt® 2001 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx and Spartan are registered trademarks, WebPACK ia a trademark and The Programmable Logic Company is a service mark of Xilinx, Inc.

For digital video, Spartan®-IIE is the

clear choice.

Page 100: Xcell Journal: Issue 43

Available now, the new

Virtex-II Pro™ Platform FPGAs

herald an astonishing breakthrough in

system-level solutions. With up to four IBM PowerPC™ 405

processors immersed into the industry’s leading FPGA fabric,

Xilinx/Conexant’s flawless high-speed serial I/O technology, and

Wind River System’s cutting-edge embedded design tools, Xilinx

delivers a complete development platform of infinite possibilities.

The era of the programmable system is here.

The Power of Xtreme Processing

Each IBM PowerPC runs at 300+ MHz and 420 Dhrystone

MIPS, and is supported by IBM CoreConnect™ bus technology.

In addition, the FPGA fabric enables

ultra-fast hardware processing, such

as TeraMACs/s DSP applications. And Xilinx’s unique IP-

Immersion™ architecture gives you the power of high-perform-

ance processors, and easy integration of soft IP. A new perform-

ance standard now enables hardware accelerated processing and

multiple processing in a single off-the-shelf device.

The ultimate Connectivity platform

The first programmable device to combine embedded processors

along with Rocket I/O™ 3.125 Gbps transceivers, the Virtex-II Pro

series supports 10 Gigabit Ethernet with XAUI, 3GIO, SerialATA,

InfiniBand, you name it. And our SelectI/O™- Ultra supports 840

Mbps LVDS and other parallel methodologies. With 40+Gbps serial

bandwidth, market challenges become market solutions.

With so many features on a single device such as microproces-

sors, multi-gigabit transceivers, highest density on-chip memory and

on-chip termination, the benefits include simplified board layout, a

reduced bill of materials, and unbeatable time to market.

Industry-Leading Tools from Wind River and Xilinx

Wind River’s embedded tools are the premier support for real-time

microprocessor and logic designs. And Xilinx’s lightning-fast

ISE 4.2i software provides the most comprehensive,

easy-to-use development system available.

See the new Virtex-II Pro Platform FPGA in

detail. Visit www.xilinx.com/virtex2pro today and

step into the era of the programmable system.

The Programmable Logic CompanySM

www.xilinx.com/virtex2pro©2002, Xilinx, Inc. All rights reserved. The Xilinx name, the Xilinx logo, registered trademarks. RocketI/O and SelectI/O, Virtex-II Pro are trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc. The following are trademarks of International Business Machines Corporation in the United States,

or other countries, or both: IBM, IBM logo, PowerPC, PowerPC logo, and CoreConnect. All other trademarks and registered trademarks are the property of their respective owners.

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