Xcell Journal 日本語版 79 & 80 合併号

All ProgrammableVivado Design Suite

FPGA IP /

Kintex-7 FPGA 19nm PCIe SSD

Xilinx 3D FPGAVirtex-7 H580TCFP22x100G

Artix-7 FPGA

S O L U T I O N S F O R A P R O G R A M M A B L E W O R L D

Xcell journalXcell journal7 98 0 2013 SPRING

36

12,80013,440

12,00012,600

19,50020,475

FPGA / CPLD PLCC68

FPGA

ACM/XCM

Spartan-6

XP68-01PLCC 68PIN Spartan-6 FPGA

FPGA Board100

FPGA

ICFPGA/CPLDPLCC68ICFPGACPLDICFPGACPLDFPGA/CPLDI/OIO2

50I/O(4) 3.3VFPGA/CPLD IC25.3 25.3 [mm] VIOAVIOB (FPGA/CPLD 3.3V JTAG RoHS

XC6SLX16-2CSG225C 50I/O 3.3V 50MHz ROM 6 IC

RoHS

RoHS

XP68-02PLCC 68 Spartan-3AN FPGA

XC3S200AN-4FTG256C 50I/O 3.3V 50MHz ROMFPGA

6 IC

RoHS

XP68-03PLCC 68 Spartan-6 FPGA

XC6SLX45-2CSG324C 50I/O 3.3V 50MHz ROM 6 IC

RoHS11,00011,550

XCM-306Spartan-6 LX TQG144 FPGA

XC6SLX4-2TQG144C XC6SLX9-2TQG144C

DDR2 SDRAM

MRAM

RoHS44,46,200

XCM-110/110ZSpartan-6 FGG484 FPGA

XC6SLX45-2FGG484CXC6SLX75-2FGG484CXC6SLX100-2FGG484CXC6SLX150-2FGG484C

DDR2 SDRAM

RoHS

RocketI/O

MRAM

66,00069,300

XC6SLX45T-2FGG484CXC6SLX75T-2FGG484CXC6SLX100T-2FGG484CXC6SLX150T-2FGG484C

XCM-020Spartan-6 LXT FGG484 FPGA

USBCong

FRAM

SDRAM

USBComm

Virtex-5

XCM-011Virtex-5 FFG676

XC5VLX676BGA

108,000113,400

EDX-006FPGA Virtex-5 USB-FPGA

XC5VLX30-1FFG676C

99,000103,950

XCM-109Virtex-5 FFG676

XC5VLX30-1FFG676CXC5VLX50-1FFG676CXC5VLX85-1FFG676CXC5VLX110-1FFG676C77,00080,850

RocketI/O

MRAM

XCM-107Virtex-5 LXT FFG665

XC5VLX30T-1FFG665CXC5VLX50T-1FFG665C

108,000113,400

SDRAM

RoHS

RoHS

RoHS

RoHS

RoHS

40,00042,000

XC6SLX45-2FGG484CXC6SLX75-2FGG484CXC6SLX100-2FGG484CXC6SLX150-2FGG484C

XCM-018/018ZSpartan-6 FGG484 FPGA

MRAM

DDR2 SDRAM

5VTolerant5V I/O

RoHS

38,80040,740

XC6SLX45-2FGG484CXC6SLX75-2FGG484C

XCM-019YSpartan-6 FGG484 FPGA

RoHS

39,00040,950

XC6SLX45-2FGG484CXC6SLX75-2FGG484C

XCM-019Spartan-6 FGG484 FPGA

HES-7SoC/ASICFPGAASIC1HES-71 Xilinx Virtex-7 2000T2400FPGA2,400ASICDSP

HES-7FPGAFPGA12HES-79,600ASIC

HES-7

SoC/AS

IC Proto

typing

THE DESIGN VERIFICATION COMPANYR

SoC HES-7SoCDUTWLAN 802.11 b/g/n BluetoothHDMIHES-7

496M ASIC

Xilinx Zynq All Programmable SoCARM Cortex

SoC

OS

HES-7 SoC/ASIC Prototyping Platform

MotherBoardup to 24m ASIC gates

FPGA2

FPGA1

FPGA0

Prog.

FPGA

CON

NEC

TOR

SoCEssentialsPeripherals

Wi-Fi

Bluetooth

HDMI

Audio Codec

USB 2.0 OTG

NAND Flash

DDR3

ARM Cortex-A9

freeRTOS

ARM Cortex HES-7Xilinx Zynq-7000 All Programmable SoC ARM Cortex-A9HES-7 ASIC

HES-74009,600ASICXilinxLinux,AndroidFreeRTOS

2013 Aldec, Inc. Aldec

Headquarters-USPh. [email protected]

EuropePh. +44.1295. 20.1240 [email protected]

EuropePh. +44.1295. [email protected]

ChinaPh. [email protected]

TaiwanPh. [email protected]

IndiaPh. [email protected]

160-0022 2-1-9 7FPh. [email protected]

www.aldec.com/jp

TM

member

03-5312-179103-5312-1795

L E T T E R F R O M T H E P U B L I S H E R

4 40nm 6

FPGA 28nm 7 2 FPGA XC2064 1985

2011 28nm Zynq -7000 All Programmable SoC Virtex-7 2000T FPGA 2

23 Xcell Journal 2 Zynq-7000 AP SoC ARM Cortex -A9 MPCore FPGA

Zynq-7000 AP SoC EE Times EDN UBM Electronics ACE SoC ( ) (http://www.eetimes.com/electronics-news/4370156/Xilinx-Zynq-7000-receives-product-of-the-year-ACE-award )

Virtex-7 2000T ACE IC Zynq-7000 AP SoC Virtex-7 2000T 3D (SSI) FPGA 4 28nm ( ) Virtex-7 2000T

SSI IC SSI Virtex-7 HT Virtex-7 HT 100Gbps Virtex-7 HT Virtex-7 H870T 400Gbps

Vivado Design Suite ( 12-17 )5 Vivado ISE Design Suite ( ) EDA 7 FPGA

7 Vivado Design Suite 6 Design Automation Conference (www.dac.

com) Vivado Design Suite

Mike Santarini

Xcell journal Mike Santarini [email protected] +1-408-626-5981

Jacqueline Damian

Scott Blair

/ Teie, Gelwicks & Associates

[email protected]

[email protected]

Xcell Journal 7980

2013 2 28

Xilinx, Inc2100 Logic DriveSan Jose, CA 95124-3400

141-0032 1-2-2 4F

2013 Xilinx, Inc. All Right Reserved.

XILINX Xcell Xilinx

Xilinx, Inc.

Xilinx, Inc.

!!

FPGA

FPGA

FPGA/SoC

FPGAFPGAFPGA /CPLD

FPGA

FPGA

FPGAFPGA

30! FPGA

Zynq-7000 All Programmable SoC C Zynq-7000 All Programmable SoC C

AMBA AXI4

FPGA PlanAhead 1 2 3

7

15! FPGA

7 FPGA

ISE Design Suite

http://japan.xilinx.com/webseminar/

All Programmable FPGA SoC3D IC

New!!New!!

Web Seminar

Zynq-7000

Zynq-7000 EPP

28nm 7 FPGA

VIEWPOINTS

Letter From the Publisher

2

Cover Story 10

All Programmable Vivado Design Suite

Cover Story D FPGA

6

18

12

XCELLENCE BY DESIGN APPLICATION FEATURES

THE XILINX XPERIENCE FEATURES

Xcellence in Communications

18

Xcellence in Solid-State Storage

Kintex-7 FPGA 19nm PCIe SSD 23

Xcellence in Distributed Computing

FPGA 28

Product Feature

Artix-7 FPGA 36

7 9 8 0

2 1

Xpert Opinion

FPGA CORDIC 42

Xplanation: FPGA101

FPGA IP / 47

Xplanation: FPGA 101

FPGA : ADC DAC 53

Xpert Opinion

FPGA 58

58Excellence in Magazine & Journal Writing

2010, 2011Excellence in Magazine & Journal Design and Layout

2010, 2011, 2012

28

36

53

COVER STORY

3D FPGA :Virtex-7 H580T

Xilinx Introduces First Heterogeneous 3D FPGA:

6 Xcell Journal 7980

C O V E R S T O R Y

Mike SantariniPublisher, Xcell Journal

Xilinx, [email protected]

3D SSI 2x100G OTN 28nm Virtex-7 2000T (3D (SSI) 28nm FPGA) FPGA SSI Virtex-7 H580T 8 28Gbps ( ) 2 FPGA 1 3D FPGA 48 13.1Gbps 8 28Gbps 580,480 Virtex-7 H580T FPGA 2x100G ( 1) http://japan.xilinx.c o m /p u b l i c a t i o ns /p r o d _ m k t g /Virtex7-Product-Table.pdf Ephrem Wu

Virtex-7 HT 100Gbps MACOTNInterlaken IP CFP2 100Gbps 28Gbps 13.1Gbps 13.1Gbps 28Gbps (Wu)

Virtex-7 H580T FPGA 2 28nm 3D Virtex-7 H870T 2 8 3 FPGA 1 16 28Gbps 72 13.1Gbps 876,160 3D SSI BOM All Programmable WuVirtex-7 2000T 3D SSI 1 4 68 1,954,560 28nm 2 22 2 Virtex-7 HT 3D SSI 28Gbps 28nm FPGA 1 (Wu)SSI 100Gbps 400G (Wu)

Virtex-7 FPGA Alex Goldhammer

http://japan.xilinx.com/ 7

/ 100Gbps ( CFP2 opticsOIF CEI-28-VSR IEEE 802.3ba) 100Gbps (OTN) / 100G ( ) OTN Goldhammer 1 2 ASSP 1 FPGA 1 100Gbps OTN 1 100Gbps OTN CFP (CFP C Form-factor Pluggable )ASSP CFP 10x11.1G OTL 4.10 CAUI (100Gbps Attachment Unit Interface) 100Gbps (GFEC)OTU-4 100GE CAUI FPGA FPGA

( ) CFP 1 100Gbps OTN CFP ( ) 1/2 CFP2 (100Gbps ) CFP2 CFP 1 2 CFP2 2

2 ( 2 )Goldhammer CFP2

CFP2 25Gbps/28Gbps IBIS-AMI PCB CFP CFP CFP2 1 2 2 CFP2

C O V E R S T O R Y

CFP

CFP2 CFP2 CFP2 CFP2 CFP2 CFP2 CFP2 CFP2

CFP CFP CFP

100G CFPOPTICS

CFP2OPTICS

CAUI

CAUI4

10x10G

4x25G

100G

4 CFPs400 Gbps60 Watts

8 CFP2s800 Gbps60 Watts

1 3D SSI FPGA Virtex-7 H580T 28nm FPGA 28Gbps 1

2 CFP2 100Gbps OTN 2 CFP2 CFP 1/2 1/2


(Goldhammer) Goldhammer CFP2 1 5 (4 ASSP 1 FPGA) 2 CFP2 4x27G OTL 4.4 ASSP 4x27G OTL 4.4 10x11.1G OTL 4.10 1 ASSP 100Gbps GFECOTU-4 100GE CAUI FPGA CFP2 2 1 FPGA FPGA ( ) CAUI Interlaken ( 3) 4 ASSP 1 FPGA

ASSP 2 (Goldhammer)CFP2 CFP 2 CFP (2 100Gbps CFP2 ) CFP2 CFP 2 (Goldhammer) Virtex-7 H580T FPGA IP 100Gbps OTN 5 1 Virtex-7

H580T CFP2 OTN

Virtex-7 H580T FPGA CFP2 100Gbps OTN (Goldhammer)Virtex-7 H580T FPGA IP 2 CFP2 1 Virtex-7 H580T FPGA CFP2 FPGA 100Gbps GFECOTU-4 100GE Interlaken 1 ( 3 ) ASSP ASIC Virtex-7 H580T FPGA CFP2 OTN BOM (Goldhammer) 100G Time-to-Market IP (100Gbps MACOTN Interlaken IP) 28nm Virtex-7 FPGA TSMC 28nm [HPL] (Goldhammer)

SSI 28Gbps 1 ( )

C O V E R S T O R Y

CFP2ASSP

Gearbox

Backp

lane In

terface

FPGA

MAC toInterlaken

Bridge

100GGFEC

CAUI CAUI

Interlaken

OUT-4Framer

ASSP

100GEMapper

CFP2

CFP2

Backp

lane In

terface

CFP2

ASSPGearbox 100G

GFECCAUI CAUIOUT-4

Framer

ASSP

100GEMapper

100GGFEC

OUT-4Framer

100GEMapper

100GGFEC

Gearbox

Virtex-7 H580T

Xilinx Virtex-7 H580T Single-Chip OTN 2x100G Transponder

ASSP Solution Five-Chip OTN 2x100G Transponder

OUT-4Framer

100GEMapper

Gearbox

Interlaken

Interlaken

3 5 Virtex-7 H580T FPGA IPCFP2 100Gbps OTN


Goldhammer (Goldhammer) 10 Gbps/ Virtex-7 H580T FPGA SSI Virtex-7 H580T FPGA CFP2 4x25G 10x10G 25G/28G

SSI 28G (Goldhammer)Goldhammer 28G FPGA 28nm HPL Virtex-7 H580T FPGA 28Gbps YouTube http://www.you-tube.com/watch?v=FFZVwSjRC4c&-feature=player_profilepageGoldhammer SSI Virtex-7 H580T FPGA 8 28Gbps

2 28nm Virtex-7 H580T FPGA Virtex-7 H870T 16 28Gbps 72 13.1Gbps 876,160 Goldhammer H580T 2.78 / 1 FPGA 28Gbps SSI 8 16 28Gbps FPGA (Goldhammer)ASSP FPGA 4 28G 40nm 28nm 28Gbps Virtex-7 H870T 400G 400G 400G 400G (Goldhammer) Virtex-7 H580T FPGA Vivado Design Suite Virtex-7 H580T 28Gbps http://japan.xilinx.com/products/technology/transceiv-ers/index.htm

C O V E R S T O R Y

: Virtex-7 H580T CFP2


VivadoTM Design Suite WebPACKTM Edition

() TEL(045)443-4016 [email protected] () TEL(03)5792-8210 [email protected] () TEL(045)477-2005 [email protected]() TEL(045)415-5825 [email protected] () TEL(03)6361-8086 X-Proshinko-sj.co.jpCopyright 2013 Xilinx, Inc. All rights reserved. VivadoWebPACK

COVER STORY

Xilinx Unveils Vivado Design Suite for the Next Decade of All Programmable Devices

EDA

4 1 Vivado Design Suite Vivado IC AMBA AXI4 IP-XACT IP Tool Command Language (TcL)Synopsys Design Constraints (SDC) Vivado Design Suite 1 ASIC

Mike SantariniPublisher, Xcell JournalXilinx, [email protected]

10 All Programmable Vivado Design Suite


Steve Glaser 4 I/O ARM 3D IC All Programmable Zynq -7000 All Programmable SoC 3D (SSI) Virtex-7 FPGA Vivado 10 All Programmable All Programmable BOM All Programmable Glaser Glaser (1) C RTL (Register-Transfer Level) IP (2) DSP (3) (4) IP (1) (2) (3) (4) ECO (Engineering

Change Order) Vivado Design Suite All Programmable Vivado Design Suite EDA EDA Vivado Design Suite ISE Design Suite 7 FPGA FPGA ISE 7 FPGA Vivado Design Suite Tom Feist Vivado Design Suite ISE Vivado Design Suite 4 S y s t e mVe r i l o gS D C C / C + +/SystemCARM AMBA AXI 4 TcL Vivado

IP C++ HDL FPGA (Feist)

ISE Design Suite 1997 1995 4 NeoCAD 15 FPGA ISE Design Suite / IP Vivado Design Suite ISE ISE EDA Feist Vivado Design Suite 20nm EDA 15 Vivado Design Suite EDA (Feist)

FPGA ( / ECO) Vivado Design Suite

C O V E R S T O R Y

10 All Programmable Vivado Design Suite


ASIC (Feist)Vivado Design Suite RTL IP IntegratorPin EditorFloor PlannerDevice Editor

Vivado Design Suite HDL (Feist) Feist

Vivado Design Suite Feist Vivado Design Suite SystemVerilog Vivado SystemVerilog (Feist) ISE Design Suite XST (Xilinx Synthesis Technology) 3 RTL 1/15 ASIC

C O V E R S T O R Y

25

20

15

10

5

00.0E+00 5.0E+05 1.0E+06 1.5E+06 2.0E+06

12h/MLC

4.6h/MLC

Vivado

ISE

Competitor tools

Ru

nti

me

(ho

urs

)

Design size (LC)

1 FPGA Vivado Design Suite


Vivado Synopsys Design Constraints Synopsys PrimeTime (STA) EDA

FPGA (SA) 1 Feist SA (Feist)

SA 100 FPGA 100 (Feist) Vivado Design Suite ASIC 3 Vivado Design Suite SA 1,000 ( 1 )3 (Feist)Zynq-7000 AP SoC RTL ISE Design Suite Vivado Design

Suite FPGA SSI Virtex-7 2000T FPGA 120 Vivado Design Suite 5 ISE Design Suite 13.4 13 ( 2)Vivado Design Suite ( 2 ) ISE Design Suite 16GB Vivado Design Suite 9GB Vivado Design Suite 3/4 ( 1/4 ) (Feist)

FPGA 1

C O V E R S T O R Y

ISE13 hrs.P&R runtime

Memory usage

*Zynq emulation platform

Wire lengthand congestion

16 GB

Vivado5 hrs.9 GB

2 Vivado Design Suite


Vivado Design Suite Vivado Design Suite ASIC 30% ISE Design Suite Vivado (Feist) Vivado Design Suite Feist

ECO Vivado Design Suite ISE FPGA Editor Vivado Device Editor Vivado Device Editor DCM (Digital Clock Manager) LUT (Lookup Table) ECO (Engineering Change Order) FPGA Feist

Vivado Design Suite CC+ +SystemCVHDLVer i logSystemVerilogMATLABSimulink

IP IP GUI TcL (Feist)

IP PackagerIP IntegratorExtensible IP CatalogIP IP Vivado Design Suite IP PackagerIP IntegratorExtensible IP Catalog 3 IP IP IC IP / IP IP 20 IP (Feist)IP Packager IP (RTL ) IP IP IP-XACT IP Packager IP XML

IP IP Integrator Feist IP Integrator IP IP IP Integrator 1 RTL (Feist)IP Integrator 45

() IP Packager IP IP RTL IP (Feist) 3 Extensible IP Catalog IP IP IP-XACT IP IP Feist Vivado Extensible IP Catalog System Generator IP Integrator IP Vivado (Ramine Roane) IP IP zip Vivado Design Suite IP

ESL Vivado HLS Vivado Design Suite 2010

C O V E R S T O R Y


AutoESL Vivado HLS ( ) ESL (Electronic System-Level) BDTI ( Xcell Journal 7172 18 DSP FPGA BDTI http://japan.xilinx.com/publications/archives/xcell/issue71-72/xcell71_72.pdf ) Vivado HLS CC++SystemC ( ) RTL (Feist)Vivado HLS IP CC++SystemC C GNU Compiler Collection/G++ Visual C++ Vivado HLS Verilog VHDL RTL RTL Verilog VHDL Vivado HLS C SystemC SystemC C Vivado Design Suite

IP Packager IP IP Integrator IP System Generator Vivado HLS 1 Xcell Journal 18-22 Nathan Jachimiec Fernando Martinez Vallina VivadoHLS (ISE Design Suite AutoESL ) UDP

ESL Vivado HLS Verilog VHDL Vivado Design Suite 1 Vivado Feist

ISim 3 100

ISE Design Suite 4 (LogicEmbeddedDSPSystem) Vivado Design Suite 2 Design Edition IP System Edition Design Edition System Generator Vivado HLS ISE Design Suite Edition ISE Vivado Design Suite 28nm ISE Design Suite Vivado Design Suite japan.xilinx.com/products/design-tools/

FunctionalSpecification

CDesign

CTestbench

RTLDesign

Synthesis

CWrapper

Verification

Packaging

Vivado IP Packager

Vivado IP Packer

ArchitecturalVerification

IP Integrator System Generator RTL

Starts at C C C++ SystemC

Produces RTL Verilog VHDL SystemC

Automates Flow Verification Implementation

3 Vivado HLS

C O V E R S T O R Y


MAC (TEMAC) PC FPGA FPGA Internet Protocol (IP) AutoESL IPv4 User-Datagram Protocol (UDP) Agilent Measurement Research Lab (UDPAddress Resolution Protocol (ARP) Dynamic Host Configuration Protocol (DHCP)) Internet Engineering Task Force (IETF) Request for Comments (RFC) C CPU AutoESL 1 FIFO RAM AutoESL Xilinx ISE Design Suite Vivado Design Suite Vivado HLS

12-17

AutoESL UDP

XCELLENCE IN COMMUNICATIONS

by Nathan Jachimiec, PhDR&D EngineerAgilent Technologies Technology Leadership [email protected]

Fernando Martinez Vallina, PhD Software Applications EngineerXilinx, [email protected]

High-Level Synthesis Tool Delivers Optimized Packet Engine Design


IPV4 USER DATAGRAM PROTOCOL Internet Protocol version 4 (IPv4) Internet Protocol version 6 (IPv6) IP Transmission Control Protocol (TCP) TCP UDP UDP UDP TCP UDP IP

UDP

Agilent Xilinx Virtex-5 FPGA

(ADC) LAN FPGA IP ( PC) FPGA RAM UDP UDP 2 1

2 UDP IP ( ) UDP

HDL HDL FPGA C Wireshark Java Verilog FIFO RAM 1 RX FlowTX FlowLAN MCU 3 LAN RX Flow

RX FIFO

InstrumentCore Logic

andADC I/F

TX FIFO

TX Flow

RX Flow

TEMAC

LAN MCU

AutoESL

Control Packets, UDP,Data Streaming, ARP,

DHCP

X C E L L E N C E I N C O M M U N I C AT I O N S

1 RX FlowTX Flow LAN MCU 3 UDP


LAN MCU (ARP DHCP )TX Flow TX FIFO N ADC UDP TX FIFO LAN MCU LAN MCU IP/UDP TX LAN MCU TEMAC TEMAC ( ) TEMAC ACK TEMAC TX FIFO TEMAC N ADC (IPv4 UDP IP UDP )

HDL

Verilog 125MHz IP/UDP 17 HDL TEMAC ChipScope 125MHz HDL 4 IP UDP HDL ChipScope HDL 32 RAM 1 32 BRAM 32 32 / / (FSM) RAM 4 UDP C IP RFC UDP C

Verilog

AUTOESL AutoESL FIFO RAM C ARP DHCP 2 HDL (Verilog ) 1 FIFO Verilog 4 RAM 32 32 AutoESL C 8 32 32 C AutoESL TX Verilog 17 7 AutoESL RAM AutoESL AutoESL



AutoESL 1 RAM Verilog TEMAC 2 RAM AutoESL 2 1/2 AutoESL TEMAC 2 Verilog

FIFO AutoESL 125MHz RAM FIFO 32 ADC FIFO

FIFO AutoESL FIFO 3 20 RAM 1 3 3

Q RAM AutoESL RAM


RXInterrupt

DHCPExchange

IdentifyPacket

UDPControl

UDPDHCP

PrepareUDP

Packet

Stream ControlInstruction to Core

ADC Samplesfrom Core

GenerateChecksums

Stream toTEMAC

ARPResponse

ARPRequest

2 ARP DHCP


3 1 AutoESL ARP DHCP Verilog ARP DHCP Verilog ARP 70 Verilog FSM 1 CPU AutoESL UDP AutoESL 2 ADC TEMAC AutoESL Mentor Graphics ModelSim HDL

ARP DHCP Verilog LAN MCUTX Flow AutoESL (LUT) 1 HDL TX Flow 37% AutoESL AutoESL 59% TX 2 HDL UDP AutoESL HDL 10 6.4ns AutoESL 3 3.5ns HDL 1 AutoESL AutoESL

HDL AutoESL


TX Flow Resource Usage

HDL TX AutoESL - TX % Increase

LUTs 858 1,372 37.5

1 - AutoESL

Latency

HDL AutoESL % Improved

Clock Cycles 17 7 58.8%

2 AutoESL TX

1 AutoESL 2 HDL HDL 2 AutoESL FIFO RAM RAM RAM RAM Verilog HDL 1 AutoESL Verilog AutoESL 8086 68000 RISC AutoESL ( )


XCELLENCE IN SOLID-STATE DISKS

Xilinx 7 PCI Express SSD

Designing a 19-nm Flash PCIe SSD with Kintex-7 FPGAs

by Yilei WangSenior Hardware Engineer

Memblaze China

[email protected]

Xiangfeng LuCTO

Memblaze China

[email protected]

Kintex-7 FPGA 19nm PCIe SSD


NAND (SSD) 10 SSD PC/ PC Serial Advanced Technology Attachment (SATA) SSD SSD 19nm SATA SATA 3.0 6Gbps SSD NAND PCI Express SSD PCIe SATA PCIe 1 16 8Gbps (Gen1 2.5GbpsGen2

5GbpsGen3 8Gbps) SSD PCIe NAND 19nm PCIe SSD PCIe SATA PCIe (DMA) 19nm (wear) (NAND ) 19nm Xilinx Kintex -7 FPGA FPGA 2 1 FPGA Kintex-7 TSMC HPL ( ) 28nm 4 1 FPGA 50%

2 Kintex-7 FPGA DSP Kintex-7 FPGA 19nm PCIe SSD 1 AXI4 3 Memblaze SSD Kintex FPGA PCIe SG-DMA SSD / (SG )CPU SSD NAND SSD (ECC) 3 ECC 2 DDR3 SDRAM

X C E L L E N C E I N S O L I D - S T A T E D I S K S

PCIe Gen 2 x 8

7 SeriesPCIe Core

TLP RXEngine

DMARegister

TLP RXEngine

Interrupt

DMA RX Engine

TAG Module

DMA TX Engine

PCIe SG-DMASubsystem

Kintex-7 325 T

AXI 4 Bus

AXI 4 Lite Bus

9 x 2 GbitDDR3

32-MB XOR Flash

TemperatureSensor

Identify Chip

MIG DDR3Controller

MicroBlaze 0

MicroBlaze 1

BRAMs

Data AddressTranslate

High-Speed Wear Leveling/

Flash Block Manage

Data AddressTranslate

QSPI FlashController

IIcController UART RS-232

InterruptController

SystemController

On-Chip Register File CPUSubsystem

High-Speed Intelligent ECC Ecoding

High-Speed Intelligent ECC Ecoding

Storage Subsystem

19-nm Flash Controller 19-nm FlashArrays

1 CPU PCIe SG-DMA 3 PCIe 19nm NAND SSD Kintex-7 SoC


SG-DMA TLP SG-DMA PCIe DMA DMA TLP SG-DMA

SG-DMA SG-DMA DMA 3

AXI4 AXI IP 1 AXI 1 AXI ARM AMBA AXI 4 AXI4-Lite IP AXI4-Stream AXI

(MIG) ECC DDR3 SDRAM 7 PCIe /TLP PCIe MircoBlaze ARM AXI4 DDR3 51.2Gbps ECC

ECC I/O 19nm NAND

PCI Express SG-DMAPCIe AXI4 DMA SSD 2.5GBytes/s PCIe 8 PCIe Gen2/Gen3


PCIe 7 FPGA PCIe SG-DMA PCIe PCIe SG-DMA PCIe

PCIe 2.1 5 GT/s (Gen2) 1 2 4 8 1 7 FPGA PCIe Gen1/Gen2 x8 40Gbps PCIe IP CORE Generator 2 PCIe

LogiCORE IP 7 Series FPGAsIntegrated Block for PCI Express

UserLogic

Physical LayerControl and Status

HostInterface

UserLogic

7 Series FPGAsIntegrated Block for

PCI Express(PCIE_2_1)

Transceivers

PCIExpressFabric

User Logic

ClockandReset

PCI Express(PCI_EXP)

Optional Debug

System(SYS)

TXBlock RAM

RXBlock RAM

AX14-StreamInterface

Physical(PL)

Configuration(CFG)

Optional Debug(DRP)

2 PCI Express



IP (EDK) pCORE CORE Generator IP AXI4 IP 2 (SAMD) 1 2 (INCR) 256 32

1,024 USER USER ( )AXI4 PCIe SG-DMA DDR3 AXI4-Lite

(OS)

Receive TLP register access TLP write?

DMA command?

DMA write?

Send TLP write requestwith write data to host

Await TLP DMA completionwith read data from host

Send TLP register completewith register value

Send TLP read request

Set register with TLP value

PCIe

Gen (Integrated block)*

Artix-7 Kintex-7 Virtex-7 T Virtex-7 XT Virtex-7 HT

Gen2 Gen2 Gen2 Gen3 Gen3

x4 x8 x8 x8 x8

1 1 3-4 2-4 1-3

5 5 8 8 8

Width

Number of Blocks

Serial Date Rate (Gbps)

*Based on symmetric filter implementation

1 PCI Express 7 FPGA

3 SG-DMA


ECC 1 NAND / / (BER) SSD ECC BER BER BER SSD BER ECC 19nm NAND ECC 35% 4GByte 1,024 49 28nm Kintex-7 FPGA 50% 2 50% Virtex-5 ECC Kintex-7 5% 40% Kintex-7 FPGA 19nm PCIe SSD PCIe Memblaze SSD / 2GBytes/s 19nm NAND

1 OS (LBA) OS 1 LBA


SSD 4 /

ECC SSD 1 ECC 19nm NAND

Without wear leveling With wear leveling

4


XCELLENCE IN DISTRIBUTED COMPUTING

by Frank Opitz, MScHamburg University of Applied Sciences

Faculty of Engineering and Computer Science

Department of Computer Science

[email protected]

Edris Sahak, BScHamburg University of Applied Sciences



[email protected]

Bernd Schwarz, Prof. Dr.-Ing.Hamburg University of Applied Sciences



[email protected]

SoC

Accelerating Distributed Computing with FPGAs

FPGA


[email protected] [1, 2] CPU GPU COPACOBANA FPGA 120 Xilinx FPGA DES [3] FPGA 1 FPGA PC FPGA FPGA FPGA

FPGA 2 FPGA FPGA [4] FPGA

SoC FPGA 8 1 8 1 4 [5] DES [3] FPGA SoC

(DSN) (SoC) ( 1) SoC 1 FPGA TCP/IP 1 DSN FPGA SoC SoC SoC (PRM) PRM

X C E L L E N C E I N D I S T R I B U T E D C O M P U T I N G

Dynamic Part

Static Part

SoC Client 1

Dynamic Part

Static Part

SoC Client n

NetworkInfrastructure

TCP/IPConnection

Broker-ServerComputer

SoC 1

PRM

Data

ProjectClient 1

PRM

Data

ProjectClient m

SoC n

Project 1

Project m

NetworkInfrastructure

Accelerating Distributed Computing with FPGAs

1 FPGA SoC SoC SoC

PRR


IP 1 / FPGA IP TEMAC Soft Direct Memory Access (SDMA) PLB 1,518 SDMA lwip_read() lwip_write() TX TEMAC DMA SDMA SoC Xilkernel TCP/IP Lightweight TCP/IP (LwIP) 3

(PRR) SoC SoC (MicroBlaze ) PRM PRR SoC

SoC ML605 Xilinx Virtex-6 FPGA (XC6VLX240T) SoC MicroBlaze ( 2)PRR (PLB) PRM IP


FPGA CompactFlash DDR3 PRM FPGA 10MB PRM 50MB 10 PRR Fast Simplex Link (FSL)PLB PLB EDK IP PLB / MicroBlaze

MicroBlaze100 MHz

MPMC400 MHz

DDR3SDRAM

GMIIEthernet

PHY

Static Part

CF Card

SysACELL_TEMAC

InterruptController HW-ICAP

XilkernelTimer Dynamic

Part

PRR

IRQ

Timer IRQ

IXCL

DXCL

SDMA

SDMA Rx and Tx IRQ

TX Local Link

RX Local Link

TEMAC IRQ

PLBv46 PLB-Master IP

IF

2 SoC (PRR) ML605 Virtex-6 FPGA

XC6VLX240T



SoC PRM (pr) SoC DDR3 XILMFS Xps_hwicap ( ) PRM PRR SoC (dr) SoC output_length+ol+data_to_compute

output_length ol dr / PRR PRM done done

lwip_write() SoC PRR Xilkernel MicroBlaze Xilkernel SoC MicroBlaze

PRM PRM

Main()

ICAPinitialize

Xilkernelstart

..xilkernel.. LwIPinitialize

Setupnetwork

interfaces

LwIP Read Threadprocessing

SoC Client Threadprocessing

SoC Client

Socketcreate

Data memoryinitialize

SoCsend

Socket read

dr

aa/ao

pr

PRMreceive

Input datareceive

Handle toSend Thread

SendThread

ComputeThread

Reconfiguration

3 SoC PRM PRR

Xilkernel sys_thread_new()


( 4) 16 2 FIFO PRM 2 FIFO PLB (FSM)

MicroBlaze RISC


/ CPU PLB 2 PLB MicroBlaze DXCL /

1 PRR MicroBlaze PRR Xilkernel

2 4 1 FSM 5 FSM PLB ( 5)OUT_FIFO PRM OUT_FIFO IN_FIFO 1

IN_FIFO OUT_FIFO Memory access Next state

dont care not empty writing WRITE_REQ

not full empty reading READ_REQ

full empty STARTED

1 STARTED FSM

IPIFUser_Logic

Data Path

IN_FIFO

Control Path

PRM-Interface OUT_FIFO

5 SWRegisters

FSMAddress

Generator

32Data_in

Data_in_en

Data_in

Data_in_ready

FIFO_full_n

FIFO_read

FIFO_empty_n

Data_out

Data_out

Enable

Data_out_free

Data_out_enFIFO_write

Data_in

FIFO_full_n

FIFO_read

FIFO_empty_n

Data_out

FIFO_write

3232

32

32

8

32

Bus2IP_MstRd_d

Bus2IP_Data

Bus2IP_BE

Bus2IP_WRCE

Bus2IP_RDCE

Bus2IP_Mst_CmdAck

Start

Start_read IP2Bus_MstRD_Req

IP2Bus_MstWR_Req

IP2Bus_MstWR_d

IP2Bus_Mst_addr

IP2Bus_Mst_BE

End_read

Start_write

End_write

Bus2IP_Mst_Cmplt

4 PRM PRM


FSM ( 3) ( READ_REQ) STARTED ( 1)FSM Mealy ( Exit/) 2 FSM FSM XST FSM


RTL VHDL FPGA

PLANAHEAD FPGA

FPGA PlanAhead ML605 PetaLinux [6]

PRR PRM PLB (DCR) PLB-DCR

PlanAhead UCF AREA_GROUP

INST " dyn_interface_0/dyn_inter-face_0/USER_LOGIC_I/PRR"

AREA_GROUP = "pblock_dyn_interface_0_USER_LOGIC_I_PRR ";

AREA_GROUP " pblock_dyn_interface_0_USER_LOGIC_I_PRR " RANGE=SLICE_X0Y0 :SLICE_X57Y239 ;

AREA_GROUP " pblock_dyn_interface_0_USER_LOGIC_I_PRR " RANGE=RAMB18_X0Y0:RAMB18_X3Y95 ;

AREA_GROUP " pblock_dyn_interface_0_USER_LOGIC_I_PRR " RANGE=RAMB36_X0Y0:RAMB36_X3Y47 ; PRR (prm_interface.vhd)

Resource Amount

LUT 55,680

FD_LD 111,360

SLICEL 7,440

SLICEEM 6,480

RAMBFIFO36E1 192

STARTED

WRITE_REQ

WAIT_FOR_WCMPWAIT_FOR_WCMP

WAIT_FOR_CMP

READ_REQ

IDLE

IN_FIFO_full_n ==1and

Read_address !=end_address_read_data

Exit / Read_address

PRR FPGA BRAM DSP (MPMC) ( 2)ISE PRM dsp_utilization_ratio = 0use_dsp48 = falseiobuf = false FPGA Editor PRR PRR ( 6)

PRM SoC PRM Sobel/Median SoC TCP/IP ( 7)Simulink RTL Xilinx System Generator 3 3 Median [7] 4 FIFO 8 32 PRM MATLAB 800 600 PNG PRM 4 8 4 OUT-FIFO ( 4) 3 SoC 3 (PRM PRR ) XGpio_WriteReg()


Interval duration

Filter Slices PRM receive Reconfiguration Image module (seconds) 3.5-Mbyte processing bit file (sec) (ms)

Binarize 3 77 31.25 25.25

Erosion 3x3 237 73 31.25 85.93

Median 3x3 531 73 31.25 77.09

Sobel 3x3 479 73 31.25 86.45

3 : fclk = 100MHz

6 PRR ( ) ( )


GPIO HWICAP Xilkernel MicroBlaze FSM HWICAP 112 / SoC PRM 100 1 SoC Xilkernel PLB SoC 1 600 800/100MHz = 4.8ms PLB 2 1 5 ( 2 5 600 800/(8 100MHz) = 6ms )FIFO


CPU GPU FPGA SoC FPGA FPGA SoC FPGA SoC HWICAP SoC FSM PLB MPMC SoC LwIP Xilkernel /RTL

SoC AXI4 PRM

1. Unofficial BOINC Wiki, Boinc FAQ: Introduction to boinc, http://www.boinc-wiki.info/

2. Markus Tervooren, all project stats.com, http://www.allprojectstats.com/

3. S. Kumar, J. Pelzl, G. Pfeiffer, M. Schimmler and C. Paar, Breaking ciphers with COPACOBANA, a cost-optimized parallel code breaker, or how to break DES for 8,980 eur, http://www.copacobana.org/paper/CHES2006_copacobana_slides.pdf

4. Frank Opitz, Development of an FPGA-based distributed computing platform. Masters thesis, HAW Hamburg, 2011, http://opus.haw-ham-burg.de/volltexte/2012/1450/pdf/Masterarbeit_Frank_Opitz.pdf

5. Ivo Bolsens, Programming Modern FPGAs, http://japan.xilinx.com/uni-versity/index.htm

6. Armin Jeyrani Mamegani, Implementation and evaluation of methods for partial and dynamic reconfiguration of SoC- FPGAs. Masters thesis, HAW Hamburg, 2010, http://opus.haw-hamburg.de/ volltexte/2010/1083/pdf/MA_A_Jeyrani.pdf

7. Edris Sahak, Partial reconfigura-tion of an SoC-based image-process-ing pipeline. Bachelors thesis, HAW Hamburg, 2011, http://opus.haw-hamburg.de/volltexte/2011/1420/pdf/BA_E_Sahak.pdf

7 PRM PRM Sobel/Median PRM


PRODUCT FEATURE

Xilinx Artix-7 FPGA Ships High-End Value to Low-Cost Market

by Mike SantariniPublisher, Xcell JournalXilinx, [email protected]

Artix-7 FPGA


All Programmable 2 Artix -7 A100T FPGA Artix-7 A200T FPGA Artix-7 28nm All Programmable FPGA 3D IC FPGA Kintex -7 ARM FPGA Zynq -7000 All Programmable SoC Ehab Mohsen Artix-7 FPGA FPGA

Artix-7 FPGA Artix-7 FPGA Mohsen

Spartan-6 FPGA 15 Artix-7 10 21.5 Mohsen Artix-7 FPGA 8 16 6.6Gbps 13Mbit RAM740 DSP48E1 Maureen Smerdon Artix-7 Spartan-6 2 2 1 FPGA

P R O D U C T F E A T U R E

All Programmable Artix-7 FPGA


DSP 2 1,306GMAC DSP Artix-7 16 6.6Gbps Artix-7 (CTLE)

211Gbps Artix-7

Mohsen Mohsen / Artix-7 FPGA 1,066Mbps DDR3 AMBA AXI4 DDR3/DDR2 SDRAM (PHY)

Artix-7 Artix-7 Artix-7

HPL 7 28nm (Xcell Journal 7576 ) TSMC TSMC HPL ( ) 28nm FPGA 28nm FPGA 2

1 Mohsen BOM ( ) Mohsen Artix-7 50% 50%


I/O Mohsen 50% Mohsen 28nm All Programmable Artix-7 FPGA Xilinx Virtex-6 Spartan-6 FPGA LUT Spartan-6 FPGA Artix-7 FPGA Mohsen

Artix-7 FPGAFPGA 22 28nm Artix-7 Mohsen Artix-7 21.5 13Mbit RAM/ 740 DSP48E1

AD

C

12

8 C

ha

nn

els

Deserializer

RX Beamformer Control

DataHigh-Speed I/O

ControlHigh-Speed I/O

Artix-7 FPGARX 128-Channel Beamformer

128-Channel Transducer

547 Pins (LVDS)

46 Pins

1 Artix-7 FPGA DSP I/O 128



Artix-7 A100T Mohsen Artix-7 FPGA 3

Mohsen Artix-7 FPGA Mohsen ( ) Artix-7 FPGA Mohsen

Kintex-7 Virtex-7 FPGA Mohsen Artix-7 Spartan-6 65% 50% 16 6.6Gbps JESD204B FPGA 41% 128 1 Artix-7 All Programmable FPGA SDR BOMMohsen Artix-7 FPGA 1 (SDR) 10 Global Information Grid (GIG) (Xcell Journal 6970 ) UAV Virtex-7 FPGA Kintex-7 FPGA GIG

GIG SDR Mohsen SDR DSP Artix-7 SDR SDR Mohsen SDR RF FPGA FPGA Artix-7 Mohsen 740 DSP Artix-7 1,306GMAC DSP FPGA 3 DSP GPU 101,440 Artix-7 15 15mm

Low-NoiseAmplifierSection

RFTuning

SAWFilter

A/DData

Formatting I/O

HumanInterface

Digital WidebandFront End

Software-DefinedRadio Processing

Engine

Software Control Processing Engine

EncryptionProcessing

Engine

TxRxSwitch Artix-7 FPGA

300-MHz to 2-GHzAntenna

Traditional RF Section

2 Artix-7 FPGA DSP


215,360 / 1 (Mohsen)Mohsen

Artix-7 3 Artix-7 FPGA All Programmable FPGA Artix-7 A100T/A200T AC701 Artix-7 http://japan.xilinx.com/artix7

2 Artix-7 SDR All Programmable FPGA

Artix-7 1 Mohsen

(Mohsen)


Artix-7 FPGA Artix-7 16 6.6Gbps Jedec JESD204B RF (Mohsen)Artix-7

BOM Mohsen DSP Artix-7 IP DSP Artix-7 A100T Artix-7 A200T

Tran

scei

vers

Tran

scei

vers

AD

CD

AC

Modem

Ethernet Switch

Control Plane Processor

Traffic Management,Packet Processing

TimeSynchronization

Channel 1 RadioEthernet

Channel 2

Artix-7 FPGA

3 Artix-7 FPGA


XPLANATION: FPGA 101

by Adam P. Taylor Principal Engineer

EADS Astrium

[email protected]

DSP CORDIC

How to Use the CORDIC Algorithm in Your FPGA Design

FPGA CORDIC


FPGA ( ) CORDIC 1 1959 Convair Jack Volder B-58A Hustler CORDIC (Coordinate Rotation Digital Computer) CORDIC FPGA CORDIC DSP DSP ( 1 ) CORDIC RMS CORDIC (FFT) CORDIC FFT

CORDIC CORDIC 3 x CORDIC CORDIC 1

Tan = Sin / Cos TanH = Sinh / Cosh Exponential = Sinh + Cosh Natural Logarithm = 2 * ArcTanH (where X = Argument +1 Y = Argument 1)

SQR = (X2 Y2)(where X = Argument +0.25 Y = Argument 0.25)

CORDIC 3

X P L A N A T I O N : F P G A 1 0 1

How to Use the CORDIC Algorithm in Your FPGA Design

FPGA CORDIC


XYZ 3 2 3 ( ) XYZ

Xi+1 = Xi m * Yi * di * 2i Yi+1 = Yi + Xi * di * 2i Zi+1 = Zi di * ei

m (m = -1) (m = 0) (m = 1) ei ei FPGA 2 di Zi < 0 di = -1 di = +1 Yi < 0 di = +1 di = -1

An = (1+2-2i)

CORDIC ( ) ( ) n n n Excel MATLAB CORDIC ( ) CORDIC


( -99.7 99.7) (4, 13, 40, K 3K+1) 1.118

CORDIC CORDIC / CORDIC IQ (SFDR) SFDR CORDIC CORDIC

Configuration Rotation Vectoring

Linear Op Y = X * Y Op Z = X/Y

HyperbolicOp X = CosH(X)Op Y = SinH(Y)

Op Z = ArcTanH

CircularOp X = Cos(X)Op Y = Sin(Y)

Op Z = ArcTanH (Y)Op X = SQR(X2 + Y2)

Configuration ei

Linear 2-i

Hyperbolic ArcTanH(2-i)

Circular ArcTan(2-i)

1 CORDIC 3 2

2 CORDIC

Mode Y X Z

Circular rotation

An 0 Argument Z

Circular vectoring

1 Argument X 0

Hyperbolic rotation

An 0 Argument Z

Hyperbolic vectoring

Argument + 1 Argument - 1 0

Linear rotation

0 Argument X Argument Z

Linear vectoring

Argument Y Argument X 0

3 1


3 CORDIC

EXCEL CORDIC Excel (An) 4 Excel X An Z

CORDIC CORDIC FPGA Xilinx CORE Generator 1 CORE Generator CORDIC ( )


CORE Generator CORDIC ( ) VHDL CORDIC

LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.numeric_std.all;

ENTITY synth_cordic IS PORT(

clk : IN std_logic;resetn : IN std_logic;z_ip : IN std_logic_vector(16 DOWNTO 0); --1,16x_ip : IN std_logic_vector(16 DOWNTO 0); --1,16y_ip : IN std_logic_vector(16 DOWNTO 0); --1,16cos_op : OUT std_logic_vector(16 DOWNTO 0); --1,16

Iteration x y z Direction Gain

Initial 0.607253 0.000000 0.017453

0 0.607253 0.607253 -0.767945 1 0.707107

1 0.910879 0.303626 -0.304298 -1 0.894427

2 0.986786 0.075907 -0.059319 -1 0.970143

3 0.996274 -0.047442 0.065036 -1 0.992278

4 0.999239 0.014826 0.002617 1 0.998053

5 0.998776 0.046052 -0.028623 1 0.999512

6 0.999496 0.030446 -0.012999 -1 0.999878

7 0.999734 0.022637 -0.005186 -1 0.999969

8 0.999822 0.018732 -0.001280 -1 0.999992

9 0.999859 0.016779 0.000673 -1 0.999998

10 0.999842 0.017756 -0.000304 1 1

11 0.999851 0.017268 0.000185 -1 1

12 0.999847 0.017512 -0.000060 1 1

13 0.999849 0.017390 0.000063 -1 1

14 0.999848 0.017451 0.000001 1 1

Cos Sin An 0.607253

CORDIC 0.999848 0.017451

Actual 0.999848 0.017452

4 / CORDIC Excel


sin_op : OUT std_logic_vector(16 DOWNTO 0)); --1,16END ENTITY synth_cordic;

ARCHITECTURE rtl OF synth_cordic IS

TYPE signed_array IS ARRAY (natural RANGE ) OF signed(17 DOWNTO 0);

--ARCTAN Array format 1,16 in radians CONSTANT tan_array : signed_array(0 TO 16) := (to_signed(51471,18),to_signed(30385,18), to_signed(16054,18),to_signed(8149,18), to_signed(4090,18), to_signed(2047,18), to_signed(1023,18), to_signed(511,18), to_signed(255,18), to_signed(127,18), to_signed(63,18), to_signed(31,18), to_signed(15,18), to_signed(7,18),to_signed(3,18), to_signed(1,18), to_signed(0, 18));

SIGNAL x_array : signed_array(0 TO 14) := (OTHERS => (OTHERS =>'0'));SIGNAL y_array : signed_array(0 TO 14) := (OTHERS => (OTHERS =>'0'));SIGNAL z_array : signed_array(0 TO 14) := (OTHERS => (OTHERS =>'0'));

BEGIN --convert inputs into signed format

PROCESS(resetn, clk) BEGIN IF resetn = '0' THEN x_array (OTHERS => '0')); z_array (OTHERS => '0')); y_array (OTHERS => '0')); ELSIF rising_edge(clk) THEN


IF signed(z_ip)< to_signed(0,18) THEN x_array(x_array'low)


by Markus WedlerProf. Dr.-Ing.

Berlin Institute of Technology

[email protected]

Eric CrabillIP Design Engineer

Xilinx, Inc.

[email protected]

Graham SchelleSenior Staff Research Engineer

Xilinx, Inc.

[email protected]

Patrick LysaghtSenior Director

Xilinx, Inc.

[email protected]

Using Formal Verification for HW/SW Co-verification of an FPGA IP Core

FPGA IP /


10 1990 Pentium I [1] / OneSpin Solutions Xilinx IP (IPC)

IPC

( ) RESET RESET ( ) RESET SystemVerilog (SVA) ( )

1


PropertyADD_INSTRUCTION; t##0 ready_to_issue_instr() and t##0 decode(ADD,op1,op2,res)implies t##1 pc_updated() and t##2 reg(res)=reg(op1)+reg(op2)endproperty

ADD SVA 0 ADD 2 2 2


IP IPC (SEM) (http://japan.xilinx.com/products/intellectual-property/SEM.htm) (RTL) PicoBlaze

SEM IP IP FPGA (SEU) FPGA / SEM

(IPC) [2]IPC IPC (SAT) IPC IPC IPC (CSM) CSM CSM CSM CSM RTL / CSM 1 ( ) CSM RTL IPC


RTL RTL IP OneSpin 360 MV IPC CSM 1 CSM



FPGA FRAME_ECC (ECC) SEM PicoBlaze SEM SEM SEM FPGA SEM SEM IP SEM UART FRAME_ECCFPGA ICAP (Internal Con-

figuration Access Port) PicoBlaze SEM ( ) PicoBlaze

( ) SEM

IPC

/ [3] IPC SEM

RTL

Hardware Firmware

Jump in Firmware State Transition

SEM Core (Design) SEM Core (Verification)

Inject Error

Hardware Firmware

Loop1: 0x100 SL0 sC 0x101 AND sC 07 ... ... 0x118 JUMP C, ERRHANDLE

ERRHANDLE: 0x200 SLA s1 0x201 SL0 sC 0x202 COMPARE s1,10 ... ...

{1, x, ... } {0x118, {0,0,0,0}, ... }

{x, x, ... } {0x200, {0,0,4,0}, ... }

HW State Firmware State

{INJECT_ERR, UART_RDY, ...} {PC, Stack Contents,...}

1 OneSpin 360 MV SEMI /


(CFG) PicoBlaze PicoBlaze IPC SEM PicoBlaze FPGA RTL 1 PicoBlaze PicoBlaze (BFM) 1 IPC 1 IPC / OneSpin 360 MV 100 30 SEM


SEM PicoBlaze ( ) 1 SEM

2

RTL SEM OneSpin 360 MV

SEM ROM ROM PicoBlaze ROM PicoBlaze PicoBlaze SEM RTL

2 PicoBlaze PicoBlaze

SEM

2 /SEM

PicoBlaze SEM

OneSpin 360 MV 2 CFG ( )


CFG SEM CFG PicoBlaze PicoBlaze


SEM PicoBlaze OneSpin 360 MV

SEM 1,700 OneSpin 360 MV 30 1,700 ( 1,500 ) UART wait UART wait wait / SEM

SEM SEM

SEM SEM 1,700 SEM IP

1. Jones, R.B.; OLeary, J.W.; Seger, C.-J.H.; Aagaard, M.D.; Melham, T.F.;

Practical formal verification in microprocessor design, Design & Test of Computers, IEEE, vol. 18, no. 4, pp. 16-25, July/August 2001

2. Nguyen, M.D.; Thalmaier, M.; Wedler, M.; Bormann, J.; Stoffel, D.; Kunz, W.; Unbounded protocol com-pliance verification using interval property checking with invariants, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 11, pp. 2068-2082, November 2008

3. Nguyen, M.D.; Wedler, M.; Stoffel, D., and Kunz, W.; Formal hardware/software co-verification by interval property checking with abstraction, Design Automation Conference (DAC), 48th ACM/EDAC/IEEE, pp. 510-515, June 5-9, 2011

IPC

Infineon Technologies OneSpin Solutions IPC 360 MV CAD IPC Infineon Technologies OneSpin Solutions IPC IPC



The FPGA Engineers Guide to Using ADCs and DACs

by Adam TaylorPrincipal Engineer

EADS Astrium

[email protected]

FPGA : ADC DAC


FPGA FPGA ADC DAC FPGA 2 50MHz 100MHz

ADC DAC

ADC

DAC

(SAR) DAC SAR

2 R-2R

2 DAC 2 DAC

R-2R R-2R R-2R DAC 2 DAC

DAC PWM

ADC/DAC FPGA I/O I/O (SNR) (SFDR) (ENOB) ADC

SNR = 6.02N + 1.76 dB

N (FFT) SNRSFDR ( ) SFDR dBc


FPGA


1

ADC DAC (STUCK-AT) (I Q) (DDR) DDR 600MHZ 300MHZ ( 2 1) 75MHZ (FS 4 1) DDR 2 ADC I/O LVDS LVCMOS

DAC DAC

ENOB = (SNR 1.76 / 6.02)

FFT FFT FFT

FFT noise floor = 6.02N + 1.76 dB + 10 LOG10(FFT size / 2)

( )

Fin / FS = Ncycles / FFT size

2


ADC ADC

Nyquist Zone Range Lower Range Upper Aliasing

First DC 0.5 FS None

Second 0.5 FS FS Folds

Third FS 1.5 FS Direct

Fourth 1.5 FS 2 FS Folds

Tap Coefficient

1 -6.22102953898351E-003

2 9.56204928971727E-003

3 -1.64864415228791E-002

4 3.45071042895427E-002

5 -0.107027889432584

6 1.166276

7 -0.107027889432584

8 3.45071042895427E-002

9 -1.64864415228791E-002

10 9.56204928971727E-003

11 -6.22102953898351E-003

1

2 DAC FIR 11



1 0.5FS 4dB

(3.92dB) sinc 2 DAC FPGA

DAC sinc FIR sinc

( ) 2 DAC FIR 11 2

CDMA GSM ( ) FPGA ADC DAC

101FPGA ADC DAC FPGA ADC DAC FPGA FPGA

Sampling Frequency (FS)

Gai

n in

dB

DAC Roll-off

0

-5

-10

-15

-20

-25

-30

-35

-40

-450 0.2 0.4 0.6 0.8 1 1.2

Sampling Frequency (FS)

DAC Roll-offDAC Compensation Filter

1.8

1.6

1.4

1.2

0

0.8

0.6

0.4

0.2

00 0.1 0.2 0.3 0.4 0.5 0.6

Gain

1 0 FS DAC

2 FS/2 DAC


FPGA E-Learning I/O Architecture WizardFoorplan Editor

VHDL

VHDL

Verilog System Verilog

Verilog

Vivado

VivadoFPGA

avnet.co.jp/design/training/

xilinx.shinko-sj.co.jp/training/index.html

ppg.teldevice.co.jp/

www.paltek.co.jp/seminar/index.htm

jp.fujitsu.com/fei/services/maker/xilinx/xtraining.html

Japan.xilinx.com/training/

System Verilog

VivadoFPGA

S6

7

Chip Scope Pro

FPGA

AMS

Virtex-5 IPPCIe

IO

SimlinkMathWorks

C : Vivado HLS

SystemGenerator DSP

DSP

Zynq

Zynq

Zynq

Vivado FPGA

Linux

10 IT ( )

XPERT OPINION

FPGAs Head for the Cloud

by Michaela BlottSenior Research EngineerXilinx, [email protected]

Tom EnglishResearch ScientistXilinx, [email protected]

Emilio BilliCTOEB [email protected]

FPGA


Web Synergy Research Group

2010 22%

Google Facebook

FPGA FPGA FPGA

FPGA

FPGA

FPGA 100G

FPGA FPGA AutoESL FPGA IP

(DCB)VXLAN FPGA (NIC) Intel Broadcom CPU FPGA TCP (TOE) FPGA FPGA PCIe IP IP/ FPGA TOE IP ( Linux TCP/IP ) FPGA QuickPath Interconnect (QPI) QPI Intel CPU QPI FPGA CPU IP IP CPU

X P E R T O P I N I O N

FPGA


QPI NIC PCIe Gen2 NIC 4 QPI FPGA/CPU PCIe QPI NIC FPGA FPGA x86 x86 FPGA

FPGA FPGA Facebook x86 C FPGA

(wimpy node) SoC ARM PCIe Zynq -7000 All Programmable SoC Applied Micro X-Gene ARM SoC Zynq FPGA CPU Convey Maxeler

Maxeler Xeon E5430 37 97% QPI CPU

FPGA 3 1 PCIe SSD PCIe FPGA IP FPGA Open NAND Flash (ONFi) FPGA

FPGA CPU


Hybrid Computing

Desktop Virtualization

OPST

Optical Backhaul

Custom NICs

Smart Analytics

Super Storage

Smart NICs

Flash Controllers

Group 1 Group 2 Group 3

QPI NIC

QPI I/O & Memory Expansion

Application-specific Servers

Cloud RAN

Smart Networking

Wimpy Nodes

Optical Interconnects

1 3 FPGA


FPGA FPGA Zynq ARM OS IP FPGA

3 1 FPGA 3 1 IP FPGA Intune Networks FPGA / (OPST) 300% Maxeler Convey Computers FPGA IBM/Netezza Smart Analytic FPGA BlueArc FPGA FusionIO FPGA Napatech Nallatech FPGA NIC NIC 2 QPI QPI NIC I/O 3 FPGA (wimpy node)64 ARM

Zynq C-RAN ( RAN) 2 3 RTL 2

FPGA Kintex Virtex I/O IP FPGA FPGA ( ) ( IP ) (SSI) FPGA FPGA FPGA


Get on Target

Xcell journal PR

Xcell Journal

10,000 HP iPad

Xcell Journal

E-mail [email protected]


I/O SoC

() TEL(045)443-4016 [email protected] () TEL(03)5792-8210 [email protected] () TEL(045)477-2005 [email protected]() TEL(045)415-5825 [email protected] () TEL(03)6361-8086 X-Proshinko-sj.co.jpCopyright 2013 Xilinx, Inc. All rights reserved. ARMEUARM Limited

Xcell Journal 日本語版 79 & 80 合併号

Text of Xcell Journal 日本語版 79 & 80 合併号

Xcell Journal issue 79

Xcell Journal 日本語版 81 & 82 合併号

xCell: digitally portraying the tissue cellular

Xcell Journal Issue 73

MSA XCell® Sensors

ザイリンクス Xcell Software Journal 日本語版 3 号

Demonstration of XCell ATF 2 and XCell ATF 6 Single-use ... · Demonstration of XCell™ ATF 2 and XCell™ ATF 6 Single-use Performance ... on XCell™ ATF SU Units . Test. ... @

XCell - ZIV

ザイリンクス Xcell Journal 日本語版 91 号

Gene Pulser Xcell Electroporation System

Xcell Journal issue 80

Sensores XCell® de MSA - Inicio » Safety Group Mexicosgmx.mx/pdf-productos/sensores-xcell-altair-4x.pdf · Sensores XCell Los Sensores XCell de MSA representan un logro sin precedentes

Xcell journal issue 90

Xcell Journal

外国語と日本語併記の母子健康手帳が9か国語版に …E2%91%A5%E5%A4%96%E5%9B%BD%…公益財団法人母子衛生研究会外国語と日本語併記の母子健康手帳が9か国語版になった

Xcell - Xilinx...ISSUE 58, THIRD QUARTER 2006 XCELL JOURNAL XILINX, INC. R Issue 58 Third Quarter 2006 THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS Xcell …

ザイリンクス Xcell Journal 日本語版 88 号

Xcell CPR-041 v2.1

Xcell Journal issue 91

Xcell Journal: Issue 1992 - Xilinx

ザイリンクス Xcell Journal 日本語版 90 号

Xcell journal issue 86

Xcell Journal 日本語版 83 号

ザイリンクス Xcell Journal 日本語版 93 号

Gene Pulser Xcell Electroporation Systems

Xcell Journal: Issue 43

XCell Aerial Surveys news article

ザイリンクス Xcell Software Journal 日本語版 2 号

Xcell Journal Issue 50 - Xilinx...THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS R ISSUE 50, FALL 2004 XCELL JOURNAL XILINX, INC. Xcell journal COVER STORY COVER STORY FPGAs

Xcell Journal: Issue 5

Documents

Xcell Journal 日本語版 79 & 80 合併号

Text of Xcell Journal 日本語版 79 & 80 合併号